NRI INSTITUTE OF TECHNOLOGY EXPT NO: 01 REALISATION OF LOGIC GATES

DATE:

AIM: To develop the source code for logic gates using VHDL and VERILOG and to obtain the simulation, synthesis, place and route and implementation into FPGA. ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Write the source code in VERILOG. Step4: Check the syntax and debug the errors if found, obtain the synthesis is report. Step5: Verify the OUTPUT: by simulating the source code. Step6: Write all possible combinations of input using the test bench. Step7: Obtain the place and route report. LOGIC DIAGRAM: AND GATE: LOGIC DIAGRAM: TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 Y=AB 0 0 0 1 A 0 0 1 1 NAND GATE: TRUTH TABLE: A 0 0 Y=A 0 1 LOGICDIAGRAM TRUTH TABLE A 0 0 1 1 B 0 1 0 1 Y=(AB) 1 1 1 0 B 0 1 0 1 Y=A+B 0 1 1 1 OR GATE: LOGICDIAGRAM TRUTH TABLE:

NOT GATE: LOGIC DIAGRAM:

NOR GATE: LOGIC DIAGRAM: TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 Y=(A+B) 1 0 0 0

XOR GATE: LOGICDIAGRAM TRUTH TABLE

A 0 0 1 1

B 0 1 0 1 0 1 1 0

XNOR GATE:

NRI INSTITUTE OF TECHNOLOGY LOGIC DIAGRAM: TRUTH TABLE: A 0 0 1 1 VHDL CODE: --Design : LOGIC GATES --Description : To implement LOGIC GATES --Author : SHAIK EKBAL ALI --Roll no : 27SVL129 --Version : Xilinx- 7.1i library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity logicgates is Port ( a : in std_logic; b : in std_logic; c : out std_logic_vector(6 downto 0)); end logicgates; architecture Behavioral of logicgates is begin c(0)<= a and b; c(1)<= a or b; c(2)<= a nand b; c(3)<= a nor b; c(4)<= a xor b; c(5)<= a xnor b; c(6)<= not a; end Behavioral; VERILOG CODE: B 0 1 0 1 1 0 0 1

module LOGICGATESverilog(a, b, c); input a; input b; OUTPUT: [6:0] c; assign c[0]= a & b; assign c[1]= a | b; assign c[2]= ~(a & b); assign c[3]= ~(a | b); assign c[4]= a ^ b; assign c[5]= ~(a ^ b); assign c[6]= ~ a;
endmodule

TEST BENCH: LIBRARY ieee; USE ieee.std_logic_1164.ALL;

NRI INSTITUTE OF TECHNOLOGY USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY logicgatetb_vhd IS END logicgatetb_vhd; ARCHITECTURE behavior OF logicgatetb_vhd IS COMPONENT logicgates PORT( a : IN std_logic; b : IN std_logic; c : OUT std_logic_vector(6 downto 0) ); END COMPONENT; SIGNAL a : std_logic := '0'; SIGNAL b : std_logic := '0'; SIGNAL c : std_logic_vector(6 downto 0); BEGIN uut: logicgates PORT MAP( a => a, b => b, c => c ); tb : PROCESS BEGIN a<='0'; b<='0'; wait for 100 ps; a<='0'; b<='1'; wait for 100 ps; a<='1'; b<='0'; wait for 100 ps; a<='1'; b<='1'; wait for 100 ps; END PROCESS; END;

OUTPUT: GRAPH:

SYNTHESIS RTL SCHEMATIC:

NRI INSTITUTE OF TECHNOLOGY

SYSNTHESIS REPORT:

Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 7.985ns Timing Detail: -------------All values displayed in nanoseconds (ns) 3 out of 3584 0% 6 out of 7168 0% 9 out of 97 9%

Timing constraint: Default path analysis Total number of paths / destination ports: 13 / 7

NRI INSTITUTE OF TECHNOLOGY

------------------------------------------------------------------------Delay: 7.985ns (Levels of Logic = 3) Source: a (PAD) Destination: c<5> (PAD) Place and root report: Constraints file: logicgates.pcf. Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx. "logicgates" is an NCD, version 3.1, device xc3s400, package tq144, speed -5 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) Device speed data version: "ADVANCED 1.35 2005-01-22". Device Utilization Summary: Number of External IOBs Number of LOCed IOBs Number of Slices Number of SLICEMs 9 out of 97 0 out of 9 9% 0%

3 out of 3584 1% 0 out of 1792 0%

Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Starting Placer Phase 1.1 Phase 1.1 (Checksum:989697) REAL time: 3 secs Phase 2.31 Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs Phase 3.2 Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs Phase 4.3 Phase 4.3 (Checksum:26259fc) REAL time: 3 secs Phase 5.5 Phase 5.5 (Checksum:2faf07b) REAL time: 3 secs Phase 6.8. Phase 6.8 (Checksum:98a1bf) REAL time: 3 secs Phase 7.5 Phase 7.5 (Checksum:42c1d79) REAL time: 3 sec Phase 8.18 Phase 8.18 (Checksum:4c4b3f8) REAL time: 3 secs Phase 9.5 Phase 9.5 (Checksum:55d4a77) REAL time: 3 secs Writing design to file logicgates.ncd Total REAL time to Placer completion: 3 secs Total CPU time to Placer completion: 1 secs Starting Router Phase 1: 19 unrouted; REAL time: 3 secs

NRI INSTITUTE OF TECHNOLOGY

Phase 2: 19 unrouted; Phase 3: 0 unrouted; Phase 4: 0 unrouted;

REAL time: 3 secs REAL time: 3 secs REAL time: 3 secs

Total REAL time to Router completion: 3 secs Total CPU time to Router completion: 1 secs Generating "PAR" statistics. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 2 secs Peak Memory Usage: 74 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 0 Number of info messages: 1 Writing design to file logicgates.ncd PAR done!

RESULT:

The OUTPUT:s of LOGIC GATES (and, or, not, nand, nor, xor, xnor) are verified by synthesizing and simulating the VHDL and VERILOG source code.

EXPT NO: 02 ADDERS AND SUBTRACTORS

DATES:

AIM: To develop the source code for adders and subtractors using VHDL and VERILOG and to obtain the simulation, synthesis, place and route and implementation into FPGA. ALGORITHM: Step1: Define the specifications and initialize the design.

NRI INSTITUTE OF TECHNOLOGY Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Write the source code in VERILOG. Step4: Check the syntax and debug the errors if found, obtain the synthesis is report. Step5: Verify the OUTPUT: by simulating the source code. Step6: Write all possible combinations of input using the test bench. Step7: Obtain the place and route report. LOGIC DIAGRAM: HALF ADDER: LOGIC DIAGRAM: TRUTH TABLE:

A 0 0 1 1 FULL ADDER: LOGIC DIAGRAM:

B 0 1 0 1

SUM 0 1 1 0

CARRY 0 0 0 1

TRUTH TABLE: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 CARRY 0 0 0 1 0 1 1 1

HALF SUBTRACTOR: LOGIC DIAGRAM: TRUTH TABLE A 0 0 1 1 B 0 1 0 1 DIFFERENCE 0 1 1 0 BORROW 0 1 0 0

FULL SUBTRACTOR:

LOGIC DIAGRAM: A 0 0 0 0 1

TRUTH TABLE: B 0 0 1 1 0 C 0 1 0 1 0 DIFFERENCE 0 1 1 0 1 BORROW 0 1 1 1 0

NRI INSTITUTE OF TECHNOLOGY 1 1 1 0 1 1 1 0 1 0 0 1 0 0 1

FULL ADDER USING TWO HALF ADDERS: LOGIC DIAGRAM:

TRUTH TABLE: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 CARRY 0 0 0 1 0 1 1 1

FULL SUBTRACTOR USING TWO HALF SUBTRACTORS: LOGIC DIAGRAM: A 0 0 0 0 1 1 1 1 TRUTH TABLE: B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 DIFFERENCE 0 1 1 0 1 0 0 1 BORROW 0 1 1 1 0 0 0 1

HALF ADDER VHDL CODE: --Design --Description --Author --Roll no --Version

: HALF ADDER : To implement HALF ADDER : SHAIK EKBAL ALI : 27SVL129 : Xilinx- 7.1i

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating

NRI INSTITUTE OF TECHNOLOGY ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity halfadder is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic); end halfadder; architecture Behavioral of halfadder is begin sum<= a xor b; carry<= a and b; end Behavioral; VERILOG CODE: module halfadder(a, b, sum, carry); input a; input b; OUTPUT: sum; OUTPUT: carry; assign sum = a ^ b; assign carry = a & b; endmodule TEST BENCH: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY halfaddertb_vhd IS END halfaddertb_vhd; ARCHITECTURE behavior OF halfaddertb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT halfadder PORT( a : IN std_logic; b : IN std_logic; sum : OUT std_logic; carry : OUT std_logic ); END COMPONENT; --Inputs SIGNAL a : std_logic := '0'; SIGNAL b : std_logic := '0'; --OUTPUT:s SIGNAL sum : std_logic; SIGNAL carry : std_logic; BEGIN

NRI INSTITUTE OF TECHNOLOGY -- Instantiate the Unit Under Test (UUT) uut: halfadder PORT MAP( a => a, b => b, sum => sum, carry => carry ); tb : PROCESS BEGIN a<='0'; b<='0'; a<='0'; b<='1'; a<='1'; b<='0'; a<='1'; b<='1'; END PROCESS; END; OUTPUT: GRAPH: wait for 100 ps; wait for 100 ps; wait for 100 ps; wait for 100 ps;

SYNTHESIS RTL SCHEMATIC:

SYNTHESIS REPORT: Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: 1 out of 3584 0% 2 out of 7168 0% 4 out of 97 4%

NRI INSTITUTE OF TECHNOLOGY TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 7.824ns Timing Detail: -------------All values displayed in nanoseconds (ns) Timing constraint: Default path analysis Total number of paths / destination ports: 4 / 2 ------------------------------------------------------------------------Delay: 7.824ns (Levels of Logic = 3) Source: a (PAD) Destination: carry (PAD)

FULL ADDER VHDL CODE: --Design --Description --Author --Roll no --Version

: FULL ADDER : To implement FULL ADDER : SHAIK EKBAL ALI : 27SVL129 : Xilinx- 7.1i

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fulladder is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end fulladder; architecture Behavioral of fulladder is signal w,x,y,z:std_logic; begin w<= a xor b;

NRI INSTITUTE OF TECHNOLOGY sum<= w xor c; x<= a and b; y<= b and c; z<= c and a; carry <= x or y or z; end Behavioral; VERILOG CODE: module fulladder(a, b, cin, sum, carry); input a; input b; input cin; OUTPUT: sum; OUTPUT: carry; assign sum = a ^ b ^ cin; assign carry = ( a & b) | ( b & cin) | ( cin & a);

endmodule

TEST BENCH: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY fulladdertb_vhd IS END fulladdertb_vhd; ARCHITECTURE behavior OF fulladdertb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT fulladder PORT( a : IN std_logic; b : IN std_logic; c : IN std_logic; sum : OUT std_logic; carry : OUT std_logic ); END COMPONENT; --Inputs SIGNAL a : std_logic := '0'; SIGNAL b : std_logic := '0'; SIGNAL c : std_logic := '0'; --OUTPUT:s SIGNAL sum : std_logic; SIGNAL carry : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: fulladder PORT MAP( a => a, b => b, c => c, sum => sum, carry => carry

NRI INSTITUTE OF TECHNOLOGY ); tb : PROCESS BEGIN a<='0'; b<='0'; c<='0'; wait for 100 ps; a<='0'; b<='0'; c<='1'; wait for 100 ps; a<='0'; b<='1'; c<='0'; wait for 100 ps; a<='0'; b<='1'; c<='1'; wait for 100 ps; a<='1'; b<='0'; c<='0'; wait for 100 ps; a<='1'; b<='0'; c<='1'; wait for 100 ps; a<='1'; b<='1'; c<='0'; wait for 100 ps; a<='1'; b<='1'; c<='1'; wait for 100 ps;

END PROCESS; END; OUTPUT: GRAPH:

SYNTHESIS RTL SCHEMATIC:

SYSNTHESIS REPORT: Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: 1 out of 3584 0% 2 out of 7168 0%

NRI INSTITUTE OF TECHNOLOGY Number of bonded IOBs: 5 out of TIMING REPORT

97

5%

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 7.824ns Timing Detail: -------------All values displayed in nanoseconds (ns) Timing constraint: Default path analysis Total number of paths / destination ports: 6 / 2 ------------------------------------------------------------------------Delay: 7.824ns (Levels of Logic = 3) Source: a (PAD) Destination: carry (PAD) Data Path: a to carry Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------IBUF:I->O 2 0.715 1.040 a_IBUF (a_IBUF) LUT3:I0->O 1 0.479 0.681 Mxor_sum_Xo<1>1 (sum_OBUF) OBUF:I->O 4.909 sum_OBUF (sum) ---------------------------------------Total 7.824ns (6.103ns logic, 1.721ns route) (78.0% logic, 22.0% route)

HALF SUBTRACTOR VHDL CODE: --Design : HALF SUBSTRACTOR --Description : To implement HALF SUBSTRACTOR --Author : SHAIK EKBAL ALI --Roll no : 27SVL129 --Version : Xilinx- 7.1i library IEEE;

NRI INSTITUTE OF TECHNOLOGY use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity halfsubstractor is Port ( a : in std_logic; b : in std_logic; difference : out std_logic; barrow : out std_logic); end halfsubstractor; architecture Behavioral of halfsubstractor is signal abar:std_logic; begin abar<= not a; difference<= a xor b; barrow <= abar and b; end Behavioral; VERILOG CODE: module halfsub(a, b, diff, barr); input a; input b; OUTPUT: diff; OUTPUT: barr; wire abar; assign abar = ~a; assign diff = a ^ b; assign barr = abar & b;

endmodule

TEST BENCH: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY HALFSUBTB_vhd IS END HALFSUBTB_vhd; ARCHITECTURE behavior OF HALFSUBTB_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT halfsubstractor PORT( a : IN std_logic; b : IN std_logic; diff : OUT std_logic; barrow : OUT std_logic ); END COMPONENT; --Inputs

NRI INSTITUTE OF TECHNOLOGY SIGNAL a : std_logic := '0'; SIGNAL b : std_logic := '0'; --OUTPUT:s SIGNAL diff : std_logic; SIGNAL barrow : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: halfsubstractor PORT MAP( a => a, b => b, diff => diff, barrow => barrow ); tb : PROCESS BEGIN a<='0'; b<='0'; a<='0'; b<='1'; a<='1'; b<='0'; a<='1'; b<='1'; END PROCESS; END; wait for 100 ps; wait for 100 ps; wait for 100 ps; wait for 100 ps;

OUTPUT: GRAPH:

SYNTHESIS RTL SCHEMATIC:

NRI INSTITUTE OF TECHNOLOGY SYSNTHESIS REPORT: Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: 1 out of 3584 0% 2 out of 7168 0% 4 out of 97 4%

========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 7.824ns Timing Detail: -------------All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 4 / 2 ------------------------------------------------------------------------Delay: 7.824ns (Levels of Logic = 3) Source: a (PAD) Destination: difference (PAD)

FULL SUBSTRACTOR VHDL CODE: --Design --Description --Author --Roll no --Version

: FULL SUBSTRACTOR : FULL SUBSTRACTOR : SHAIK EKBAL ALI : 27SVL129 : Xilinx- 7.1i

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fullsubstractor is Port ( a : in std_logic;

NRI INSTITUTE OF TECHNOLOGY b : in std_logic; c : in std_logic; difference : out std_logic; barrow : out std_logic); end fullsubstractor; architecture Behavioral of fullsubstractor is signal abar,w,x,y,z:std_logic; begin abar<= not a; w<= a xor b; difference <= w xor c; x<= abar and b; y<= abar and c; z <= b and c; barrow <= x or y or z; end Behavioral;

VERILOG CODE: module fullsub(a, b, c, diff, barr); input a; input b; input c; OUTPUT: diff; OUTPUT: barr; wire abar; assign abar = ~a; assign diff = a ^ b ^ c; assign barr = (abar&b) | (b&c) | (c&abar); endmodule

TEST BENCH: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY fulladdertb_vhd IS END fulladdertb_vhd; ARCHITECTURE behavior OF fulladdertb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT fullsubstractor PORT( a : IN std_logic; b : IN std_logic; c : IN std_logic; diff : OUT std_logic; barrow : OUT std_logic ); END COMPONENT; --Inputs SIGNAL a : std_logic := '0'; SIGNAL b : std_logic := '0'; SIGNAL c : std_logic := '0';

NRI INSTITUTE OF TECHNOLOGY --OUTPUT:s SIGNAL diff : std_logic; SIGNAL barrow : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: fullsubstractor PORT MAP( a => a, b => b, c => c, diff => diff, barrow => barrow ); tb : PROCESS BEGIN a<='0'; b<='0'; c<='0'; wait for 100 ps; a<='0'; b<='0'; c<='1'; wait for 100 ps; a<='0'; b<='1'; c<='0'; wait for 100 ps; a<='0'; b<='1'; c<='1'; wait for 100 ps; a<='1'; b<='0'; c<='0'; wait for 100 ps; a<='1'; b<='0'; c<='1'; wait for 100 ps; a<='1'; b<='1'; c<='0'; wait for 100 ps; a<='1'; b<='1'; c<='1'; wait for 100 ps; END PROCESS; END; OUTPUT: GRAPH:

SYNTHESIS RTL SCHEMATIC:

SYNTHESIS REPORT:

NRI INSTITUTE OF TECHNOLOGY Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: 1 out of 3584 0% 2 out of 7168 0% 5 out of 97 5%

========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 7.824ns Timing Detail: -------------All values displayed in nanoseconds (ns) Timing constraint: Default path analysis Total number of paths / destination ports: 6 / 2 ------------------------------------------------------------------------Delay: 7.824ns (Levels of Logic = 3) Source: a (PAD) Destination: difference (PAD) FULL ADDER USING TWO HALF ADDERS VHDL SOURCE CODE: --Design : FULL ADDER USING TWO HALF ADDERS --Description : FULL ADDER USING TWO HALF ADDERS --Author : SHAIK EKBAL ALI --Roll no : 27SVL129 --Version : Xilinx- 7.1i library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Fulladd is port (a,b,c : in std_logic; sum,carry: out std_logic); end Fulladd; architecture structural of Fulladd is component halfadd is Port ( A : in std_logic; B : in std_logic;

NRI INSTITUTE OF TECHNOLOGY S : out std_logic; C : out std_logic); end component; component orgate is port(x,y : in std_logic; z: out std_logic); end component; signal p,q,r: std_logic; begin h1:halfadd port map(a,b,p,q); h2:halfadd port map(p,c,sum,r); o1:orgate port map(r,q,carry); end structural; VERILOG SOURCE CODE: module Fulladd(a,b,c,sum,carry); input a,b,c; OUTPUT: sum,carry; wire p,q,r; halfadd h1(a,b,p,q), h2(p,c,sum,q); or o1(carry,q,r);

endmodule TEST BENCH(VHDL) : LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY full_adder_vhd IS END full_adder_vhd; ARCHITECTURE behavior OF full_adder_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT fulladd PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; sum : OUT std_logic; carry : OUT std_logic END COMPONENT; --Inputs SIGNAL a : std_logic := '0'; SIGNAL b : std_logic := '0'; SIGNAL c : std_logic := '0'; --OUTPUT:s SIGNAL sum : std_logic; SIGNAL carry : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: fulladd PORT MAP( a => a, b => b,

NRI INSTITUTE OF TECHNOLOGY c => c, sum => sum, carry => carry); tb : PROCESS BEGIN a<='0';b<='0';c<='1';wait for 200 ps; a<='0';b<='1';c<='0';wait for 200 ps; a<='0';b<='0';c<='1';wait for 200 ps; a<='1';b<='0';c<='1';wait for 200 ps; a<='1';b<='1';c<='0';wait for 200 ps; END PROCESS; END;

SIMULATION OUTPUT:

SYNTHESIS RTL SCHEMATIC:

SYNTHESIS REPORT: =========================================================================

NRI INSTITUTE OF TECHNOLOGY Macro Statistics # Xors :2 1-bit xor2 :2 ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: 1 out of 3584 0% 2 out of 7168 0% 5 out of 97 5%

=========================================================================

TIMING REPORT Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 7.824ns

FULL SUBTRACTOR USING TWO HALF SUBTRACTORS VHDL SOURCE CODE: --Design --Description --Author --Roll no --Version : FULL SUBTRACTOR USING TWO HALF SUBTRACTORS : FULL SUBTRACTOR USING TWO HALF SUBTRACTORS : SHAIK EKBAL ALI : 27SVL129 : Xilinx- 7.1i

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fullsub is Port ( a,b,c : in std_logic; bor,diff : out std_logic); end fullsub; architecture structural of fullsub is component halfsub1 is Port ( a : in std_logic; b : in std_logic; diff : out std_logic; borr : out std_logic);

NRI INSTITUTE OF TECHNOLOGY end component; component orgate is port ( x,y : in std_logic; z: out std_logic); end component; signal p,q,r: std_logic; begin h1:halfsub1 port map(a,b,p,q); h2:halfsub1 port map (p,c,diff,r); o1: orgate port map(q,r,bor); end structural; VERILOG SOURCE CODE: module fsub_2hs( diff,bor, a,b,c); OUTPUT: diff; OUTPUT: bor; input a,b,c; wire p,q,r; halfsub hs1(p,q,a,b); halfsub hs2(diff,r,p,c); or o1(bor,r,q); endmodule TEST BENCH(VHDL): LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL;

ENTITY full_subtractor_vhd IS END full_subtractor_vhd; ARCHITECTURE behavior OF full_subtractor_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT fullsub PORT( a : IN std_logic; b : IN std_logic; c : IN std_logic; bor : OUT std_logic; diff : OUT std_logic ); END COMPONENT; --Inputs SIGNAL a : std_logic := '0'; SIGNAL b : std_logic := '0'; SIGNAL c : std_logic := '0'; SIGNAL bor : std_logic; SIGNAL diff : std_logic; BEGIN uut: fullsub PORT MAP( a => a, b => b,

NRI INSTITUTE OF TECHNOLOGY c => c, bor => bor, diff => diff ); tb : PROCESS BEGIN wait for 100 ns; END PROCESS; a<='1','0' after 10 ns, '1' after 20 ns,'1' after 30 ns; b<='1','0' after 10 ns, '0' after 20 ns,'1' after 30 ns; c<='1','0' after 10 ns, '1' after 20 ns,'0' after 30 ns; END; SIMULATION OUTPUT:

SYNTHESIS RTL SCHEMATIC:

SYNTHESIS REPORT: ========================================================================= Macro Statistics # Xors :2 1-bit xor2 :2 ========================================================================= * Final Report *

NRI INSTITUTE OF TECHNOLOGY ========================================================================= Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: 1 out of 3584 0% 2 out of 7168 0% 5 out of 97 5%

========================================================================= TIMING REPORT Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 7.824ns

RIPPLE CARRY ADDER

FAST ADDERS: CARRY SELECT ADDER: LOGIC DIAGRAM:

NRI INSTITUTE OF TECHNOLOGY

CARRY LOOKAHEAD ADDER: LOGIC DIAGRAM:

CARRY SKIP ADDER: LOGIC DIAGRAM:

RIPPLE CARRY ADDER VHDL CODE: --Design : RIPPLE CARRY ADDER --Description : RIPPLE CARRY ADDER --Author : SHAIK EKBAL ALI --Roll no : 27SVL129 --Version : Xilinx- 7.1i

NRI INSTITUTE OF TECHNOLOGY library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity rca is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); cin : in std_logic; sum : out std_logic_vector(7 downto 0); cout : out std_logic); end rca; architecture structural of rca is component fulladder port (a,b,c: in std_logic; sum,carry: out std_logic); end component; signal c1,c2,c3,c4,c5,c6,c7:std_logic; begin f1:fulladder port map(a(0),b(0),cin,sum(0),c1); f2:fulladder port map(a(1),b(1),c1,sum(1),c2); f3:fulladder port map(a(2),b(2),c2,sum(2),c3); f4:fulladder port map(a(3),b(3),c3,sum(3),c4); f5:fulladder port map(a(4),b(4),c4,sum(4),c5); f6:fulladder port map(a(5),b(5),c5,sum(5),c6); f7:fulladder port map(a(6),b(6),c6,sum(6),c7); f8:fulladder port map(a(7),b(7),c7,sum(7),cout); end structural;

VERILOG CODE: module rca(a, b, cin, sum, cout); input [7:0] a; input [7:0] b; input cin; OUTPUT: [7:0] sum; OUTPUT: cout; wire c1,c2,c3,c4,c5,c6,c7; fulladder fulladder fulladder fulladder fulladder fulladder fulladder fulladder endmodule TEST BENCH(VHDL): LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; f1(a[0],b[0],cin,sum[0],c1); f2(a[1],b[1],c1,sum[1],c2); f3(a[2],b[2],c2,sum[2],c3); f4(a[3],b[3],c3,sum[3],c4); f5(a[4],b[4],c4,sum[4],c5); f6(a[5],b[5],c5,sum[5],c6); f7(a[6],b[6],c6,sum[6],c7); f8(a[7],b[7],c7,sum[7],cout);

NRI INSTITUTE OF TECHNOLOGY ENTITY riple_carry_vhd IS END riple_carry_vhd; ARCHITECTURE behavior OF riple_carry_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ripplecarry PORT( a : IN std_logic_vector(7 downto 0); b : IN std_logic_vector(7 downto 0); cin : IN std_logic; sum : OUT std_logic_vector(7 downto 0); cout : OUT std_logic ); END COMPONENT; --Inputs SIGNAL cin : std_logic := '0'; SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0'); SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0'); --OUTPUT:s SIGNAL sum : std_logic_vector(7 downto 0); SIGNAL cout : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ripplecarry PORT MAP( a => a, b => b, cin => cin, sum => sum, cout => cout ); tb : PROCESS BEGIN wait for 100 ns; END PROCESS; a<="00000000","00010001" after 10 ns,"11111111" after 20 ns; a<="01100110","11010001" after 10 ns,"11111111" after 20 ns; END;

OUTPUT: GRAPH:

NRI INSTITUTE OF TECHNOLOGY

SYNTHESIS RTL SCHEMATIC:

SYNTHESIS REPORT: Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 17.102ns 10 out of 3584 0% 17 out of 7168 0% 26 out of 97 26%

NRI INSTITUTE OF TECHNOLOGY Timing Detail: -------------All values displayed in nanoseconds (ns) Timing constraint: Default path analysis Total number of paths / destination ports: 97 / 9 ------------------------------------------------------------------------Delay: 17.102ns (Levels of Logic = 10) Source: cin (PAD) Destination: cout (PAD)

CARRY SELECT ADDER VHDL CODE: --Design : CARRY SELECT ADDER --Description : CARRY SELECT ADDER --Author : SHAIK EKBAL ALI --Roll no : 27SVL129 --Version : Xilinx- 7.1i

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity csela is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); cin : in std_logic; sum : out std_logic_vector(7 downto 0); cout : out std_logic); end csela; architecture structural of csela is component rcafourbit is port (a,b: in std_logic_vector(3 downto 0); cin: in std_logic; sum: out std_logic_vector(3 downto 0); cout: out std_logic); end component; component mux2 is port (a,b,s: in std_logic; z: out std_logic); end component; signal s0,s1,s2,c0,c1:std_logic; signal s3,s4:std_logic_vector(3 downto 0); begin s1 <= '0'; s2 <= '1'; r1:rcafourbit port map (a(3downto 0),b(3 downto 0),cin,sum(3 downto 0),s0); r2:rcafourbit port map (a(7downto 4),b(7 downto 4),s1,s3(3 downto 0),c0); r3:rcafourbit port map (a(7downto 4),b(7 downto 4),s2,s4(3 downto 0),c1); m1:mux2 port map (s3(3),s4(3),s0,sum(7));

NRI INSTITUTE OF TECHNOLOGY m2:mux2 port map (s3(2),s4(2),s0,sum(6)); m3:mux2 port map (s3(1),s4(1),s0,sum(5)); m4:mux2 port map (s3(0),s4(0),s0,sum(4)); m5:mux2 port map (c0,c1,s0,cout); end structural; VERILOG CODE: module csa(a, b, cin, sum, cout); input [7:0] a; input [7:0] b; input cin; OUTPUT: [7:0] sum; OUTPUT: cout; wire c1,c2,c3; wire [3:0]s1,s2; rcafourbit r1(a[3:0],b[3:0],cin,sum[3:0],c1), r2(a[7:4],b[7:4],1'b0,s1[3:0],c2), r3(a[7:4],b[7:4],1'b1,s2[3:0],c3); muxtwo m1(s1[3],s2[3],c1,sum[7]), m2(s1[2],s2[2],c1,sum[6]), m3 (s1[1],s2[1],c1,sum[5]), m4(s1[0],s2[0],c1,sum[4]); endmodule TEST BENCH(VHDL) : LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY cs_adder_vhd IS END cs_adder_vhd; ARCHITECTURE behavior OF cs_adder_vhd IS COMPONENT csa PORT( a : IN std_logic_vector(7 downto 0); b : IN std_logic_vector(7 downto 0);

ss

cin : IN std_logic; sum : OUT std_logic_vector(7 downto 0); cout : OUT std_logic ); END COMPONENT; SIGNAL cin : std_logic := '0'; SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0'); SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0'); SIGNAL sum : std_logic_vector(7 downto 0); SIGNAL cout : std_logic; BEGIN uut: csa PORT MAP( a => a, b => b, cin => cin, sum => sum, cout => cout );

NRI INSTITUTE OF TECHNOLOGY tb : PROCESS BEGIN cin<='0'; wait for 100ps; cin<='1'; wait for 100ps; END PROCESS; a<="00000000","00101001" after 100 ps,"00010010" after 200 ps,"11110010" after 300 ps; b<="01001000","10101101" after 100 ps,"00000010" after 200 ps,"11111111" after 300 ps; END;

OUTPUT: GRAPH:

SYNTHESIS RTL SCHEMATIC:

SYSNTHESIS REPORT:

NRI INSTITUTE OF TECHNOLOGY Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 15.794ns Timing Detail: -------------All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 105 / 9 ------------------------------------------------------------------------Delay: 15.794ns (Levels of Logic = 9) Source: cin (PAD) Destination: sum<6> (PAD) CARRY LOOK AHEAD ADDER 12 out of 3584 0% 20 out of 7168 0% 26 out of 97 26%

VHDL SOURCE CODE: --Design : CARRY LOOK AHEAD ADDER --Description : CARRY LOOK AHEAD ADDER --Author : SHAIK EKBAL ALI --Roll no : 27SVL129 --Version : Xilinx- 7.1i

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity cla is

NRI INSTITUTE OF TECHNOLOGY Port ( a : in std_logic_vector(8 downto 1); b : in std_logic_vector(8 downto 1); cin : in std_logic; sum : out std_logic_vector(8 downto 1); cout : out std_logic); end cla; architecture Behavioral of cla is signal tsum:std_logic_vector(8 downto 1); signal tc:std_logic_vector(8 downto 1); signal p:std_logic_vector(8 downto 1); signal g:std_logic_vector(8 downto 1); begin tsum <= a xor b; g <= a and b; p <= a or b; process (g,p,tc,tsum) begin tc(1) <= g(1) or (p(1) and cin); for i in 2 to 8 loop tc(i) <= g(i) or (p(i) and tc(i)); end loop; end process; sum(1) <= tsum(1) xor cin; sum( 8 downto 2) <= tsum(8 downto 2) xor tc(8 downto 2); cout <= tc(8); end Behavioral; VERILOG SOURCE CODE: module carrylookaheadadder(a, b, cin, sum, cout); input [7:0] a; input [7:0] b; input cin; OUTPUT: [7:0] sum; OUTPUT: cout; reg [7:0] tc; wire [7:0] p,tsum,g; integer i; assign tsum = a ^ b; assign g = a & b; assign p = a | b; always @ (g or p or tsum) begin tc[0]=cin; tc[1]=g[0]|(p[0]+cin); for (i=1;i<8;i=i+1) tc[i] = g[i] | (p[i] & tc[i]); end assign sum[0] = tsum[0] ^ cin; assign sum[7:1] = tsum[7:1] ^ tc[7:1]; assign cout = tc[7]; endmodule TEST BENCH(VHDL): LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY carrylook_vhd IS

NRI INSTITUTE OF TECHNOLOGY END carrylook_vhd; ARCHITECTURE behavior OF carrylook_vhd IS COMPONENT carry_look PORT( a : IN std_logic_vector(7 downto 0); b : IN std_logic_vector(7 downto 0); cin : IN std_logic; sum : OUT std_logic_vector(7 downto 0); carry : OUT std_logic ); END COMPONENT; --Inputs SIGNAL cin : std_logic := '0'; SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0'); SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0'); --OUTPUT:s SIGNAL sum : std_logic_vector(7 downto 0); SIGNAL carry : std_logic; BEGIN uut: carry_look PORT MAP( a => a, b => b, cin => cin, sum => sum, carry => carry ); tb : PROCESS BEGIN cin<='0'; wait for 100ps; cin<='1'; wait for 100ps; END PROCESS; a<="00000000","00101001" after 100 ps,"00010010" after 200 ps,"11110010" after 300 ps; b<="01001011","10101101" after 100 ps,"11100010" after 200 ps,"11111111" after 300 ps; END; SIMULATION OUTPUT:

SYNTHESIS RTL SCHEMATIC:

NRI INSTITUTE OF TECHNOLOGY

SYNTHESIS REPORT: Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 9.119ns Timing Detail: -------------All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default path analysis 9 out of 3584 0% 15 out of 7168 0% 26 out of 97 26%

NRI INSTITUTE OF TECHNOLOGY Total number of paths / destination ports: 33 / 9 ------------------------------------------------------------------------Delay: 9.119ns (Levels of Logic = 4) Source: a<8> (PAD) Destination: sum<8> (PAD) CARRY SKIP ADDER VHDL SOURCE CODE: --Design : CARRY SKIP ADDER --Description : CARRY SKIP ADDER --Author : SHAIK EKBAL ALI --Roll no : 27SVL129 --Version : Xilinx- 7.1i

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity csa is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); cin : in std_logic; sum : out std_logic_vector(7 downto 0); cout : out std_logic); end csa; architecture Behavioral of csa is component rcafourbit is port (a,b: in std_logic_vector(3 downto 0); cin : in std_logic; sum: out std_logic_vector(3 downto 0); cout : out std_logic); end component; component orgate port (a,b: in std_logic; c:out std_logic); end component; component andgate5 port (p,q,r,s,t: in std_logic; u: out std_logic); end component; signal p:std_logic_vector(7 downto 0); signal s0,s1,s2,s3,s4 : std_logic; begin

q1:rcafourbit port map (a(3 downto 0),b(3 downto 0),cin,sum(3 downto 0),s3); process (a,b) begin for i in 0 to 7 loop p(i) <= a(i) xor b(i);

NRI INSTITUTE OF TECHNOLOGY end loop; end process; a1:andgate5 port map (p(0),p(1),p(2),p(3),cin,s0); a2:andgate5 port map (p(4),p(5),p(6),p(7),s2,s1); r1:orgate port map (s3,s0,s2); q2:rcafourbit port map (a(7 downto 4),b(7 downto 4),s2,sum(7 downto 4),s4); r2:orgate port map (s4,s1,cout);

end Behavioral; VERILOG SOURCE CODE: module csa(a, b, cin, s, c8); input [8 :1]a, b; input cin; OUTPUT: [8 :1]s; OUTPUT: c8; wire cout, c4, cout1; ripple r1(a[4 :1], b[4:1], cin, s[4 :1], cout), r2(a[8 :5], b[8:5], c4, s[8 :5], cout1); skip s1(a[4:1], b[4:1], cin, cout, c4), s2(a[8:5], b[8:5], c4, cout1, c8); endmodule VERILOG CODE FOR SKIP CIRCUIT: module skip(a,b,cin, ccout, cout); input [4:1]a, b; input cin, ccout; OUTPUT: cout; reg [4:1]p; reg cskip, pout; reg cout; always @(a, b, cin, ccout) begin p[1] = a[1] ^ b[1]; p[2] = a[2] ^ b[2]; p[3] = a[3] ^ b[3]; p[4] = a[4] ^ b[4]; pout = p[1] & p[2] & p[3] & p[4]; cskip = pout & cin; cout = ccout | cskip; end endmodule

VERILOG CODE FOR RIPPLE CARRY ADDER: module ripple(a, b, cin, s, cout); input [3:0] a, b; input cin; OUTPUT: cout; OUTPUT: [3:0]s; wire c0,c1,c2; FADD f1(a[0], b[0], cin, s[0],c0), f2(a[1], b[1], c0, s[1],c1), f3(a[2], b[2], c1, s[2],c2), f4(a[3], b[3], c2, s[3],cout); endmodule TEST BENCH: LIBRARY ieee; USE ieee.std_logic_1164.ALL;

NRI INSTITUTE OF TECHNOLOGY USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY csatb_vhd IS END csatb_vhd; ARCHITECTURE behavior OF csatb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT csa PORT( a : IN std_logic_vector(7 downto 0); b : IN std_logic_vector(7 downto 0); cin : IN std_logic; sum : OUT std_logic_vector(7 downto 0); cout : OUT std_logic ); END COMPONENT; --Inputs SIGNAL cin : std_logic := '0'; SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0'); SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0'); --OUTPUT:s SIGNAL sum : std_logic_vector(7 downto 0); SIGNAL cout : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: csa PORT MAP( a => a, b => b, cin => cin, sum => sum, cout => cout ); tb : PROCESS BEGIN

a <= "10000110"; b <= "00010011"; cin <= '0'; a <= "10110110"; b <= "00000011"; cin <= '0'; a <= "10000110"; b <= "01110010"; cin <= '0'; END PROCESS; END; OUTPUT:

wait for 100 ps; wait for 100 ps; wait for 100 ps;

NRI INSTITUTE OF TECHNOLOGY

SYNTHESIS RTL SCHEMATIC:

SYNTHESIS REPORT: Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 20.207ns Timing Detail: -------------All values displayed in nanoseconds (ns) Timing constraint: Default path analysis Total number of paths / destination ports: 249 / 9 16 out of 3584 0% 27 out of 7168 0% 26 out of 97 26%

NRI INSTITUTE OF TECHNOLOGY ------------------------------------------------------------------------Delay: 20.207ns (Levels of Logic = 12) Source: b<0> (PAD) Destination: cout (PAD)

RESULT: Thus the OUTPUT:s of Adders,Subtractors and Fast Addres are verified by synthesizing and simulating the VHDL and VERILOG code.

EXPT NO: 03 ENCODERS AND DECODERS AIM:

DATES:

To develop the source code for encoders and decoders by using VHDL/VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code.

NRI INSTITUTE OF TECHNOLOGY Step3: Write the source code in VERILOG. Step4: Check the syntax and debug the errors if found, obtain the synthesis is report. Step5: Verify the OUTPUT: by simulating the source code. Step6: Write all possible combinations of input using the test bench. Step7: Obtain the place and route report. LOGIC DIAGRAM: ENCODER: LOGIC DIAGRAM: TRUTH TABLE:

D0 1 0 0 0 0 0 0 0

D1 0 1 0 0 0 0 0 0

D2 0 0 1 0 0 0 0 0

D3 0 0 0 1 0 0 0 0

D4 0 0 0 0 1 0 0 0

D5 0 0 0 0 0 1 0 0

D6 0 0 0 0 0 0 1 0

D7 0 0 0 0 0 0 0 1

X 0 0 0 0 1 1 1 1

Y 0 0 1 1 0 0 1 1

Z 0 1 0 1 0 1 0 1

DECODERS: LOGIC DIAGRAM: TRUTH TABLE:

Z(0)

Z(1)

Z(2)

Z(3)

0 0 1 1

0 1 0 1

1 1 1 1

0 1 1 1

1 0 1 1

1 1 0 1

1 1 1 0

VHDL SOURCE CODE: --Design : ENCODER --Description : To implement ENCODER --Author : SHAIK EKBAL ALI --Roll no : 27SVL129 --Version : Xilinx- 7.1i library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

NRI INSTITUTE OF TECHNOLOGY entity encoder is Port ( d : in std_logic_vector(0 to 7); x : out std_logic; y : out std_logic; z : out std_logic); end encoder2; architecture Behavioral of encoder is begin process (d) begin x<=d(4) or d(5) or d(6) or d(7); y<=d(2) or d(3) or d(6) or d(7); z<=d(1) or d(3) or d(5) or d(7); end process; end Behavioral; VERILOG SOURCE CODE: module encoder_behavioral(d, x, y, z); input [7:0] d; OUTPUT: x; OUTPUT: y; OUTPUT: z; reg x,y,z; always @ (d[7:0]) begin x=d[4]|d[5]|d[6]|d[7]; y=d[2]|d[3]|d[6]|d[7]; z=d[1]|d[3]|d[5]|d[7]; end

endmodule TEST BENCH(VHDL): LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_encoder_vhd IS END test_encoder_vhd; ARCHITECTURE behavior OF test_encoder_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT encoder2 PORT( d : IN std_logic_vector(0 to 7); x : OUT std_logic; y : OUT std_logic; z : OUT std_logic ); END COMPONENT; --Inputs SIGNAL d : std_logic_vector(0 to 7) := (others=>'0'); --OUTPUT:s SIGNAL x : std_logic;

NRI INSTITUTE OF TECHNOLOGY SIGNAL y : std_logic; SIGNAL z : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: encoder2 PORT MAP( d => d, x => x, y => y, z => z ); tb : PROCESS BEGIN wait for 100 ns; END PROCESS; d<="00000000","00010000" after 10 ns, "00000010" after 20 ns,"00000100" after 30 ns; END;

SIMULATION OUTPUT:

SYNTHESIS RTL SCHEMATIC:

NRI INSTITUTE OF TECHNOLOGY SYNTHESIS REPORT: ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: 2 out of 3584 0% 3 out of 7168 0% 11 out of 97 11%

========================================================================= TIMING REPORT

Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 7.760ns

DECODER VHDL SOURCE CODE: --Design : DECODER --Description : To implement DECODER --Author : SHAIK EKBAL ALI --Roll no : 27SVL129 --Version : Xilinx- 7.1i library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder2to4 is Port ( a,b,en_l : in std_logic; z0,z1,z2,z3 : out std_logic); end decoder2to4; architecture Behavioral of decoder2to4 is begin process(a,b,en_l) begin z0<=not((not a)and (not b) and en_l); z1<=not((not a)and b and en_l); z2<=not(a and (not b) and en_l); z3<=not(a and b and en_l); end process;

NRI INSTITUTE OF TECHNOLOGY end Behavioral; VERILOG SOURCE CODE: module decoder2_4(z0,z1,z2,z3, a,b,en); OUTPUT: z0,z1,z2,z3; input a,b,en; reg z0,z1,z2,z3; always@ (a,b,en) begin z0=~((~ a)& (~ b) & en); z1=~((~ a)& b & en); z2=~(a & (~ b) & en); z3=~(a & b & en); end endmodule TEST BENCH(VHDL): LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY encoder2_4_vhd IS END encoder2_4_vhd;

ARCHITECTURE behavior OF encoder2_4_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT decoder2to4 PORT( a : IN std_logic; b : IN std_logic; en_l : IN std_logic; z0 : OUT std_logic; z1 : OUT std_logic; z2 : OUT std_logic; z3 : OUT std_logic ); END COMPONENT; --Inputs SIGNAL a : std_logic := '0'; SIGNAL b : std_logic := '0'; SIGNAL en_l : std_logic := '0'; --OUTPUT:s SIGNAL z0 : SIGNAL z1 : SIGNAL z2 : SIGNAL z3 : BEGIN -- Instantiate the Unit Under Test (UUT) uut: decoder2to4 PORT MAP( a => a, b => b, en_l => en_l,

std_logic; std_logic; std_logic; std_logic;

NRI INSTITUTE OF TECHNOLOGY z0 => z0, z1 => z1, z2 => z2, z3 => z3 ); tb : PROCESS BEGIN wait for 100 ns; END PROCESS; a<='0','0' after 10 ns,'1' after 20 ns, '1' after 30 ns, '0' after 40 ns; b<='0','1' after 10 ns,'0' after 20 ns, '1' after 30 ns; en_l<='1','0' after 40ns,'1' after 60ns; END;

SIMULATION OUTPUT:

SYNTHESIS RTL SCHEMATIC:

NRI INSTITUTE OF TECHNOLOGY SYNTHESIS REPORT: ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: 5 out of 3584 0% 8 out of 7168 0% 11 out of 97 11%

========================================================================= TIMING REPORT

Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 7.999ns

RESULT: Thus the OUTPUT:s of Encoders and Decoders are verified by synthesizing and simulating the VHDL and VERILOG code.

NRI INSTITUTE OF TECHNOLOGY

EXPT NO: 04 MULTIPLEXER AND DEMULTIPLEXER AIM:

DATES:

To develop the source code for multiplexer and demultiplexer by using VHDL/VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Write the source code in VERILOG. Step4: Check the syntax and debug the errors if found, obtain the synthesis is report. Step5: Verify the OUTPUT: by simulating the source code. Step6: Write all possible combinations of input using the test bench. Step7: Obtain the place and route report. LOGIC DIAGRAM: MULTIPLEXER: LOGIC DIAGRAM: TRUTH TABLE: SELECT INPUT S1 0 0 1 1 S0 0 1 0 1 OUTPUT: Y D0 D1 D2 D3

DEMULTIPLEXER: LOGIC DIAGRAM: INPUT S0 S1 0 0 0 1 1 0 1 1 `TRUTH TABLE: OUTPUT: Y1 Y2 0 0 1 0 0 1 0 0

D 1 1 1 1

Y0 1 0 0 0

Y3 0 0 0 1

NRI INSTITUTE OF TECHNOLOGY VHDL SOURCE CODE: --Design : MULTIPLEXER --Description : To implement MULTIPLEXER --Author : SHAIK EKBAL ALI --Roll no : 27SVL129 --Version : Xilinx- 7.1i library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is Port ( s : in std_logic_vector(1 downto 0); i : in std_logic_vector(3 downto 0); y : out std_logic); end mux; architecture dataflow of mux is signal s1bar, s0bar, p, q, r, t : std_logic; begin y<= p or q or r or t; p<= i(0) and s1bar and s0bar; s1bar<= not s(1); s0bar<= not s(0); q<= i(1) and s1bar and s(0); r<= i(2) and s(1) and s0bar; t<= i(3) and s(1) and s(0); end dataflow; VERILOG SOURCE CODE: module mux(s, i, y); input [1 : 0]s; input [3 : 0]i; OUTPUT: y; wire s0bar, s1bar, p, q, r, t; assign s0bar = ~ s[0]; assign s1bar = ~ s[1]; assign p= s0bar & s1bar &i[0]; assign q= s[0] & s1bar &i[1]; assign r= s0bar & s[1] &i[2]; assign t= s[0] & s[1] &i[3]; assign y = p | q | r | t; endmodule TEST BENCH(VHDL): LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY amux_vhd IS END amux_vhd; ARCHITECTURE behavior OF amux_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT mux PORT(

NRI INSTITUTE OF TECHNOLOGY s : IN std_logic_vector(1 downto 0); i : IN std_logic_vector(3 downto 0); y : OUT std_logic ); END COMPONENT; --Inputs SIGNAL s : std_logic_vector(1 downto 0) := (others=>'0'); SIGNAL i : std_logic_vector(3 downto 0) := (others=>'0'); --OUTPUT:s SIGNAL y : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: mux PORT MAP( s => s, i => i, y => y ); tb : PROCESS BEGIN

s <="00";i <="0001"; wait for 200 ps; s <="01";i <="0010"; wait for 200 ps; s <="10";i <="0100"; wait for 200 ps; s <="11";i <="1000"; wait for 200 ps; END PROCESS; END;

SIMULATION OUTPUT:

SYNTHESIS RTL SCHEMATIC:

NRI INSTITUTE OF TECHNOLOGY

SYNTHESIS REPORT: ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: 1 out of 3584 0% 2 out of 7168 0% 7 out of 97 7%

========================================================================= TIMING REPORT Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 8.138ns DEMULTIPLEXER VHDL SOURCE CODE --Design : DEMULTIPLEXER --Description : To implement DEMULTIPLEXER --Author : SHAIK EKBAL ALI --Roll no : 27SVL129

NRI INSTITUTE OF TECHNOLOGY --Version : Xilinx- 7.1i library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux2 is Port ( d : in std_logic; s : in std_logic_vector(0 to 1); y : out std_logic_vector(0 to 3)); end demux2; architecture Behavioral of demux2 is begin process(d,s(0),s(1)) variable s1bar,s0bar:std_logic; begin s1bar:=not(s(1)); s0bar:=not(s(0)); y(0)<=d and s0bar and s1bar; y(1)<=d and s0bar and s(1); y(2)<=d and s(0) and s1bar; y(3)<=d and s(0) and s(1); end process; end Behavioral; VERILOG SOURCE CODE: module dmux(i,a,b,d); input i,a,b; OUTPUT:[3:0]d; wire ibar,abar,bbar; assign# 0.1 ibar=~i; assign# 0.1 abar=~a; assign# 0.1 bbar=~b; assign#0.1 d[0]=~(abar & bbar & ibar); assign#0.1 d[1]=~(abar & b & ibar); assign#0.1 d[2]=~(a & bbar & ibar); assign#0.1 d[3]=~(a & b & ibar); endmodule TEST BENCH(VHDL): LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY demux_test_vhd IS END demux_test_vhd; ARCHITECTURE behavior OF demux_test_vhd IS COMPONENT demux2 PORT( d : IN std_logic; s : IN std_logic_vector(0 to 1); y : OUT std_logic_vector(0 to 3) ); END COMPONENT; --Inputs SIGNAL d : std_logic := '0'; SIGNAL s : std_logic_vector(0 to 1) := (others=>'0');

NRI INSTITUTE OF TECHNOLOGY --OUTPUT:s SIGNAL y : std_logic_vector(0 to 3); BEGIN uut: demux2 PORT MAP( d => d, s => s, y => y ); tb : PROCESS BEGIN d<='1'; wait for 100 ps; END PROCESS; s(0)<='1','1' after 10 ns,'0' after 20 ns, '0' after 30 ns; s(1)<='1','0' after 10 ns,'1' after 20 ns, '0' after 30 ns; END;

SIMULATION OUTPUT:

SYNTHESIS RTL SCHEMATIC:

SYNTHESIS REPORT: ========================================================================= * Final Report *

NRI INSTITUTE OF TECHNOLOGY ========================================================================= Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: 2 out of 3584 0% 4 out of 7168 0% 7 out of 97 7%

========================================================================= TIMING REPORT Clock Information: -----------------No clock signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: No path found Maximum combinational path delay: 7.858ns

RESULT: Thus the OUTPUT:s of Multiplexers and Demultiplexers are verified by synthesizing and simulating the VHDL and VERILOG code.

NRI INSTITUTE OF TECHNOLOGY EXPT NO: 09 SYNCHRONOUS AND ASYNCHRONOUS COUNTER AIM: To develop the source code for synchronous and asynchronous counter by using VHDL/VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. DATES:

ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Write the source code in VERILOG. Step4: Check the syntax and debug the errors if found, obtain the synthesis is report. Step5: Verify the OUTPUT: by simulating the source code. Step6: Write all possible combinations of input using the test bench. Step7: Obtain the place and route report.

LOGIC DIAGRAM: SYNCHRONOUS COUNTER:

ASYNCHRONOUS COUNTER:

NRI INSTITUTE OF TECHNOLOGY VHDL SOURCE CODE: --Design : SYNCHRONOUS COUNTER --Description : To implement SYNCHRONOUS COUNTER --Author : SHAIK EKBAL ALI --Roll no : 27SVL129 --Version : Xilinx- 7.1i library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity syncount is Port ( clk : in std_logic; rst : in std_logic; dout : inout std_logic_vector(3 downto 0)); end syncount; architecture structural of syncount is component tff2 Port ( clk : in std_logic; rst : in std_logic; t : in std_logic; q : inout std_logic; qbar : inout std_logic); end component; component andgate Port ( p : in std_logic; q : in std_logic; r : out std_logic); end component; signal x1,x2:std_logic; signal xdum:std_logic:='1'; signal x3,x4,x5,x6:std_logic:='Z'; begin t1:tff2 port map(clk,rst,xdum,dout(0),x3); t2:tff2 port map (clk,rst,dout(0),dout(1),x4); a1:andgate port map(dout(0),dout(1),x1); t3:tff2 port map(clk,rst,x1,dout(2),x5); a2:andgate port map(x1,dout(2),x2); t4:tff2 port map(clk,rst,x2,dout(3),x6); end structural; tff2: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff2 is Port ( clk : in std_logic; rst : in std_logic; t : in std_logic; q : inout std_logic; qbar : inout std_logic); end tff2; architecture Behavioral of tff2 is begin process (clk,rst,t) begin

NRI INSTITUTE OF TECHNOLOGY if(rst='1')then q<='0'; qbar<='1'; elsif(clk='1' and clk'event)then if(t='0')then q<=q; qbar<=qbar; else q<=not(q); qbar<=not(qbar); end if; end if; end process; end Behavioral;

VERILOG SOURCE CODE: module synch_counter(dout, clk, rst); OUTPUT: [3:0] dout; input clk; input rst; wire x1,x2,x3,x4; tff t1(dout[0],x1,1'b1,clk,rst); tff t2(dout[1],x2,dout[0],clk,rst); and a1(xin1,dout[0],dout[1]); tff t3(dout[2],x3,xin1,clk,rst); and a2(xin2,xin1,dout[2]); tff t4(dout[3],x4,xin2,clk,rst);

endmodule TEST BENCH(VHDL) : LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY synch_counter_vhd IS END synch_counter_vhd; ARCHITECTURE behavior OF synch_counter_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT syncount PORT( clk : IN std_logic; rst : IN std_logic; dout : INOUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs SIGNAL clk : std_logic := '0'; SIGNAL rst : std_logic := '0'; --BiDirs SIGNAL dout : std_logic_vector(3 downto 0);

NRI INSTITUTE OF TECHNOLOGY BEGIN -- Instantiate the Unit Under Test (UUT) uut: syncount PORT MAP( clk => clk, rst => rst, dout => dout ); tb : PROCESS BEGIN clk<='0';wait for 100 ps; clk<='1';wait for 100 ps; END PROCESS; rst<='1','0' after 50 ps; END; SIMULATION OUTPUT:

SYNTHESIS RTL SCHEMATIC:

NRI INSTITUTE OF TECHNOLOGY SYNTHESIS REPORT: Macro Statistics # Registers :8 1-bit register :8 ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number of bonded IOBs: Number of GCLKs: 2 out of 3584 0% 4 out of 7168 0% 2 out of 7168 0% 6 out of 97 6% 1 out of 8 12%

========================================================================= TIMING REPORT

Clock Information: ----------------------------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP |4 | -----------------------------------+------------------------+-------+ Timing Summary: --------------Speed Grade: -5 Minimum period: 3.388ns (Maximum Frequency: 295.186MHz) Minimum input arrival time before clock: No path found Maximum OUTPUT: required time after clock: 6.318ns Maximum combinational path delay: No path found Timing Detail: -------------All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'clk' Clock period: 3.388ns (frequency: 295.186MHz) Total number of paths / destination ports: 10 / 7 ------------------------------------------------------------------------Delay: 3.388ns (Levels of Logic = 1) Source: t1/q (FF) Destination: t4/q (FF) Source Clock: clk rising Destination Clock: clk rising Data Path: t1/q to t4/q Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------FDCE:C->Q 5 0.626 1.078 t1/q (t1/q) LUT2:I0->O 1 0.479 0.681 a1/r1 (x1) FDCE:CE 0.524 t3/q

NRI INSTITUTE OF TECHNOLOGY ---------------------------------------Total 3.388ns (1.629ns logic, 1.759ns route) (48.1% logic, 51.9% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 4 / 4 ------------------------------------------------------------------------Offset: 6.318ns (Levels of Logic = 1) Source: t1/q (FF) Destination: dout<0> (PAD) Source Clock: clk rising Data Path: t1/q to dout<0> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------FDCE:C->Q 5 0.626 0.783 t1/q (t1/q) OBUF:I->O 4.909 dout_0_OBUF (dout<0>) ---------------------------------------Total 6.318ns (5.535ns logic, 0.783ns route) (87.6% logic, 12.4% route) ========================================================================= CPU : 5.59 / 6.08 s | Elapsed : 6.00 / 6.00 s PLACE AND ROUTE:

Constraints file: syncount.pcf. Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx. "syncount" is an NCD, version 3.1, device xc3s400, package tq144, speed -5 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

Device speed data version: "ADVANCED 1.35 2005-01-22".

Device Utilization Summary: Number of BUFGMUXs Number of External IOBs Number of LOCed IOBs Number of Slices Number of SLICEMs 1 out of 8 6 out of 97 0 out of 6 12% 6% 0%

5 out of 3584 1% 0 out of 1792 0%

Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user)

Starting Placer Phase 1.1 Phase 1.1 (Checksum:9896a3) REAL time: 2 secs

NRI INSTITUTE OF TECHNOLOGY Phase 2.31 Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs Phase 3.2

Phase 3.2 (Checksum:1c9c37d) REAL time: 2 secs Phase 4.3 Phase 4.3 (Checksum:26259fc) REAL time: 2 secs Phase 5.5 Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs Phase 6.8 . Phase 6.8 (Checksum:98ac4b) REAL time: 2 secs Phase 7.5 Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs Phase 8.18 Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs Phase 9.5 Phase 9.5 (Checksum:55d4a77) REAL time: 2 secs Writing design to file syncount.ncd

Total REAL time to Placer completion: 2 secs Total CPU time to Placer completion: 1 secs Starting Router Phase 1: 26 unrouted; Phase 2: 21 unrouted; Phase 3: 4 unrouted; Phase 4: 0 unrouted; REAL time: 3 secs REAL time: 3 secs REAL time: 3 secs REAL time: 3 secs

Total REAL time to Router completion: 3 secs Total CPU time to Router completion: 1 secs Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 4 | 0.000 | 0.901 | +---------------------+--------------+------+------+------------+-------------+ Generating Pad Report.

NRI INSTITUTE OF TECHNOLOGY All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 2 secs Peak Memory Usage: 74 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 0 Number of info messages: 1 Writing design to file syncount.ncd PAR done! ASYNCHRONOUS COUNTER VHDL SOURCE CODE: --Design : ASYNCHRONOUS COUNTER --Description : To implement ASYNCHRONOUS COUNTER --Author : SHAIK EKBAL ALI --Roll no : 27SVL129 --Version : Xilinx- 7.1i library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity asynch is Port ( clk,rst : in std_logic; dout : inout std_logic_vector(3 downto 0)); end asynch; architecture Behavioral of asynch is component tff2 Port ( clk : in std_logic; rst : in std_logic; t : in std_logic; q : inout std_logic; qbar : inout std_logic); end component; signal x1,x2,x3:std_logic; signal x:std_logic:='Z'; begin t1:tff2 port map(clk,rst,'1',dout(0),x1); t2:tff2 port map(x1,rst,'1',dout(1),x2); t3:tff2 port map(x2,rst,'1',dout(2),x3); t4:tff2 port map(x3,rst,'1',dout(3),x); end Behavioral; VERILOG SOURCE CODE: module asynch_counter(dout, clk, rst); OUTPUT: [3:0] dout; input clk; input rst; wire x1,x2,x3,x4; tff t1(dout[0],x1,1'b1,clk,rst); tff t2(dout[1],x2,1'b1,x1,rst);

NRI INSTITUTE OF TECHNOLOGY tff t3(dout[2],x3,1'b1,x2,rst); tff t4(dout[3],x4,1'b1,x3,rst); endmodule

TEST BENCH(VHDL): LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY asy_test_vhd IS END asy_test_vhd; ARCHITECTURE behavior OF asy_test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT asynch PORT( clk : IN std_logic; rst : IN std_logic; dout : INOUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs SIGNAL clk : std_logic := '0'; SIGNAL rst : std_logic := '0'; --BiDirs SIGNAL dout : std_logic_vector(3 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: asynch PORT MAP( clk => clk, rst => rst, dout => dout ); tb : PROCESS BEGIN clk<='0';wait for 100 ps; clk<='1';wait for 100 ps; END PROCESS; rst<='1','0' after 500 ps; END;

SIMULATION OUTPUT:

NRI INSTITUTE OF TECHNOLOGY

SYNTHESIS RTL SCHEMATIC:

SYNTHESIS REPORT: Macro Statistics # Counters :1 8-bit updown counter :1 ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: 4 out of 3584 0% Number of Slice Flip Flops: 8 out of 7168 0% Number of 4 input LUTs: 8 out of 7168 0% Number of bonded IOBs: 12 out of 97 12% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ----------------------------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP |8 | -----------------------------------+------------------------+-------+ Timing Summary: --------------Speed Grade: -5 Minimum period: 3.750ns (Maximum Frequency: 266.635MHz) Minimum input arrival time before clock: 4.181ns Maximum OUTPUT: required time after clock: 6.280ns Maximum combinational path delay: No path found Timing Detail: -------------All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'clk' Clock period: 2.733ns (frequency: 365.925MHz) Total number of paths / destination ports: 2 / 2 -------------------------------------------------------------------------

NRI INSTITUTE OF TECHNOLOGY Delay: 2.733ns (Levels of Logic = 1) Source: t1/qbar (FF) Destination: t1/qbar (FF) Source Clock: clk rising Destination Clock: clk rising Data Path: t1/qbar to t1/qbar Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------FDPE:C->Q 3 0.626 0.771 t1/qbar (t1/qbar) INV:I->O 1 0.479 0.681 t1/_n00031_INV_0 (t1/_n0003) FDPE:D 0.176 t1/qbar ---------------------------------------Total 2.733ns (1.281ns logic, 1.452ns route) (46.9% logic, 53.1% route) PLACE AND ROUTE: Constraints file: asynch.pcf. Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx. "asynch" is an NCD, version 3.1, device xc3s400, package tq144, speed -5 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) Device speed data version: "ADVANCED 1.35 2005-01-22". Device Utilization Summary: Number of BUFGMUXs Number of External IOBs Number of LOCed IOBs Number of Slices Number of SLICEMs 1 out of 8 6 out of 97 0 out of 6 12% 6% 0%

7 out of 3584 1% 0 out of 1792 0%

Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Starting Placer Phase 1.1 Phase 1.1 (Checksum:9896a9) REAL time: 1 secs Phase 2.31 Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs Phase 3.2 Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs Phase 4.3 Phase 4.3 (Checksum:26259fc) REAL time: 1 secs Phase 5.5 Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs Phase 6.8 .Phase 6.8 (Checksum:98ac4b) REAL time: 1 secs Phase 7.5 Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs Phase 8.18 Phase 8.18 (Checksum:4c4b3f8) REAL time: 1 secs Phase 9.5 Phase 9.5 (Checksum:55d4a77) REAL time: 1 secs

NRI INSTITUTE OF TECHNOLOGY Writing design to file asynch.ncd Total REAL time to Placer completion: 1 secs Total CPU time to Placer completion: 1 secs Starting Router Phase 1: 27 unrouted; Phase 2: 24 unrouted; Phase 3: 4 unrouted; Phase 4: 0 unrouted; REAL time: 2 secs REAL time: 2 secs REAL time: 2 secs REAL time: 2 secs

Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 1 secs Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 2 | 0.000 | 0.901 | +---------------------+--------------+------+------+------------+-------------+ | t1/qbar | Local| | 3 | 0.284 | 1.230 | +---------------------+--------------+------+------+------------+-------------+ | t2/qbar | Local| | 3 | 0.000 | 1.424 | +---------------------+--------------+------+------+------------+-------------+ | t3/qbar | Local| | 2 | 0.000 | 1.576 | +---------------------+--------------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 2 secs Total CPU time to PAR completion: 2 secs Peak Memory Usage: 74 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 0 Number of info messages: 1 Writing design to file asynch.ncd PAR done!

RESULT: Thus the OUTPUT:s of Synchronous and Asynchronous counter are verified by synthesizing and simulating the VHDL and VERILOG code.

NRI INSTITUTE OF TECHNOLOGY EXPT NO: 10 DESIGN OF MOORE AND MELAY FSM AIM: To develop the source code for moore and melay FSM by using VHDL/VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Write the source code in VERILOG. Step4: Check the syntax and debug the errors if found, obtain the synthesis is report. Step5: Verify the OUTPUT: by simulating the source code. Step6: Write all possible combinations of input using the test bench. Step7: Obtain the place and route report. LOGIC DIAGRAM: MOORE FSM: DATE:13-3-08

``````````

MEALY FSM:

MOORE FSM VHDL SOUCE CODE: --Design : Moore fsm --Description : To implement Moore fsm --Author : SHAIK EKBAL ALI --Roll no : 27SVL129 --Version : Xilinx- 7.1i library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

NRI INSTITUTE OF TECHNOLOGY entity moore is Port ( a : in std_logic; clk : in std_logic; z : out std_logic); end moore; architecture Behavioral of moore is type state_type is (st0,st1,st2,st3); signal moore_state:state_type; begin process(clk) begin if(clk='0')then case moore_state is when st0=>z<='1'; if(a='1')then moore_state<=st2; end if; when st1=> z<='0'; if(a='1')then moore_state<=st3; end if; when st2=>z<='0'; if(a='0')then moore_state<=st1; else moore_state<=st3; end if; when st3=>z<='1'; if(a='1')then moore_state<=st0; end if; end case; end if; end process; end Behavioral; VERILOG SOURCE CODE: module moore_fsm(z, a, clk); OUTPUT: z; input a; input clk; reg z; parameter st0=0,st1=1,st2=2,st3=3; reg [0:1]moore_state; initial begin moore_state=st0; end always @(posedge(clk)) case (moore_state) st0: begin z=1; if(a) moore_state=st2; end st1: begin

NRI INSTITUTE OF TECHNOLOGY z=0; if(a) moore_state=st3; end st2: begin z=0; if(~a) moore_state=st1; else moore_state=st3; end st3: begin z=1; if(a) moore_state=st0; end endcase endmodule TEST BENCH(VHDL) : LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY moore_fsm_vhd IS END moore_fsm_vhd; ARCHITECTURE behavior OF moore_fsm_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT moore PORT( a : IN std_logic; clk : IN std_logic; z : OUT std_logic ); END COMPONENT; --Inputs SIGNAL a : std_logic := '0'; SIGNAL clk : std_logic := '0'; --OUTPUT:s SIGNAL z : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: moore PORT MAP( a => a, clk => clk, z => z ); tb : PROCESS begin clk<='1'; wait for 1 ns; clk<='0'; wait for 1 ns; END PROCESS; --rst<='1','0' after 1 ns; a<='1','0' after 2 ns,'1' after 3 ns,'0' after 4 ns; END;

NRI INSTITUTE OF TECHNOLOGY SIMULATION OUTPUT:

SYNTHESIS RTL SCHEMATIC:

SYNTHESIS REPORT: ========================================================================= Macro Statistics # Latches :2 1-bit latch :1 4-bit latch :1 ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number of bonded IOBs: Number of GCLKs: 3 out of 3584 0% 5 out of 7168 0% 5 out of 7168 0% 3 out of 97 3% 1 out of 8 12%

========================================================================= TIMING REPORT

NRI INSTITUTE OF TECHNOLOGY Clock Information: ----------------------------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP |5 | -----------------------------------+------------------------+-------+ Timing Summary: --------------Speed Grade: -5 Minimum period: 2.910ns (Maximum Frequency: 343.648MHz) Minimum input arrival time before clock: 2.444ns Maximum OUTPUT: required time after clock: 6.141ns Maximum combinational path delay: No path found

MEALY FSM VHDL SOUCE CODE: --Design : melay fsm --Description : To implement melay fsm --Author :SHAIK EKBAL ALI --Roll no : 27SVL129 --Version : Xilinx- 7.1i library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mealyfsm is Port ( a : in std_logic; clk : in std_logic; z : out std_logic); end mealyfsm; architecture Behavioral of mealyfsm is type mealy_type is(st0,st1,st2,st3); signal p_state,n_state:mealy_type; begin seq_part:process(clk) begin if(clk='1')then p_state<=n_state; end if; end process seq_part; comb_part:process(p_state,a) begin case p_state is when st0=> if a='1' then z<='1';n_state<=st3; else z<='0'; end if; when st1=> if(a='1')then z<='0';n_state<=st0; else z<='1'; end if; when st2=> if(a='0') then

NRI INSTITUTE OF TECHNOLOGY z<='0'; else z<='1';n_state<=st1; end if; when st3=> z<='0'; if(a='0')then n_state<=st2; else n_state<=st1; end if; end case; end process comb_part; end Behavioral; VERILOG SOURCE CODE: module mealy_fsm(z, a, clk); OUTPUT: z; input a; input clk; reg z; parameter st0=0,st1=1,st2=2,st3=3; reg [1:2]p_state,n_state; initial begin n_state=st0; end always @(posedge(clk)) p_state=n_state; always @(p_state or a) begin:comb_part case(p_state) st0: if(a) begin z=1; n_state=st3; end else z=0; st1: if(a) begin z=0; n_state=st0; end else z=1; st2: if(~a) z=0; else begin z=1; n_state=st1; end st3: begin z=0; if(~a) n_state=st2;

NRI INSTITUTE OF TECHNOLOGY else n_state=st1; end endcase end endmodule TEST BENCH(VHDL) : LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY mealy_test_vhd IS END mealy_test_vhd; ARCHITECTURE behavior OF mealy_test_vhd IS COMPONENT mealyfsm PORT( a : IN std_logic; clk : IN std_logic; z : OUT std_logic ); END COMPONENT; --Inputs SIGNAL a : std_logic := '0'; SIGNAL clk : std_logic := '0'; --OUTPUT:s SIGNAL z : std_logic; BEGIN uut: mealyfsm PORT MAP( a => a, clk => clk, z => z ); tb : PROCESS BEGIN clk<='1'; wait for 1 ns; clk<='0'; wait for 1 ns; END PROCESS; a<='1','0' after 2 ns,'1' after 3 ns,'0' after 4 ns; END; SIMULATION OUTPUT:

NRI INSTITUTE OF TECHNOLOGY SYNTHESIS RTL SCHEMATIC:

SYNTHESIS REPORT: ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------Selected Device : 3s400tq144-5 Number of Slices: 5 out of 3584 0% Number of Slice Flip Flops: 8 out of 7168 0% Number of 4 input LUTs: 6 out of 7168 0% Number of bonded IOBs: 3 out of 97 3% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP |4 | _n0008(_n00081:O) | NONE(*)(n_state_3) | 4 | -----------------------------------+------------------------+-------+ Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: 2.518ns Maximum OUTPUT: required time after clock: 7.561ns Maximum combinational path delay: 7.931ns

RESULT: Thus the OUTPUT:s of Moore and Mealy fsm are verified by synthesizing and simulating the VHDL and VERILOG code.