SystemVerilog basics

Jean-Michel Chabloz

How we study SystemVerilog

Huge language:

last LM has !"!# $ages

%ot $ossible to co&er e&erything' we co&er

maybe #( o) the constructs

*ou can succeed in the course using only the

subset o) the language that is treated in these
slides

+) you want you are )ree to use other

constructs' research them by yoursel)

SystemVerilog Hello ,orld
module M();

initial
$display(Hello world);

endmodule

SystemVerilog sim$le $rogram
module M();
logic a,b;
logic [7:! c;

assign b " #a;
initial begin
a $" ;
%&ns;
repeat(')
%(ns a $" #a;
%&ns $display(c);
$)inis*();
end
initial
c $" ;
always +(posedge a)
c $" c , -;
endmodule

SystemVerilog synta-

Case sensiti&e

C-style comments: .. or ./comment/.

Code bloc0s delimited by 1begin2 1end23 +)

a single-line' can be omitted

Modules

Let4s start to consider systems without

hierarchy 5no submodules6

7 module contains ob8ects declarations

and concurrent $rocesses that o$erate in
$arallel3

+nitial bloc0s

7lways bloc0s

Continuous assignments

5instantiations o) submodules6

SystemVerilog basic data ty$es

9ata ty$es:

logic : &alued data ty$e:

;' !' <' =
initialized to <
can also be called reg .. de$recated &erilog legacy name

bit > &alued data ty$e:

;' !
initialized to ;

9e)ining a data ty$e:

bit a?
logic b?
bit c' d?

@ac0ed arrays o) logic and bits

bit A#:;B a?

logic A>:;B b?

logic A;:>;:CB AC:;B c? ..array o) >;:D bytes

integer: eEui&alent to logic A"!:;B

int' byte: eEui&alents to bit A"!:;B and bit AC:;B

arrays o) bits and logics de)ault to unsigned'

can be o&erriden with the 0eyword signed

e-: bit signed AC:;B a?

Literals

9ecimal literal:
a FG #:? .. automatically e-tended to the length o) a with ;
$adding
a FG Hd#:?
a FG !>4d#:? .. s$eci)ies that a is !>-bits wide

Ins$eci)ied length:
H!' H;' H-' Hz .. )ills with all !s' ;s' -s' zs

binary literal
!>4b!;;;J!!;;J!!!; .. underscores can be $ut anywhere
e-ce$t the beginning o) a literal
Hb!!;!! .. automatically resized with zeroes i) )ed to something
bigger

he-adecimal literal:
!>4hc? .. 1;;;;;;;;!!;;2
Hhcd: .. 2K3;;;;;!!;;!!;!2

@ac0ed array access

Single element access:

bit AC:;B a
aA#B FG aALB?

bit AM:;BAC:;B b:
bA#B FG !#?

@ac0ed arrays can be sliced:

bit AC:;B a?
aA":>B FG >4b!;?
aA":;B FG aAC::B?

bit A>;:C:;BAC:;B a? bit A!:;BAC:;B b?

aA>;:C:>;:LB FG b

$ac0ed structures

eEui&alent to a $ac0ed array subdi&ided into named

)ields:
e-am$le: :D bit $ac0ed array
can be accessed as $ac0!A!#:;B FG Hb;?
can access $ac0!AM::B FG !#?
can be accessed as $ac0!3d FG Hb;?
the whole struct can be resetted with $ac0! FG Hb;?

un$ac0ed struct 5no 1$ac0ed2 0eyword6 allow only acces

through the named )ields 5$ac0!3d FGHb;6?
struct packed {
int a;
bit [7:0] c;
bit [7:0] d;
} pack1;

Nther data ty$es

Onumerated data ty$e:

enum bit A!:;B Pidle' writing' readingQ state

+) s0i$$ing the ty$e an int ty$e is assumed

Can be ty$ede))ed 5li0e all other data ty$es6:

ty$ede) enum Pred' green' blue' yellow' white'

blac0Q Colors?

Colors A>:;B setN)Colors? .. array o) " elements o)

ty$e colors

Ry$es in SV

SystemVerilog is a wea0ly-ty$ed language

ad&antages: sim$ler and shorter code
disad&antages: easy to do mista0es

Many assignment-com$atible ty$es

a bit and a logic are assignment-com$atible' we can assign one
to the other
a longer array can be assigned to a shorter one or &ice&ersa
5truncation or e-tension will ha$$en automatically6
arrays can be inde-ed by logic arrays' bit arrays
a $ac0ed struct has the same $ro$erties as an array
struct $ac0ed PbitA":;B a' b?Q can be assigned a bit array' a logic
array' etc3

i)s' whiles' etc3 can ta0e as condition bits' logic' arrays'

etc3
non-zero &alues count as RIO' all-zero &alues count as )alse
i) a is a bit or logic' then we can write i) 5aGG!6 or i) 5a6' they do
the same thing

@rocesses

Modules contain $rocesses 5initial' always6

code inside $rocesses is called 1$rocedural
code2

+nitial: e-ecuted only once' at the beginning o) the

simulation
initial begin
%-ns;
a $" -.b-;
%&ns;
a $" -.b;
end

@rocesses

7lways - no sensiti&ity list: triggers as soon as

it )inishes e-ecuting
always begin
%-ns;
a $" -.b-;
%&ns;
a $" -.b;
end

@rocesses

7lways - with sensiti&ity list: triggers when it

has )inished e-ecuting and one o) the e&ents
in the sensiti&ity list ha$$ens
always +(posedge b, negedge c) begin
%-ns;
a $" -.b-;
%&ns;
a $" -.b;
end
posedge: positive edge
negedge: negative edge
signal name: any toggle

7lways bloc0' combinational
$rocess

Rhe sensiti&ity list must contain all elements in

the right-hand side
always +(a,b) begin
c $" a,b;
end

SystemVerilog allows using alwaysJcomb

instead

the sensiti&ity list is automatically com$iled

always/comb begin
c $" a,b;
end

7lways bloc0' )li$-)lo$

9 )li$-)lo$ with async reset:

@ossible to s$eci)y alwaysJ)) to declare intent

we declare to the com$iler we want to do a SS 5in the sense
o) edge-triggered logic' can also be an SSM6' i) it is not an SS
we get an error
always +(posedge cl0, negedge rst) begin
i) (rst"")
1 $" ;
else 22 posedge cl0, rst""-
1 $" d;
end
always/)) +(posedge cl0, negedge rst) begin
i) (rst"")
1 $" ;
else 22 posedge cl0, rst""-
1 $" d;
end

@rocedural code
i) (a""-) begin
22code
end
w*ile (a""-) begin
22code
end
)ore3er begin 22 loops )ore3er
22code
end
)or (i"; i$4; i,,) begin 22 loops t*ree times
22code
end
i) (a) begin 22 - counts as true
22code
end
repeat (4) begin
22code
end

i) trees
i) (condition) begin
5
end
else begin
5
end

i) trees
i) (condition-) begin
5
end
else i) (condition&) begin
5
end
else i) (condition4) begin
5
end
else begin
5
end

%o elsi) construct' but this is eEui&alent

Titwise logic o$erators

Titwise logic o$erators return a number o) bits

eEual to the length o) the in$uts:

U: and

V : or

W : -or

X : not

%egate one bit.logic array:

a FG Xa

9o a bit-wise N between two bit.logic arrays:

c FG a V b

logic o$erators

logic o$erators return one bit only' treat as one

e&erything that is non-zero:

UU: and

V V: or

Y : not

)or one-bit elements 1i) 5Ya62 is eEual to 1i) 5Xa62

)or a :-bit elements' i) aG!!;;

i)5Ya6 will not e-ecute 5Ya returns ;6

i)5Xa6 will e-ecute 5Xa returns ;;!! which is not all-

zeros6

com$arisons

eEuality: GG

diseguality: YG

greather than: Z

lower than: F

greater or eEual than: ZG

lower or eEual than: FG

arithmetic

[ and can be used with logic arrays' bit arrays'

automatically wra$ around:

u$ counter:
KKK3
!!!;!
!!!!;
!!!!!
;;;;;
;;;;!
;;;!;
KKK3

Riming Control in @rocesses
\!;ns: waits )or !; ns
\!;: wait )or !; time units time unit s$eci)ied during elaboration or
with a ]timescale directi&e in the code
\5a6: wait )or a number o) time units eEual to the &alue o) &ariable a
\5a/!$s6: wait )or a number o) $icoseconds eEual to the &alue o) a
^5$osedge a6: waits )or the $ositi&e edge o) a
^5b6: wait until b toggles
wait5e-$r6: waits until e-$r is true
wait5b6: wait until b is one
Riming chec0s can be bundled with the ne-t instr: \!;ns aFGYa

)or0K 8oin
S$awn concurrent $rocesses )rom a single $rocess: 7 is $rinted at
";ns? T at >;ns? 8oin waits until both sub$rocesses ha&e )inished'
the last dis$lay ta0es $lace at :;ns
initial begin
%-ns;
fork
begin
%&ns;
$display( 67n8 );
end
begin
%-ns;
$display( 97n8 );
%&ns;
end
join
$display(bot* )inis*ed);
end

@rocedural assignments

%on-bloc0ing assignment

1FG1

ta0es $lace a)ter a delta delay

Tloc0ing assignment

1G1

ta0es $lace immediately

Rhe two can be mi-ed but $robably not a

good idea

@rocedural assignments

bloc0ing assignments corres$ond to the VH9L

&ariable assignment 1:G1

non-bloc0ing assignments corres$ond to the

VH9L signals assignment 1FG1

TIR:

+n VH9L :G is reser&ed )or &ariables' FG )or signals

+n Verilog' both can be used )or &ariables

@ossible to mi- them - but $robably not a good idea

7 better idea is to use some ob8ects as VH9L

&ariables and only assign them with 1G1' others as
VH9L signals and only assign them with 1FG1

@rocedural assignments
always +(posedge cl0) begin
a $" b;
b $" a;
end
always +(posedge cl0) begin
a " b;
b " a;
end

@rocedural assignments
initial begin
a " -;
$display(a);
end
initial begin
a $" -;
$display(a);
end
initial begin
a $" -;
%-ns;
$display(a);
end

9e)ault assignments

de)ault &alues to a&oid latches and to a&oid writing long i)

else trees

wor0s li0e in VH9L 5the last write is 0e$t6

always/comb
a $" ; 22 de)ault 3alue o) a
5
i) (c)
i) (b""-)
a $" -;
end

Console.control commands

introduced with the _ 0eyword

_dis$lay used to dis$lay in)ormation to the

console

e-:

_dis$lay51hello26? .. dis$lays 1hello2

_dis$lay5a6? .. dis$lays the &alue o) a' de$ending

on its data ty$e

_sto$56' _)inish56: sto$ 5brea06 and )inish

5terminate6 the simulation

9irect generation o) random
numbers

_urandom returns a ">-bit random unsigned

number e&ery time it is called

Can be automatically assigned to shorter &alues'

automatic cli$$ing will ta0e $lace:
bit a? a FG _urandom?

Ro generate a random number between ; and

#M we can use: _urandom(L; 5modulus6

%ote: i) not seeded' e&ery time the testbench is

run we get the same &alues

this beha&ior is reEuired )or being able to re$eat tests

9irect generation o) random
numbers

_urandomJrange5!;';6 returns a random

number between !; and ;

%ote: i) not seeded' e&ery time the

testbench is run we get the same &alues

this beha&ior is reEuired )or being able to

re$eat tests

O&ent-dri&en simulation

Rhe simulator e-ecutes in a random order any o)

the o$erations scheduled )or a gi&en timeste$3

+t continues until the e&ent Eueue )or the

timeste$ is em$ty' then ad&ances time to the
ne-t non-em$ty timestam$

Rhis might create race conditions:

,hat ha$$ens is not de)ined by the rules o)

SystemVerilog

%o error is signaled

Rhe beha&ior o) the system might be simulator-

de$endent or e&en change )rom run to run

ace condition
initial begin
%-ns;
a " -;
end
initial begin
%- ns;
a " ;
end
initial begin
%& ns;
$display(a);
end

ace condition
initial begin
%-ns;
a $" -;
end
initial begin
%- ns;
a $" ;
end
initial begin
%& ns;
$display(a);
end

ace condition
initial begin
%-ns;
a $" -;
end
initial begin
%- ns;
a " ;
end
initial begin
%& ns;
$display(a);
end

ace condition
initial begin
%-ns;
a " -;
a " ;
end
initial begin
%& ns;
$display(a);
end

ace conditions

Ha$$en when two di))erent $rocesses try

to write the same signal during the same
time ste$

,ays to a&oid:

don4t write the same signal in di))erent

$rocesses' unless you really 0now what you
do 5you 0now that the two $rocesses will
ne&er write the signal in the same time ste$6

Continuous assignments

continuously $er)orms an assignment

outside $rocedural code

e-: assign a G b[c?

%ote: module in$ut.out$ut $orts count as

continuous assignments

can be done on &ariables or nets

nets can be dri&en by multi$le continuous

assignments' &ariables no

Variables &s %ets

Variables:

7re de)ined as: var type name

O-am$le: var logic a 5logic is de)ault' can be

omitted6

Rhe 0eyword 1var2 is the de)ault' it can be

omitted

So when we de)ine something li0e

logic a;

bit [7:0] b;
we are actually de)ining &ariables

Variables &s %ets

Variables can be assigned:

in a $rocedural assignment 5bloc0ing or non-

bloc0ing assignment inside an initial or always
$rocess6

Ty a single continuous assignment

How &ariables wor0
initial
%-ns a $" -;
initial
%&ns a $" ;

a &ariable 0ee$s the newest &alue that is written

to it

V7+7TLOS H7VO %NRH+%` RN 9N ,+RH

VH9L V7+7TLOS

Variables &s %ets

%ets:

9i))erent ty$es: wire' wand' wor' etc3 ,e consider

only wire

7re de)ined as: wire type name

O-am$les: wire logic a' wire logic [2:0] c

logic is the de)ault and can be omitted

7 wire cannot be a >-&alued data ty$e

7 net can be assigned only by one or more

continuous assignments' cannot be assigned
into $rocedural code

Variables &s %ets

So there is only one thing

in SV that nets can do
and that &ariables cannot:
be dri&en by multi$le
continuous assignments

%ets should be used

when modeling tri-state
bu))ers and buses

Rhe &alue is determined

by a resolution )unction
0 1 X Z
0 ; < < ;
1 < ! < !
X < < < <
Z ; ! < =

Nb8ects sco$e

ob8ects declared inside

modules.$rograms:

local to that module.$rogram

ob8ects declared inside bloc0s 5i)s' loo$s'

etc36 between a begin and an end:

local to that bloc0 o) code

Subroutines

Sunctions: return a &alue' cannot consume

time

Ras0s: no return' can consume time

Sunctions
in$ut.ou$ut.inout $orts 5inouts are read at the beginning and written
at the end6
the 0eyword in$ut is the de)ault' no need to s$eci)y it3
cannot consume time
a )unction can return &oid 5no return &alue6
+t is allowed to ha&e non-bloc0ing assignments' writes to cloc0ing
dri&ers and other constructs that schedule assignments )or the
)uture but don4t delay the )unction e-ecution
)unction logic my)unc4(input int a, output int b);
b " a , -;
return (a""-);
end)unction

Ras0s
task light 5output color' input A"!:;B tics6?
repeat 5tics6
^ 5posedge cloc06?
color G o))? .. turn light o))3
endtask: light
Ras0s can consume time' they do not return
&alues

@ac0ages
ty$e de)initions' )unctions' etc3 can be de)ined in $ac0ages
package :omple;<0g;
typedef struct =
s*ortreal i, r;
> :omple;;
function :omple; add(:omple; a, b);
add?r " a?r , b?r;
add?i " a?i , b?i;
endfunction
function :omple; mul(:omple; a, b);
mul?r " (a?r @ b?r) A (a?i @ b?i);
mul?i " (a?r @ b?i) , (a?i @ b?r);
endfunction
endpackage

@ac0ages

Stu)) that is in $ac0age can be called as:

c FG @ac0age%ame::Sunction%ame5a'b6

or

the $ac0age can be im$orted' then we can 8ust

write:

c FG Sunction%ame5a'b6?

+m$orting a $ac0age is done through:

im$ort @ac0age%ame::/?

In$ac0ed arrays

bit a A#:;B?

7rrays can ha&e multi$le un$ac0ed

dimensions or can e&en mi- $ac0ed and
un$ac0ed dimensions:

logic AC:;B c A;:>;:CB? .. array o) >;:D bytes

In$ac0ed dimensions cannot be sliced' only

single elements can be accessed

Rhey do not reside in memory in contiguous

locations they can be bigger than a $ac0ed
array because o) this reason

dynamic arrays

arrays with an un$ac0ed dimension that is

not s$eci)ied in the code:

logic AC:;B b AB?

Can only be used a)ter ha&ing been

initialized with the 0eyword 1new2

b G newA!;;B?
Can be resized with: b G newA>;;B5b6?

7)ter ha&ing been initialized it can be used

li0e any other array with un$ac0ed
dimension

associati&e arrays

associati&e array o) bytes:

declared as logic AC:;B a A/B?

7cts e-actly as a &ector o) >W"> bytes:

aA:!;>":#:">B FG D4b!;;;;!!; is legal

Memory s$ace is allocated only when used

Slow to access the elements in terms o)

simulation time

+) we would try to write to all locations we would

crash e&erything or generate an error

+deal to model big memories used only s$arsely

Eueues

logic AC:;B EA_B?

Su$$orts all o$erations that can be done on un$ac0ed

arrays

E3$ushJ)ront5a6? .. $ushes element to the )ront

E3$ushJbac05a6? .. $ushes element to the bac0

bGE3$o$Jbac056? .. $o$s element )rom bac0

bGE3$o$J)ront56? .. $o$s element )rom )ront

E3insert5"'a6 .. inserts element at $osition "

E3delete5"6 .. deletes the third element

E3delete56 .. delete all the Eueue

E3size56 .. returns size o) Eueue

Eueues

Can also be accessed using slicing and _:

E G P E' L Q? .. E3$ushJbac05L6

E G P e' E Q? .. E3$ushJ)ront5e6

E G EA!:_B? .. E3$o$J)ront56 or E3delete5;6

E G EA;:_-!B? .. E3$o$Jbac056 or E3delete5E3size-!6

E G P EA;:$os-!B' e' EA$os:_B Q? .. E3insert5$os' e6

E G P EA;:$osB' e' EA$os[!:_B Q? .. E3insert5$os[!' e6

E G PQ? .. E3delete56

Structure

Hierarchy is enca$sulated and hidden in

modules
module dut (
output bit c,
input bit [7:! a,
input bit [7:! b);
22 module code (processes, continuos assignments,
instantiations o) submodules)
endmodule

Rhere e-ists legacy &erilog $ort declaration

methods

Structure

Verilog legacy $ort declarations

module test(a,b,c);
input logic [7:! a;
input b; 22unspeci)ied type: logic
output bit [7:! c;

endmodule

Structure

Module declaration with $orts

module simple/)i)o (
input bit cl0,
input bit rst,
input bit [7:! a,
output bit [7:! b);
22 module code (processes, continuous
assignments, instantiations o) submodules)
endmodule

Structure

Module instantiation in a to$-le&el testbench

module tb (); 22 topAle3el testbenc* *as no inputs2outputs
bit cl0, reset;
bit [7:! a3, b3;
simple/)i)o dut(?cl0(cl0), 22 module instantiation
?rst(reset),
?b(b3),
?a(a3));
always
%(ns cl0 $" Bcl0;
initial
%4ns reset $" -;
initial begin
)ore3er
%-ns a3 $" $random();
end
endmodule

Module instantiation

Module instantiation in a to$-le&el testbench

@orts can be named out o) order

module tb ();
bit cl0, reset;
bit [7:! a3, b3;
simple/)i)o dut(?cl0(cl0), 22 module instantiation
?rst(reset),
?a(a3),
?b(b3));
always
%(ns cl0 $" Bcl0;
initial
%4ns reset $" -;
initial begin
)ore3er
%-ns a3 $" $random();
end
endmodule

Module +nstantiation

+) signals ha&e the same names in the including and the

included modules we can use the synta- 53/6 )or $ort
connection3
module tb ();
bit cl0, rst;
bit [7:! a, b;
simple/)i)o dut(?@); 22 aACa; bACb; cl0ACcl0; rstAC rst
always
%(ns cl0 $" Bcl0;
initial
%4ns rst $" -;
initial begin
)ore3er
%-ns a $" $random();
end
endmodule

Module +nstantiation

$ositional connection' each signal is connected

to the $ort in the same $osition easy to ma0e
errors
module tb (); 22 topAle3el testbenc* *as no inputs2outputs
bit cl0, reset;
bit [7:! a3, b3;
simple/)i)o dut(cl0,reset,a3,b3);
always
%(ns cl0 $" Bcl0;
initial
%4ns rst $" -;
initial begin
)ore3er
%-ns a $" $random();
end
endmodule

Module instantiation

module tb ();
bit cl0, reset;
bit [7:! a3, b3;
simple/)i)o dut(?@, 22 ports are connected to signals wit* t*e same name
?a(a3), 22 e;cept t*e ones named later
?b()); 22 b is le)t open
always
%(ns cl0 $" Bcl0;
initial
%4ns reset $" -;
initial begin
)ore3er
%-ns a3 $" $random();
end
endmodule

@arameters

used to e-$ress con)igurability

module tb (); 22 topAle3el testbenc*
*as no inputs2outputs
bit cl0, rst;
bit [7:! a, b;
simple/)i)o %(
?DE<FH(G'),
?HIDFH(J))
dut (
?cl0(cl0),
?rst(rst),
?a(a),
?b(b));
5
endmodule
module %(
parameter DE<FH"G',
parameter HIDFH"J
)
simple/)i)o (
input logic cl0,
input logic rst,
input logic [HIDFHA-:! a,
output logic [HIDFHA-:! b
);
localparam internal/param/name;
endmodule

@arameters

used to e-$ress con)igurability

module tb (); 22 topAle3el testbenc*
*as no inputs2outputs
bit cl0, rst;
bit [7:! a, b;
simple/)i)o %(
?DE<FH(G'),
?HIDFH(J))
dut (
?cl0(cl0),
?rst(rst),
?a(a),
?b(b));
5
endmodule
module %(
parameter DE<FH"G',
parameter HIDFH"J
)
simple/)i)o (
input logic cl0,
input logic rst,
input logic [HIDFHA-:! a,
output logic [HIDFHA-:! b
);
localparam internal/param/name;
endmodule

@arameters

@ositional instantiation
module tb (); 22 topAle3el testbenc*
*as no inputs2outputs
bit cl0, rst;
bit [7:! a, b;
simple/)i)o %(G',J)
dut (
?cl0(cl0),
?rst(rst),
?a(a),
?b(b));
5
endmodule
module %(
parameter DE<FH"G',
parameter HIDFH"J
)
simple/)i)o (
input logic cl0,
input logic rst,
input logic [HIDFHA-:! a,
output logic [HIDFHA-:! b
);
localparam internal/param/name;
endmodule

@arameters

Nther notation
module tb (); 22 topAle3el testbenc*
*as no inputs2outputs
bit cl0, rst;
bit [7:! a, b;
simple/)i)o %(
?DE<FH(G'),
?HIDFH(J))
dut (
?cl0(cl0),
?rst(rst),
?a(a),
?b(b));
5
endmodule
module simple/)i)o (
input logic cl0,
input logic rst,
input logic [HIDFHA-:! a,
output logic [HIDFHA-:! b
);
parameter DE<FH"G'
parameter HIDFH"J
localparam internal/param/name;
5
endmodule

@arameters

+) not o&erwritten' they 0ee$ their de)ault &alue

Can ha&e a ty$e:

$arameter logic AC:;B 9O@RH G L:?

local$aram: li0e $arameters' but cannot be

modi)ied hierarchically during the instantiation

Ised to indicate a $arameter that there is not

any sense )or it to be modi)ied by some higher
bloc0 in the hierarchy

Hierarchical access

Srom anywhere' it is $ossible to access any

ob8ect in the hierarchy by accessing through its
)ull $ath starting )rom the to$ module name:

a <= top.dut.subDutUnit.intObjectName;

Rhe testbench can monitor any internal 9IR

signal 5white.grey bo- &eri)ication6 without
ha&ing the signal )orwarded through $orts

SystemVerilog @rograms

@rograms are and loo0 li0e modules' but:

Rhey cannot contain always bloc0s

Rhey cannot include modules

Simulation )inishes automatically when all

initial ha&e been com$leted

7lways bloc0s are the basic building bloc0

o) RL code' not needed by the
testbenches

@rograms can do e&erything that is

needed )or &eri)ication

Cloc0ing bloc0
default clocking c0- +(posedge cl0);
default input %-ns output %-ns; 22 reading and writing s0ew
input a; 22 a, b, 5 obKects 3isible )rom t*is scope
output b; 22 input: can read; output: can write
output negedge rst; 22 o3erwrite t*e de)ault s0ew to t*e negedge

22 o) t*e cloc0
inout c; 22 inout: can bot* read and write
input d " top?dut?internal/dut/signal/name;
endclocking
+nside a module.$rogram' we access signals )or read.write inside $rocesses in this
way:
c0!3a FG !4b!?
c G c0!3b? .. or c FG c0!3b?
c0!3d FG e?
7 write will ta0e $lace !ns a)ter the cloc0 edge' a read will read the &alue that the
signal had !ns be)ore the cloc0 edge

Cloc0ing bloc0

Rhe cloc0ing bloc0 ma0es the timing

relation 5$ositi&e-edge o) the cloc0 or other
e-$licit6

Since we only &eri)y synchronous systems

with a single cloc0' we need a single
cloc0ing bloc0

,e add only one and s$eci)y it as 1de)ault2

+t gi&es a in$ut and out$ut s0ew to

read.write to the signals

Rhe in$ut.out$ut s0ew can also be omitted

Cloc0ing bloc0s and $rograms
Rhe rules o) SV say that i) we access signals )rom a $rogram
through a cloc0ing bloc0' there will be no race condition between
testbench and 9IR
O&en i) no timing s0ew is s$eci)ied
,hen there is a de)ault cloc0ing bloc0 in a $rogram.module we can
use the \\n timing construct: wait n cycles as s$eci)ied by the
de)ault cloc0ing bloc0
e-am$les:
\\"? .. wait " cycles
\\5>/a6? ..wait a number o) cycles eEual to the double o) the &alue o) &ariable
a
initial begin
%%4 reset $" ;
)ore3er begin
%%- a $" #a;
end
end
\\! e-ecuted at a time instant in which there is no cloc0 edge will
delay by a )raction o) the cloc0 cycle 5wait until the )irst cloc0 edge
only6

generate
Ised to generate $rocesses and continuous assignments
%o need o) generateK endgenerate statements
9e)ine a &ariable o) ty$e gen&ar
,e can then do a generate using a loo$ or i) with with the gen&ar
O-am$le:
gen3ar i;
initial %%& b $" ;
)or(i";i$4;i,,) begin
initial begin %%(i) a $" $urandom; end
i) (i""-) begin
always +(posedge cl0) begin
5
end
end
end

named bloc0s

a)ter e&ery begin there can be an o$tional name

7llows hierarchical access to local &ariables and

to )ind the &ariables in the simulator window

e-:
initial begin : input:ontroller
5
i) (a""-) begin : terminationHandler
end
end

`ood Restbench Structure

,rite all your

testbenches in this
way

Rhe testbench
$rogram must use
access all 9IR
signals in read and
write through the
de)ault cloc0ing
bloc0

Nnly timing
construct allowed
in the testbench
$rogram: \\
top module
generation of clock
testbench
program
drive
DUT inputs
check
DUT outputs
DUT
clk

`ood Restbench Structure
7lternati&e: se&eral $rograms are allowed
all use cloc0ing bloc0 in lin0s to the 9IR
top module
generation of clock
testbench
program
drive inputs
DUT
clk
testbench
program
check outputs

`ood testbench structure
*ou can use any structure you li0e' e&erything is allowed
Rhe one below is more IVM-li0e
top module
generation of clock
testbench
program
drive some inputs
DUT
clk
testbench
program
collect outputs
translate them into
a higher level
model
testbench
program
drive other inputs
program
check outputs

`ood testbench structure

*ou can use multi$le $rograms' but gi&en the

size o) the testbenches used in this course' one
$rogram that does e&erything is a good choice

7ll in$uts.out$uts to the 9IR through the de)ault

cloc0ing bloc0

Nnly timing construct allowed: \\ 5no need )or

other le&els o) granularity6

Rry to 0ee$ se$arated the di))erent )unctions

5in$ut generation' out$ut chec0ing6 using se&eral
initial bloc0s