Taking Advantage of the PCI Express Specification

ABSTRACT: By understanding the topology-related aspects of the PCI Express

specification, you can plan effectively and implement your design with greater
confidence. Certain connectivity rules and conventions apply to PCI Express
signals just as with any other interface. However, some inherent features that are
built into the specification make your life as the system designer somewhat
easier. This article explores these features, as well as system-level floor-planning
to position your system for success.

Connectivity Rules

As you learn to apply the PCI Express specification’s connectivity rules to your
designs, you can take full advantage of the allowances for PCI Express topologies
and layouts. The following requirements and guidelines apply specifically to
connectivity:
 Each connection between PCI Express devices must be point-to-point. In
other words, a connection can only exist between one driver and one
receiver. Daisy-chaining, or connections of multiple transmitters and
receivers on one wire or interconnect, is not allowed. You should make sure
that all components in your designs are routed such that they directly
connect with just one other PCI Express component.
Do not confuse this rule with link bifurcation and link width negotiation, in
which point-to-point lanes are grouped together to form up to x32 links
between two separate devices.

 The PCI Express specification dictates that each lane of a link be AC-coupled
between its corresponding transmitter and receiver. The AC coupling
capacitance is required either within the transmitter component/package or
along the interconnect link on the Printed Circuit Board (PCB). In most
scenarios, the AC coupling must be located external to the transmitter or
receiver device components in the form of discrete capacitors on your
system PCB. It is your responsibility to verify the AC coupling capacitor
requirements of each PCI Express Transmit (TX) component in your design.

 Each end of a PCI Express link is terminated on-die into a nominal 100 Ω
differential DC termination. This is often done by using 50 Ω terminations
on each signal of the differential pair. Because each component contains
this on-die termination, you do not need to worry about any external on-
board terminations for the PCI Express high-speed differential pairs in your
system.

 The PCI Express specification also requires each TX component to utilize on-

Copyright © 2009 Intel Corporation 1

 die equalization by means of de-emphasis for all PCI Express signals. The
de-emphasis is required to be a typical value of 3.5 dB (±0.5 dB) down with
respect to the nominal output voltage. You are not required to include any
additional external equalization for the differential pairs in your design.

 Each lane on a PCI Express link is assigned a sequential numerical value

and is identified as such in the component’s pinout. Each TX pair on a
transmitting device must connect with the identically numbered Receive
(RX) pair on the receiving device. For example, two devices that constitute
a link with a width of x1 might be identified as device A and device B. To
represent the D+ or D– signals, respectively, a ―p‖ or ―n‖ is usually
appended to the pin name. Each device’s respective TX and RX labels would
then be similar to the following:
A_PETp0, A_PETn0, A_PERp0, A_PERn0
B_PETp0, B_PETn0, B_PERp0, B_PERn0
To properly connect device A to device B, device A’s TX pairs (A_PETp0,
A_PETn0) should connect to device B’s RX pairs (B_PERp0, B_PERn0) and
vice versa. The same connectivity rules apply regardless of link size,
including x16 or x32 links. For possible exceptions to this guideline, see the
following section, ―Bowtie Topology Considerations.‖

Bowtie Topology Considerations

When physically routing or interconnecting PCI Express devices, whether across a

connector or on the same PCB, you might encounter one of the following ―bowtie‖
or signal-crossing scenarios:
 D+, D– crisscrossing within a pair. This scenario occurs when the D+ and
D– signals of a differential pair from a transmitter device must crisscross in
order to connect to the respective D+ and D– signals of the receiving
device.
 Crossing of lanes. This scenario occurs on a x2 or greater link, when lane 0
of the transmitting device must cross the other lanes in order to connect
with lane 0 on the receiving device.
 Crossing of transmit and receive pairs within a lane. This scenario occurs
when the transmit and receive differential signal pairs that constitute an
individual lane must crisscross each other in order to properly connect from
one device to another.

To help you overcome the first two scenarios, the PCI Express Base Specification
includes provisions for two features: polarity inversion and lane reversal. The
specification does not provide a provision to overcome the third scenario.

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Scenario 1: Crisscrossing Within a Pair—Making Use of Polarity Inversion

The PCI Express specification requires support for polarity inversion. This feature
allows for the TX and RX devices to fix any connections automatically within a
lane where the D+ and D– connections are reversed. Figure 1 illustrates polarity
inversion.

Polarity inversion can make your life as a designer a lot easier. First, the inversion
process is completely transparent and automatically happens on-die, within the
component, becoming enabled only when necessary. As the system designer, you
don’t need to do anything to make it work! Second, you no longer have to
scrutinize your CAD layout, doublechecking all the differential pairs; polarity
inversion effectively neutralizes the differential pair, and the D+ and D–
designations may in fact become unnecessary during layout. You can simply tell
your CAD layout engineer to ―connect TX pair A to RX pair B and don’t worry
about the + and – signs.‖ For debug purposes, it still makes sense to keep track
of which signals are D+ and which are D–, but polarity inversion makes them
irrelevant for layout purposes.

Figure 1 Polarity Inversion on an RX to TX Interconnect

Making use of polarity inversion allows you to reduce the number of via
transitions for your differential signals, have a more uniform differential route on
the PCB, and subsequently reduce the amount of PCB real estate used for
differential pair routing.

Scenario 2: Crossing of Lanes—Making Use of Lane Reversal

The PCI Express Base Specification does not require support for this optional
feature. Where supported, lane reversal allows you to reassign the TX and RX
lane 0 pairs on a given device to connect respectively to the highest ordered lane

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RX and TX pairs on a second device, and so on for the entire link.

Only one component forming part of a link needs to support lane reversal in order
to make it operational. Consider an example design with a x8 component, located
on the system PCB, that supports lane reversal and is routed to a connector
interface. In such a scenario, if the x8 component pinout is ―reversed‖—forcing
you to crisscross lanes in order to properly route and connect lane 0 through lane
7 with the connector—you could simply rearrange the link so that lane 0 of the x8
PCB component is now connected with lane 7 of the connector. The remaining
lanes would be similarly connected such that lane 1 of the PCB component would
now connect with lane 6 of the connector, and so on. Figure 2 illustrates this
scenario.

Figure 2 Example of Lane Reversal on a x8 Link

Unless you are certain that lane reversal is supported and guaranteed by at least
one of the devices in question, do not rely upon this feature. Instead, follow the
basic connectivity rules, which dictate that the lane 0 differential pairs on the first
device must connect to the lane 0 pairs on the second device or connector.

Scenario 3: Crossing of Transmit and Receive Pairs Within a Lane—Making Use of

Vias and Layer Transitions

While polarity inversion and lane reversal help to overcome the first two bowtie
scenarios, the PCI Express Base Specification does not include any provisions to
alleviate the third bowtie scenario. Simply put, an RX input on a device always
remains an RX input and cannot switch roles to become a TX output. If you find

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that your particular design forces you to crisscross RX and TX pairs within a lane,
you must untangle them during layout by means of bowtie routing—using vias to
transition layers in order to alleviate RX and TX pair crisscrossing. Figure 3
depicts this scenario.

Figure 3 Bowtie Routing to Alleviate Crisscrossing RX/TX Pairs

System-level Floor-planning
Proper floor-planning for PCI Express interfaces allows you to position your
system for success before any actual CAD time is spent routing—or re-routing—
the interface. A simple approach to floor-planning might involve these basic
steps:
1. Create a block diagram connectivity plan for devices and/or connectors and
placement studies. In addition to the actual PCI Express components, your
initial diagram should include the necessary peripheral components
interacting with your PCI Express components: clock sources, power supply
connectors, and the like. As you apply this diagram to initial placement
studies with your CAD tools, you can size up the general location on the
system board of each component and assess the routing distances and
areas that apply to each component or connector. The location and
placement of your components is also influenced by the type of system
board form factor you follow, such as ATX, micro-ATX, BTX, etc.
2. Verify connectivity rules, as explained in this article. Making sure that you
comply with all of the specification requirements can save you from design
changes down the road. Note general locations of AC capacitors and verify
whether the pinouts of the PCI Express devices and components require
any bowtie routing to achieve proper connectivity. Also follow the EMI and
Power Delivery guidelines, and determine the ability to maintain good

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 reference planes for your signals and place high power consuming devices
close to their power sources.
3. Assignment of routing restrictions. You should revisit this step several times
throughout your design. For four-layer desktop designs, begin by using the
routing length guidelines in this article. After applying the initial trace
length recommendations, refine your initial floor-planning in Step 1 so that
all devices and components conform to the maximum routing length limits
for your design. Then conduct your own simulations. By following this
approach, you can properly customize the layout guidelines for your own
particular situation.

Your floor-planning hinges on the type of design you are undertaking—whether it

be a desktop, server, mobile, communications, or even a customized design lying
somewhere in between—and the associated variations of the PCI Express
specifications that you plan to follow.

Routing Length Recommendations and Restrictions

As mentioned in Step 3 above, successful floor-planning involves an early

consideration of the routing length restrictions and requirements for the PCI
Express differential signals. While each design dictates its own requirements, it is
possible to state some general guidelines, based on a common implementation.

Table 1 presents a summary of PCB-related PCI Express microstrip routing criteria

for a common four-layer board. Designs that are not four-layer microstrip
implementation will of course have slightly different guidelines. The
recommendations in the table are based on system-level simulations and test
board implementations. You can use the length recommendations in the table to
ensure that as you do the floor-planning for a four-layer microstrip design, you
also meet the timing/jitter and loss/attenuation budgets across the entire PCI
Express interconnect path.

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Table 1 Example PCB Routing Guidelines for a Common Microstrip-Routed, 2116 Dielectric-
Based, Four-Layer PCB

While the general physical guidelines and suggestions in Table 1 help to ensure
good high-speed signal design practices, they might not necessarily guarantee
adequate performance of the interconnect for all layout variations and
implementations. In fact, these guidelines should only be applied to designs
where a four-layer, 2116-based dielectric is used for the PCB stack-up.

For more information about PCI Express, please refer to the book PCI Express
Electrical Interconnect Design by Dave Coleman, Scott Gardiner, Mohammad
Kolbehdari, and Stephen Peters.

About the Authors

Copyright © 2009 Intel Corporation 7

Scott Gardiner is a Senior Hardware Engineer at Intel and holds a Master's
degree in Electrical Engineering. Since joining Intel in 1997, Scott has made
significant contributions to various high-speed interconnect and PCB designs.
Involved with PCI Express since its inception, Scott was the lead engineer on one
of Intel's first prototype PCI Express boards and a key contributor to Intel's first
PCI Express desktop motherboard.

Dave Coleman is a Platform Application Engineer with 19 years of electrical

engineering experience. At Intel, he specializes in electrical modeling and
simulation of PCI Express platform designs. Dave is the co-author and editor of
Intel's PCI Express Design Guide, and regularly contributes articles to Printed
Circuit Design magazine.

Stephen Peters leads a group at Intel developing methodologies for validating

next generation chip and board-level interfaces for PCI Express. Over the past 15
years, Stephen has designed high-speed bus interfaces and solved signal integrity
issues. From 2001 through 2003, he served as chair of the I/O Buffer Information
Specification (IBIS) Open Forum and continues to be major contributor to the
IBIS specification.

Mohammad Kolbehdari is a Senior Staff Hardware Engineer at Intel involved

with PCI Express interconnect design and simulation. He developed a 3D full-
wave modeling methodology for high-speed bus and package design used
extensively throughout Intel and is currently creating second-generation PCI
Express design guidelines. Mohammad holds a PhD in Electrical Engineering and
is a regular contributor to IEEE professional journals, COMPEL, and Journal of the
Franklin Institute.

Copyright © 2009 Intel Corporation. All rights reserved.

This article is based on material found in book PCI Express Electrical Interconnect
Design by Dave Coleman, Scott Gardiner, Mohammad Kolbehdari, and Stephen
Peters. Visit the Intel Press web site to learn more about this book:
http://www.intel.com/intelpress/sum_pcieh.htm

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