Kommirisetti Bheema Raju. Int. Journal of Engineering Research and Application www.ijera.

com
ISSN: 2248-9622, Vol. 7, Issue 1, (Part -1) January 2017, pp.87-90

RESEARCH ARTICLE OPEN ACCESS

Design And Verification of AMBA APB Protocol

1
Kommirisetti Bheema Raju,2 Bala Krishna Konda, M.Tech,
1
M.Tech Digital Electronics & Communication Systems(Decs) Student In Elure College Of Engineering And
Technology, Affiliated To Jntuk, Eluru, Andhra Pradesh.
2
Asistant Professor In The Department Of Ece In Eluru College Of Engineering And Technology, Affiliated To
Jntuk, Eluru, Andhra Pradesh

ABSTRACT:
Advanced microcontroller bus architecture (AMBA) is a well established open specification for the proper
management of functional blocks comprising system-on-chips (SOCs). A Memory Controller is designed to
cater to this problem. This design presents an intellectual property (IP) for inter-Advanced peripheral bus (APB)
protocol. The Memory Controller is a digital circu it which manages the flo w of data going to and fro m the main
memo ry. It can be a separate chip or can be integrated into the system chipset. This paper revolves around
building an Advanced Microcontroller Bus Architecture (AMBA) co mpliant Memory Controller as an
Advanced High-performance Bus (AHB) slave. The work involved is of APB Protocol and its slave
Verification. The whole design is captured using VHDL, simulated with ModelSim and configured to a FPGA
target device belonging to the Virtex4 family using Xilin x.

I. INTRODUCTION an industry standard for ASIC design for portable

In the realm of processing, these elements applications. Creat ing and applying powerful,
perform different tasks in order to realize an overall portable and at the same time re-usable intellectual
solution. Consider a set-top box for television (TV) Property (IP), capable o f enhancing an ARM core is
sets as an example [1]. A set-top box must generate therefore of ut most importance to any ASIC design
inputs for a part icular television channel fro m the centre.
received digital satellite signal. The entire process
incorporates several phases. The first is to split the Descripti on Of Amba Ahb B us.
incoming digital signal into its component video and An AMBA AHB design may include one or
audio data streams. The next phase is to convert the more bus masters, typically a system would contain
video data stream into its actual television signal. at least the processor and the test interface . However,
Also, the audio data stream has to be changed into it would also be common for a Direct Memory
audio signal for the TV set. Besides, an additional job Access (DMA) or Dig ital Signal Processor (DSP) to
to look after will be to handle the user input for be included as bus masters. The external memory
changing the channel when the remote control will be interface, the Advanced Peripheral Bus (APB) Bridge
pressed. All these operations have to be completed and any internal memo ry are the most common AHB
not only simu ltaneously but within a certain time slaves. Any other peripheral in the system could also
frame. The cost of not accomplishing these within the be included as an AHB slave. However, lo w-
stipulated time frame or deadline will be manifested bandwidth peripherals typically reside on the APB.
in the form of b lank screen or audible noises. This is
obviously unacceptable and hence, it is necessary to
always deliver the data within real-t ime deadlines.
The needed computational elements here will be
either general-purpose or special-purpose processors
(such as signal processors). Nowadays, mult itudes of
these devices are integrated in the form of an SOC. A
processor needs to interact with other processors,
memo ries or input/output (I/O) devices to complete a
task. Currently, bus systems are used to interconnect
the intellectual property (IP) blocks.
Many SoCs comprise Application Specific
Integrated Circuits (ASICs) that are offered by Fig. 1 A typical AMBA architecture.
several companies. The Advanced RISC Machines
(ARM) microprocessor is very popular for SoC Before an AM BA AHB transfer can
solutions. Today it is fair to say that the ARM commence the bus master must be granted access to
Embedded Technology is universally recognized as the bus. This process is started by the master
www.ijera.co m DOI: 10.9790/ 9622-0701018790 87 | P a g e
Kommirisetti Bheema Raju. Int. Journal of Engineering Research and Application www.ijera.com
ISSN: 2248-9622, Vol. 7, Issue 1, (Part -1) January 2017, pp.87-90

asserting a request signal to the arbiter. Then the Table 1. List of APB signals
arbiter indicates when the master will be granted use
of the bus. A granted bus master starts an AMBA
AHB transfer by d riv ing the address and control
signals. These signals provide information on the
address, direction and width of the transfer, as well as
an indication if the transfer fo rms part of a burst. Two
different forms of burst transfers are allowed:
incrementing bursts, which do not wrap at address
boundaries; and wrapping bursts, which wrap at
particular address boundaries. A write data bus is
used to move data fro m the master to a slave, wh ile a
read data bus is used to move data fro m a slave to the
master.

Idle is the normal state of the APB. When a Transfer

is necessary the bus relocates into the Setup state,
where the suitable select signal, Pselx, is asserted.

Fig.2 An AMBA AHB design with three masters and

four slaves.

Apb Block Di agram:

The APB is the member of the AMBA 3
protocol family which imp lements a low cost
interface wh ich min imizes the power consumption Fig3: State diagram.
and reduces the interface comp lexity. Since APB has
unpipelined protocol. Therefore, it interfaces to the The bus only waits in the SETUP state for
low bandwidth peripherals that do not demand the one clock cycle and always moves to the ACCESS
high performance of the pipelined bus interface. All state on the next rising edge of the clock. ACCESS
the signal transitions are associated with the rising will enable signal, PENABLE, is asserted in the
edge of the clock which makes it simple to integrate ACCESS state. The write, write data signals, select,
APB peripherals into any design flow. APB can and address must remain stable during the transition
interface with the AMBA AHB-Lite and AMBA fro m the SETUP to ACCESS state. ACCESS state is
Advanced Extensible Interface (A XI). APB can also controls when to exit by the PREADY s ignal fro m
be used to access the programmab le control reg isters the slave.
of the peripheral devices. These are the conditions one is if PREADY
is held LOW by the slave then the peripheral bus
remains in the ACCESS state another is PREADY is
driven HIGH by the slave then the ACCESS state is
exited and the bus returns to the IDLE state if no
more transfers are required after that it will start the
same cycle.

Fig3: Interfacing of APB Master & Slave.

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Kommirisetti Bheema Raju. Int. Journal of Engineering Research and Application www.ijera.com
ISSN: 2248-9622, Vol. 7, Issue 1, (Part -1) January 2017, pp.87-90

Simulati on Results

Fig6: RTL Schematic d iagram o f APB Master Slave

Burst. Fig6: simu lation result for amba apb master slave
Write cycle burst.
At T1, a write transfer starts with PADDR,
PWDATA, PWRITE, and PSEL, being registered at II. CONCLUSION
the rising edge of PCLK. It is called the SETUP This paper gives an outline of the AMBA
cycle. At the next rising edge of the clock T2 it is bus architecture and explains the APB bus in detail.
called ACCESS cycle, PENA BLE, and PREADY, The design has taken care of balance between area
are registered. When asserted, PENABLE indicates overhead and speed. The read write operation is
starting of Access phase of the transfer. When accomplished with zero wait states from the external
asserted, PREA DY indicates that the slave can ROM and the write operation with zero states to the
complete the transfer at the next rising edge of external RAM. The APB bus is designed using the
PCLK. The PADDR, PWDATA, and control signals Verilog HDL according to the specification and is
all remain valid until the transfer co mp letes at T3, the verified using Xilin x.
end of the Access phase. The PENA BLE, is disabled
at the end of the transfer. The select signal PSEL is REFERENCES
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www.ijera.co m DOI: 10.9790/ 9622-0701018790 89 | P a g e

Kommirisetti Bheema Raju. Int. Journal of Engineering Research and Application www.ijera.com
ISSN: 2248-9622, Vol. 7, Issue 1, (Part -1) January 2017, pp.87-90

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Bala Krishna Konda is currently working

as an Asst. Prof. in the Department of ECE
in Eluru College of Engineering and
Technology. He completed his B.T ech in
ECE from Sri Vasavi Engineering College,
Tadepalligudem, Andhra Pradesh and
M.Tech from Sri Vasavi Engineering
College, Tadepalligudem, Andhra Pradesh.
He is interested in the field of VLSI.

Kommirisetti Bheema Raju has obtained

his Graduation at Akula Gopayya College
of Engineering, Tadepalligudem, Andhara
Pradesh and currently pursuing his Post
Graduation From Eluru College of
Engineering and T echnology, Eluru,
Andhra Pradesh.

www.ijera.co m DOI: 10.9790/ 9622-0701018790 90 | P a g e