5A, 28V Input, Step Down Swift™ DC/DC Converter With Eco-Mode™

0
10
20
30
40
50
60
70
80
90
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
E
f
f
i
c
i
e
n
c
y

-

%

Output Current - A C007
V
IN
= 12 V
V
IN
= 24 V
PH
VIN
GND
BOOT
VSENSE
COMP
SS
C
SS
D1
VIN EN
C
I
C
BOOT
L
O
C
O
Ren1
R
O2
C
1
C
2
R
3
Ren2
R
O1
TPS54531
V
OUT
T P S 5 4 5 3 1
www.ti.com SLVSBI5 MAY 2013
5 A , 2 8 V I N P U T , S T E P D O W N S W I F T D C / D C C O N V E R T E R W I T H E C O - mod e
C he ck for S ample s: T P S 5 4 5 3 1
1 F E A T U R E S D E S C R I P T I O N
The TPS54531 is a 28-V, 5-A non-synchronous buck
2 3 .5 V to 2 8 V I nput V oltage R ange
converter that integrates a low R
DS(on)
high side
A d justable O utput V oltage D own to 0.8 V
MOSFET. To increase efficiency at light loads, a
I nte grate d 8 0 m H igh S id e MO S F E T S upports
pulse skipping Eco-mode feature is automatically
up to 5 A C ontinuous O utput C urre nt activated. Furthermore, the 1 A shutdown supply
current allows the device to be used in battery
H igh E fficie ncy at Light Load s with a P ulse
powered applications. Current mode control with
S kipping E co- mod e
internal slope compensation simplifies the external
F ixe d 5 70kH z S witching F re que ncy
compensation calculations and reduces component
T ypical 1 A S hutd own Quie sce nt C urre nt count while allowing the use of ceramic output
capacitors. A resistor divider programs the hysteresis
A d justable S low S tart Limits I nrush C urre nts
of the input under-voltage lockout. An overvoltage
P rogrammable U V LO T hre shold
transient protection circuit limits voltage overshoots
O ve rvoltage T ransie nt P rote ction during startup and transient conditions. A cycle by
cycle current limit scheme, frequency fold back and
C ycle - by- C ycle C urre nt Limit, F re que ncy F old
thermal shutdown protect the device and the load in
Back and T he rmal S hutd own P rote ction
the event of an overload condition. The TPS54531 is
A vailable in E asy- to- U se T he rmally E nhance d
available in 8-pin SOIC PowerPAD
TM
package that
S O I C 8 P owe rP A D
T M
P ackage
have been internally optimized to improve thermal
performance.
A P P LI C A T I O N S
C onsume r A pplications such as S e t- T op
Boxe s, C P E E quipme nt, LC D D isplays,
P e riphe rals, and Batte ry C harge rs
I nd ustrial and C ar A ud io P owe r S upplie s
5 V , 1 2 V and 2 4 V D istribute d P owe r S yste ms
S I MP LI F I E D S C H E MA T I C E F F I C I E N C Y
T P S 5 4 5 3 1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Eco-mode, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
T P S 5 4 5 3 1
SLVSBI5 MAY 2013 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
D E S C R I P T I O N C O N T I N U E D
For additional design needs, see:
T P S 5 4 2 3 1 T P S 5 4 2 3 2 T P S 5 4 2 3 3 T P S 5 4 5 3 1 T P S 5 4 3 3 2
I
O
(Max) 2A 2A 2A 5A 3.5A
Input Voltage Range 3.5V - 28V 3.5V - 28V 3.5V - 28V 3.5V - 28V 3.5V - 28V
Switching Freq. (Typ) 570kHz 1000kHz 285kHz 570kHz 1000kHz
Switch Current Limit (Min) 2.3A 2.3A 2.3A 5.5A 4.2A
Pin/Package 8SOIC 8SOIC 8SOIC 8SO PowerPAD 8SO PowerPAD
O R D E R I N G I N F O R MA T I O N
(1 )
T
J
P A C KA GE S W I T C H I N G F R E QU E N C Y P A R T N U MBE R
(2 )
40C to 150C 8 pin SOIC PowerPAD 570 kHz TPS54531DDA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) The DDA package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54531DDAR). See applications
section of data sheet for layout information.
A BS O LU T E MA XI MU M R A T I N GS
(1 )
over operating free-air temperature range (unless otherwise noted)
V A LU E U N I T
VIN 0.3 to 30
EN 0.3 to 6
BOOT 38
Input Voltage V
VSENSE 0.3 to 3
COMP 0.3 to 3
SS 0.3 to 3
BOOT-PH 8
Output Voltage PH 0.6 to 30 V
PH (10 ns transient from ground to negative peak) 5
EN 100 A
BOOT 100 mA
Source Current
VSENSE 10 A
PH Current Limit A
VIN Current Limit A
Sink Current COMP 100
A
SS 200
Electrostatic Human body model (HBM) 2 kV
Discharge
Charged device model (CDM) 1 kV
Operating Junction Temperature 40 to 150 C
Storage Temperature 65 to 150 C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2 Submit Documentation Feedback Copyright 2013, Texas Instruments Incorporated
Product Folder Links: TPS54531
T P S 5 4 5 3 1
P A C KA GE D I S S I P A T I O N R A T I N GS
(1 ) (2 ) (3 )
T H E R MA L I MP E D A N C E P S E U D O T H E R MA L I MP E D A N C E
P A C KA GE
JU N C T I O N T O A MBI E N T JU N C T I O N T O T O P
SOIC8 PowerPAD 50C/W 5C/W
(1) Maximum power dissipation may be limited by overcurrent protection
(2) Power rating at a specific ambient temperature T
A
should be determined with a junction temperature of 150C. This is the point where
distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below
150C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more
information.
(3) Test board conditions:
(a) 2 inches x 1.5 inches, 2 layers, thickness: 0.062 inch
(b) 2-ounce copper traces located on the top and bottom of the PCB
(c) 6 thermal vias located under the device package
R E C O MME N D E D O P E R A T I N G C O N D I T I O N S
over operating free-air temperature range (unless otherwise noted)
MI N T YP MA X U N I T
Operating Input Voltage on (VIN pin) 3.5 28 V
Operating junction temperature, T
J
40 150 C
E LE C T R I C A L C H A R A C T E R I S T I C S
T
J
= 40C to 150C, VIN = 3.5V to 28V (unless otherwise noted)
D E S C R I P T I O N T E S T C O N D I T I O N S MI N T YP MA X U N I T
S U P P LY V O LT A GE (V I N P I N )
Internal undervoltage lockout threshold Rising and Falling 3.5 V
Shutdown supply current EN = 0V, VIN = 12V, 40C to 85C 1 4 A
Operating non switching supply current VSENSE = 0.85 V 110 190 A
E N A BLE A N D U V LO (E N P I N )
Enable threshold Rising and Falling 1.25 1.35 V
Input current Enable threshold 50 mV -1 A
Input current Enable threshold + 50 mV -4 A
V O LT A GE R E F E R E N C E
Voltage reference 0.772 0.8 0.828 V
H I GH - S I D E MO S F E T
BOOT-PH = 3 V, VIN = 3.5 V 115 200 m
On resistance
BOOT-PH = 6 V, VIN = 12 V 80 150
E R R O R A MP LI F I E R
Error amplifier transconductance (gm) 2 A < I
(COMP)
< 2 A, V
(COMP)
= 1 V 92 mhos
Error amplifier DC gain
(1)
VSENSE = 0.8 V 800 V/V
Error amplifier unity gain bandwidth
(1)
5 pF capacitance from COMP to GND pins 2.7 MHz
Error amplifier source/sink current V
(COMP)
= 1 V, 100 mV overdrive 7 A
Switch current to COMP transconductance
(1)
VIN = 12 V 20 A/V
S W I T C H I N G F R E QU E N C Y
Switching Frequency VIN = 12V, 25C 456 570 684 kHz
Minimum controllable on time VIN = 12V, 25C 105 130 ns
Maximum controllable duty ratio
(1)
BOOT-PH = 6 V 90% 93%
P U LS E S KI P P I N G E C O - MO D E
Pulse skipping Eco-mode switch current threshold 160 mA
C U R R E N T LI MI T
Current limit threshold VIN = 12 V 6.3 10.5 A
(1) Specified by design
Copyright 2013, Texas Instruments Incorporated Submit Documentation Feedback 3
1
2
3
4
5
6
7
8 BOOT
VIN
EN
SS
PH
GND
COMP
VSENSE
PowerPAD
(Pin 9)
TM
T P S 5 4 5 3 1
E LE C T R I C A L C H A R A C T E R I S T I C S (continue d )
T
J
= 40C to 150C, VIN = 3.5V to 28V (unless otherwise noted)
D E S C R I P T I O N T E S T C O N D I T I O N S MI N T YP MA X U N I T
T H E R MA L S H U T D O W N
Thermal Shutdown 165 C
S LO W S T A R T (S S P I N )
Charge current V
(SS)
= 0.4 V 2 A
D E V I C E I N F O R MA T I O N
P I N A S S I GN ME N T S
D D A P A C KA GE
(T O P V I E W )
P I N F U N C T I O N S
P I N D E S C R I P T I O N
N A ME N O .
BOOT 1 A 0.1 F bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor falls
below the minimum requirement, the high-side MOSFET is forced to switch off until the capacitor is
refreshed.
VIN 2 Input supply voltage, 3.5 V to 28 V.
EN 3 Enable pin. Pull below 1.25V to disable. Float to enable. Programming the input undervoltage lockout with
two resistors is recommended.
SS 4 Slow start pin. An external capacitor connected to this pin sets the output rise time.
VSENSE 5 Inverting node of the gm error amplifier.
COMP 6 Error amplifier output, and input to the PWM comparator. Connect frequency compensation components
to this pin.
GND 7 Ground.
PH 8 The source of the internal high-side power MOSFET.
PowerPAD 9 GND pin must be connected to the exposed pad for proper operation. This pin is only available in the
DDA package.
Error
Amplifier
R Q
S
Boot
Charge
Boot
UVLO
Current
Sense
Oscillator
Frequency
Shift
Gate
Drive
Logic
Slope
Compensation
PWM
Latch
PWM
Comparator
ECO-MODE
Minimum Clamp
Maximum
Clamp
Voltage
Reference
Discharge
Logic
VSENSE
COMP
PH
BOOT
VIN
GND
Thermal
Shutdown
EN
Enable
Comparator
Shutdown
Logic
Shutdown
Enable
Threshold
S
1.25 V
0.8 V
80 mW
165C
2.1V
SS
Shutdown
VSENSE
1 A m 3 A m
gm = 92 A/V
DC gain = 800 V/V
BW = 2.7 MHz
m
2 kW
2 A m
TPS54531
T P S 5 4 5 3 1
F U N C T I O N A L BLO C K D I A GR A M
I
-

S
S

C
h
a
r
g
e

C
u
r
r
e
n
t

-

A
S
S
T - Junction Temperature - C
J
2
2.1
50 25 0 25 50 75 100 125
1.9
150
V = 12 V
IN
5
6
7
8
9
10
11
12
3 8 13 18 23 28
C
u
r
r
e
n
t

L
i
m
i
t

T
h
r
e
s
h
o
l
d

(
A
)

Input Voltage (V)
T = 40C
T = 25C
T = 150C
C014
T
J

T
J

T
J

T
m
i
n
o
n

-

M
i
n
i
m
u
m

C
o
n
t
r
o
l
l
a
b
l
e

O
n
T
i
m
e

-

n
s
J
110
120
130
140
50 25 0 25 50 75 100 125
100
150
V = 12 V
IN
D
m
i
n

-

M
i
n
i
m
u
m

C
o
n
t
r
o
l
l
a
b
l
e

D
u
t
y

R
a
t
i
o

-

%
J
5.0
5.5
6.0
7.0
7.5
50 25 0 25 50 75 100 125
6.5
V = 12 V
IN
150
V
-

V
o
l
t
a
g
e

R
e
f
e
r
e
n
c
e

-

V
r
e
f
J
0.788
0.800
0.812
0.824
50 25 0 25 50 75 100 125
0.776
150
V = 12 V
IN
0.782
0.794
0.806
0.818
R
d
s
o
n

-

O
n

R
e
s
i
s
t
a
n
c
e

-

m
J
80
90
100
110
120
50 25 0 25 50 75 100 125
70
60
150
V = 12 V
IN
F
-

O
s
c
i
l
l
a
t
o
r

F
r
e
q
u
e
n
c
y

-

k
H
z
S
W
J
560
570
580
590
50 25 0 25 50 75 100 125
550
150
V = 12 V
IN
I
-

S
h
u
t
d
o
w
n

C
u
r
r
e
n
t

-

A
S
D
V - Input Voltage - V
IN
0
1
2
3
4
3 8 13 18 23 28
EN = 0V
T = 150C
J
T = 40C
J
T = 25C
J
T P S 5 4 5 3 1
C H A R A C T E R I ZA T I O N C U R V E S
O N R E S I S T A N C E S H U T D O W N QU I E S C E N T C U R R E N T S W I T C H I N G F R E QU E N C Y
vs vs vs
JU N C T I O N T E MP E R A T U R E I N P U T V O LT A GE JU N C T I O N T E MP E R A T U R E
F igure 1 . F igure 2 . F igure 3 .
MI N I MU M C O N T R O LLA BLE D U T Y
V O LT A GE R E F E R E N C E MI N I MU M C O N T R O LLA BLE O N T I ME R A T I O
vs vs vs
JU N C T I O N T E MP E R A T U R E JU N C T I O N T E MP E R A T U R E JU N C T I O N T E MP E R A T U R E
F igure 4 . F igure 5 . F igure 6.
S S C H A R GE C U R R E N T C U R R E N T LI MI T T H R E S H O LD
vs vs
JU N C T I O N T E MP E R A T U R E I N P U T V O LT A GE
F igure 7. F igure 8 .
T P S 5 4 5 3 1
O V E R V I E W
The TPS54531 is a 28-V, 5-A, step-down (buck) converter with an integrated high-side n-channel MOSFET. To
improve performance during line and load transients, the device implements a constant frequency, current mode
control which reduces output capacitance and simplifies external frequency compensation design. The
TPS54531 has a pre-set switching frequency of 570kHz.
The TPS54531 needs a minimum input voltage of 3.5V to operate normally. The EN pin has an internal pull-up
current source that can be used to adjust the input voltage under-voltage lockout (UVLO) with two external
resistors. In addition, the pull-up current provides a default condition when the EN pin is floating for the device to
operate. The operating current is 110 A typically when not switching and under no load. When the device is
disabled, the supply current is 1A typically.
The integrated 80 m high-side MOSFET allows for high efficiency power supply designs with continuous output
currents up to 5A.
The TPS54531 reduces the external component count by integrating the boot recharge diode. The bias voltage
for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pin. The boot
capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the voltage falls
below a preset threshold of 2.1V typically. The output voltage can be stepped down to as low as the reference
voltage.
By adding an external capacitor, the slow start time of the TPS54531 can be adjustable which enables flexible
output filter selection.
To improve the efficiency at light load conditions, the TPS54531 enters a special pulse skipping Eco-mode
TM
when the peak inductor current drops below 160mA typically.
The frequency foldback reduces the switching frequency during startup and over current conditions to help
control the inductor current. The thermal shut down gives the additional protection under fault conditions.
D E T A I LE D D E S C R I P T I O N
F I XE D F R E QU E N C Y P W M C O N T R O L
The TPS54531 uses a fixed frequency, peak current mode control. The internal switching frequency of the
TPS54531 is fixed at 570kHz.
E C O - MO D E
T M
The TPS54531 is designed to operate in pulse skipping Eco-mode
TM
at light load currents to boost light load
efficiency. When the peak inductor current is lower than 160 mA typically, the COMP pin voltage falls to 0.5 V
typically and the device enters Eco-mode
TM
. When the device is in Eco-mode
TM
, the COMP pin voltage is
clamped at 0.5V internally which prevents the high side integrated MOSFET from switching. The peak inductor
current must rise above 160mA for the COMP pin voltage to rise above 0.5V and exit Eco-mode
TM
. Since the
integrated current comparator catches the peak inductor current only, the average load current entering Eco-
mode
TM
varies with the applications and external output filters.
V O LT A GE R E F E R E N C E (V
re f
)
The voltage reference system produces a 2% initial accuracy voltage reference (3.5% over temperature) by
scaling the output of a temperature stable bandgap circuit. The typical voltage reference is designed at 0.8V.
BO O T S T R A P V O LT A GE (BO O T )
The TPS54531 has an integrated boot regulator and requires a 0.1 F ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R or X5R
grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve
drop out, the TPS54531 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is
greater than 2.1 V typically.
( )
( ) ( )
( )
SS ref
SS
SS
C nF V V
T ms =
I A
m
EN
START EN
V
Ren2 =
V - V
+ 1 A
Ren1
m
START STOP
V - V
Ren1 =
3 A m
EN
1.25 V
VIN
+
Ren1
Ren2
TPS54531
1 A m 3 A m
T P S 5 4 5 3 1
E N A BLE A N D A D JU S T A BLE I N P U T U N D E R - V O LT A GE LO C KO U T (V I N U V LO )
The EN pin has an internal pull-up current source that provides the default condition of the TPS54531 operating
when the EN pin floats.
The TPS54531 is disabled when the VIN pin voltage falls below internal VIN UVLO threshold. It is recommended
to use an external VIN UVLO to add at least 500 mV Hysteresis unless VIN is greater than (V
OUT
+ 2 V). To
adjust the VIN UVLO with Hysteresis, use the external circuitry connected to the EN pin as shown in Figure 9.
Once the EN pin voltage exceeds 1.25 V, an additional 3 A of hysteresis is added. Use Equation 1 and
Equation 2 to calculate the resistor values needed for the desired VIN UVLO threshold voltages. The V
START
is
the input start threshold voltage, the V
STOP
is the input stop threshold voltage and the V
EN
is the enable threshold
voltage of 1.25 V. The V
STOP
should always be greater than 3.5 V.
F igure 9. A d justable I nput U nd e rvoltage Lockout
(1)
(2)
The external start and stop voltages are approximate. Actual start and stop voltages may vary.
P R O GR A MMA BLE S LO W S T A R T U S I N G S S P I N
It is highly recommended to program the slow start time externally because no slow start time is implemented
internally. The TPS54531 effectively uses the lower voltage of the internal voltage reference or the SS pin
voltage as the power supplys reference voltage fed into the error amplifier and will regulate the output
accordingly. A capacitor (C
SS
) on the SS pin to ground implements a slow start time. The TPS54531 has an
internal pull-up current source of 2A that charges the external slow start capacitor. The equation for the slow
start time (10% to 90%) is shown in Equation 3 . The V
ref
is 0.8 V and the I
SS
current is 2 A.
(3)
The slow start time should be set between 1ms to 10 ms to ensure good start-up behavior. The slow start
capacitor should be no more than 27nF.
If during normal operation, the input voltage drops below the VIN UVLO threshold, or the EN pin is pulled below
1.25 V, or a thermal shutdown event occurs, the TPS54531 stops switching.
E R R O R A MP LI F I E R
The TPS54531 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier. The
transconductance of the error amplifier is 92 A/V during normal operation. Frequency compensation
components are connected between the COMP pin and ground.
T P S 5 4 5 3 1
S LO P E C O MP E N S A T I O N
In order to prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the
TPS54531 adds a built-in slope compensation which is a compensating ramp to the switch current signal.
C U R R E N T MO D E C O MP E N S A T I O N D E S I GN
The device is able to work with various types of output capacitors with appropriate compensation designs. For
designs using ceramic output capacitors, proper derating of ceramic output capacitance is recommended when
doing the stability analysis. This is because the actual ceramic capacitance drops considerably from the nominal
value when the applied voltage increases. Please refer to the Step by Step Design Procedure in the Application
Information section for the detailed guidelines.
O V E R C U R R E N T P R O T E C T I O N A N D F R E QU E N C Y S H I F T
The TPS54531 implements current mode control that uses the COMP pin voltage to turn off the high-side
MOSFET on a cycle by cycle basis. Every cycle the switch current and the COMP pin voltage are compared;
when the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off. During
overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high,
causing the switch current to increase. The COMP pin has a maximum clamp internally, which limit the output
current.
The TPS54531 provides robust protection during short circuits. There is potential for overcurrent runaway in the
output inductor during a short circuit at the output. The TPS54531 solves this issue by increasing the off time
during short circuit conditions by lowering the switching frequency. The switching frequency is divided by 8, 4, 2,
and 1 as the voltage ramps from 0 V to 0.8 V on VSENSE pin. The relationship between the switching frequency
and the VSENSE pin voltage is shown in Table 1.
T able 1 . S witching F re que ncy C ond itions
S W I T C H I N G F R E QU E N C Y V S E N S E P I N V O LT A GE
570 kHz VSENSE 0.6 V
570 kHz / 2 0.6 V > VSENSE 0.4 V
570 kHz / 4 0.4 V > VSENSE 0.2 V
570 kHz / 8 0.2 V > VSENSE
O V E R V O LT A GE T R A N S I E N T P R O T E C T I O N
The TPS54531 incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage
overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an
overvoltage comparator to compare the VSENSE pin voltage and internal thresholds. When the VSENSE pin
voltage goes above 109% V
ref
, the high-side MOSFET will be forced off. When the VSENSE pin voltage falls
below 107% V
ref
, the high-side MOSFET will be enabled again.
T H E R MA L S H U T D O W N
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 165C, the device reinitiates the power up sequence.
4.7 uH L1
BOOT
1
VIN
2
EN
3
SS
4
VSNS
5
COMP
6
GND
7
PH
8
PWR PAD 9
U1
TPS54531
4.7F
C1
4.7F
C2
0.01F
C3
0.1F
C4
47F
C8
47F
C9 C10
open
0.55V
D1
CDBC540-G
10.2K
R5
51.1
R4
1.96k
R6 130k
R1
665k
R2
2200pF
C6
22pF
C7
C11
open
37.4k
R3
0.01F
C5
VIN 8-28VOLTS
VOUT
VIN
VOUT 5V, 5A
T P S 5 4 5 3 1
A P P LI C A T I O N I N F O R MA T I O N
F igure 1 0. T ypical A pplication S che matic
S T E P BY S T E P D E S I GN P R O C E D U R E
The following design procedure can be used to select component values for the TPS54531. Alternately, the
WEBENCH software may be used to generate a complete design. The WEBENCH software uses an iterative
design procedure and accesses a comprehensive database of components when generating a design. This
section presents a simplified discussion of the design process.
To begin the design process a few parameters must be decided upon. The designer needs to know the following:
Input voltage range
Output voltage
Input ripple voltage
Output ripple voltage
Output current rating
Operating frequency
For this design example, use the following as the input parameters
T able 2 . D e sign P arame te rs
D E S I GN P A R A ME T E R E XA MP LE V A LU E
Input voltage range 8 V to 28V
Output voltage 5 V
Transient response, 2.5 A load step Vout = +/- 5 %
Input ripple voltage 400 mV
Output ripple voltage 30 mV
Output current rating 5 A
Operating Frequency 570 kHz
S W I T C H I N G F R E QU E N C Y
The switching frequency for the TPS54531 is fixed at 570 kHz.
2
OUT(MAX)
CIN
I
I =
( )
OUT(MAX)
IN OUT(MAX) MAX
BULK SW
I 0.25
V = + I ESR
C f
OUT REF
R5
V = V +1
R6

REF
OUT REF
R5 V
R6 =
V V
-
T P S 5 4 5 3 1
O U T P U T V O LT A GE S E T P O I N T
The output voltage of the TPS54531 is externally adjustable using a resistor divider network. In the application
circuit of Figure 10, this divider network is comprised of R5 and R6. The relationship of the output voltage to the
resistor divider is given by Equation 4 and Equation 5:
(4)
(5)
Choose R5 to be approximately 10.0 k. Slightly increasing or decreasing R5 can result in closer output voltage
matching when using standard value resistors. In this design, R5 = 10.2 k and R6 = 1.96 k, resulting in a 4.96
V output voltage. The 51.1 ohm resistor R4 is provided as a convenient place to break the control loop for
stability testing.
U nd e r V oltage Lockout S e t P oint
The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R1 and R2.
R1 is connected between VIN and the EN pin of the TPS54531 and R2 is connected between EN and GND .
The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or
brown outs when the input voltage is falling. For the example design, the minimum input voltage is 8 V, so the
start voltage threshold is set to 7 V with 2 V hysteresis. Equation 1 and Equation 2 can be used to calculate the
values for the upper and lower resistor values of R1 and R2.
I N P U T C A P A C I T O R S
The TPS54531 requires an input decoupling capacitor and depending on the application, a bulk input capacitor.
The typical recommended value for the decoupling capacitor is 10 F. A high-quality ceramic type X5R or X7R is
recommended. The voltage rating should be greater than the maximum input voltage. A smaller value may be
used as long as all other requirements are met; however 10 F has been shown to work well in a wide variety of
circuits. Additionally, some bulk capacitance may be needed, especially if the TPS54531 circuit is not located
within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated
to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple
voltage is acceptable. For this design two 4.7 F capacitors are used for the input decoupling capacitor. They are
X7R dielectric rated for 50 V. The equivalent series resistance (ESR) is approximately 2m, and the current
rating is 3 A. Additionally, a small 0.01 F capacitor is included for high frequency filtering.
This input ripple voltage can be approximated by Equation 6
(6)
Where I
OUT(MAX)
is the maximum load current, f
SW
is the switching frequency, C
BULK
is the bulk capacitor value
and ESR
MAX
is the maximum series resistance of the bulk capacitor.
The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be
approximated by Equation 7
(7)
In this case, the input ripple voltage would be 243 mV and the RMS ripple current would be 2.5 A. It is also
important to note that the actual input voltage ripple will be greatly affected by parasitics associated with the
layout and the output impedance of the voltage source. The actual input voltage ripple for this circuit is shown in
Design Parameters and is larger than the calculated value. This measured value is still below the specified input
limit of 300 mV. The maximum voltage across the input capacitors would be VIN max plus VIN/2. The chosen
bulk and bypass capacitors are each rated for 50 V and the ripple current capacity is greater than 3 A, both
providing ample margin. It is very important that the maximum ratings for voltage and current are not exceeded
under any circumstance.
2
f
D
>
D
Iout
Co
sw Vout
( ) OUT IN(MAX) OUT
L(PK) OUT(MAX)
IN(MAX) OUT SW
V V V
I = I +
1.6 V L F
-

( )
2
OUT IN(MAX) OUT
2
L(RMS) OUT(MAX)
IN(MAX) OUT SW
V V V
1
I = I +
12 V L F 0.8

-

( )
OUT IN(MAX) OUT
MIN
IN(MAX) IND OUT SW
V V V
L =
V K I F
-

T P S 5 4 5 3 1
O U T P U T F I LT E R C O MP O N E N T S
Two components need to be selected for the output filter, L
OUT
and C
OUT
. Since the TPS54531 is an externally
compensated device, a wide range of filter component types and values can be supported.
I nd uctor S e le ction
To calculate the minimum value of the output inductor, use Equation 8
(8)
K
IND
is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
In general, this value is at the discretion of the designer; however, the following guidelines may be used. For
designs using low ESR output capacitors such as ceramics, a value as high as K
IND
= 0.3 may be used. When
using higher ESR output capacitors, K
IND
= 0.2 yields better results.
For this design example, use K
IND
= 0.3 and the minimum inductor value is calculated to be 4.8 H. For this
design, a close standard value was chosen: 4.7 H.
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from Equation 9
(9)
and the peak inductor current can be determined with Equation 10
(10)
For this design, the RMS inductor current is 5.03 A and the peak inductor current is 5.96 A. The chosen inductor
is a Wurth 4.7 H. It has a saturation current rating of 19.0 A and an RMS current rating of 7.0 A, meeting these
requirements. Smaller or larger inductor values can be used depending on the amount of ripple current the
designer wishes to allow so long as the other design requirements are met. Larger value inductors will have
lower ac current and result in lower output voltage ripple, while smaller inductor values will increase ac current
and output voltage ripple. In general, inductor values for use with the TPS54531 are in the range of 1 H to
47H.
C apacitor S e le ction
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is also temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from
no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change
in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be
sized to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a
tolerable amount of drop in the output voltage. Equation 11 shows the minimum output capacitance necessary to
accomplish this.
(11)
p
Iout max
p mod =
2 Vout Cout
( )
12
OUT IN(MAX) OUT
COUT(RMS)
IN(MAX) OUT SW C
V V V
1
I =
V L F N

-

<
Voripple
Resr
Iripple
1 1
8 f
>
Co
Voripple
sw
Iripple
T P S 5 4 5 3 1
Where Iout is the change in output current, Fsw is the regulators switching frequency and Vout is the
allowable change in the output voltage. For this example, the transient load response is specified as a 5%
change in Vout for a load step of 2.5 A. For this example, Iout = 2.5 A and Vout = 0.05 x 5.0 = 0.250 V. Using
these numbers gives a minimum capacitance of 35 F. This value does not take the ESR of the output capacitor
into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in
this calculation.
Equation 12 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. Under this requirement
Equation 12, yields 14 F.
(12)
Equation 13 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 13 indicates the ESR should be less than 15.6 m. In this case, the ceramic caps ESR is
much smaller than 15.6 m.
(13)
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, two 47 F 10V X5R ceramic capacitor with 3 m of ESR are used. Capacitors
generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An
output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets
specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 14 can be used to calculate
the RMS ripple current the output capacitor needs to support. For this application, Equation 14 yields 554 mA.
(14)
C O MP E N S A T I O N C O MP O N E N T S
There are several possible methods to design closed loop compensation for dc/dc converters. For the ideal
current mode control, the design equations can be easily simplified. The power stage gain is constant at low
frequencies, and rolls off at -20 dB/decade above the modulator pole frequency. The power stage phase is 0
degrees at low frequencies and starts to fall one decade below the modulator pole frequency reaching a
minimum of -90 degrees one decade above the modulator pole frequency. The modulator pole is a simple pole
shown in Equation 15
(15)
For the TPS54531 most circuits will have relatively high amounts of slope compensation. As more slope
compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase
loss of the power stage will now approach -180 degrees, making compensation more difficult. The power stage
transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple
approximations. It is best to use Pspice to accurately model the power stage gain and phase so that a reliable
compensation circuit can be designed. Alternately, a direct measurement of the power stage characteristics can
be used. That is the technique used in this design procedure. For this design, L1 = 4.7 H. C8 and C9 are set to
47F each, and the ESR is 3 m. Now the power stage characteristics are shown in Figure 11.
CO
1
C7 =
2 R3 10 F p
CO
1
C6 =
F
2 R3
10
p
PWRSTG
G
20
REF
EA OUT
V 10
R3 =
gm V
-
-180
-120
-60
0
60
120
180
-60
-40
-20
0
20
40
60
10 100 1000 10000 100000 1000000
P
h
a
s
e
-
D
e
g
r
e
e
s
G
a
i
n

-
d
B
Frequency - Hz C011
Gain
Phase
Power Stage
Gain = 5.1 dB
@ 20 kHz
T P S 5 4 5 3 1
F igure 1 1 . P owe r S tage Gain and P hase C haracte ristics
For this design, the intended crossover frequency is 20 kHz. From the power stage gain and phase plots, the
gain at 20 kHz is 5.1 dB and the phase is about -100 degrees. For 60 degrees of phase margin, additional phase
boost from a feed forward capacitor in parallel with the upper resistor of the voltage set point divider is not
needed. R3 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at
crossover. The required value of R3 can be calculated from Equation 16.
(16)
To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 20 kHz.
The required value for C6 is given by Equation 17.
(17)
To maximize phase gain the high frequency pole is placed one decade above the crossover frequency of 20 kHz.
The pole can also be useful to offset the ESR of aluminum electrolytic output capacitors. The value for C7 can be
calculated from Equation 18.
(18)
For this design the calculated values for the compensation components are R3 = 37.4 k ,C6 = 2200 pF and C7
= 22 pF.
BO O T S T R A P C A P A C I T O R
Every TPS54531 design requires a bootstrap capacitor, C4. The bootstrap capacitor must be 0.1 F. The
bootstrap capacitor is located between the PH pins and BOOT pin. The bootstrap capacitor should be a high-
quality ceramic type with X7R or X5R grade dielectric for temperature stability.
C A T C H D I O D E
The TPS54531 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum
voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the
peak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note
that the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode
parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is
capable of dissipating the power losses. For this design, a CDBC540-G is chosen, with a reverse voltage of 40
V, forward current of 5 A, and a forward voltage drop of 0.55 V.
( ) ( )
( )
Omin IN max O min DS(on) min D O min L D
V = 0.089 V I R + V I R V - - -
( ) ( )
( )
Omax IN min O max DS(on) max D O max L D
V = 0.91 V I R + V I R V - - -
T P S 5 4 5 3 1
S LO W S T A R T C A P A C I T O R
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate.
This is also used if the output capacitance is very large and would require large amounts of current to quickly
charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may
make the TPS54531 reach the current limit or excessive current draw from the input power supply may
cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The
soft start capacitor value can be calculated using Equation 3. For the example circuit, the soft start time is
not too critical since the output capacitor value is 2 x 47 F which does not require much current to charge to
5 V. The example circuit has the soft start time set to an arbitrary value of 4 ms which requires a 10 nF
capacitor. In TPS54531, Iss is 2 A and Vref is 0.8V.
O U T P U T V O LT A GE LI MI T A T I O N S
Due to the internal design of the TPS54531, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 91%
and is given by Equation 19:
(19)
Where:
V
IN min
= Minimum input voltage
I
O max
= Maximum load current
V
D
= Catch diode forward voltage
R
L
= Output inductor series resistance
The equation assumes maximum on resistance for the internal high-side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 130 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by Equation 20:
(20)
Where:
V
IN max
= Maximum input voltage
I
O min
= Minimum load current
V
D
= Catch diode forward voltage
R
L
= Output inductor series resistance
This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device should be carefully
checked to assure proper functionality.
P O W E R D I S S I P A T I O N E S T I MA T E
The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working in the discontinuous conduction mode (DCM) or
pulse skipping Eco-mode
TM
.
The device power dissipation includes:
1) Conduction loss: Pcon = Iout
2
x R
DS(on)
x V
OUT
/V
IN
2) Switching loss: Psw = 0.5 x 10
-9
x V
IN
2
x I
OUT
x Fsw
3) Gate charge loss: Pgc = 22.8 x 10
-9
x Fsw
4) Quiescent current loss: Pq = 0.11 x 10
-3
x V
IN
Where:
I
OUT
is the output current (A).
T P S 5 4 5 3 1
R
DS(on)
is the on-resistance of the high-side MOSFET ().
VOUT is the output voltage (V).
VIN is the input voltage (V).
Fsw is the switching frequency (Hz).
So
Ptot = Pcon + Psw + Pgc + Pq
For given T
A
, T
J
= T
A
+ Rth x Ptot.
For given T
JMAX
= 150C, T
AMAX
= T
JMAX
Rth x Ptot.
Where:
Ptot is the total device power dissipation (W).
T
A
is the ambient temperature (C).
T
J
is the junction temperature (C) .
Rth is the thermal resistance of the package (C/W).
T
JMAX
is maximum junction temperature (C).
T
AMAX
is maximum ambient temperature (C).
P C B LA YO U T
The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor. Care should be taken to
minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch
diode. The typical recommended bypass capacitance is 10-F ceramic with a X5R or X7R dielectric and the
optimum placement is closest to the VIN pins and the source of the anode of the catch diode. See Figure 12 for
a PCB layout example. The GND pin should be tied to the PCB ground plane at the pin of the IC. The PH pin
should be routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the
switching node, the catch diode and output inductor should be located very close to the PH pins, and the area of
the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the
exposed thermal pad should be soldered directly to the top side ground area under the IC. Use thermal vias to
connect the top side ground area to an internal or bottom layer ground plane. The total copper area must provide
adequate heat dissipation. Additional vias adjacent to the device can b used to improve heat transfer to the
infernal or bottom layer ground plane . The additional external components can be placed approximately as
shown. It may be possible to obtain acceptable performance with alternate layout schemes, however this layout
has been shown to produce good results and is intended as a guideline.
BOOT
VSENSE
PH
VIN GND
EN
Vout
PH
Vin
TOPSIDE
GROUND
AREA
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
BOOT
CAPACITOR
INPUT
BYPASS
CAPACITOR
CATCH
DIODE
Signal VIA
Route BOOT CAPACITOR
trace on other layer to provide
wide path for topside ground
RESISTOR
DIVIDER
Feedback Trace
COMP
SS
COMPENSATION
NETWORK
Thermal VIA
SLOW START
CAPACITOR
UVLO
RESISTOR
DIVIDER
EXPOSED
THERMAL PAD
T P S 5 4 5 3 1
F igure 1 2 . T P S 5 4 5 3 1 D D A Board Layout
E LE C T R O MA GN E T I C I N T E R F E R E N C E (E MI ) C O N S I D E R A T I O N S
As EMI becomes a rising concern in more and more applications, the internal design of the TPS54531 takes
measures to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage
ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used
to lower the parasitics effects.
To achieve the best EMI performance, external component selection and board layout are equally important.
Follow the Step by Step Design Procedure above to prevent potential EMI issues.
A P P LI C A T I O N C U R V E S
spacer
V = 200 mV/div (ac coupled)
OUT
I = 1 A/div
OUT
Time = 200 s/div
1.25 A to 3.75 A load step,
slew rate = 500 mA / sec
-180
-120
-60
0
60
120
180
-60
-40
-20
0
20
40
60
10 100 1000 10000 100000 1000000
P
h
a
s
e

-

D
e
g
r
e
e
s

G
a
i
n

-

d
B

Frequency - Hz C011
Gain
Phase
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
L
o
a
d

R
e
g
u
l
a
t
i
o
n

-

%

V
IN
= 24 V
V
IN
= 12 V
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.1
8 10 12 14 16 18 20 22 24 26 28
L
i
n
e

R
e
g
u
l
a
t
i
o
n

-

%

Input Voltage - V C010
I
OUT
= 2.5 A
0
10
20
30
40
50
60
70
80
90
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
E
f
f
i
c
i
e
n
c
y

-

%

V
IN
= 12 V
V
IN
= 24 V
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
E
f
f
i
c
i
e
n
c
y

-

%

V
IN
= 12 V
V
IN
= 24 V
T P S 5 4 5 3 1
F igure 1 3 . T P S 5 4 5 3 1 D E fficie ncy F igure 1 4 . T P S 5 4 5 3 1 D Low C urre nt E fficie ncy
spacer
spacer
F igure 1 5 . T P S 5 4 5 3 1 D Load R e gulation F igure 1 6. T P S 5 4 5 3 1 D Line R e gulation
spacer
spacer
F igure 1 7. T P S 5 4 5 3 1 T ransie nt R e sponse F igure 1 8 . T P S 5 4 5 3 1 Loop R e sponse
spacer
spacer
V = 2 V/div
OUT
Time = 2 ms/div
EN = 2 V/div
V = 10 V/div
IN
SS = 2 V/div
V = 2 V/div
OUT
Time = 5 ms/div
EN = 2 V/div
V = 10 V/div
IN
SS = 2 V/div
IN
Time = 1 s/div
PH = 5 V/div
V = 2 V/div
OUT
Time = 2 ms/div
EN = 2 V/div
V = 10 V/div
IN
SS = 2 V/div
OUT
Time = 1 s/div
PH = 5 V/div
OUT
Time = 500 s/div
PH = 5 V/div
T P S 5 4 5 3 1
F igure 1 9. T P S 5 4 5 3 1 F ull Load O utput R ipple F igure 2 0. T P S 5 4 5 3 1 E co- mod e O utput R ipple
spacer
spacer
F igure 2 1 . T P S 5 4 5 3 1 F ull Load I nput R ipple F igure 2 2 . T P S 5 4 5 3 1 S tart U p R e lative to V I N
spacer
spacer
F igure 2 3 . T P S 5 4 5 3 1 S tart- up R e lative to E nable F igure 2 4 . T P S 5 4 5 3 1 S hut D own R e lative to V I N
spacer
V = 2 V/div
OUT
Time = 5 ms/div
EN = 2 V/div
V = 10 V/div
IN
SS = 2 V/div
T P S 5 4 5 3 1
F igure 2 5 . T P S 5 4 5 3 1 S hut D own R e lative to E N
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jun-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (C) Device Marking
(4/5)
Samples
TPS54531DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 54531
TPS54531DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 54531

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TPS54531DDAR SO
Power
PAD
DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54531DDAR SO PowerPAD DDA 8 2500 364.0 364.0 27.0
PACKAGE MATERIALS INFORMATION
Pack Materials-Page 2
IMPORTANT NOTICE
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