Fpga DSP Whitepaper
Fpga DSP Whitepaper
Fpga DSP Whitepaper
and Altera
, VxWorks
, QNX
, and Linux
It is well understood by designers of DSP applications that the complexity of developing
DSP systems involves both the accurate modeling of the of the signal processing flow
and the precise control/synchronization of the data flow. Designers must accurately
control the data flow between device interfaces, processing blocks, sub-DSP systems, and
memories interlaced throughout the signal processing flow.
MathWorks
is well known for tools dedicated to handling both of these critical aspects
of the DSP application development process. MATLAB aids in the mathematical
modeling of the signal processing flow in a high level interactive environment.
SIMULINK
and Xilinx System Generator for DSP make it possible for engineers to take
advantage of the best modeling tools to simulate DSP performance and facilitate transfer
of logic into the FPGA. Figure 7 outlines the process.
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Figure 7: Flowchart for development of FPGA-based DSP applications.
DSP Modeling Envionment
Xilinx DSP Design Tool & IP
Xilinx FPGA Implementation Tool
Algorithm Developer
System Engineer
Hardware Engineer
IP Library
IP Library
IP Library
RTL
top-level
Simulink
Block
RTL top-level RTL top-level
RTL
Module
MATLAB
Accel Ware
Xilinx AccelDSP
Synthesis Tool
Simulink
Xilinx DSP
Blockset
Core
Generator
ModelSim/ISim
Xilinx System
Generator For DSP
Spartan-3A
DSP
Virtex-5
SXT
Virtex-4
SX
ISE 9.1i
Source: Adapted from Xilinx Inc. XtremeDSP Solutions 2007
DSP application development is a complex process in many aspects. Understanding and
modeling the application is the first major hurdle. Traditionally, DSP engineers would
use readily available programming tools such as C, C++, Fortran, Visual Basic
and the
like to develop and test algorithms to be deployed in the DSP application. Although not
insurmountable, the use of productivity tools such as MATLAB make this task much
easier and provide a development environment inclusive of:
a high level modeling language
access to add-on toolboxes with extensions for signal processing, communications,
and wavelet processing
code management facilities
interactive tools to explore and aid in the DSP application design
commonly used mathematical functions (linear algebra, statistics, Fourier analysis,
filtering, etc.)
optimization tools
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graphical visualization and publishing tools to aid in the modeling process and
recording of data
ability to integrate new or existing algorithms from applications written in C, C++,
Fortran, Excel
, etc.
The high level MATLAB language supports a wide and increasing range of vector and
matrix operations, as well as common arithmetic operators, flow control, data structures,
data typing, object-oriented programming, and debug features. The MATLAB Editor,
aside from providing a simple to use editor, includes breakpoint and logic single stepping
as debug aids. Other performance optimization tools include the M-Lint Code Checker
which will analyze the MATLAB code and recommend changes for performance
enhancement and maintainability. The MATLAB Profiler enables the developer to
measure and rationalize the time spent in the various lines of coded application.
At this point, the DSP engineer will have suitably modularized the DSP application and
completed testing for accuracy and performance, but only at the algorithmic modeling
level. MathWorks SIMULINK can now be used to combine the algorithmic modeling
level product developed with MATLAB into an interactive graphical environment. This
environment enables the DSP engineer to design, implement, simulate and test the DSP
application within the context of required control, synchronization, and parameterization
on a processor based platform.
To accomplish the above tasks, SIMULINK provides extensive pre-defined block
libraries, graphical editing and management tools for assembling and managing intuitive
block diagrams, model segmenting tools, simulation modes of Normal / Accelerator /
Rapid Accelerator, and a number of model analysis and diagnostic tools. Models are built
by combining drag & drop blocks and connecting them with lines that determine the
relationships between the blocks. The blocks are segmented into design components then
simulated and tested either individually or collectively. Additionally, the design
components can be saved and used across projects.
After the model is built in SIMULINK, it becomes possible to simulate the timing,
synchronization, and algorithmic processing afforded by the DSP design. Diagnostic
tools are available to compute system dynamics, evaluate timing and synchronization,
and diagnose the overall behavior of the model all from a graphical user interface.
Simulation is configurable to execute in normal or accelerated timeframes. Information
can be collected on performance bottlenecks and documentation added. Using the HDL
Coder, it is possible to generate FPGA target VHDL and test benches.
Once the DSP engineer has successfully demonstrated that algorithmically and
structurally the model meets application requirements, it is necessary to implement the
MATLAB models in the appropriate form factor for execution on the Xilinx FPGA
platform of choice. The Xilinx System Generator for DSP is a SIMULINK-like graphical
environment designed to create DSP designs in FPGAs. Access to a pre-defined block of
Xilinx cores facilitates interfacing with Xilinx FPGAs.
The Xilinx AccelDSP synthesis tool enables DSP algorithm designers to incorporate their
MATLAB M-files to perform stimulus definition and generation, algorithm evaluation,
and results post-processing in the context of the Xilinx FPGA. Remember, SIMULINK
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enables the DSP engineer to design, implement, simulate and test the DSP application
within the context of required control, synchronization, and parameterization on a
processor based platformnot on the FPGA itself. The Xilinx AccelDSP synthesis tool
creates, based upon the MATLAB floating point models, System Generator IP blocks in
cycle-accurate fixed point. The fixed point design can be simulated with options for
saturation and rounding applied. Precision growth through arithmetic operations is
automatically propagated through the design under user-controlled override options until
the designer determines the suitability of the performance against the accuracy.
Fine Tuning the FPGA Design
At this point, the AccelDSP synthesis tool is used to generate the Register Transfer Level
(RTL) for the target FPGA device and to apply optimizations as might be applicable and
permissible by boundary conditions (performance requirements, memory cells available,
block RAM availability, etc.). Some of the optimizations and their effect are summarized
in Table 3:
Table 3: DSP optimizations and their effects
DSP Synthesis Directive Effect on Generated Hardware
Rolling / unrolling of loops Improves input sampling rate by reducing throughput
Expansion of vector and matrix
additions and multiplications
Improves input sampling rate by reducing throughput
RAM / ROM memory mapping of arrays Improves FPGA utilization by mapping arrays into
dedicated Xilinx Block RAM resources
Pipeline insertion Improves input sampling rate by improving clock
frequency performance
Shift register mapping Improves FPGA utilization by mapping shift register
logic into SRL16s
Utilizing the synthesis directives produces a very hardware-specific design composition
RTL. The AccelDSP synthesis tool will permit evaluation of the entire algorithm based
upon the RTL and perform boundary optimizations when possible. Additionally, it will
report throughput and latency which are necessary for the DSP designer to judge
performance of the design prior to generating a cycle-accurate System Generator model.
Final Simulation and RTL Code Generation
Once the RTL is successfully generated and optimized to perform at required
specifications, the AccelDSP synthesis tool can be used to generate a System Generator
IP block which will support both simulation activities and RTL code generation. This
new IP block appears in the SIMULINK library browser. To incorporate the new
AccelDSP IP block into a model, it is only necessary to select the IP Block and drag it
into the destination model. To compile your design for installation on the Xilinx FPGA
target, use System Generator for DSP to generate the appropriate bit stream file(s) which
can then be converted into .mcs files for PROM load using the Xilinx iMPACT utility.
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Summary and Conclusions
Using the well-known mathematical modeling of MATLAB together with the
conversions and optimizations available through the Xilinx AccelDSP synthesis tool and
Xilinx System Generator for DSP, it is possible to enjoy the benefits of desktop
simulation, test and the final Xilinx FPGA hardware-specific targeting of DSP
applications. Acromag provides a large family of Xilinx-based PMC FPGA products
which augment these capabilities. A variety of models offer many performance levels
with a range of available logic cells and DSP Blocks, memory capacities, and many I/O
options. The combination of tools from MathWorks and Xilinx, plus the flexibility and
breadth of the Xilinx FPGA line available on many PMC modules, provides a
tremendous development time and cost advantage to DSP engineers.
For more information, contact:
J oe Primeau P: 248-624-1541 x1823 E: jprimeau@acromag.com
Rowland S. Demko P: 248-624-1541 x1825 E: rdemko@acromag.com
Ronald Moquin P: 248-624-1541 x1824 E: rmoquin@acromag.com
Acromag is a registered trademark of Acromag, Inc. Xilinx and Virtex are registered trademarks of Xilinx, Inc. XtremeDSP and
AccelDSP are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.