WEPM 7-3

A 25MHz 20dB Variable Gain Amplifier

Khayrollah Hadidi and Haruo Kobayashi

Electronics laboratory, Yokogawa Electric Co.
Tokyo 180, Japan

Abstract -- This paper describes a new special purpose [3] except that the gain control part still includes parasi-
Variable Gain Amplifier (VGA) using a standard 1.2 pm tic bipolar devices. The main drawback of the above
digital CMOS process. The new architecture allows the structures, from our application view point, is large
gain to be vaned over a wide range (more than 20dB), power consumption, although they can handle large sig-
while temperature induced drift in gain is kept very nals. For our application, low distortion, low gain-
small over a wide temperature range (5' C to 70' C ) . bandwidth dependency, low gain drift with temperature,
With the new VGA architecture, bandwidth is almost wide bandwidth, and low power consumption were very
independent of gain. Despite low power consumption important goals. Thus, another approach was taken to
(19mW) the circuit has a large bandwidth (27MHz), a meet all these requirements.
high maximum gain (14). and shows low THD (better
than -55dB) over its fill frequency range. The circuit Circuit Design
does not use any capacitor for gain adjustment, thus it is
very compact (0.28 mm x 0.25 mm) and has a large input Gain Adjustment Element
impedance (transistor gate). A simplied schematic that contains element of gain
variation is shown in Fig. 1. It is essentially a folded
Introduction cascode op-amp with current feedback (using a

Variable gain amplifiers (VGA) or programmable

gain amplifiers (PGA), are an important component of
any signal conditioning system. And are used in a wide
range of applications. Often a VGA is used in an AGC bias2
loop, and the gain is adjusted to produce a constant out-
put level. Many VGAs or PGAs which have been fabri-
cated using CMOS processes have been reported, [l],
PI, ~31,[41.
PGAs in [l] and [2] used capacitor and resistor
arrays in the feedback path of an op-amp loop. Gain is
adjusted by adjusting the amount of feedback. There is a
trade off of the bandwidth for gain. This dependence of
bandwidth on gain is very undesirable for our applica-
tion. Furthermore, the bandwidth in both cases was very
limited, although, 2pm and 3pm processes were used.
The reason is that for such architecturers as in [l] and
[2], the PGA bandwidth must be at least an order of
magnitude less than that of op-amp for satisfactory
operation.
[3] on the other hand, although fabricated in a
CMOS process, uses parasitic bipolar devices to create a I

Gilbert cell as the main mechanism for varying the gain GND
of the VGA. And [41 is essentially a CMOS version of Fig. 1 An amplifier with gain adjustment element

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 differential pair). If the open loop gain of the op-amp is V V
dd dd
large and MO is off, then the maximum gain will be
7

where gm,in and g m f are transconductances of the input

and feedback differential pairs. When the transistor MO R
in Fig. 1 turns on, the more it conducts, the more
current signal coming from input differential pair is
bypassed before being directed to the output nodes. This
reduces effective transconductance of the input
1
differential pair. It is expected that the overall gain of
the circuit will also reduce. However, turning on transis- GND GND
tor M O also affects the effective transconductance of the Fig. 2 Gain adjustment model Fig. 4 Circuit for Vgain
feedback differential pair. Thus to a large degree, the
gain does not decrease when Vgninis increased. Further-
more, the open loop output impedance changes due to Vdd
parallel combination of rds of MIO and M and M 2. See
the half circuit model in Fig. 2. Thus, with both poles
changed the bandwidth will change and stabhty can be
degraded. The cure for the above problems is the final
circuit shown in Fig. 3 which contains the common-
mode feedback circuit as well. The extra cascode dev-
ices M, and M, isolate the input differential pair and
the gain adjusting device from the feedback pair. Thus
only the effective transconductance of the input
differential pair varies with Vgain. And the feedback
loop, and the circuit's poles are not affected by gain
variation. Bandwidth remains constant over the whole
gain range due to fixed position of the poles. Moreover,
unlike the schemes that vary feedback loop-gain for
overall gain adjustment, the loop-gain is fixed in the
new VGA. The important result is that harmonic distor-
tion is not degraded as gain increases. The division of
the current signal from the input differential pair,
between MO and M, in Fig.3, depends on the gds of M O
and g, of M,. However, as the temperature changes,
the gds and g, fail to track each other. The reason is
that g , is proportional to p whde gds is proportional to
$. The circuit of Fig. 4, with proper choice of the
resistor and the MOS resistor sizes, causes the current
splitting elements, g, and g d s , track each other closely GND
over a wide temperature range.
Fig. 3 Complete schematic of VGA
Common -Mode Feedback
The common-mode feedback is a conventional one devices in saturation whde the reference bias current is
using a differential pair to average the differential out- vaned over a wide range. By adjusting reference bias
puts. current one can compensate for process variations or
increase the overall gain-bandwidth (GBW) product.
Bias Circuit Note that bias circuit contains feedback loops which
were simulated for stability.
The bias circuit for the VGA is shown in Fig. 5 . It
conveniently generates all bias voltages. It maintains all

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 Vdd (dB)
25.00

20.00

15.00
)
10.00
[
bias
5.00

0.00
bias4
--c

%
-5.00

-10.00

-15.00

-20.00
1
bias3 -25.00

leM5 le& le47 le48 le-

1 Fig. 6 Frequency response at different gain levels (*)

GND
Fig. 5 Bias circuit for VGA

Simulation Results
rER=Rl
24.90

24.80 I I I I

24.70
The V G A circuit has been extensively simulated.
Fig. 6 shows the frequency response at different gain 24.60
levels. It shows that the -3dB bandwidth is not affected 24.50
by gain variations. This is a very rare feature.
Bandwidth of most existing architectures, including those 24.40
of some of the references here, is sensitive to gain varia-
24.30
tions. Furthermore, they show peaking in frequency
responge. Peaking very often happens in multistage 24.20
amplifiers, because of parasitic zeros that move with
variation of gain. Small amount of peaking, although 24.10
acceptable in certain applications, must be avoided in 24.00
many other applications. This was an important reason
for adopting the new architecture. Figures 7 and 8 show
the frequency response (at a fixed low and a fixed high (Hz)
gain) for different temperatures. It is achieved due to the Fig. 7 Full gain vs. frequency at 5,25,40,55,70° C
fact that devices which determine the gain are of the Conclusions
same type, and partly by the circuit of Fig. 4. Figure 9
shows the total harmonic distortion (THD) variation A special purpose VGA was described. Its new
versus gain. method of adjusting gain allows special features which
are difficult to achieve using other methods. A feature of
the new architecture is that the gain adjusting element
affects only the transconductance of the input differential
pair, without changing the bias current. The bandwidth
is fairly independent of the gain, and gain is fairly

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 independent of the temperature (especially at high gains). (dB)
The power consumption is very low, and the bandwidth 1 .00
is very large. The power consumption of the circuit can
be reduced and the input range can be increased if 0.90
NMOS devices are used. The reason for using PMOS
0.80
devices was to enable the VGA to handle signals down
to ground level. The GBW product of the amplifier 0.70
amounts to 380MHz.
0.60

References 0.50

0.40
[l] C.-C. Shih, K.-K. Lam, K.-L. Lee, and R. W.
Schalk, “A CMOS Analog Front End for a 0.30
9600BPS Facsimile Modem,” in ISSCC Dig. Tech.
Papers, 1987, vol. 30, pp. 300-301. 0.20

[2] J. N. Babanezhad, R. Gregorian, “A Programmable 0.10

Gain /Loss Circuit,” IEEE J. Solid-state Circuits,
vol. SC-22, pp. 1082-1089, Dec. 1987. 0.00

[3] T.-W. Pan and A. A. Abidi, “A 50-dB Variable le45 le46 le47 le48 le49
Gain Amplifier Using Parasitic Bipolar Transistors (Hd
in CMOS,” IEEE J. Solid-state Circuits, vol. 24, pp. Fig. 8 Low gain vs. frequency at 5 , 25, 40, 55, 70’ C
951-961, Dec. 1987.
[4] R. Gomez and A. A. Abidi, A 50-MHz Variable
Gain Amplifier for Magnetic Data Storage Systems,“
IEEE J. Solid-state Circuits, vol. 27, pp. 935-939,
Dec. 1992.

0.00 1.00 2.00 3.00 4.00 5.00

volt
Fig. 9 THD vs. Vgainat maximum output swhg

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