Pioneer Cdj-1000mk3 SM
Pioneer Cdj-1000mk3 SM
Pioneer Cdj-1000mk3 SM
CDJ-1000MK3
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~ 1
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=
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#16G 15G 14G
FL Display
Upper Panel
Jog Dial Display
FL Display
Jog Dial
Display
CDJ-1000MK3
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4. Mode for checking the operation of the player simple substance
This mode consists of "Player operation mode" and "Test operation mode."
<Player oparation mode>
Basic operation of the servo, such as setup, play, pause, and track search, is carried out.
Moreover, measurement of an error rate can also be performed.
<Test opalation mode>
Servo operation is finely controllable gradually.
* It becomes player operation mode and shifts to test operation mode by the key input in the beginning.
* The command treated here is for mainly testing a mechanism and a servo system, and is not for DJ functions, such as scan
and tempo.
Player operation mode: ON
Player operation mode: CANCEL
POWER OFF
Player operation mode
TEST MODE
POWER ON
HOT CUE
A
TIME
MODE
MASTER
TEMPO
AUTO
CUE
/
Flashes 100 points of MEMORY and CUE.
Test operation mode
All Servo Off
MASTER TEMPO
LED ON
MASTER
TEMPO
MASTER TEMPO
LED OFF
Function Button of the Main Unit
Play(trace) / Pause PLAY/PAUSE
Track Search F/R TRACK SEARCH /4
Error Rate Count CUE
Eject EJECT
Mode Change MASTER TEMPO
Player oparation mode
Function Button of the Main Unit
Servo All Off TIME
Slider Move Fwd SEARCH
Slider Move Rev SEARCH 1
Step Command FOLDER SEARCH |/\
Mode Change MASTER TEMPO
Test oparation mode
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Commands in Player Operation mode
Play (trace)/Pause
If the unit is in Stop mode when this command is issued, the unit is set up, the PLAY/PAUSE button lights, then playback
starts. If the unit is in Playback mode, it enters Pause mode. If in Pause mode, it releases Pause mode then restarts playback.
When a CD is played, the progress of signal trace and track number are indicated on the FL display.
Note: In this mode, auto setup will not be performed even if a disc is loaded. Playback does not mean audio playback but
tracing of the signal surface of a disc. In playback, tracing is performed at 4000 rpm CAV.
Track Search F/R
For a CD, the displayed track is searched in the forward or reverse direction, then the unit will pause.
Note: When a CD-ROM (MP3) is used, track search cannot be performed.
Error Rate Count
For a CD, the error rate is measured for about 20 seconds from the current playback/pause position, then the result is
displayed on the FL display. Normally, you would search the track for which you wish to measure the error rate, pause the
unit, then press the CUE button. The result of measurement will be displayed, for example, as "3.56E-4 OK."
If the error rate is 3.00E-3 or less, that CD is judged okay. If it is greater than 3.00E-3, the CD is considered defective.
The parameter is derived from the results of measurements with control discs at the factory.
This function must not be used for judgment of failure of a product during servicing.
Eject
To eject a disc.
Mode Change (to shift to Test Operation mode)
When the MASTER TEMPO button is pressed during normal player operation, the MASTER TEMPO LED lights. Playback is
stopped, and the unit shifts to Test Operation mode, described below. "All Servo Off" is displayed on the FL display.
Commands in Test Operation mode
Servo operations can be controlled step by step. Care must be taken when using a command in Test Operation mode,
because a wrong command may damage the player.
Servo All Off
When the TIME button is pressed during Servo ON, all the servos are shut off.
"All Servo Off" is displayed on the FL display while the TIME button is held pressed. If it is held pressed for less than 1 second,
the indication will remain displayed for 1 second.
Slider Move Fwd
Each time the SEARCH FWD button is pressed, the slider moves about 1.8 mm outward.
"Slider Move Fwd" is displayed on the FL display while the SEARCH FWD button is held pressed. If it is held pressed for less
than 1 second, the indication will remain displayed for 1 second.
Slider Move Rev
Each time the SEARCH REV button is pressed, the slider moves about 1.8 mm inward.
"Slider Move Rev" is displayed on the FL display while the SEARCH REV button is held pressed. If it is held pressed for less
than 1 second, the indication will remain displayed for 1 second.
Step command
A series of operations for startup will be performed step by step.
Each time the FOLDER SEARCH FWD button is pressed, the step is advanced. Each time the FOLDER SEARCH REV button
is pressed, the step is reversed. Each step and its operation is shown in the table below:
CDJ-1000MK3
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Mode Change (termination of Test Operation mode)
When the MASTER TEMPO button is pressed during Test Operation mode, the MASTER TEMPO LED goes dark, the servo
is stopped, then the unit shifts to Player Operation mode, described above.
Operation Step FL Display
STEP0: Servo All Off All Servo Off
STEP1: Laser diode on STEP1 LD
STEP2: Disc presence judgment STEP2 D.SENSE
STEP3: Spindle on (2000rpm) STEP3 SPDL
STEP4: Disc search STEP4 D.SRCH
STEP5: Focus serve on STEP5 FCS
STEP6: Focus position coarse adjustment STEP6 F.POS
STEP7: Tracking balance adjustment STEP7 T.BAL
STEP8: Tracking servo on STEP8 TRK
STEP9: Focus position adjustment STEP9 F.POS
STEP10: Focus gain adjustment STEP10 F.GAIN
STEP11: Tracking gain adjustment STEP11 T.GAIN
STEP12: Address lead start STEP12 READ
FOLDER SEARCH FWD button : step up
FOLDER SEARCH REV button : step down
"All Servo Off" is displayed for about 1 second. The indications for steps 1 to 12 are displayed on the FL display until the next step is
entered.
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7.1.2 HOW TO UPGRADE THE SOFTWARE OF THE MICROCOMPUTER
REC MODE RELOOP/EXIT
NO - D l SC
POWER ON
CDJ-1000MK3
Version up disc
Scrolling of [Download-Main]
(during downloading)
FL Display
POWER
Success
POWER OFF
POWER
Note:
Do NOT turn off the power after the upgrade disc is loaded till it is automatically ejected. If you do, the unit may not operate
properly afterward.
Eject a disc automatically even if updating fails.
CDJ-1000MK3
Automatically ejected (Note)
Automatically
ejected (Note)
FL Display
DOWN L OAD
Failure
FL Display
ERR OR
Repeat from
the beginning.
FL Display
COMP L E T E
REC MODE RELOOP/EXIT
Release
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7.1.3 SEQUENCE
Player section
Power on
MAIN CPU CPU for the Operation section
Canceling reset of SODC
(IC603), Pin 45 "H"
Initial setting
Reading data, etc.
Initialization of
loading mechanism
Power on
Canceling reset of CPU
(IC101), Pin 193 "H"
Device check
Canceling reset of
peripheral devices
Long press processing
of the key In the power ON
DVD
CD
Distinction
between
DVD/CD
Eject
CD playback process
/MP3 playback
Program transfer from
FLASH to SDRAM
Program transfer to the
FPGA (IC301)
Program transfer to the
DSP (IC401, IC402)
Initial setting for the CPU
Communications with the
Operation section start.
Input of statuses of keys,
output of display data
Communications with the
ATAPI system start.
Checking result of
peripheral devices
Initialization of the SDRAM
Power on
Canceling reset of the
CPU (IC1002), Pin 12
Initial setting for the CPU
"POWER ON" is indicated
on the FL display.
Long press processing
of the key In the power ON
After a disc is loaded, loading
and startup processes begin.
After a disc is loaded, loading
and startup processes begin.
A disc can be loaded
before communication
between the main CPU
and the player section
starts.
Data and clock output
from Pins 164 and 165
of the CPU (IC101).
When data transfer to
the FPGA is finished,
FPGA_DONE (Pin 71)
becomes high.
Once communication
with the main CPU is
established, the
"POWER ON"
indication disappears.
If the result of the check
is NG, error E70** is
generated.
If a disc is loaded,
the playback process
starts.
Power On Sequence
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Focus search
After the CD/CD-RW is judged according
to the disc reflectivity, FE, TE, AS, and
RFENV amplification gains are switched.
Canceling offset for FE, TE,
AS, RFENV, LNSC, and JIT
Focus on
Coarse adjustment of
focus position
Offset adjustment of the
tracking actuator
Tracking balance adjustment
Adjustment of tracking-error
amplitude
Off-track threshold
adjustment
Measuring eccentricity
Tracking on
Accurate adjustment of
focus position
Start of acquiring addresses
Focus gain adjustment
Tracking gain adjustment
Lens-error gain adjustment
Learning focus-error
attenuation
Detection of the 8-cm adaptor
Searching for 0m01s time
point
Spindle starts rotating
at 4000 rpm.
Lighted the CD laser
Reading
lead-in data: If the total
duration of data areas in the
TOC is less than 30
minutes
No
Yes
Disc installation
Carriage shifted to the
focus position
Canceling offset for FE, TE,
AS, RFENV, LNSC, and JIT
Focus search,
detection of disc presence,
measuring Focus Drive voltage
turn out the CD laser
Lighted the CD laser
Spindle starts rotating
at 2,000 rpm.
Disc present
Unloading
No disc present
Sequence of Starting Up the Drive
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7.1.4 DISASSEMBLY
PCB Location
SW POWER SUPPLY Assy M MJCB Assy F MFLB Assy G
SDCB Assy E
MAIN Assy A
SLDB Assy H
SLMB Assy
Slot-in Mecha. G11 Assy
Traverse Mecha. Assy-S
B
INSW Assy D
SPCN
Assy
C
JOGB Assy L KSWB Assy K
JFLB Assy J RSWB Assy I
Bottom view
Bottom view
Note 1: Do NOT look directly into the pickup lens. The laser beam may cause eye injury.
Note 2: Even if the unit shown in the photos and illustrations in this manual may differ from your product, the procedures
described here are common.
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1 Remove the seven screws.
2 Remove the bottom plate.
Bottom plate
MAIN Assy
3 Remove the four screws.
4 Stand the MAIN Assy.
5 Stand the MAIN Assy.
6 Disconnect the flexible cable: (CN401).
Set the MAIN Assy in the upright position, by engaging
it at the two hooks.
7
Diagnosis of MAIN Assy
Bottom view
Bottom view
Bottom view
Bottom view
1
3 3
3 3
1 1
1 1
1
1
2
4
MAIN Assy
MAIN Assy
Bottom view
5
Diagnosis
Diagnosis
6
7
7
MAIN Assy
-1
-2
Note:
If diagnosis of the SD card block is not required, the
diagnostic procedures can be performed with the MAIN
Assy kept in the upright position. Continue to Steps 5
through 7.
CDJ-1000MK3
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Disassembly
1 Remove the one screw.
2 Remove the five screws.
Control Panel Section 1 Slot-in Mecha. Section 2
1
Rear view
Bottom view
2
2
2
2 2
1 Remove the control panel section.
(Refet to "Control panel section".)
2 Remove the seven screws.
3 Remove the bottom plate.
Bottom plate
MAIN Assy
4 Remove the four screws.
5 Stand the MAIN Assy.
Bottom view
Bottom view
Bottom view
2
4 4
4 4
2 2
2 2
2
2
3
5
3 Remove the control panel section.
Control panel section
3
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12 Disconnect the two connectors.
13 Disconnect the three flexible cables.
7
8
Disconnect the flexible cable (CN401).
Bottom view
Bottom view
Bottom view
13 13 13
12
12
MAIN Assy
CN605
CN603
CN601 CN602 CN604
7
8
8
6
MAIN Assy
-1
-2
9
10
9
Shield Case
9 Remove the two screws.
10 Remove the shield case.
6 Stand the MAIN Assy.
C
D
11 Short-circuit two points of C and D soldering.
Note: After replacement, connect the flexible cable,
then remove the soldered joint (open).
Set the MAIN Assy in the upright position, by engaging it
at the two hooks.
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14 Remove the earth lead unit by removing the one screw.
15 Remove the four DM screws.
Earth lead unit
16 Remove the four float spring G5s.
17 Remove the slot-in mecha. section.
Float spring G5
Damper
14
16
17
15
Slot-in mecha. section
15 15
15
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5 Remove the three float screws.
6 Remove the traverse mecha. Assy-S.
6
Traverse mecha. Assy-S
Pickup lens
5
5 5
1 Remove the three screws.
2 Remove the mecha. plate.
3 Unhook the four hooks.
4 Remove the slot-in mecha. G11 Assy.
Slot-in mecha. G11 Assy
Traverse Mecha. Assy-S 3
2
3
1
1
1
Mecha. plate
3
3
3
4
Caution:
Be careful not to lost earth spring.
Before shipment, be sure to clean the pickup lens,
using the following cleaning materials:
Cleaning liquid : GEM1004
Cleaning paper : GED-008
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5 Remove the two screws.
6 Remove the JOG A and JOG Bs.
7 Remove the three screws.
8 Remove the SW ring.
JOG A JOG B
SW ring SW spring 25
6
8
5
7
7
7
5
1 Remove the adjust knob.
2 Disconnect the flexible cable.
3 Remove the five screws.
4 Remove the JOG section.
JOG Section 4
Adjust knob
JOG section
MFLB Assy
1
2
4
Bottom view
CN1001
3 3
3
3
3
Caution:
Be careful not to lost SW spring 25.
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Align.
Joint gear 1
Joint gear 1
JOG holder 1000
JOG holder 1000
Projection
Align the projection of JOG holder 1000 ( ) with the
arrow head ( ) on joint gear 1.
Forced eject pin
Forced eject pin
Positioning hole
Slit
Positioning hole
Gear stopper
Cam plate
Slit
Note: When reassembling the JOG ADJ. mechanism,
be sure to perform positioning, as shown below:
Note: When mounting joint gears 2, engage the gears,
being careful not to move joint gear 1.
Mount the joint gear 1. 1
2
Mount the cam plate on place it so that the slit of the cam
plate aligns with the gear stopper.
3
Turn the cam plate clockwise until the slit aligns with the
positioning hole.
4
Insert the forced eject pin through the positioning hole to
immobilize the cam plate.
5
4
Mount the joint gear 3. 6
Mount the two joint gears 2. 7
Cam plate
Forced eject pin Cam plate
Cam plate
Joint gear 1
Joint gear 2
Joint gear 3
Positioning of the JOG ADJ. mechanism
1
2
3
6
7
5
5
4
-2
7 -1
Notes on Replacement
CDJ-1000MK3
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Secure the gear plate, using the four screws.
Mount the gear plate. 8
9
Remove the forced eject pin. 10
Mount the cam plate. 11
Install the gear spring 200. 12
Mount the adjust plate. 13
Secure the adjust plate, using one screw. 14
Gear plate
Gear spring 200
Cam plate
Adjust plate
To decrease
the load
To increase
the load
+1
0
-1
-2
-3
+2
Default value "0"
Note:
For details on adjustment, see "Load
Check mode for the JOG Dial."
8
9
10
13
11
12
14
9
9
9
Forced eject pin
Notes on replacing the Sheet SW
Rib
Sheet SW
Sheet SW
JOG holder 1000
SW cushion HH48/2 SW cushion HH48/2 Engraved arrow
Notes:
1. Be careful not to warp the sheet SW.
2. Remove any dirt on the JOG holder to which the sheet SW
is to be adhered. If some adhesive for the old sheet SW
remains on the JOG holder, completely remove it with a cloth
moistened with alcohol.
3. Do NOT place the sheet SW so that it is mounted on the
rib of JOG holder 1000.
4. When adhering the sheet SW, be careful not to trap air
bubbles in it. If air bubbles are formed, remove the sheet SW
and adhere a new sheet SW.
Do NOT reuse the removed sheet SW.
5. When making a connection, be sure to first release the lock
of the connector then securely relock the connector after
making the connection.
Adhere the cushions to the right and left of the engraved
arrows () (12 positions in total) on the sheet SW.
Notes on Replacement
Place to adhere the Sheet SW
Place to adhere the SW cushions HH48/2
CDJ-1000MK3
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7.2 PARTS
7.2.1 IC
HD6417709SF133B-D, XC3S50-4TQG144C, MN103S71F, PEG237B-K
No. Pin Name Signal Name I/O Pin Function
1 MD1 SHMD1 I Clock mode setting (pullup with 3.3V)
2 MD2 SHMD2 I Clock mode setting (pullup with 3.3V)
3 Vcc-RTC V+1R8 Power supply for RTC
4 XTAL2 N.C. Not used
5 EXTAL2 Not used (connect to 1.8V power)
6 Vss-RTC GND Ground for RTC
7 NMI Not used
8 IREQ0 TI BSREQ I TI DSP Input data request ( edge)
9 IREQ1 TI PCMREQ I TI DSP Output data request ( edge)
10 IREQ2 Not used
11 IREQ3 Not used
12 IREQ4 DIS_XCS I Receiving completion interrupt of FL microcomputer data ( edge)
13 D31 D31 For debugging
14 D30 D30 For debugging
15 D29 D29 For debugging
16 D28 D28 For debugging
17 D27 D27 For debugging
18 D26 D26 For debugging
19 VssQ GND Ground
20 D25 D25 For debugging
21 VccQ V+3R3 Power supply for I/O (3.3V)
22 D24 D24 For debugging
23 D23 D23 For debugging
24 D22 D22 For debugging
25 D21 D21 For debugging
26 D20 D20 For debugging
27 Vss GND Ground
28 D19 D19 For debugging
29 Vcc V+1R8 Power supply for core (1.8V)
30 D18 D18 Connect with the servo DSP (Not used, pull down)
31 D17 D17 Connect with the servo DSP (Not used, pull down)
32 D16 D16 Connect with the servo DSP (Not used, pull down)
33 VssQ GND Ground
34 D15 D15 I/O Data bus
35 VccQ V+3R3 Power supply for I/O (3.3V)
36 D14 D14 I/O Data bus
37 D13 D13 I/O Data bus
38 D12 D12 I/O Data bus
39 D11 D11 I/O Data bus
40 D10 D10 I/O Data bus
41 D9 D9 I/O Data bus
42 D8 D8 I/O Data bus
43 D7 D7 I/O Data bus
44 D6 D6 I/O Data bus
45 VssQ GND Ground
HD6417709SF133B-D (MAIN ASSY : IC101)
The information shown in the list is basic information and may not correspond exactly to that shown in the schematic diagrams.
List of IC
CPU
Pin Function
CDJ-1000MK3
100
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No. Pin Name Signal Name I/O Pin Function
46 D5 D5 I/O Data bus
47 VccQ V+3R3 Power supply for I/O (3.3V)
48 D4 D4 I/O Data bus
49 D3 D3 I/O Data bus
50 D2 D2 I/O Data bus
51 D1 D1 I/O Data bus
52 D0 D0 I/O Data bus
53 A0 A0 O Address bus
54 A1 A1 O Address bus
55 A2 A2 O Address bus
56 A3 A3 O Address bus
57 VssQ GND Ground
58 A4 A4 O Address bus
59 VccQ V+3R3 Power supply for I/O (3.3V)
60 A5 A5 O Address bus
61 A6 A6 O Address bus
62 A7 A7 O Address bus
63 A8 A8 O Address bus
64 A9 A9 O Address bus
65 A10 A10 O Address bus
66 A11 A11 O Address bus
67 A12 A12 O Address bus
68 A13 A13 O Address bus
69 VssQ GND Ground
70 A14 A14 O Address bus
71 VccQ V+3R3 Power supply for I/O (3.3V)
72 A15 A15 O Address bus
73 A16 A16 O Address bus
74 A17 A17 O Address bus
75 A18 A18 O Address bus
76 A19 A19 O Address bus
77 A20 A20 O Address bus
78 A21 A21 O Address bus
79 Vss GND Ground
80 A22 N.C. Not used
81 Vcc V+1R8 Power supply for core (1.8V)
82 A23 N.C. Not used
83 VssQ GND Ground
84 A24 N.C. Not used
85 VccQ V+3R3 Power supply for I/O (3.3V)
86 A25 N.C.
Not used
87 BS XBS O Bus cycle start signal
88 RD XRD O Read strobe
89 WE0 XWE0 O Write strobe
90 WE1 XWE1 O Write strobe
91 WE2 N.C. Not used
92 WE3 N.C. Not used
93 RD/WR RDWR O Read/write
94 AUDSYNC XAUSYC For development
95 VssQ GND Ground
CDJ-1000MK3
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No. Pin Name Signal Name I/O Pin Function
96 CS0 XCS0 O Area 0 chip select
97 VccQ V+3R3 Power supply for I/O (3.3V)
98 CS2 XCS2 O Area 2 chip select
99 CS3 XCS3 O Area 3 chip select
100 CS4 XCS4 O Area 4 chip select
101 CS5 XCS5 O Area 5 chip select
102 CS6 XCS6 O Area 6 chip select
103 CE2A N.C. Not used
104 CE2B N.C. Not used
105 CKE CKE O CK enable (SDRAM)
106 RAS3L XRAS3L O RAS3L (SDRAM)
107 RAS2L N.C. Not used
108 CASLL XCASLL O CASL (SDRAM)
109 VssQ GND GND
110 CASLH MOT_RST O Reset output of Motorola DSP (reset with H)
111 VccQ V+3R3 Power supply for I/O (3.3V)
112 CASHL TI_RST O Reset output for TI DSP (reset with H)
113 CASHH N.C. Not used
114 DACK0 XDACK0 Not used (connect to FPGA)
115 DACK1 XDACK1 Not used (connect to FPGA)
116 CAS2L N.C. Not used
117 CAS2H N.C. Not used
118 RAS3U DAXLAT O DAC latch signal
119 RAS2U MUTE O Audio output stage mute (H: Mute on)
120 TDO TDO For development
121 BACK N.C. Not used
122 BREQ I Bus request (Not used, pullup with 3.3V)
123 WAIT XWAIT I Hardware wait request (FPGA)
124 RESETM I Manual reset (Not used, pullup with 3.3V)
125 PTH FPGA_DONE I DONE signal for FPGA configuration
126 IOIS RY/XBY I Connect to flash ROM
127 ASEMD0 ASEMD0 For development
128 ASEBRKAK XASKAK For development
129 PTG FPGA_XINIT I INIT signal for FPGA configuration
130 AUDATA3 AUDATA3 For development
131 AUDATA2 AUDATA2 For development
132 Vss GND GND
133 AUDATA1 AUDATA1 For development
134 Vcc V+1R8 Power supply for core (1.8V)
135 AUDATA0 AUDATA0 For development
136 TRST XTRST For development
137 TMS TMS For development
138 TDI TDI For development
139 TCK TCK For development
140 PINT11 Not used
141 PINT10 Not used
142 PINT9 UPDATE For development
143 PINT8 MOT EMPTY I Motorola FIFO empty signal input (High with EMPTY)
144 MDO SHMD0 I Clock mode setting (pull up with 3.3V)
145 Vcc-PLL1 V+1R8 Power supply for PLL1
CDJ-1000MK3
102
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B
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No. Pin Name Signal Name I/O Pin Function
146 CAP1 External capacitor pin for PLL1
147 Vss-PLL1 GND Ground for PLL1
148 Vss-PLL2 GND Ground for PLL2
149 CAP2 N.C. External capacitor pin for PLL2 (Not used)
150 Vcc-PLL2 V+1R8 Power supply for PLL2
151 AUDCK AUDCK For development
152 Vss GND Ground
153 Vss GND Ground
154 Vcc V+1R8 Power supply for core (1.8V)
155 XTAL N.C. Not used
156 EXTAL GND Connect to ground
157 STATUS0 TI PCMACK O TI DSP output data acknowledge
158 STATUS1 TI BSACK O TI DSP input data acknowledge
159 TCLK FPGA_XPRG O PRG signal for FPGA configuration
160 IREQOUT N.C. Not used
161 VssQ GND Ground
162 CKIO SH_66M I Clock input (65.975MHz)
163 VccQ V+3R3 Power supply for I/O (3.3V)
164 TxDO CONFDAT/DASSO O FPGA configuration/serial data output for DAC
165 SCKO
CONFIG_CLK/DASCK
O FPGA configuration/serial clock output for DAC
166 TxD1 N.C. Not used
167 SCK1 N.C. Not used
168 TxD2 TXD2 O TXD signal for production
169 SCK2 N.C. Not used
170 RTS2 N.C. Not used
171 RxDO Not used
172 RxD1 Not used
173 Vss GND Ground
174 RxD2 RxD2 I RXD signal for production
175 Vcc V+1R8 Power supply for core (1.8V)
176 CTS2 CTS2 I Not used
177 MCS7 CONT0 O Control signal output
178 MCS6 DMA RST O FPGA reset output (reset with H)
179 MCS5 CONT1 I Control signal input
180 MCS4 CONT2 I Control signal input
181 VssQ GND Ground
182 WACKUP CARD RST O TE4300 reset output (reset with H)
183 VccQ V+3R3 Power supply for I/O (3.3V)
184 RESETOUT GSL RST O ATA reset output (reset with H)
185 MCS3 MCS3 Not used
186 MCS2 CARD XINT I TE4300 interrupt input
187 MCS1 ATAIRQ I FPGA interrupt input
188 MCS0 MCS0 Not used
189 DRAK0 N.C. Not used
190 DRAK1 N.C. Not used
191 DREQ0 XDREQ0 I DMA request 0 (FPGA)
192 DREQ1 XDREQ1 Not used (connect to FPGA)
193 RESETTP RSTCPU I Reset input
194 CA CA I Chip active (pull up with 3.3V)
195 MD3 SHMD3 I Clock mode setting (pull down)
CDJ-1000MK3
103
5 6 7 8
5 6 7 8
C
D
F
A
B
E
No. Pin Name Signal Name I/O Pin Function
196 MD4 SHMD4 I Clock mode setting (pull up with 3.3V)
197 MD5 SHMD5 I Clock mode setting (pull down)
198 AVss GND Ground
199 AN0 Not used
200 AN1 Not used
201 AN2 Not used
202 AN3 Not used
203 AN4 Not used
204 AN5 Not used
205 AVcc V+3R3 Analog power supply (3.3V)
206 AN6 Not used
207 AN7 Not used
208 AVss GND Ground
CDJ-1000MK3
104
1 2 3 4
1 2 3 4
C
D
F
A
B
E
No. Pin Name Signal Name I/O Pin Function
1 I/O DCI N.C. Not used
2 I/O DCI TI_XCS O DSP (IC401) chip select signal
3 VCCO V+3R3 Power supply for I/O
4 IO/VREF TI_XHDS1 O DSP (IC401) data strobe signal
5 I/O DMA_XRST I FPGA reset input
6 I/O ATADREQ I ATADMA request signal
7 I/O ATAWR O ATA write signal
8 I/O ATARD O ATA read signal
9 GND GND Ground
10 I/O ATARDY I ATA ready signal
11 I/O ATADACK O ATADMA acknowledge signal
12 I/O ATAA1 O ATA address bus
13 I/O ATAA0 O ATA address bus
14 I/O ATAA2 O ATA address bus
15 I/O ATACS0 O ATA chip select 0
16 GND GND Ground
17 I/O ATACS1 O ATA chip select 1
18 IO/VREF ATA15 I/O ATA data bus
19 VCCO V+3R3 Power supply for I/O
20 IO/VREF ATA0 I/O ATA data bus
21 I/O ATA14 I/O ATA data bus
22 GND GND Ground
23 I/O ATA1 I/O ATA data bus
24 IO/VREF ATA13 I/O ATA data bus
25 I/O ATA2 I/O ATA data bus
26 I/O ATA12 I/O ATA data bus
27 I/O ATA3 I/O ATA data bus
28 I/O ATA11 I/O ATA data bus
29 GND GND Ground
30 I/O ATA4 I/O ATA data bus
31 I/O ATA10 I/O ATA data bus
32 I/O ATA5 I/O ATA data bus
33 I/O ATA9 I/O ATA data bus
34 VCCO V+3R3 Power supply for I/O
35 I/O DCI ATA6 I/O ATA data bus
36 I/O DCI ATA8 I/O ATA data bus
37 M1 V+2R5FPGA I Configuration mode setting (connect to 2.5V)
38 M0 V+2R5FPGA I Configuration mode setting (connect to 2.5V)
39 M2 V+2R5FPGA I Configuration mode setting (connect to 2.5V)
40 I/O DUAL ATA7 I/O ATA data bus
41 I/O DUAL DIS_DIN O FL microcomputer (IC1002) data output
42 GND GND Ground
43 VCCO V+3R3 Power supply for I/O
44 IO/VREF DIS_XCS I FL microcomputer (IC1002) chip select input
XC3S50-4TQG144C (MAIN ASSY : IC301)
FPGA (Field Programmable Gate Array)
Pin Function
CDJ-1000MK3
105
5 6 7 8
5 6 7 8
C
D
F
A
B
E
No. Pin Name Signal Name I/O Pin Function
45 GND GND Ground
46 I/O DUAL DIS_DOUT I FL microcomputer (IC1002) data input
47 I/O DUAL DIS_SCLK I FL microcomputer (IC1002) clock input
48 VCCAUX V+2R5FPGA Auxiliary power
49 VCCINT V+1R2FPGA Internal core power supply
50 I/O DUAL SUB_CODE I Subcode input
51 I/O DUAL M_DATR2 O DSP (IC402) audio data R2 output
52 IO/GCLK2 M_DATR1 O DSP (IC402) audio data R1 output
53 IO/GCLK3 M_DATL2 O DSP (IC402) audio data L2 output
54 VCCO V+3R3 Power supply for I/O
55 IO/GCLK0 M_DATL1 O DSP (IC402) audio data L1 output
56 IO/GCLK1 FPGA_66M I System clock input
57 IO/DOUT/BUSY N.C. Not used
58 IO/INIT FPGA_XINIT I/O INIT signal for FPGA configuration
59 I/O DUAL M_DBCLK O DSP (IC402) audio data clock output
60 I/O DUAL M_BCLK O DSP (IC402) audio data clock output
61 VCCINT V+1R2FPGA Internal core power supply
62 VCCAUX V+2R5FPGA Auxiliary power
63 I/O DUAL M_REQ I DSP (IC402) request signal
64 GND GND Ground
65 IO/DIN/D0 CONFDAT I Data input for FPGA configuration
66 VCCO V+3R3 Power supply for I/O
67 GND GND Ground
68 I/O DCI M_XWE O DSP (IC402) write signal
69 I/O DCI M_XRD O DSP (IC402) read signal
70 IO/VREF M_XCS O DSP (IC402) chip select signal
71 DONE FPGA_DONE O DONE signal for FPGA configuration
72 CCLK CONFIG_CLK I Clock input for FPGA configuration
73 I/O DCI M_VALID O DSP (IC402) audio data valid signal
74 I/O DCI XWE0 I CPU write signal
75 VCCO V+3R3 Power supply for I/O
76 I/O RDWR I CPU read/write signal
77 I/O XRD I/O CPU data bus
78 I/O D0 I/O CPU data bus
79 I/O D1 I/O CPU data bus
80 I/O D2 I/O CPU data bus
81 GND GND Ground
82 I/O D3 I/O CPU data bus
83 I/O D4 I/O CPU data bus
84 IO/VREF D5 I/O CPU data bus
85 I/O D6 I/O CPU data bus
86 I/O D7 I/O CPU data bus
87 I/O XWE1 I CPU write signal
88 GND GND Ground
89 I/O D8 I/O CPU data bus
90 IO/VREF D9 I/O CPU data bus
91 VCCO V+3R3 Power supply for I/O
92 IO/VREF D10 I/O CPU data bus
93 I/O D11 I/O CPU data bus
94 GND GND Ground
CDJ-1000MK3
106
1 2 3 4
1 2 3 4
C
D
F
A
B
E
No. Pin Name Signal Name I/O Pin Function
95 I/O D12 I/O CPU data bus
96 I/O D13 I/O CPU data bus
97 I/O D14 I/O CPU data bus
98 IO/VREF D15 I/O CPU data bus
99 I/O A1 I CPU address bus
100 I/O A2 I CPU address bus
101 GND GND Ground
102 I/O A3 I CPU address bus
103 I/O A4 I CPU address bus
104 I/O A5 I CPU address bus
105 I/O A6 I CPU address bus
106 VCCO V+3R3 Power supply for I/O
107 I/O DCI A7 I CPU address bus
108 I/O DCI A8 I CPU address bus
109 TDO N.C. Not used
110 TCK N.C. Not used
111 TMS N.C. Not used
112 I/O A11 I CPU address bus
113 I/O A10 I CPU address bus
114 GND GND Ground
115 VCCO V+3R3 Power supply for I/O
116 I/O A9 I CPU address bus
117 GND GND Ground
118 I/O N.C. Not used
119 I/O CARD_XRD O TE4300 (IC403) read signal
120 VCCAUX V+2R5FPGA Auxiliary power
121 VCCINT V+1R2FPGA Internal core power supply
122 I/O CARD_XCS O TE4300 (IC403) chip select signal
123 IO/VREF CARD_XWR O TE4300 (IC403) write signal
124 IO/GCLK4 XBS I CPU bus cycle signal
125 IO/GCLK5 N.C. Not used
126 VCCO V+3R3 Power supply for I/O
127 IO/GCLK6 XCS2 I CPU area 2 chip select signal
128 IO/GCLK7 XCS4 I CPU area 4 chip select signal
129 IO/VREF XCS5 I CPU area 5 chip select signal
130 I/O XCS6 I CPU area 6 chip select signal
131 I/O XDACK0 Not used (connect to CPU)
132 I/O XDACK1 Not used (connect to CPU)
133 VCCINT V+1R2FPGA Internal core power supply
134 VCCAUX V+2R5FPGA Auxiliary power
135 I/O XWAIT O CPU wait signal
136 GND GND Ground
137 I/O XDREQ0 O CPUDMA request output 0
138 VCCO V+3R3 Power supply for I/O
139 GND GND Ground
140 I/O DCI XDREQ1 Not used (connect to CPU)
141 I/O DCI TI_HRDY I DSP (IC401) data ready signal
142 HSWAP_EN V+2R5FPGA I Bus state setting in configuration (pull down)
143 PROG_B FPGA_XPRG I PRG signal for FPGA configuration
144 TDI N.C. I Not used
CDJ-1000MK3
107
5 6 7 8
5 6 7 8
C
D
F
A
B
E
No. Mark Pin Name I/O Pin Function
1 P2 XDMUTE1 O Mute control of driver IC
2 P3 XDMUTE2 O Mute control of driver IC
3 P4/EXCNT0 ILMUSK I Connect to VSS
4 VDD3 VDD3 Power supply (VD3V)
5 VSS VSS GNDD
6 P5/EXCNT1 INSIDE I Servo mecha inside SW input (L: ON)
7 P6/NSPCCS SPGAIN O SPDL motor current switching control (at inversion brakes: H)
8 P7/FADR17 FADR17/NSPCCS O Address output to FLASH ROM
9 P8/FADR18 FADR18 O NC
10 FADR11 FADR11 O Address output to FLASH ROM
11 FADR9 FADR9 O Address output to FLASH ROM
12 VDD15 VDD15 Power supply (VD1R5)
13 FADR8 FADR8 O Address output to FLASH ROM
14 FADR13 FADR13 O Address output to FLASH ROM
15 FADR14 FADR14 O Address output to FLASH ROM
16 NWE NWE O Write enable output to FLASH ROM
17 FADR16 FADR16 O Address output to FLASH ROM
18 FADR15 FADR15 O Address output to FLASH ROM
19 DRAMVDD15 DRAMVDD15 DRAM power supply (DRAMD1R5)
20 DRAMVSS DRAMVSS GND for DRAM
21 VSS VSS GNDD
22 FADR12 FADR12 O Address output to FLASH ROM
23 FADR7 FADR7 O Address output to FLASH ROM
24 FADR6 FADR6 O Address output to FLASH ROM
25 FADR5 FADR5 O Address output to FLASH ROM
26 FADR4 FADR4 O Address output to FLASH ROM
27 FADR3 FADR3 O Address output to FLASH ROM
28 FADR2 FADR2 O Address output to FLASH ROM
29 FADR1 FADR1 O Address output to FLASH ROM
30 FADR0 FADR0 O Address output to FLASH ROM
31 VSS VSS GNDD
32 VDD3 VDD3 Power supply (VD3V)
33 FDT0 FDT0 I/O Data input/output to FLASH ROM
34 FDT1 FDT1 I/O Data input/output to FLASH ROM
35 FDT2 FDT2 I/O Data input/output to FLASH ROM
36 FDT3 FDT3 I/O Data input/output to FLASH ROM
37 FDT4 FDT4 I/O Data input/output to FLASH ROM
38 FDT5 FDT5 I/O Data input/output to FLASH ROM
39 FDT6 FDT6 I/O Data input/output to FLASH ROM
40 FDT7 FDT7 I/O Data input/output to FLASH ROM
41 NCE NCE O Chip enable output to FLASH ROM
42 FADR10 FADR10 O Address output to FLASH ROM
43 NOE NOE O Output enable output to FLASH ROM
44 MMOD MMOD I Connect to VSS
MN103S71F (MAIN ASSY : IC603)
SODC
Pin Function
CDJ-1000MK3
108
1 2 3 4
1 2 3 4
C
D
F
A
B
E
No. Mark Pin Name I/O Pin Function
45 NRST NRST I Hardware reset input
46 VSS VSS GNDD
47 SCLOCK SCLOCK I/O NC
48 SDATA SDATA I/O NC
49 TxD/EXTRG0/MDATA TXD I/O NC
50 RxD/EXTRG1/MCLOCK RXD I/O NC
51 VDD3 VDD3 Power supply (VD3V)
52 OSCI OSCI I Oscillation input
53 OSCO OSCO O Oscillation output (16.93MHz)
54 VSS VSS GNDD
55 DRV0 DRV0(VRCAP) O NC
56 DRV1 DRV1(SPDRV) O Spindle motor control
57 DRV2 DRV2(FBAL) O Focus balance control
58 DRV3 DRV3(TBAL) O NC
59 DRV4 DRV4(STPM1P) O Stepping motor control
60 DRV5 DRV5(STPM1N) O Stepping motor control
61 DRV6 DRV6(6VRSW) O NC
62 DRV7 DRV7(7VRSW) O NC
63 VSS VSS GNDD
64 DRV8 DRV8(FCSG) O NC
65 DRV9 DRV9(NFEPRST) O NC
66 DRV10 DRV10 O NC
67 DRV11 DRV11(LOAD) O Loading motor control
68 DRV12 DRV12(FEPCK) O Clock output to FEP
69 DRV13 DRV13(FEPDT) I/O Data input/output to FEP
70 DRV14 DRV14(FEPEN) O Enable output to FEP
71 DRAMVSS DRAMVSS GND for DRAM
72 DRAMVDD15 DRAMVDD15 DRAM power supply (DRAMD1R5)
73 DRAMVDD33 DRAMVDD33 Power supply (VD3V)
74 VDD3 VDD3 Power supply (VD3V)
75 FG FG I Spindle motor FG input
76 TX TX O NC
77 VDD15 VDD15 Power supply (VD1R5)
78 VSS VSS GNDD
79 TSTSG TSTSG O EQ calibration signal to FEP
80 VFOSHORT VFOSHORT O VFO short control
81 JLINE JLINE O NC
82 BDO BDO I BDO (Black Dog Out) input
83 OFTR OFTR I OFTR (Off Track) input
84 AVSSD AVSSD GNDA
85 ROUT ROUT O NC
86 LOUT LOUT O NC
87 AVDDD AVDDD Power supply (VA3V)
88 VCOF VCOF I VCO control voltage
89 TRCRS TRCRS I Input for TRCRS (Track Cross) generation
90 AVDDC AVDDC Power supply (VA3V)
91 WBLIN WBLIN I Connect to VSS
92 CSLFLT CSLFLT I NC
93 RFDIF RFDIF I NC
94 AVSSC AVSSC GNDA
CDJ-1000MK3
109
5 6 7 8
5 6 7 8
C
D
F
A
B
E
No. Mark Pin Name I/O Pin Function
95 PLFLT2 PLFLT2 I Connect a capacitor for PLL
96 PLFLT1 PLFLT1 I Connect a capacitor for PLL
97 AVSSB AVSSB GNDA
98 ARF ARF I RF+ input
99 NARF NARF I RF- input
100 VHALF VHALF I Reference voltage (1.65V) input
101 RVI RVI I VREFH reference current control
102 VREFH VREFH I Reference voltage (2.2V) input
103 DSLF2 DSLF2 I Connect a capacitor for DSL (Data SLicer)
104 DSLF1 DSLF1 I Connect a capacitor for DSL (Data SLicer)
105 AVDDB AVDDB Power supply (VA3V)
106 JITOUT JITOUT O Jitter monitor output
107 AVDDA AVDDA Power supply (VA3V)
108 TECAPA TECAPA I NC
109 AD0 AD0(FE) I Focus error input
110 AD2 AD2(AS) I RFAS input
111 AD1 AD(TE) I Tracking error input
112 AD3 AD3(RFENV) I RF envelope input
113 AD4 AD4(RFDIF) I Radial differential input
114 AD5 AD5(FEDRV) I Focus drive input
115 AD6 AD6(TEDRV) I Tracking drive input
116 AD7 AD7(T+) I Connect to VSS
117 AD8 AD8(T-) I Connect to VSS
118 AVSSA AVSSA GNDA
119 PWM0 PWM0 O Focus drive control
120 PWM1 PWM1 O Tracking drive control
121 VSS VSS GNDD
122 VDD3 VDD3 Power supply (VD3V)
123 IDGT IDGT O NC
124 DTR DTR O NC
125 MONI0/P9 BUSY/MONI0 I/O Monitor output
126 MONI1/P10 NAMUTE/MONI1 I/O Monitor output
127 MONI2/P11 NDMUTE1/MONI2 I/O Monitor output
128 MONI3/P12 NDMUTE2/MONI3 I/O Monitor output
129 MSTPOL/MONI4 MSTPOL/MONI4 I
130 DASPST/MONI5 DASPST/MONI5 I Connect to VSS
131 NEJECT/MONI6 NEJECT/MONI6 O NC
132 NTRYCL/MONI7 NTRYCL/MONI7 O NC
133 DMARQ DMARQ O DMA request output to the host
134 NIOWR NIOWR I Host write input
135 VDD3 VDD3 Power supply (VD3V)
136 VSS VSS GNDD
137 NIORD NIORD I Host read input
138 IODRY IODRY O Ready output to the host
139 NDMACK NDMACK I Host DMA acknowledge input
140 INTRQ INTRQ O Interrupt output to the host
141 NIOCS16 NIOCS16 O Data bus width select
142 DA1 DA1 I Assress input
143 NPDIAG NPDIAG I/O
144 DA0 DA0 I Assress input
CDJ-1000MK3
110
1 2 3 4
1 2 3 4
C
D
F
A
B
E
No. Mark Pin Name I/O Pin Function
145 VSS VSS GNDD
146 VDD3 VDD3 Power supply (VD3V)
147 DA2 DA2 I Address input
148 NCS1FX NCS1FX I Chip select input
149 NCS3FX NCS3FX I Chip select input
150 NDASP NDASP I/O
151 HDD15 HDD15 I/O Data input/output
152 HDD0 HDD0 I/O Data input/output
153 HDD14 HDD14 I/O Data input/output
154 HDD1 HDD1 I/O Data input/output
155 HDD13 HDD13 I/O Data input/output
156 VDD3 VDD3 Power supply (VD3V)
157 VDD15 VDD15 Power supply (VD1R5)
158 VSS VSS GNDD
159 HDD2 HDD2 I/O Data input/output
160 HDD12 HDD12 I/O Data input/output
161 HDD3 HDD3 I/O Data input/output
162 HDD11 HDD11 I/O Data input/output
163 HDD4 HDD4 I/O Data input/output
164 HDD10 HDD10 I/O Data input/output
165 HDD5 HDD5 I/O Data input/output
166 VSS VSS GNDD
167 VDD3 VDD3 Power supply (VD3V)
168 HDD9 HDD9 I/O Data input/output
169 HDD6 HDD6 I/O Data input/output
170 HDD8 HDD8 I/O Data input/output
171 HDD7 HDD7 I/O Data input/output
172 VDDH VDDH Power supply (VD5V)
173 NRESET NRESET I Reset input from the host
174 MASTER MASTER I Connect to VSS
175 P0/SERIAL LPS1 I Loading mecha SW input
176 P1/SERIAL LPS2 I Loading mecha SW input
CDJ-1000MK3
111
5 6 7 8
5 6 7 8
C
D
F
A
B
E
No. Pin Name
Signal
Name
I/O Pin Function
1 P96/ANEX1 T/B I VINYL SPEED ADJUST input Clockwise direction: Vcc side
2 P95/ANEX0 R/S I VINYL SPEED ADJUST input Clockwise direction: Vcc side
3 P94 MODEL1 I Model setting 1 (pull up with 5V) Distinguish between CDJ-800MK2 and CDJ-1000MK3.
4 P93/DA0 MODEL2 I Model setting 2 (pull up with 5V) Distinguish between CDJ-800MK2 and CDJ-1000MK3.
5 P92/TB2IN N.C. Not used
6 P91/TB1IN JOG1 I Pulse period measurement processing (connect to JOG1)
7 P90/TB0IN N.C. Not used
8 BYTE Not used (Connect to GND)
9 CNVss CNVSS Not used (GND pull down)
10 P87/XCIN Not used (Connect to GND)
11 P86/XCOUT Not used (Connect to GND)
12 XRESET XRESET I Reset input
13 Xout XOUT O Oscillator (16MHz)
14 Vss GNDD GND
15 Xin XIN I Oscillator (16MHz)
16 Vcc1 V+5D Power supply
17 P85/XNMI XNMI I Not used (pull up with 5V)
18 P84/XINT2 Not used (connect to 5V)
19 P83/XINT1 Not used (connect to 5V)
20 P82/XINT0 Not used (connect to 5V)
21 P81 Not used (connect to 5V)
22 P80 Not used (connect to 5V)
23 P77 Not used (connect to 5V)
24 P76