Figure 1-1 Basic Gates

A A
C C
B B
AND: C = A B OR: C = A + B

A
A C C
B
NOT: C = A' EXCLUSIVE OR: C = A + B
 Figure 1-2 Full Adder

X Y Cin CoutSum
0 0 0 0 0
Cout 0 0 1 0 1
X 0 1 0 0 1
FULL
Y 0 1 1 1 0
ADDER 1 0 0 0 1
Cin Sum 1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
(a) Full adder module
(b) Truth Table

Sum = X'Y'Cin + X'YCin' + XY'Cin' + XYCin = X + Y + Cin

Cout = X'YCin + XY'Cin + XYCin' + XYCin = XY + XCin + YCin
 Figure 1-3 Four-Variable Karnaugh Maps

AB AB
CD 00 01 11 10 CD 00 01 11 10 four corner terms
combine to give B' D'
00 0 4 12 8 00 1 0 0 1

01 1 5 13 9 C 01 0 1 0 0
A'BD
11 3 7 15 11 11 1 1 X 1

10 2 6 14 10 10 1 1 X 1

F =∑m(0,2,3,5,6,7,8,10,11) + ∑d(14,15)
= C + B' D' + A' BD
= (B' + C + D) (B + C + D') (A'+B')
Figure 1-4 Selection of Prime Implicants

AB
CD 00 01 11 10

00 1 X
0 4 12 8
A'C'
01 1 1
1 5 13 9

11 1 1 1 ACD
3 7 15 11

10 1 X
2 6 14 10

A'B'D'

F = A'C' + A'B'D' + ACD + A'BD

or
F = A'C' + A'B'D' + ACD + BCD
 Figure 1-5
Simplification Using Map-Entered Variables

AB AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 1 00 1 00 X 00 X

01 X E X F 01 X X 01 X 1 X 01 X X 1

11 1 E 1 1 11 1 1 1 11 X 1 X X 11 X X X

10 1 X 10 1 X 10 X X 10 X X

G E=F=0 E = 1, F = 0 E = 0, F = 1
MS 0 = A'B' + ACD MS 1 = A'D MS 2 = AD

G = MS0 + EMS 1 + FMS 2

= A'B' + ACD + EA'D + FAD

 Figure 1-6 NAND and NOR Gates

NAND:
A A
C C C = (AB)' = A' + B'
B B
NOR:
A A
C C C = (A+B)' = A'B'
B B
Figure 1-7 Conversion to NOR Gates

A
B' G
C Z
D
E
F
(a) AND-OR network

Double inversion cancels

A
B'
C'
D G' Z
Complemented input
cancels inversion E
F
(b) Equivalent NOR-gate network
 Figure 1-8
Conversion of AND-OR Network to NAND Gates
A
B
C
D F
E
(a) AND_OR network

Bubbles cancel
A
B
C
D F
E
(b) First step in NAND conversion

Added inverter
Added inverter
A
B'
C
D' F
E'
(c) Completed conversion
Figure 1-9 Elimination of 1-Hazard
A D A
B F BC 0 1
E 00 0 1

C F = AB' + BC 01 0 1

(a) Network with 1-hazard 1 - Hazard

11 1 1

10 0 0
B'
B
D
E
F
0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns
(b) Timing Chart

A A
B BC 0 1
00 0 1
F
C 01 0 1

11 1 1
A F = AB' + BC + AC
10 0 0
(c) Network with hazard removed
 Figure 1-10
Clocked D Flip-flop
with Rising-edge Trigger

Q' Q
D Q Q+

DFF 0 0 0
0 1 0
1 0 1
1 1 1
CLK D
Q+ = D
 Figure 1-11 Clocked J-K Flip-flop

J K Q Q+
0 0 0 0
0 0 1 1
Q' Q 0 1 0 0
FF 0 1 1 0
CK 1 0 0 1
K J 1 0 1 1
1 1 0 1
1 1 1 0

Q + = JQ' + K'Q
Figure 1-12 Clocked T Flip-flop

Q' Q
T Q Q+

FF 0 0 0
0 1 1
1 0 1
1 1 0
CLK T

Q+ = QT' + Q'T = Q + T
 Figure 1-13 S-R Latch

S S R Q Q+
P 0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
Q 1 1 0 –
R 1 1 1 –

Q += S + R'Q
 Figure 1-14 Transparent D Latch

G D Q Q+
0 0 0 0
0 0 1 1
Q 0 1 0 0
Latch 0 1 1 1
1 0 0 0
G D 1 0 1 0
1 1 0 1
1 1 1 1
 Figure 1-15 Implementation of D Latch

D
G

Q Q+ = DG + G'Q + (DQ)

D
Figure 1-16 General Model of Mealy Sequential Machine

Inputs (X) Outputs (Z)

Combinational
Network Next state State
State
Reg
clock
 Figure 1-17 State Graph and Table
for Code Converter

t0 S0
NS Z
t1 0/1 1/0
NC S1 S2 C PS X=0 X=1 X=0 X=1
1/0 S0 S1 S2 1 0
0/1 0/0,1/1
0/0,1/1 0/1 S1 S3 S4 1 0
S2 S4 S4 0 1
t2 NC S3 S4 C S3 S5 S5 0 1
S4 S5 S6 1 0
0/0,1/1 0/1 1/0 S5 S0 S0 0 1
S6 S0 – 1 –
t3 S5 S6
NC C
(b) State Table
(a) Mealy state graph
From Page 20

I. States which have the same next state (NS) for a given input should be given adjacent
assignments (look at the columns of the state table).
II. States which are the next states of the same state should be given adjacent assignments
(look at the rows).
III. States which have the same output for a given input should be given adjacent assignments.

I. (1,2) (3,4) (5,6) (in the X=1 column, S1 and S2 both have NS S4;
in the X=0 column, S3 & S4 have NS S5, and S5 & S6 have NS S0)

II. (1,2) (3,4) (5,6) (S1 & S2 are NS of S0; S3 & S4 are NS of S1;
and S5 & S6 are NS of S4)

III. (0,1,4,6) (2,3,5)

Q1
Q2 Q3 0 1

00 S0 S1

Figure 1-18(a) 01 S2
State Assignment Map
11 S5 S3

10 S6 S4
Figure 1-17(b) State Table Figure 1-18(b) Transition Table

NS Z Q1:Q2:Q3: Z
PS X=0 X=1 X=0 X=1 Q1Q2Q3 X=0 X=1 X=0 X=1
S0 S1 S2 1 0 000 100 101 1 0
S1 S3 S4 1 0 100 111 110 1 0
S2 S4 S4 0 1 101 110 110 0 1
S3 S5 S5 0 1 111 011 011 0 1
S4 S5 S6 1 0 110 011 010 1 0
S5 S0 S0 0 1 011 000 000 0 1
S6 S0 – 1 – 010 000 xxx 1 x
001 xxx xxx x x

S0 = 000, S1 = 100, S2 = 101, S3 = 111, S4 = 110, S5 = 011, S6 = 010

 Figure 1-19
Karnaugh Maps for Figure 1-17
XQ 1 XQ1
Q 2Q 3 00 01 11 10 Q 2 Q 3 00 01 11 10
00 1 1 1 1 00 0 1 1 0

01 X 1 1 X 01 X 1 1 X

11 0 0 0 0 11 0 1 1 0

10 0 0 0 X 10 0 1 1 X

D 1 = Q1+ = Q2' D 2 = Q2+= Q1

XQ1 XQ1
Q 2Q 3 00 01 11 10 Q 2Q 3 00 01 11 10
00 0 1 0 1 00 1 1 0 0
01 X 0 0 X 01 X 0 1 X

11 0 1 1 0 11 0 0 1 1

10 0 1 0 X 10 1 1 0 X

D 3 = Q3+ = Q1Q 2Q 3 + X'Q1Q 3' + XQ1'Q 2' Z = X'Q3' + XQ3

 Figure 1-20 Realization of Code Converter

Q2' D Q Q1
Q1
Q2 G1 A1 FF1
Q3 Q' Q1'

Q1 Q1 D Q Q2
Q3' A2
G2 FF2
I1 X
X' Q' Q2' A5
G5

X D3 Q3
A3 G4 D Q G7 Z
Q1' G3 A6
Q2' FF3 X'
Q3' G6
CLK Q'
 Figure 1-21 Derivation of J-K Input Equations
Q + J1= Q 2'
XQ1 1 XQ1 XQ1 K1 = Q 2
Q 2 Q 3 00 01 11 10 Q 2 Q 3 00 01 11 10 Q 2 Q 3 00 01 11 10
00 1 1 1 1 00 1 X X 1 00 X 0 0 X

01 X 1 1 X 01 X X X X 01 X 0 0 X

11 0 0 0 0 11 0 X X 0 11 X 1 1 X

10 0 0 0 X 10 0 X X X 10 X 1 1 X

(a) Derivation using separate J-K map

Q1+ Q2+ Q3+

XQ1 XQ1 XQ 1
Q 2 Q 3 00 01 11 10 Q 2 Q 3 00 01 11 10 Q 2 Q 3 00 01 11 10
00 1 1 1 1 00 0 1 1 0 00 0 1 0 1 J3
J2
01 X 1 1 X 01 X 1 1 X 01 X 0 0 X
K3'
11 0 0 0 0 11 0 1 1 0 11 0 1 1 0
K2'
10 0 0 0 X 10 0 1 1 X 10 0 1 0 X J3

J1 K1' J1 J2 = Q1 J3 = X'Q 1 + XQ1'

J1 = Q2' K1 = Q2 K2 = Q 1' K3 = Q 1' + Q2'
(b) Derivation using the shortcut method
Figure 1-22
Coding Schemes for Serial Data Transmission

bit sequence 0 1 1 1 0 0 1 0

NRZ

NRZI

RZ

Manchester

1 bit
time
 Figure 1-23 Moore network
for NRZ-to-Manchester Conversion
X
NRZ data Conversion Z
Manchester data
CLK2 Network

(a) Conversion network

S0 0 S1 Present Next State Present

0 0 State X = 0 X=1 Output (Z)
S0 S1 S3 0
1 1 0 0 S1 S2 – 0
S3 S2 S1 S3 1
S2
1 1 1 S3 – S0 1
(b) State Graph (c) State table
 Figure 1-24 Timing for Moore Network

1 bit
time

X (NRZ) 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0

CLOCK2

State S0 S1 S2 S3 S0 S3 S0 S3 S0 S1 S2 S1 S2 S3 S0 S1
Z
(Manchester) 0 0 1 1 0 1 0 1 0 0 1 0 1 1 0 0
1 bit
time
Figure 1-25 Determination of Equivalent States

si N1 Z1 = 1( s i, X )
X

sj N2 Z2 = 2( sj , X )

si s j iff Z1 = Z 2
for every input sequence X
Figure 1-26(i) State Table Reduction

Present Next Present

State State Output c-d
X=0 1 X=0 1 b e-f
a ≡ b iff c ≡ d and e ≡ f
a c f 0 0
b d e 0 0 a- d
c h/ a g 0 0 c f -g
e- g
d b g 0 0
e e b 0 1 b-c
f f a 0 1 d e- g a- b
f -g
g c g 0 1
h c f 0 0
e

f a- b

c-e e-f
g b-g a- g

a b c d e f
Figure 1-26(ii) State Table Reduction

c-d c-d
b e-f
a ≡ b iff c ≡ d and e ≡ f b e-f
a- d a- d
c f -g c f -g
e- g e- g
b-c b-c
d e- g a- b d e- g a-b
f -g f -g

e e

f a- b f a- b

c-e e-f c-e e-f

g b-g a- g g b-g a-g

a b c d e f a b c d e f

a ≡ b, c ≡ d, e ≡ f
Figure 1-26(iii) State Table Reduction

Present Next Present

State State Output a ≡ b, c ≡ d, e ≡ f
X=0 1 X=0 1
a c f 0 0 Present
b d e 0 0 State X=0 1 X=0 1
c h/ a g 0 0 a c e 0 0
d b g 0 0 c a g 0 0
e e b 0 1 e e a 0 1
f f a 0 1 g c g 0 1
g c g 0 1
h c f 0 0 Final Reduced Table
 Figure 1-27 Timing Diagram for Code Converter

Clock

X 0 0 1 0 1 0 0 1

State S1 S3 S5 S0 S2 S4 S5 S0
S0
Next
State S1 S3 S5 S0 * S2 S4 S5 S0 S2

Z 1 1 1 0 0 0 1 1
ta t b tc *=S1
 Figure 1-28 Timing Diagram for Figure 1-20

Clock

X 0 0 1 0 1 0 0 1
Q3

Q2

Q1

Z 1 1 1 0 0 0 1 1
 Figure 1-29 Setup and Hold Times for D Flip-flop

t su t h

Clock

Q t plh t phl
Figure 1-30 Setup and Hold Timing for Changes in X

CLK

X ty tcxmin
tx
tsu th
tcxmax
D
 Figure 1-31 Synchronous Digital System

Clock Data
In
Control
Control Signals
Inputs CONTROL DATA
SECTION SECTION
Condition
Signals
Data
Out
Figure 1-32 Timing Chart for System with Falling-Edge Devicves
State Change Initiated Here

Clock
Uncertain
Switching
Transients

Control
Signal

Clock·CS

Figure 1-33 Gated Control Signal

Clock Clock
CK CS CK
CS
CLK

(a) Faling-edge device (b) Rising-edge device

 Figure 1-34 Timing Chart with Rising-Edge Devices
State Change Initiated Here

Clock

Switching
Transients

Control
Signal (CS)
CLK1 =
Clock · CS (a) (b)

CS
CLK2 =
Clock + CS

Figure 1-35 Incorrect Design Figure 1-36 Correct Design

(a) with gated clock (b) With enble
Clock
CK CS Enable
CS CLK1 Clock
CS CK
CLK2 Clock CK

"Rising Edge"
Device
Synchronous Design Principals (from page 34)

Method: All clock inputs to flip-flops, registers, counters, etc. are driven
directly from the system clock or from the clock ANDed with a
control signal.

Result: All state changes occur immediately following the active edge of
the clock signal.

Advantage: All switching transients, switching noise, etc. occur between clock
pulses and have no effect on system performance.
 Figure 1-37 Four Kinds of Tristate Buffers

B B B B
A C A C A C A C

B A C B A C B A C B A C
0 0 Hi-Z 0 0 Hi-Z 0 0 0 0 0 1
0 1 Hi-Z 0 1 Hi-Z 0 1 1 0 1 0
1 0 0 1 0 1 1 0 Hi-Z 1 0 Hi-Z
1 1 1 1 1 0 1 1 Hi-Z 1 1 Hi-Z
(a) (b) (c) (d)
 Figure 1-38 Data Transfer Using Tristate Bus

Eni
Input 8 TRI-STATE BUS
Data
Ena 8 Enb Enc

Lda Reg. A Ldb Reg. B Ldc Reg. C

Clock