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GATE CS Topic wise Questions Digital Logic

YEAR 2001

Question. 1

Given the following Karnaugh map, which one of the following represents the minimal sum-of-Products of the map ?

(A) xy + y'z (C) w'x + y'z + xy

(B) wx'y' + xy + xz (D) xz + y

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SOLUTION

There are 2 quads. y'z + yx So xy + y'z Hence (A) is correct option.

Question. 2

Consider the following circuit with initial state Q 0 = Q1 = 0 . The D flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.

Consider the following timing diagrams of X and C ; the clock of C $ 40 nanosecond. Which one is the correct plot of Y

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CS Topicwise 2001-2010 Digital Logic

SOLUTION

Consider the following circuit with initial state Q 0 = Q1 = 0 . The D flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0. Figure Consider the following timing diagrams of X and C ; the clock period of C $ 40 nanosecond. Which one is the correct plot of Y ? Figure

Question. 3

The 2s complement representation of ( 539) 10 is hexadecimal is (A) ABE (C) DE5

SOLUTION

(B) DBC (D) 9E7

Binary of 539 = 1000011011

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Binary : 0010 0001 1011 2's comp : 1101 1110 0101 Hexadecimal D E 5 (DES) 16 Hence (C) is correct option.
Question. 4

Consider the circuit shown below. The output of a 2:1 Mux is given by the function (ac' + bc).

Which of the following is true ? (A) f = x1' + x2 (C) f = x1x2 + x1'x2'

SOLUTION

(B) f = x1'x2 + x1x2' (D) f = x1 + x2

Output of any 2:1 MUX = ac' + bc Here output of MUX 1. ' g = ax 1 + bx1 Output of MVX 2 ' f = gx 2 + x1 x 2 ' ' f = (ax 1 + bx1) x 2 + x1 x 2 ' ' ' f = ax 1 x 2 + bx1 x 2 + x1 x2 Given a = 1, b = 0 ' ' f = x1 x 2 + x1 x 2 Hence (C) is correct option.
Question. 5

Consider the circuit given below the initial state Q 0 = 1, Q1 = Q2 = 0 . The state of the circuit is given by the value 4Q2 + 2Q1 + Q 0
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CS Topicwise 2001-2010 Digital Logic

Which one of the following is the correct state sequence of the circuit ? (A) 1, 3, 4, 6, 7, 5, 2 (C) 1, 2, 7, 3, 5, 6, 4 (B) 1, 2, 5, 3, 7, 6, 4 (D) 1, 6, 5, 7, 2, 3, 5

SOLUTION

Initially Clk 1 2 3 4 5 6

Q0 1 0 1 1 1 0 0

Q1 0 1 0 1 1 1 0

Q2 0 0 1 0 1 1 1

Value 4Q2 + 2Q1 + Q 0 1 2 5 3 7 6 4

Hence (B) is correct option.

YEAR 2002

Question. 6

Minimum sum of product expression for f (w, x, y, z) shown in Karnaugh-map below is

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(A) xz + y'z (C) x'y + zx'

SOLUTION

(B) xz' + zx' (D) None of the above

There are 2 quads possible xz' + x'z Hence (B) is correct option.
Question. 7

The decimal value of 0.25 (A) is equivalent to the binary value 0.1 (B) is equivalent to the binary value 0.01 (C) is equivalent to the binary value 0.00111..... (D) cannot be represented precisely in binary.
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SOLUTION

CS Topicwise 2001-2010 Digital Logic

Given decimal no. 0.25 Binary = ? .25 # 2 = .5 .5 # 2 = 1 (.01) 2 Hence (B) is correct option.
Question. 8

The 2s complement represent representation of the decimal value 15 is (A) 1111 (C) 111111
SOLUTION

(B) 11111 (D) 10001

Given ( 15) 10 Binary of 15 = (01111) 2 2s complement of 15 would represent ( 15). 0 1111 (10001) 2 Hence (D) is correct option.
Question. 9

Sign extension is a step in (A) floating point multiplication (B) signed 16 bit integer addition (C) arithmetic left shift (D) converting a signed integer from one size to another.
SOLUTION

Sign extension is the operation in computer arithmetic of increasing no. of bits of a binary no., while preserving sign and value done by appending MSBs. In the floating point multiplication to bring the no. in desired no. of significant digits sign extension is done. Hence (A) is correct option.
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Question. 10

In 2s complement addition, overflow (A) Relational algebra is more powerful than relational calculus (B) Relational algebra has the same power as relational calculus. (C) Relational algebra has the same power as safe relational calculus. (D) None of the above.

SOLUTION

In 2s complement addition, overflow occurs when the carries from sign bit & previous bit doesnt match. So overflow cant occur when a positive value is added to some negative value. Hence (B) is correct option.
Question. 11

Consider the following logic circuit whose inputs are functions f1, f2, f3 and output is f

Given that f1 (x, y, z) = (0, 1, 3, 5) f2 (x, y, z) = (6, 7), and f (x, y, z) = (1, 4, 5) f3 is (A) (1, 4, 5) (C) (0, 1, 3, 5)
SOLUTION

(B) (6, 7) (D) None of the above

f1 (x, y, z) = (0, 1, 3, 5)
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= x'y' + y'z + x'z f2 (x, y, z) = (6, 7)

= xy f (x, y, z) = (1, 4, 5)

= xy' + y'z f (x, y, z) = f1 f2 : f3 = f1 : f2 + f3 = xy (x'y' + y'z + x'z) + (xy' + y'z) f3 = xy'z + xy'z' + xy'z + x'y'z f3 = (1, 4, 5) Hence (A) is correct option.
Question. 12

Consider the following multiplexor where 10, 11, 12, 13 are four data input lines selected by two address line combinations A1A0 = 00, 01, 10, 11 respectively and f is the output of the multiplexor. EN is the Enable input.
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The function f (x, y, z) implemented by the above circuit is (A) xyz' (C) x + y
SOLUTION

(B) xy + z (D) None of the above

A1 A 0 EN (MUX) work 0 0 1 1 0 1 0 1 1 0 1 0 do not (MUX) Work do not

So MUX is ENABLED only if A 0 = 0 So output should have Z' . Consider xyz' option (A) A, A 0 = 1 0 gives correct answer. Hence (A) is correct option.
Question. 13

Let f (A, B) = A' + B . Simplified expression for function f (f (x + y, y), z) is (A) x' + z (C) xy' + z
SOLUTION

(B) xyz (D) None of the above

f (x + y, y) = (x + y) ' + y & x+y+y f (f (x + y, y), z) = x + y + y + z & (x + y : y ) + z [(x + y) : y ] + z

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[xy + yy ] + z xy + z Hence (C) is correct option.
Question. 14

CS Topicwise 2001-2010 Digital Logic

What are the states of the Auxiliary Carry (AC) and Carry Flag (CY) after executing the following 8085 program ? MIV H, MIV L, MOV A, ADD L (A) AC = 0 and CY = 0 (C) AC = 1 and CY = 0
SOLUTION

5DH 6BH H

(B) AC = 1 and CY = 1 (D) AC = 0 and CY = 1

Program is to add 2 nos kept in H & L, result of addition is stored in A. (5D) 16 + (6B) 16 &

0 is the carry so CY = 0 (1) is auxillary carry AC = 1 Hence (C) is correct option.

Question. 15

The finite state machine described by the following state diagram with A as starting state, where an arc label is x and x stands for y 1-bit input and y stands for 2-bit output.
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(A) Outputs the sum of the present and the previous bits of the input. (B) Outputs 01 whenever the input sequence contains 11 (C) Outputs 00 whenever the input sequence contains 10 (D) None of the above.
SOLUTION

Previous input Present i/p Output 0(A) 0(A) 1(B) 1(B) 1(C) 1(C) 0(A) 1(B) 0(A) 1(C) 1(C) 0(A) 00 01 01 10 10 01

So output is always sum of the present and previous bits of input. Hence (A) is correct option.
YEAR 2003 Question. 16

Assuming all numbers are in 2s complement representation, which of the following number is divisible by 11111011? (A) 11100111 (C) 11010111
SOLUTION

(B) 11100100 (D) 11011011

We cant judge the nos in 2s complement first we need to convert them in decimal Given no. 11111011"00000101 = 5
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(A) 11100111 " 00011001 = 25 (B) 11100100 " 00011100 = 28 (C) 11010111 " 00101001 = 41 (D) 11011011 " 00100101 = 37 From all only option (A) is divisible by 5. Shortcut : To convert 2s complement no. directly into original binary, we should complement all the digits from MSB till the last one (1). Keep the last 1 from the LSB as it is. Observe in the example.
Question. 17

CS Topicwise 2001-2010 Digital Logic

The following is a scheme for floating point number representation using 16 bits.

Let s, c and m be the number represented in binary in the sign, exponent, and mantissa fields respectively. Then the flouting point number represented id ( 1) 2 (1 + m # 2 9)2 e 31, if the exponent 111111 ) 0 otherwise What is the maximum difference between two successive real numbers representable in this system? (A) 2 40 (B) 2 9 (C) 222
SOLUTION

(D) 231

e has 6 bits so max value can be 26 1 = 63 when e = 111111 But given e = Y 111111 So max e = 62 = 111110 Two consecutive number will have same exponent but difference in mantissa by 1. Difference would be ( 1) 2 (1 + (m + 1) 2 9) 262 31 ( 1) 2 (1 + m # 2 9) 262 31 231 # 2 9 = 222 Hence (C) is correct option.
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Question. 18

A 1-input, 2-output synchronous sequential circuit behaves as follows. Let zk , nk denote the number of 0s and 1s respectively in initial k bits of the input (zk + nk = k). The circuit outputs 00 until one of the following conditions holds. 1. nk nk = 2 . In this case, the output at the k -th and all subsequency clock ticks is 10. 2. nk zk = 2 . In this case, the output at the k -th and all subsequent clock ticks is 01. What in the minimum number of states required in the state transition graph of the above circuit? (A) 5 (B) 6 (C) 7
SOLUTION

(D) 8

The sequential circuit has 3 variables to decide the state in which input & 2 inputs are present. Output for particular inputs decide states. i/p 0 0 0 0 1 1 1 1 op 1 op 2 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 State Intial nK zK = 2 zK nK = 2 Not applicable Initial nK zK = 2 zK nK = 2 is correct

Using 3 bits we require 23 1 = 7 states here. Hence (C) is correct option.

Question. 19

The literal count of a boolean expression is the sum of the number of times each literal appears in the expression. For example, the literal count of (xy + xz) is 4. What are the minimum possible literal counts
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of the product-of-sum and sum-of-product representations respectively of the function given by the following karnaugh map? Here, denotes dont care

CS Topicwise 2001-2010 Digital Logic

(A) (11,9) (C) (9,10)

SOLUTION

(B) (9,13) (D) (11,11)

Considering product of sum & sum of product separately.

Sum of product = wy + w'y' + z'wx' + xyz' 12 34 567 8910 Literal count =10 Hence (C) is correct option.

Product of sum = (y' + z') (z' + y) (w' + z') (x + z + w) Lateral count =9

In SOP the K-map is solved for 1 & POS K-map solved for 0
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Question. 20

Consider the following circuit composed of XOR gates and noninverting buffers.

The non-inverting buffers have delays 1 = 2ns and 2 = 4ns as shown in the figure. both XOR gates and al wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0. If the following waveform is applied at input. A, how many transition (s) (change of logic levels) occur (s) at B during the interval from 0 to 10 ns ?

(A) 1 (C) 3
SOLUTION

(B) 2 (D) 4

Due to delays S1 = 2 & S2 = 4 the transitions would occur at time 1, 2 & 4. Time Input (A) Output (B) 0 I II III 1 2 4 1 1 1 0 0 0 0 1 Transition Transition Transition

So total 3 transitions Hence (C) is correct option.

YEAR 2004 Question. 21

The Boolean function x'y' + xy + x'y is equivalent to

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(A) x' + y' (C) x + y'
SOLUTION

CS Topicwise 2001-2010 Digital Logic

(B) x + y (D) x' + y

x'y' + xy + xy' x' (y + y') + xy (A + A') = 1 x' + xy (A + AB) = (A + A) : (A + B) (x' + x) : (x' + y) 1 : (x' + y) x' + y Hence (D) is correct option.
Question. 22

In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in (A) Q = 0, Q' = 1 (B) Q = 1, Q' = 0 (C) Q = 1, Q' = 1
SOLUTION

(D) Indeterminate states

SR latch both S and R when 0 leads to invalid state.

Transition table for SR flip flop. S R Q(Next state) 0 0 Invalid so Q=Q=1 change 0 1 1 1 0 0 1 1 previous state For S=R=0 Q=Q=1 Hence (C) is correct option.
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Question. 23

If 73x (in base-x number system) is equal to 54, (in base-y number system), the possible values of x and y are (A) 8, 16 (B) 10, 12 (C) 9, 13
SOLUTION

(D) 8, 11

(73) x = (54) y 7x + 3 = 5y + 4 (x', y) 7x + 3 8, 16 59 10, 12 73 9, 13 64 8, 11 59 Hence (D) is correct option.

Question. 24

5y + 4 84 64 69 59

What is the result of evaluating the following two expressions using three-digit floating point arithmetic with rounding? (113.+111.)+7.51 113.+(111.+7.51) (A) 9.51 and 10.0 respectively (C) 9.51 and 9.51 respectively
SOLUTION

(B) 10.0 and 9.51 respectively (D) 10.0 and 10.0 respectively

Expression 1 (113.0 + ( 111.) + 7.51 (113.0 111.0) + 7.51 2.0 + 7.51 9.51 rounded off 10 Expression 2 113.0 + ( 111.0 + 7.51) 113.0 + ( 103.49) 113.0 103.00 10.0 rounded off Hence (D) is correct option
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Question. 25

CS Topicwise 2001-2010 Digital Logic

A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001,...9 by 1001. A combinational circuit is to be diesigned which takes these 4 bits as input and outputs 1 if the digit $ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required? (A) 2 (B) 3 (C) 4
SOLUTION

(D) 5

CKT takes 4 bits as the input so K-Map will have 4 variable so 16 options are available.

1 digit = 5 0 otherwise Here for 0 to 4 we have 0 output, from 5 to 9 1 output & for 10 to 15 dont care. 1 octed & 2 pounds. a + bd + bc a + b (d + c) Two OR gates One AND gate Total 3 Hence (B) is correct option.
Question. 26

Which are the essential prime implicates of the following Boolean function? f (a, b, c) = a'c + ac' + b'c (A) a'c and ac' (B) a'c and b'c
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(C) a'c only
SOLUTION

(D) ac' and bc'

f (a, b, c) = a'c + ac' + b'c Making min terms a'bc + a'b'c + abc' + ab'c' + a'b'c + ab'c Since b'c gives no new term. So a'c & ac' are only essential prime implicants. Solution detailed method Tabulation method Since b'c gives no new term. So a'c & ac' are only essential prime implicants. Solution detailed method Tabulation method f (a, b, c) = / m (1, 3, 5, 6, 4) Figure Figure 3 & 6 have only 1 cross they are in a'c & ac'
Question. 27

Consider the partial implementation fo a 2-bit counter using T flip flops following the sequence 0-2-3-1-0, as shown below

To complete the circuit, the input X should be (A) Q2 ' (C) (Q1 5 Q2)'
SOLUTION

(B) Q2 + Q1 (D) Q1 5 Q2

Counter counts the no. of signal inversion change of states. Sequence input is 0 2 3 1 0
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Binary 00 10 11 01 00 to generate signals if we XOR gate then it outputs 1 if both are different. So output sequence would be. 0 1 0 1 0 & the sequence would be counted. So. X = Q1 5 Q2 Hence (D) is correct option.
Question. 28

CS Topicwise 2001-2010 Digital Logic

A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncompensated forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic. (A) 4 time units (C) 10 time units
SOLUTION

(B) 6 time units (D) 12 time units

Carry of any higher order bit is dependent upon previous order bit addition generated carry. C out = g 0 + p 0 C in P3 P2 P1 P0 g 3 g 2 g1 g 0 c 3 c 2 c1 c 0 c 3 g 3 + P3 g2 + P3 P2 g1 +| P3 P2 P1 g 0 + P3 P2 P2 P0 C in This is 4 bit look ahead adder equation total gate delay = 1+1+2+2 =6 Hence (B) is correct option.
Question. 29

Let A = 11111010 and B 0000 1010 be two 8-bit 2s complement numbers. Their product in 2s complement is (A) 1100 0100 (C) 1010 0101 (B) 1001 1100 (D) 1101 0101
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SOLUTION

A and B are in 2s complement form. A = 11111010 Binary = 00000110 = 6 2s complement represent ve number So A = 6 B = 00001010 MSB is 0 so + ve no. decimal 10. B = 10 A # B = 6 # 10 = 60 Binary of 60 = 00111100 2s complement 11000100 Hence (A) is correct option.

YEAR 2005

Question. 30

Consider the following circuit.

Which one of the following is TRUE? (A) f is independent of X (C) f is independent of Z (B) f is independent of Y (D) None of X, Y, Z is redundant

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SOLUTION

CS Topicwise 2001-2010 Digital Logic

f = X:Y:Y:Z = X:Y+Y:Z = X:Y+Y:Z For redundant check we need to draw K map to min terms. XY (Z + Z ) + (X + X ) : YZ XY Z + XY Z + XYZ + X YZ

X Y + YZ + XZ Hence (D) is correct option.

Question. 31

The range of integers that can be represented by an a bit 2s complement number system is (A) 2n 1 to (2n 1 1) (B) (2n 1 1) to (2n 1 1) (C) 2n 1 to 2n 1
SOLUTION

(D) (2n 1 + 1) to (2n 1 1)

n bit 2s complement system must have corresponding bit binary system. But to implement + ve & ve nos. Both we require MSB to be sign bit. So maximum magnitude can be 2n 1 1 suppose we take n = 4.
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Using 4 bits. 1 1 1 1,. . . . . .0 0 0 0, . . . . .01 1 1 7 +7 This would be the range. So (2n 1 1) to + (2n 1 1) Hence (B) is correct option.
Question. 32

The hexadecimal representation of 6578 is (A) 1AF (C) D71

SOLUTION

(B) D78 (D) 32F

(657) 8 = (?) 16 Making binary 0 0 01 01 1 1 1 = (IAF) 16 B01 CS S A BB Hence (A) is correct option.
Question. 33

The switching expression corresponding to f (A, B, C, D) = / (1, 4, 5, 9, 11, 12) is (A) BC'D' + A'C'D + AB'D (C) ACD' + A'BC' + AC'D'
SOLUTION

(B) ABC' + ACF + B'C'D (D) A'BD + ACD' + BCD'

f (A, B, C, D) = / (1, 4, 5, 9, 11, 12) Drawing K map for min terms.

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BC D + A C D + A B D So min terms are B C D + A C D + AB D Hence (A) is correct option.
Question. 34

CS Topicwise 2001-2010 Digital Logic

Consider the following circuit involving a positive edge triggered D -FF.

Consider the following timing diagram. Let Ai represent the logic level on the line A in the i th clock period.

Let A represent the complement of A . The correct output sequence on Y over the clock perids 1 through 5 is (A) A0 A1 A1 'A3 A4 (C) A1 A2 A2 'A3 A4
SOLUTION

(B) A0 A1 A2 'A3 A4 (D) A1 A2 'A3 A4 A5

We need to calculate equation for D input. D = (Ai X') ' (X'Q') ' = Ai + X + X + Q D = Ai ' + X + Q Drawing truth table for ckt Clock X Q 0 = 0 Q1 = 1 A i Y
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0 1 2 3 4 5 1 1 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 A0 ' A1 ' A2 ' A3 ' A4 ' A5 ' A0 ' A0 ' A1 ' A1 ' A3 ' A4 '

Hence (A) is correct option.

Question. 35

The following diagram represents a finite state machine which takes as input a binary number from the least significant bit

Which one of the following is TRUE? (A) It computes 1s complement of the input number (B) It computes 2s complement of the input number (C) It increments the input number (D) It decrements the input number
SOLUTION

The transition table for the diagram Present state Input Next state Output Q0 Q0 Q1 Q1 0 1 0 1 Q0 Q1 Q1 Q1 0 1 1 0

So the FSM takes input from LSB side it doesnt change state till the first 1 comes from LSB side, after that it complement all the bits. This is logic for 2s complement. Hence (B) is correct option.
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Question. 36

CS Topicwise 2001-2010 Digital Logic

Consider the following circuit

The flip-flops are positive edge triggered D FFs . Each state is designated as a two bit string Q0, Q1 . Let the initial state be 00. The state transition sequence is (A) 00 " 11 " 01 (B) 00 " 11 A BBBBBB BC A BBB BC (C) 00 " 10 " 01 " 11 (D) 00 " 11 " 01 " 10 A BBBBBBBBB BC A BBBBBBBBBB C
SOLUTION

Truth table for DFF CP 0 1 1 D X 0 1 Qn + 1 Qn 0 1 Action No change Reset Set

D here AX + X'Q' Truth table for ckt

and so on. Hence (D) is correct option.

Data for Q. 37 & 38 are given below.

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Solve the problems and choose the correct answers. Consider the following floating point format

Mantissa is a pure fraction is sign-magnitude form.

Question. 37

The decimal number 0.239 # 213 has the following hexadecimal representation without normalization and rounding off (A) 0D 24 (C) 4D 0D
SOLUTION

(B) 0D 4D (D) 4D 3D

Sign bit 0 Exponent = 13 Excess 64 = 13 + 64 = 77 = 1001101 Binary of 239

We have 8 bits for Mantissa 0 0 1 1 1 1 0 1 So the floating point format.

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0 0100 4 1001101 1101 D 00111101 0011 3 1101 D

CS Topicwise 2001-2010 Digital Logic

Hence (D) is correct option.

Question. 38

The normalized representation for the above format is specified as follows. The mantissa has an implicit 1 preceding the binary (radix) point. Assume that only 0s are padded in while shifting a field. The normalized representation of the above number (0.239 # 213) is (A) 0A 20 (B) 11 34 (C) 4D D0
SOLUTION

(D) 4A E8

Given no. .239 # 213 Normalized form of binary. Binary " .239 = (00111101) 2 Normalized = 1.11101 # 210 Proceeding implicit 1 So 8 bit mantissa 11101000 S padding Excess 64 exponent 1 0 0 1 0 1 0 = 74 Sign bit = 0 Floating 0 0100 4 Point 1001010 1010 A Format 11101000 1110 E 1000 8

GAE8 Hence (D) is correct option.

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YEAR 2006

Question. 39

You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip flops) will delay the phase of f by 180c ?

SOLUTION

We require phase shift of 180 in f In ckt (B) the negation of signal f & clock delays signal f by 180.
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CS Topicwise 2001-2010 Digital Logic

So phase shift occurs. Hence (B) is correct option.

Question. 40

Consider the circuit below. Which one of the following options correctly represents f (x, y, z)?

(A) xz + xy + yz (C) xz + xy + yz
SOLUTION

(B) xz + xy + yz

(D) xz + xy + yz

MVXI Selects X when Z = 0 Y' when Z = 0 MVX II Selects (XZ' + Y'Z) when y = 0 X when y = 0 so (XZ' + YZ) Y' + XY Simplifying = xz'y' + zy'y' + xy = xz'y' + xy (z + z') + zy' = xz'y' + xyz + xyz' + zy' (x + x') = xz'y' + xyz + xyz' + xy'z + x'y'z = y'z + xy'z + xyz' + xyz + xyz' [a + a = a] = y'z + xz' (y + y') + xy (z + z') = y'z + xz' + xy
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Hence (A) is correct option.
Question. 41

Given two three bit numbers a2 a1 a0 and b2 b1 b0 and c , the carry in, the function that represents the carry generate function when these two numbers are added is (A) a2 b2 + a1 a1 b1 + a2 a1 a0 b0 + a2 a0 b1 b0 + a1 b2 b1 + a1 a0 b2 b0 + a0 b2 b1 b0 (B) a2 b2 + a2 b1 b0 + a2 a1 b1 b0 + a1 a0 b21 b1 + a1 a0 b2 + a1 a0 b2 b0 + a2 a0 b1 b0 (C) a2 + b2 + (a2 5 b2)[ a1 + b1 + (a1 5 b1)( a0 + b0)] (D) a2 b2 + a2 a1 b1 + a2 a1 a0 b0 + a2 a0 b1 b0 + a1 b2 b1 a1 a0 b2 b0 + a0 b2 b1 b0
SOLUTION

a 2 a1 a 0 b 2 b 1 b 0 C 0 0 0 0 1 1 1 1 Case I 0 0 1 1 0 0 1 1 0 1 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1

These are the possible value of a2 a1 a 0 & b2 b1 b 0 when a2 = 1 c=1 Case II b2 = 1 c = 1 so a2 + b2 Case III If any 1 of a2 or b2 is 1 a2 5 b2 then if a1 = 1 c = 1 b1 = 1 c = 1 so a2 5 b2 [a1 + b1] Case IV If any of a2 or b2 is 1 & any of a2 or b1 is 1 then if a 0 = 1 c = 1 or if b 0 = 1 then c = 1 so overall. a2 + b2 + [(a2 5 b2) {a1 + b1 + (a1 5 b1) (a 0 + b 0)}] Hence (C) is correct option.

Question. 42

Consider a boolean function f (w, x, y, z). Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors i1 + < w1, x1, y1, x1 > and i2 + < w2, x2, y2, z2 >
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, we would like the function to remain true as the input changes from i1 to i2 (i1 and i2 differ in exactly one bit position), without becoming false momentarily. Let f (w, x, y, z) = / (5,, 711, 12, 13, 15). Which of the following cube covers of f will ensure that the required property is satisfied? (A) wxz, wxy, xyz, xyz, wyz (C) wxyz, xz, wxyz
SOLUTION

CS Topicwise 2001-2010 Digital Logic

(B) wxy, wxz, wyz (D) wzy, wyz, wxz, wwxz, xyz, xyz

Given function f (w, x, y, z) = (5, 7, 11, 12, 13, 15) draw K-map of the above function.

1 quad = xz = xz (y + y') = xzy + xy'z 2 pairs = wxy' + wyz xyz + xy'z + wxy' + wyz Hence (A) is correct option.
Question. 43

We consider addition of two 2s complement numbers bn 1 bn 2 .....b0 and an 1 an 2 ....a0 . A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by cn 1 cn 2 ....c0 and the carryout by cout . Which one of the following options correctly identifies the overflow condition? (A) cout (an 1 5 bn 1) (C) cout 5 cn 1
SOLUTION

(B) an 1 bn 1 cn 1 + an 1 bn 1 cn 1 (D) an 1 5 bn 1 5 cn 1

Binary adder generates C out only if

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1 C in 0 a 1 b 1 1 0 0 1 1 1 1 1 1 1

1 C out 1 C in is Cn 2 So

C out in this case is Cn 1 generated carry.

b' n 1 a' n 1 cn 2 + bn 1 an 1 c' n 2 f = Cout 5 Cn 1 Hence (C) is correct option.

Question. 44

Consider number represented in 4-bit gray code. Let h3 h2 h1 h0 be the gray code representation of a number n and let g3 g2 g1 g0 be the gray code of (n + 1) (modulo 16) value of the number. Which one of the following functions is correct? (A) g0 (h1 h2 h1 h0) = / (1, 2, 3, 6, 10, 13, 14, 15) (B) g1 (h1 h2 h1 h0) = / (4,9,10,11,12,,13,14,15) (C) g2 (h1 h2 h1 h0) = / (2,4, 5, 6, 7,12,,13,15) (D) g3 (h1 h2 h1 h0) = / (0, 1,6,7, 10, 11,12,,13,)
SOLUTION

Binary h 0000 0001 0010 0011 0100 0101 0110 0111 1000
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h 3 h2 h1 h 0 (n + 1) mod 16 0000 0001 0011 0010 0110 0111 0101 0100 1100 1 2 3 4 5 6 7 8 9

g 3 g 2 g1 g 0 0001 0011 0010 0110 0111 0101 0100 1100 1101

0 1 2 3 4 5 6 7 8

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1001 1010 1011 1100 1101 1110 1111 9 1101 10 11 12 13 14 15 0 1111 1110 1010 1011 1001 1000 0000

CS Topicwise 2001-2010 Digital Logic

10 1111 11 1110 12 1010 13 1011 14 1001 15 1000

This gives the solution option (B) g1 (h 3, h2, h1, h 0) = / (4, 9, 10, 11, 12, 13, 14, 15)
YEAR 2007 Question. 45

What is the maximum number of different Boolean functions involving n Boolean variables? (B) 2n (A) n2 (C) 22
n

(D) 2n

SOLUTION

Each boolean variable can have values involving n boolean variables will have need to be arranged in different manner So this arrangement would take 2M ways Hence (C) is correct option.
Question. 46

0 or 1, so for expression terms 2n . These 2n terms and nos., suppose 2n = M . n or 22 ways.

How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates? (A) 7 (B) 8 (C) 9
SOLUTION

(D) 10

Total output lines required = 64 We need to use 3 to 8 decoders. So decoders required 64 = 8 decoders for output. 8

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But we need one more decoder i.e for combining result. 8 + 1 = 9 decoders. Hence (C) is correct option.
Question. 47

Consider the following Boolean function of four variables f (w, x,, y, z) = / (1, 3, 4, 6, 9, 11, 12, 14) The function is (A) independent of one variable (B) independent of two variables (C) independent of three variables (D) dependent on all the variables
SOLUTION

f (w, x, y, z) = / m (1, 3, 4, 6, 9, 11, 12, 14)

2 qlead xz' 1st qlead nd x'z 2 qlead xz' + x'z xz' + x'z So independent of 2 variables. Hence (B) is correct option.
Question. 48

Let f (w, x, y, z) = / (0, 4, 5, 7, 8, 9, 13, 15). Which of the following expressions are NOT equivalent to f ? (B) w'y'x' + wx'y' + xz (A) x'y'z + w'xy' + wy'z + xz (C) w'y'z' + wx'y' + xyz + xy'z
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(D) x'y'z + wx'y' + w'y

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SOLUTION

CS Topicwise 2001-2010 Digital Logic

f (w, x, y, z) = / m (0, 4, 5, 7, 8, 9, 13, 15) Drawing K-map.

xz + w'y'z' + wx'y' Hence (B) is correct option.

Question. 49

Define the connective* for the boolean variable X and Y as: X * Y = XY + X'Y' Let Z = X * Z Consider the following expression P, Q and R . P: X = Y * ZQ: Y = X * Z R: X * Y * Z = 1 Which of the following is TRUE? (A) only P and Q are valid (B) Only Q and R are valid (C) Only P and R are valid
SOLUTION

(D) All P, Q , R are valid

Given Z = X ) Z & XZ + X'Z' P: X = Y ) Z = YZ + Y'Z' = Y (XZ + X'Z') + Y'Z' = XYZ + X'YZ' + Y'Z' = XYZ + X'YZ' + XY'Z' + X'Y'Z' valid. Q: Y = X ) Z = XZ + X'Z' = X (XZ + X'Z') + X'Z'
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= XZ + X'Z' = X (Y + Y') Z + X' (Y + Y') Z' = XYZ + XY'Z + X'YZ' + X'Y'Z' valid R: X ) Y ) Z = 1 (XY + X'Y') ) Z & (XZ + X'Y') Z + (XY + X'Y') Z' & XYZ + X'Y'Z + [(XY : X'Y') Z'] & XYZ + X'Y'Z + [(X + Y ) : (X + Y)] Z' & XYZ + X'Y'Z + X'YZ' + XY'Z' = Y 1 So invalid Hence (A) is correct option.
Question. 50

Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed? (B) 2n + 1 line to 1 line (A) 2n line to 1 line (C) 2n 1 line to 1 line
SOLUTION

(D) 2n 2 line to 1 line

To select 2n lines we need a select function with n bits. Here with n variables we have (n 1) select bits thus 2n 1 data lines. So MUX has 2n 1 lines to 1. Hence (C) is correct option.
Question. 51

In a look-ahead carry generator, the carry generate function Gi and the carry propagate function Pi for inputs, Ai and Bi are given by Pi = Ai 5 Bi and Gi = Ai Bi The expressions for the sum bit S and carry bit Ci + 1 of the look ahead carry adder are given by Si + Pi 5 Ci and Ci + 1 Gi + Pi Ci , Where C0 is the input carry. Consider a two-level logic implementation of the look-ahead carry generator.. Assume that all Pi and Gi are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with S3, S2, S1, S0 and C4 as its outputs are respectively
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(A) 6,3 (C) 6,4
SOLUTION

CS Topicwise 2001-2010 Digital Logic

(B) 10,4 (D) 10,5

The equation for 4 bit carry look ahead adder is Cout g 3 + p 3 g2 + p 3 p2 g1 + p 3 p2 p1 g 0 + p 3 p2 p1 p 0 Cin Here no. of AND gates = 10 OR gates = 4 Hence (B) is correct option.
Question. 52

The control signal functions of 4-bit binary counter are given below (where X is dont care) Clear Clock Load Count Function 1 0 0 0 X X X 0 1 0 X 0 X 1 Clear to 0 No change Load input Count next

The counter is connected as follows

Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence (A) 0,3,4 (C) 0,1,2,3,4 (B) 0,3,4,5 (D) 0,1,2,3,4,5
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SOLUTION

From the truth table for the counter ckt we can see that when counter = 1. & load = 0 , count next is the function. So it would count from 0 to 4 & then clear to 0 & again start if clock input is increasing. Hence (C) is correct option.
YEAR 2008 Question. 53

In the IEEE floating point representation the hexadecimal value 0x00000000 corresponds to (A) the normalized value 2 127 (C) the normalized value + 0
SOLUTION

(B) the normalized value 2 126 (D) the special value + 0

This 0X00000000 hexadecimal value can be converted into 32 bit binary. 0000 0000 0000 0000 0000 0000 0000 0000 0 # 2c This is representation in IEEE floating point format. Case for special + 0 . Hence (D) is correct option.
Question. 54

In the karnaugh map shown below, X denoted a dont care term. What is the nominal form of the function represented by the karnaugh map

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(A) b.d + a.d

CS Topicwise 2001-2010 Digital Logic

(B) a.b + b.d + a.b.d (D) a.b + b.d + a.d

(C) b.d + a.b.d

SOLUTION

Given K-map is

quad 1 " a b quad 2 " b d pair 1 " a c d So a b + b d + a d (c + c ) a b+b d+a d Hence (D) is correct option.
Question. 55

Let a denote number system radix. The only value(s) of r that satisfy the equation 121 + 11, is/are (A) decimal 10 (B) decimal 11 (C) decimal 10 and 11
SOLUTION

(D) any value> 2

(121) r = (11) r If r = 10 it is true it cant be 2 since bit value cant be 2 then. It is not true for r = 11 It is true for 3 to 10. So it is true for r>2 Hence (D) is correct option.
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Question. 56

Give f1, f3 and f in canonical sum of products form (in decimal) for the circuit

f1 = /m (4, 5, 6, 7, 8) f3 = /m (1, 6, 15) f = /m (1, 6, 8, 15) Then f2 is (A) /m (4, 6) (C) /m (6, 8)
SOLUTION

(B) /m (4, 8) (D) /m (4,6,8)

Given f = m (1, 6, 8, 15) f3 = m (1, 6, 15) So output 1,6,8,15 here 1,6,15 can come form f3 . Since the final gate is OR gate so from f1 AND f2 no minterm except 1,6,8,15 should come. f1 = m (4, 5, 6, 7, 8) So f2 can be m (6, 8) Since 4,5, & 7 should no 7 come here. Hence (C) is correct option.
Question. 57

If P , Q , R are Boolean variables, (P + Q) (P.Q + P.R) (P.R + Q) simplifies to (A) P.Q

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(B) P.R

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(C) P.Q + R
SOLUTION

CS Topicwise 2001-2010 Digital Logic

(D) P.R + Q

= (P + Q ) : (P Q + PR) : (P R + Q) = (PPQ + PPR + PQ Q + PQR) (P R + Q ) = (P Q + PR + PQ + PQR) (P R + Q) = (PQ + PR + PQR) (P R + Q ) = [PQ (1 + R) + PR] (P R + Q) = P (Q + R) (P R + Q ) = (P P R + PQ ) (Q + R) = PQ : (Q + R) = PQ + PQR = PQ (1 + R) = PQ Hence (A) is correct option.
YEAR 2009 Question. 58

(1217) 8 is equivalent to (A) (1217) 16 (C) (2297) 10

SOLUTION

(B) (028F) 16 (D) (0B17) 16

= (1217) 8 = 001010001111 SSS = (028F) 16 Hence (B) is correct option.

Question. 59

What is the minimum number of gates required to implement the Boolean function (AB + C) if we have to use only 2-input NOR gates ? (A) 2 (C) 4 (B) 3 (D) 5
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SOLUTION

AB+C implementation through NOR gate (X + Y ) We require one AND gate & 1 OR gate

AND gate & OR gate can be implemented by NOR gate. = A+C+B+C = A+C:B+C = (A + C) : (B + C) = C + AB So we require & NOR gates. Hence (B) is correct option.
YEAR 2010 Question. 60

The minterm expansion of f (P, Q, R) = PQ + QR + PR is (A) m2 + m 4 + m6 + m1 (B) m 0 + m1 + m 3 + m5 (C) m 0 + m1 + m6 + m1

SOLUTION

(D) m2 + m 3 + m 4 + m5

Given expression is f (P, Q, R) = PQ + QR + PR For min term expansion we add the remaining variables in the expression. = PQ (R + R ) + (P + P ) QR + P (Q + Q ) R = PQR + PQR + PQR + PQR + PQR + PQR = PQR + PQR + PQR + PQ R = m7 + m 6 + m2 + m 4 = 111 + 110 + 010 + 100 So = m2 + m 4 + m6 + m7
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Hence (A) is correct option.
Question. 61

CS Topicwise 2001-2010 Digital Logic

P is a 16-bit signed integer. The 2s complement representation of P is (F87B) 16 . The 2s complement representation of 8)P is (A) (C3D8) 16 (B) (187B) 16 (C) (F878) 16
SOLUTION

(D) (987B) 16

Ps 2s complement. = (F87B) 16 Is complement = F87B 1 = (F87A) 16 In base 16 complement is done by subtracting from 15 i.e F. P = (0785) 16 = (0000 0111 1000 0101) 2 = 1 # 2c + 1 # 22 + 1 # 27 + 1 # 28 + 1 # 29 + 1 # 210 P = 1925 8 # P = 8 # 1925 = 15400 Its binary 0011110000101000 SSSS For hexadecimal make pairs of 4 i.e. (3C28) 16 2s complement P = 1100 0011 1101 1000 C 3 D 8 2s complement of P = (C3D8) 16 Hence (A) is correct option.
Question. 62

The Boolean expression for the output f of the multiplexer shown below is

(A) P 5 Q 5 R

(B) P 5 Q 5 R
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(C) P + Q + R
SOLUTION

(D) P + Q + R

S1 & so are the select bits which are used to select any 1 of the 4 inputs. Selection table S1 (P) S 0 (Q) Input 0 0 1 1 0 1 0 1 0R 1R 2R 3R

The expression has 3 variables So K-map

This is K-map for P 5 Q 5 R i.e PQ R + P Q R + PQR + P QR Hence (B) is correct option.

Question. 63

What is the boolean expression for the output f of the combinational logic circuit of NOR gates given below ?

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(A) Q + R (C) P + R
SOLUTION

CS Topicwise 2001-2010 Digital Logic

(B) P + Q (D) P + Q + R

After 1 stage P+Q Q+R Q+R P+R After 2 stage P+Q+Q+R P+R+Q+R After 3 stage = P+Q+Q+R+P+R+Q+R

"A + B = A : B "A = A

= (P + Q + Q + R ) : (P + R + Q + R )

= (P + Q + Q + R ) : (P + R + Q + R ) "A + B = A : B = (P + Q) : (Q + R) : (P + R) : (Q + R) = Q + PR : R + PQ = Q + PR + R + PQ = R (P + 1) + Q (P + 1) = (Q + R) Hence (A) is correct option.

Question. 64

In the sequential circuit shown below, if the initial value of the output Q1 Q 0 is 00, what are the next four values of Q1 Q 0 ?

(A) 11, 10, 01, 00 (C) 10, 00, 01, 11

SOLUTION

(B) 10, 11, 01, 00 (D) 11, 10, 00, 01

There are 2 T-toggle flip flops in the ckt. Truth table for TFF.
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CP 0 1 1 T X 0 1 Qn + 1 Qn Qn Qn Qn previous state CP clock pulse Qn + 1 next state T toggle input Since initially Q, Q 0 = 00, so during 1st clock cycle both T & clock signals in ckt are 1. After Q 0 = 1 this fed to 2nd TFF which invert previous state Q1 = 1 so Q1 Q 0 = 11 11 when fed to next cycle clock = 1 so Q 0 = 0 Q1 = 1 since no inversion Q, Q 0 = 10 In next cycle clock = 1 Q 0 = 1 inverse, Q1 = 0 in the end Q1 Q 0 = 00 So order 11, 10, 01, 00 Hence (A) is correct option.

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