PC Technical Reference Apr83

LIMITED WARRANTY
The International Business Machines Corporation warrants this IBM Personal

Computer Product to be in good working order for a period of 90 days from the
date of purchase from IBM or an authorized IBM Personal Computer dealer.
Should this Product fail to be in good working order at any time during this
90-day warranty period, IBM will, at its option, repair or replace this Product
at no additional charge except as set forth below. Repair parts and replacement
Products will be furnished on an exchange basis and will be either reconditioned
or new. All replaced parts and Products become the property of IBM. This
limited warranty does not include service to repair damage to the Product
resulting from accident, disaster, misuse, abuse, or non-IBM modification of
the Product.
Limited Warranty service may be obtained by delivering the Product during the
90-day warranty period to an authorized IBM Personal Computer dealer or IBM
Service Center and providing proof of purchase date. If this Product is delivered
by mail, you agree to insure the Product or assume the risk of loss or damage in
transit, to prepay shipping charges to the warranty service location and to use the
original shipping container or equivalent. Contact an authorized IBM Personal
Computer dealer or write to IBM Personal Computer, Sales and Service, P.O.
Box 1328-W, Boca Raton, Florida 33432, for further information.
ALL EXPRESS AND IMPLIED WARRANTIES FOR THIS PRODUCT

INCLUDING THE WARRANTIES OF MERCHANTABILITY AND FITNESS
FORA PARTICULAR PURPOSE, ARE LIMITED IN DURATION TO A
PERIOD OF 90 DAYS FROM THE DATE OF PURCHASE, AND NO
WARRANTIES, WHETHER EXPRESS OR IMPLIED, WILL APPLY AFTER
THIS PERIOD. SOME STATES DO NOT ALLOW LIMITATIONS ON HOW
LONG AN IMPLIED WARRANTY LASTS, SO THE ABOVE LIMITATIONS
MAY NOT APPLY TO YOU.
IF THIS PRODUCT IS NOT IN GOOD WORKING ORDER AS WARRANTED

ABOVE, YOUR SOLE REMEDY SHALL BE REP AIR OR REPLACEMENT
AS PROVIDED ABOVE. IN NO EVENT WILL IBM BE LIABLE TO YOU FOR
ANY DAMAGES, INCLUDING ANY LOST PROFITS, LOST SAVINGS OR
OTHER INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF
THE USE OF OR INABILITY TO USE SUCH PRODUCT, EVEN IF IBM OR
AN AUTHORIZED IBM PERSONAL COMPUTER DEALER HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, OR FOR ANY
CLAIM BY ANY OTHER PARTY.
SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF

INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR CONSUMER
PRODUCTS, SO THE ABOVE LIMITATIONS OR EXCLUSIONS MAY NOT
APPLY TO YOU.
THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS, AND YOU MAY
ALSO HAVE OTHER RIGHTS WHICH MAY VARY FROM STATE TO STATE.
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- - --- Hardware Reference
Library
Technical
Reference
Federal Communications Commission
Radio Frequency Interference Statement
WARNING: This equipment has been certified to comply with

the limits for a Class B computing device,
pursuant to Subpart J of Part 15 of FCC rules.
Only peripherals (computer input/output devices,
terminals, printers, etc.) certified to comply with
the Class B limits may be attached to this
computer. Operation with non-certified
peripherals is likely to result in interference to
radio and TV reception. If peripherals not offered
by IBM are used with this equipment, it is
suggested to use shielded grounded cables with
in-line filters if necessary.
Notice: As sold by the manufacturer, the Prototype card does

not require certification under the FCC's rules for Class B
devices. The user is responsible for any interference to radio or
TV reception which may be caused by a user-modified prototype
card.
CAUTION: This product is equipped with a UL-listed and

CSA-certified plug for the user's safety. It is to be
used in conjunction with a properly grounded
receptacle to avoid electrical shock.
Revised Edition (April 1983)
Changes are periodically made to the information herein; these changes will be
incorporated in new editions of this publication.
Products are not stocked at the address below. Requests for copies of this product and for
technical information about the system should be made to your authorized IBM Personal
Computer dealer.
A Reader's Comment Form is provided at the back of this pUblication. If this form has
been removed, address comments to: IBM Corp., Personal Computer, P.O. Box 1328-C,
Boca Raton, Florida 33432. IBM may use or distribute any of the information you supply
in any way it believes appropriate without incurring any obligations whatever.
© Copyright International Business Machines Corporation, 1981, 1982, 1983
ii
PREFACE
The IBM Personal Computer Technical Reference manual

describes the hardware design and provides interface information
for the IBM Personal Computer. This publication also has
information about the basic input/output system (BIOS) and
programming support.
The information in this pUblication is both introductory and for

reference, and is intended for hardware and software designers,
programmers, engineers, and interested persons who need to
understand the design and operation of the computer.
You should be familiar with the use of the Personal Computer,

and you should understand the concepts of computer architecture
and programming.
This manual has two sections:
"Section 1: Hardware" describes each functional part of the

system. This section also has specifications for power, timing, and
interface. Programming considerations are supported by coding
tables, command codes, and registers.
"Section 2: ROM BIOS and System Usage" describes the basic

input/output system and its use. This section also contains the
software interrupt listing, a BIOS memory map, descriptions of
vectors with special meanings, and a set oflow memory maps. In
addition, keyboard encoding and usage is discussed.
The publication has seven appendixes:
Appendix A: ROM BIOS Listings

Appendix B: 8088 Assembly Instruction Set Reference
Appendix C: Of Characters, Keystrokes, and Color
Appendix D: Logic Diagrams
Appendix E: Specifications
Appendix F: Communications
Appendix G: Switch Settings
A glossary and bibliography are included.
iii
Prerequisite Publication:
Guide to Operations for the IBM Personal Computer

Part Number 6025000
Suggested Reading:
BASIC for the IBM Personal Computer

Part Number 6025010
Disk Operating System (DOS) for the IBM Personal Computer

Part Number 6024061
Hardware Maintenance and Service for the IBM Personal

Computer
Part Number 6025072
MACRO Assembler for the IBM Personal Computer

Part Number 6024002
Related publications are listed in the bibliography.
iv
TABLE OF CONTENTS
Section 1: Hardware
IBM Personal Computer System Unit ................. 1-3
IBM Personal Computer Math Coprocesser ............ 1-33
IBM Keyboard .................................... 1-73
IBM Expansion Unit ............................... 1-79
IBM 80 CPS Printers .............................. 1-91
IBM Printer Adapter ............................... 1-117
IBM Monochrome Display and Printer Adapter ........ 1-123
IBM Monochrome Display .......................... 1-131
IBM Color/Graphics Display Adapter ................ 1-133
IBM Color Display ................................ 1-157
IBM 5-W' Diskette Drive Adapter ................... 1-159
IBM 5-W' Diskette Drive ........................... 1-183
Diskettes ......................................... 1-185
IBM Fixed Disk Drive Adapter ...................... 1-187
IBM 10MB Fixed Disk Drive ....................... 1-203
IBM Memory Expansion Options .................... 1-205
IBM Game Control Adapter. . . . . . . . . . . . . . . . . . . . . . . .. 1-211
IBM Prototype Card ............................... 1-217
IBM Asynchronous Communications Adapter. . . . . . . . .. 1-223
IBM Binary Synchronous Communications Adapter ..... 1-251
IBM Synchronous Data Link Control (SDLC)
Communication Adapter .......................... 1-271
IBM Communications Adapter Cable ................. 1-301
Section 2: ROM BIOS and System Usage

ROM BIOS ....................................... 2-2
Keyboard Encoding and Usage ...................... 2-11
BIOS Cassette Logic ............................... 2-21
Appendix A: ROM BIOS Listings .............. A-I

System BIOS ..................................... A-2
Fixed Disk BIOS .................................. A-85
Appendix B: 8088 Assembly Instruction

Set Reference ................................. B-1
v
Appendix C: Of Characters, Keystrokes,
and Colors .................................... C-l
Appendix D: Logic Diagrams ................... D-l
System Board (16/64K) ............................ D-2
System Board (64/256K) ........................... D-12
Keyboard - Type 1 ................................ D-22
Keyboard - Type 2 ................................ D-24
Expansion Board .................................. D-25
Extender Card .................................... D-26
Receiver Card .................................... D-29
Printer ........................................... D-32
Printer Adapter ................................... D-35
Monochrome Display Adapter ...................... D-36
Color/Graphics Monitor Adapter .................... D-46
Color Display .................................... D-52
Monochrome Display .............................. D-54
5-JA Inch Diskette Drive Adapter .................... D-55
5-JA Inch Diskette Drive - Type 1 ................... D-59
5-JA Inch Diskette Drive - Type 2 ................... D-62
Fixed Disk Drive Adapter .......................... D-64
Fixed Disk Drive - Type 1 ......................... D-70
Fixed Disk Drive - Type 2 ......................... D-73
32K Memory Expansion Option ..................... D-76
64K Memory Expansion Option ..................... D-79
64/256K Memory Expansion Option ................. D-82
Game Control Adapter ............................. D-86
Prototype Card ................................... D-87
Asynchronous Communications Adapter .............. D-88
Binary Synchronous Communications Adapter ......... D-89
SDLC Communications Adapter .................... D-91
Appendix E: Specifications ..................... E-l

Appendix F: Communications .................. F-l
Appendix G: Switch Settings ................... G-l
Glossary ........................................ H-l
Index ............................................ 1-1
vi
INDEX TAB LISTING
Section 1: Hardware ............................. .
Section 2: ROM BIOS and System Usage .......... .
Appendix A: ROM BIOS Listings ................. .
Appendix B: 8088 Assembly Instruction

Set Reference
Appendix C: Of Characters, Keystrokes,

and Color
Appendix D: Logic Diagrams ..................... .
vii
viii
Appendix E: Specifications ....................... .
Appendix F: Communications ..................... .
Appendix G: Switch Settings ...................... .
Glossary ........................................ .
Bibliography ..................................... .
Index ........................................... .
ix
x
SECTION 1: HARDWARE
IBM Personal Computer System Unit ................. 1-3

IBM Personal Computer Math Coprocesser ............ 1-33
IBM Keyboard .................................... 1-73
IBM Expansion Unit ............................... 1-79
IBM 80 CPS Printers .............................. 1-91
IBM Printer Adapter ............................... 1-117
IBM Monochrome Display and Printer Adapter ........ 1-123
IBM Monochrome Display .......................... 1-131
IBM Color/Graphics Display Adapter ................ 1-133
IBM Color Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-157
IBM 5-14" Diskette Drive Adapter ................... 1-159
IBM 5-1A" Diskette Drive ........................... 1-183
Diskettes ......................................... 1-185
IBM Fixed Disk Drive Adapter ...................... 1-187
IBM 10MB Fixed Disk Drive ....................... 1-203
IBM Memory Expansion Options .................... 1-205
IBM Game Control Adapter. . . . . . . . . . . . . . . . . . . . . . . .. 1-211
IBM Prototype Card ............................... 1-217
IBM Asynchronous Communications Adapter .......... 1-223
IBM Binary Synchronous Communications Adapter ..... 1-251
IBM Synchronous Data Link Control (SDLC)
Communication Adapter .......................... 1-271
IBM Communications Adapter Cable ................. 1-301
1-1
SYstem Unit Expansion Unit
System Board Expansion Board
Oscillator
8088 Cassette Oscillator

Adapter
8 Interrupt Speaker
levels Adapter
4 Channels
Direct Memory Keyboard
Access Adapter
Memory Read-Only
Memory
Math
Coproctlssor
(Optional) 8 Slot Expanded
110 Channel
Receiver
Card
5 Slot
110 Channel
Extender Card
Monochrome 0 isplay Monochrome Oisplay Synchronous Data Link Control

and Printer Adapter (SOlC) Adapter
Matrix Printer
Diskette Drive Adapter Diskette Drive(s) Prototype Card
Color Display Game Control Adapter
Light Pen Printer Adapter
Home Television Binary Synchronous
Communications
Adapter
System Block Diagram
1-2 System Unit

IBM Personal Computer System Unit
The system unit is the standalone tabletop unit that contains the
power supply, the speaker, and the system board.
The system unit contains one of two system boards. One system
board supports 16K to 64K of read/write memory. The other
system board supports 64K to 256K of read/write memory. Both
system boards are functionally identical.
The power supply provides dc voltage to the system board and the
internal drive( s).
System Board
The system board fits horizontally in the base of the system unit
and is approximately 8-1/2 by 12 inches. It is a multilayer,
single-Iand-per-channel design with ground and internal planes
provided. DC power and a signal from the power supply enter the
board through two six-pin connectors. Other connectors on the
board are for attaching the keyboard, audio cassette, and speaker.
Five 62-pin card edge-sockets are also mounted on the board. The
I/O channel is bussed across these five I/O slots.
Two dual-in-line package (DIP) switches (two eight-switch packs)

are mounted on the board and can be read under program control.
The DIP switches provide the system software with information
about the installed options, how much storage the system board
has, what type of display adapter is installed, what operation
modes are desired when power is switched on (color or
black-and-white, 80- or 40-character lines), and the number of
diskette drives attached.
The system board consists of five functional areas: the processor

subsystem and its support elements, the read-only memory
(ROM) subsystem, the read/write (RIW) memory subsystem,
integrated I/O adapters, and the I/O channel. All are described
in this section.
System Unit 1· 3
The heart of the system board is the Intel 8088 microprocessor.
This processor is an 8-bit external bus version of Intel's 16-bit
8086 processor, and is software-compatible with the 8086. Thus,
the 8088 supports 16-bit .operations, including multiply and
divide, and supports 20 bits of addressing (1 megabyte of storage).
It also operates in maximum mode, so a co-processor can be
added as a feature. The processor operates at a 4.77 MHz. This
frequency, which is derived from a 14.31818-MHz crystal, is
divided by 3 for the processor clock, and by 4 to obtain the
3.S8-MHz color burst signal required for color televisions.
At the 4.77-MHz clock rate, the 8088 bus cycles are four clocks
of 210 ns, or840 ns.I/O cycles take five 21O-ns clocks or 1.05
microseconds.
The processor is supported by a set of high-function support

devices providing four channels of 20-bit direct-memory access
(DMA), three 16-bit timer-counter channels, and eight prioritized
interrupt levels.
Three of the four DMA channels are available on the I/O bus and
support high-speed data transfers between I/O devices and
memory without processor intervention. The fourth DMA channel
is programmed to refresh the system dynamic memory. This is
done by programming a channel of the timer-counter device to
periodically request a dummy DMA transfer. This action creates
a memory-read cycle, which is available to refresh dynamic
storage both on the system board and in the system expansion
slots. All DMA data transfers, except the refresh channel, take
five processor clocks of 210 ns, or 1.05 Jls if the
processor-ready line is not deactivated. Refresh DMA cycles take
four clocks or 840 ns.
The three programmable timer/counters are used by the system as

follows: Channel 0 is used as a general-purpose timer providing a
constant time base for implementing a time-of-day clock; Channel
1 is used to time and request refresh cycles from the DMA
channel; and Channel 2 is used to support the tone generation for
the audio speaker. Each channel has a minimum timing resolution
of 1.05 us.
1-4 System Unit

Of the eight prioritized levels of interrupt, six are bussed to the
system expansion slots for use by feature cards. Two levels are
used on the system board. Level 0, the highest priority, is attached
to Channel 0 of the timer/counter and provides a periodic
interrupt for the time-of-day clock. Level 1 is attached to the
keyboard adapter circuits and receives an interrupt for each scan
code sent by the keyboard. The non-maskable interrupt (NMI) of
the 8088 is used to report memory parity errors.
The system board supports both ROM and R/W memory. It has
space for 48K x 8 of ROM or EPROM. Six module sockets are
provided, each of which can accept an 8K by 8 byte device. Five
of the sockets are populated with 40K bytes of ROM. This ROM
contains the cassette BASIC interpreter, cassette operating
system, power-on self-test, I/O drivers, dot patterns for 128
characters in graphics mode, and a diskette bootstrap loader. The
ROM is packaged in 24-pin modules and has an access time of
250 ns and a cycle time of 375 ns.
The difference between the R/W memory on the two system

boards is shown in the following chart.
System Board Minimum Maximum Memory Soldered Pluggable

Storage Storage Modules (Bank 0) (Bank 1·3)
16K by 1 Bank 3 Banks

16/64K 16K 64K 1 Bit of 9 of 9
64K by 1 Bank 3 Banks

64/256K 64K 256K 1 Bit of 9 of 9
Memory greater than either system board's maximum is obtained

by adding memory cards in the expansion slots. All memory is
parity-checked and consists of dynamic 16K by 1 bit or (64K by
1 bit) chips with an access time of 250 ns and a cycle time of
410 ns.
System Unit 1·5

The system board contains circuits for attaching an audio cassette,
the keyboard, and the speaker. The cassette adapter allows the
attachment of any good quality audio cassette through the
earphone output and either the microphone or auxiliary inputs.
The system board has a jumper for either input. This interface
also provides a cassette motor control line for transport starting
and stopping under program control. This interface reads and
writes the audio cassette at a data rate of between 1,000 and
2,000 baud. The baud rate is variable and dependent on data
content, because a different bit-cell time is used for O's and 1'so
For diagnostic purposes, the tape interface can loop read to write
for testing the system board's circuits. The ROM cassette
software blocks cassette data and generates a cyclic redundancy
check (CRC) to check this data.
The system board contains the adapter circuits for attaching the
serial interface from the keyboard. These circuits generate an
interrupt to the processor when a complete scan code is received.
The interface can request execution of a diagnostic test in the
keyboard.
Both the keyboard and cassette interfaces are 5-pin DIN

connectors on the system board that extend through the rear panel
of the system unit.
The system unit has a 2-1/4 inch audio speaker. The speaker's
control circuits and driver are on the system board. The speaker
connects through a 2-wire interface that attaches to a 3-pin
connector on the system board.
The speaker drive circuit is capable of approximately 1/2 watt of

power. The control circuits allow the speaker to be driven three
different ways: 1.) a direct program control register bit may be
toggled to generate a pulse train; 2.) the output from Channel 2 of
the timer counter may be programmed to generate a waveform to
the speaker; 3.) the clock input to the timer counter can be
modulated with a program-controlled I/O register bit. All three
methods may be performed simultaneously.
1-6 System Unit

Number Usage
NMI Parity
0 Timer
1 Keyboard
2 Reserved
3 Asynchronous Communications (Secondary)
SDLC Communications
BSC (Secondary)
4 Asynchronous Communications (Primary)
SDLC Communications
BSC (Primary)
5 Fixed Disk
6 Diskette
7 Printer
8088 Hardware Interrupt Listing
System Unit 1-11

PAO +Keyboard Scan Code 0
-- r--
IPL 5-1/4 Diskette Drive (SW1-1)
Hex
Port I 1 1 Reserved (SW1-2)
Number N 2 2 System Board Read/Write *(SW1-3)
0060 P Memory Size
U 3 3 System Board Read/Write *(SW1-4)
T Or Memory Size
4 4 +Display Type 1 **(SW1-5)
5 5 +Display Type 2 **(SW1-6)
6 6 No. of 5-1/4 Drives ***(SW1-7)
7 ~ ~. of 5-1/4 Drives ***(SW1-8)
PBO +Timer 2 Gate Speaker
o 1 +Speaker Data
U 2 +(Read Read/Write Memory Size) or (Read Spare Key)
0061 T 3 +Cassette Motor Off
P 4 -Enable Read/Write Memory
U 5 -Enable I/O Channel Check
T 6 -Hold Keyboard Clock Low
7 -(Enable Keyboard) or + (Clear Keyboard and Enable Sense Switches)
PCO I/O Read/Write Memory (SW2-1)]- ] [I/O Read/
I 1 I/O Read/Write Memory (Sw2-2) Binary Or Write
N 2 I/O Read/Write Memory (Sw2-3) Value Memory
0062 P 3 I/O Read/Write Memory (Sw2-4) X 32K (Sw2-5)
U 4 +Cassette Data In
T 5 +Timer Channel 2 Out
6 +1/0 Channel Check
7 +Read /Write Memory Parity Check
0063 Command/Mode Register
Hex 99
Mode Register Value 17 6 5 4 3 2 1 0 1
~--------------~
11 0 0 1 1 0 0 1 1
PA3 PA2 Amount of Memory

Sw1-4 Sw1-3 Located on System Board
0 0 16K
0 1 32K
1 0 48K
1 1 64 to 256K
PA5 PA4 Display at Power-Up Mode

Sw1-6 Sw1-5
0 0 Reserved
0 1 Color 40 X 25 (BW Mode)
1 0 Color 80 X 25 (BW Mode)
1 1 IBM Monochrome (80 X 25)
PA7 PA6 Number of 5-1/4" Drives

Swl-8 Swl-7 in System
0 0 1
0 1 2
1 0 3
1 1 4
Note: A plus (+) indicates a bit value of 1 performs the specified function.
A minus (-) indicates a bit value of 0 performs the specified function.
PA Bit = 0 implies switch "ON." PA bit = 1 implies switch "OFF."
8255A I/O Bit Map
1-12 System Unit

Start Ad dress
Decimal Hex Function
0 00000
16K 04000 16 to 64K Read/Write Memory
32K 08000 on System Board
48K OCOOO
64K 10000
80K 14000
96K 18000
112K lCOOO
128K 20000
144K 24000
160K 28000
176K 2COOO
192K 30000
208K 34000
224K 38000
240K 3COOO Up to 576K Read/Write
256K 40000 Memory in I/O Channel
272K 44000
288K 48000
304K 4COOO
320K 50000
336K 54000
352K 58000
368K 5COOO
384K 60000
400K 64000
416K 68000
432K 6COOO
448K 70000
464K 74000
480K 78000
496K 7COOO
512K 80000
528K 84000
544K 88000
560K 8COOO
576K 90000
592K 94000
608K 98000
624K 9COOO
System Memory Map for 16/64K System Board (Part 1 of 2)
System Unit 1-13

Sta rt Add ress
640K AOOOO
656K A4000 128K Reserved
672K A800D
688K ACOOO
704K BOOOO Monochrome
720K B4000
736K B8000 Color/Graphics
752K BCOOO
768K COOOO
784K C4000
800K C8ODO Fixed Disk Control
816K CCOOO
832K 00000
848K 04000 192K Read Only Memory
864K 08000 Expansion and Control
880K OCOOO
896K EOOOO
912K E4000
928K E8000
944K ECOOO
960K FOOOO Reserved
976K F4000
992K F8000 48K Base System ROM
100BK FCOOO
1-14 System Unit

Start Address
0 00000
16K 04000
32K 08000
48K OCOOO
64K 10000
80K 14000
96K 18000
112K lCOOO 64 to 256K Read/Write Memory
128K 20000 on System Board
144K 24000
160K 28000
176K 2COOO
192K 30000
208K 34000
224K 38000
240K 3COOO
256K 40000
272K 44000
288K 48000
304K 4COOO
320K 50000
336K 54000
352K 58000
368K 5COOO
384K 60000
400K 64000
416K 68000 Up to 384K Read/Write
432K 6COOO Memory in I/O Channel
Up to 384K in I/O Channel
448K 70000
464K 74000
480K 78000
496K 7COOO
512K 80000
528K 84000
544K 88000
560K 8COOO
576K 90000
592K 94000
608K 98000
624K 9COOO
System Unit 1-15

Start Address
640K A 0000
656K A4000
128K Reserved
672K A8oo0
688K ACooO
704K 80000 Monochrome
720K B4000
736K B8000 Color/Graphics
752K BCooO
768K COOOO
784K C4000
800K C8000 Fixed Oisk Control
816K CCOOO
832K 00000
848K 04000 192K Read Only Memory
864K 08000 Expansion and Control
880K OCOOO
896K EOOOO
912K E4000
928K E8oo0
944K ECOoo
960K FooOO Reserved
976K F4000
992K F8000 48K Base System ROM
1oo8K FCOOO
System Board Switch Settings

All system board switch settings for total system memory, number
of diskette drives, and type of display adapter are located in
"Appendix G: Switch Settings."
1-16 System Unit

I/O Channel
The I/O channel is an extension of the 8088 microprocessor bus.
It is, however, demultiplexed, repowered, and enhanced by the
addition of interrupts and direct memory access (DMA) functions.
The I/O channel contains an 8-bit, bidirectional data bus, 20

address lines, 6 levels of interrupt, control lines for memory and
I/O read or write, clock and timing lines, 3 channels of DMA
control lines, memory refresh timing control lines, a
channel-check line, and power and ground for the adapters. Four
voltage levels are provided for I/O cards: +5 Vdc, -5 Vdc, +12
Vdc, and -12 Vdc. These functions are provided in a 62-pin
connector with 100-mil card tab spacing.
A 'ready' line is available on the I/O channel to allow operation

with slow I/O or memory devices. If the channel's ready line is
not activated by an addressed device, all processor-generated
memory read and write cycles take four 210-ns clock or 840-ns/
byte. All processor-generated I/O read and write cycles require
five clocks for a cycle time of 1.05 ,us/byte. All DMA transfers
require five clocks for a cycle time of 1.05 p,s/byte. Refresh cycles
occur once every 72 clocks (approximately 15 ,us) and require
four clocks or approximately 7% of the bus bandwidth.
I/O devices are addressed using I/O mapped address space. The
channel is designed so that 512 I/O device addresses are
available to the I/O channel cards.
A 'channel check' line exists for reporting error conditions to the

processor. Activating this line results in a Non-Maskable Interrupt
(NMI) to the 8088 processor. Memory expansion options use this
line to report parity errors.
The I/O channel is repowered to provide sufficient drive to power

all five system unit expansion slots, assuming two low-power
Schottky loads per slot. The IBM I/O adapters typically use only
one load.
The following pages describe the system board's I/O channel.
System Unit 1-17

Rear Panel
Signal Name \ Signal Name

.--- A1- r--
GND -81 -I/O CH CK
+RESET DRV - - +07
+5V - - +06
+IRQ2 - - +D5
-5VDC - - +04
+DRQ2 ~ - +D3
-12V ~ - +02
Reserved t-- - +01
+12V ~ - +00
GND 810 A10 +1/0 CH RDY
-MEMW t-- - +AEN
-MEMR ~ - +A19
-lOW t-- - +A18
-lOR t-- - +A17
-DACK3 ~ - +A16
+DRQ3 t-- - +A15
-DACK1 I- - +A14
+DRQ1 ~ - +A13
-DACKO I- - +A12
CLOCK 820 A20 +A11
+IRQ7 ~ - +A10
+IRQ6 I- - +A9
+IRQ5 I- - +A8
+IRQ4 ~ - +A7
+IRQ3 I- - +A6
-DACK2 I- - +A5
H/C ~ - +A4
+ALE I- - +A3
+5V I- - +A2
+OSC ~ - +A1
+GND 831 A31 +AO
~ '--
\ \ Comp onent Side
I/O Channel Diagram
1-18 System Unit

I/O Channel Description
The following is a description of the IBM Personal Computer I/O
Channel. All lines are TTL-compatible.
Signal I/O Description

OSC o Oscillator: High-speed clock with a 70-ns
period (14.31818 MHz). It has a 50%
duty cycle.
CLK o System clock: It is a divide-by-three of the

oscillator and has a period of 210 ns (4.77
MHz). The clock has a 33% duty cycle.
RESETDRV 0 This line is used to reset or initialize

system logic upon power-up or during a
low line voltage outage. This signal is
synchronized to the falling edge of clock
and is active high.
AO-AI9 o Address bits 0 to 19: These lines are used

to address memory and I/O devices within
the system. The 20 address lines allow
access of up to 1 megabyte of memory. AO
is the least significant bit (LSB) and A19 is
the most significant bit (MSB). These lines
are generated by either the processor or
DMA controller. They are active high.
DO-D7 I/O Data Bits 0 to 7: These lines provide data

bus bits 0 to 7 for the processor, memory,
and I/O devices. DO is the least significant
bit (LSB) and D7 is the most significant bit
(MSB). These lines are active high.
System Unit 1-19

ALE o Address Latch Enable: This line is
provided by the 8288 Bus Controller and is
used on the system board to latch valid
addresses from the processor. It is
available to the I/O channel as an indicator
of a valid processor address (when used
with AEN). Processor addresses are
latched with the failing edge of ALE.
I/OCHCK I -I/O Channel Check: This line provides

the processor with parity (error)
information on memory or devices in the
I/O channel. When this signal is active
low, a parity error is indicated.
I/OCHRDY I I/O Channel Ready: This line, normally

high (ready), is pulled low (not ready) by a
memory or I/O device to lengthen I/O or
memory cycles. It allows slower devices to
attach to the I/O channel with a minimum
of difficulty. Any slow device using this
line should drive it low immediately upon
detecting a valid address and a read or
write command. This line should never be
held low longer than 10 clock cycles.
Machine cycles (I/O or memory) are
extended by an integral number of CLK
cycles (210 ns).
IRQ2-IRQ7 I Interrupt Request 2 to 7: These lines are

used to signal the processor that an I/O
device requires attention. They are
prioritized with IRQ2 as the highest
priority and IRQ7 as the lowest. An
Interrupt Request is generated by raising
an IRQ line (low to high) and holding it
high until it is acknowledged by the
processor (interrupt service routine).
1-20 System Unit

lOR o -I/O Read Command: This command line
instructs an I/O device to drive its data
onto the data bus. It may be driven by the
processor or the DMA controller.
This signal is active low.
o -I/O Write Command: This command line

instructs an I/O device to read the data on
the data bus. It may be driven by the
processor or the DMA controller. This
signal is active low.
MEMR o Memory Read Command: This command

line instructs the memory to drive its data
onto the data bus. It may be driven by the
processor or the DMA controller. This
signal is active low.
MEMW o Memory Write Command: This command

line instructs the memory to store the data
present on the data bus. It may be driven
by the processor or the D MA controller.
This signal is active low.
DRQI-DRQ3 I DMA Request 1 to 3: These lines are

asynchronous channel requests used by
peripheral devices to gain DMA service.
They are prioritized with DRQ3 being the
lowest and DRQl being the highest. A
request is generated by bringing a DRQ
line to an active level (high). A DRQ line
must be held high until the corresponding
DACK line goes active.
DACKO- o -DMA Acknowledge 0 to 3: These lines

DACK3 are used to acknowledge DMA requests
(DRQI-DRQ3) and to refresh system
dynamic memory (DACKO). They are
active low.
System Unit 1-21

AEN o Address Enable: This line is used to

de-gate the processor and other devices
from the I/O channel to allow DMA
transfers to take place. When this line is
active (high), the DMA controller has
control of the address bus, data bus, read
command lines (memory and I/O), and the
write command lines (memory and I/O).
T/C o Terminal Count: This line provides a pulse

when the terminal count for any DMA
channel is reached. This signal is active
high.
The following voltages are available on the system board I/O

channel:
+5 Vdc +5%, located on 2 connector pins

-5 Vdc +10%, located on 1 connector pin
+12 Vdc +5%, located on 1 connector pin
-12 Vdc + 10%, located on 1 connector pin
GND (Ground), located on 3 connector pins
1-22 System Unit

Speaker Interface
The sound system has a small, permanent-magnet, 2-1/4 inch
)peaker. The speaker can be driven from one or both of two
)ources:
• An 8255A-5 PPI output bit. The address and bit are defined
in the "I/O Address Map."
• A timer clock channel, the output of which is programmable

within the functions of the 8253-5 timer when using a
1.19-MHz clock input. The timer gate also is controlled by an
8255A-5 PPI output-port bit. Address and bit assignment are
in the "I/O Address Map."
PPI Bit 1.110 Address Hex 0061_

1.19 MHz
AND
Clock Low To
In 2
Timer Clock Out 2 r- I-- Driver - Pass "Speaker
Gate 2 Filter
PPI Bit O. I/O Address Hex 0061
Speaker Drive System Block Diagram
Channel 2 (Tone generation for speaker)

Gate 2 - Controller by 8255A-5 PPI Bit
(See I/O Map)
Clock In 2 - 1.19318 - MHz ose
Clock Out 2 - Used to drive speaker
Speaker Tone Generation
The speaker connection is a 4-pin Berg connector. See "System

Board Component Diagram," earlier in this section, for speaker
connection or placement.
Pin Function
1 Data
2 Key
3 Ground
4 +5 Volts
Speaker Connector
System Unit 1-23
Power Supply
The system power supply is located at the right rear of the system
unit. It is designed to be an integral part of the system-unit
chassis. Its housing provides support for the rear panel, and its fan
furnishes cooling for the whole system.
It supplies the power and reset signal necessary for the operation
of the system board, install able options, and the keyboard. It also
provides a switched ac socket for the IBM Monochrome Display
and two separate connectors for power to the 5-1/4 inch diskette
drives.
It is a dc-switching power supply designed for continuous

operation at 63.5 watts. It has a fused 120-Vac input and provides
four regulated dc output voltages: 7 A of +5 Vdc, 2 A of + 12
Vdc, 0.3 A of -5 Vdc, and 0.25 A of -12 Vdc. These outputs
are over-voltage, over-current, open-circuit, and short-circuit
protected. If a dc overload or over-voltage condition occurs, all dc
outputs are shut down as long as the condition exists.
The + 5 Vdc powers the logic on the system board and the
diskette drives and allows approximately 4 A of +5 Vdc for the
adapters in the system-unit expansion slots. The + 12 Vdc power
level is designed to power the system's dynamic memory and the
two internal 5-1/4 inch diskette drive motors. It is assumed that
only one drive is active at a time. The - 5 Vdc level is designed
for dynamic memory bias voltage; it tracks the + 5 Vdc and + 12
Vdc very quickly at power-on and has a longer decay on power-off
than the +5 Vdc and + 12 Vdc outputs. The + 12 Vdc and -12
Vdc are used for powering the EIA drivers on the communications
adapters. All four power levels are bussed across the five
system-unit expansion slots.
1-24 System Unit

Operating Characteristics
Input Requirements
The following are the input requirements for the system unit
power supply.
Frequency Current
Voltage (Vac) (Hz) (Amps)
Nominal Minimum Maximum +/·3Hz Maximum
120 104 127 60 2.5 at 104 Vac
Vdc Output
The following are the dc outputs for the system unit power supply.
Voltage
(Vdc) Current (Amps) Regulation (Tolerance)
Nominal Minimum Maximum +% -%
+5.0 2.3 7.0 5 4

-5.0 0.0 0.3 10 8
+12.0 0.4 2.0 5 4
-12.0 0.0 0.25 10 9
Vac Output
The power supply provides a filtered, ac output that is switched on
and off with the main power switch. The maximum current
available at this output is 0.75 A. The receptic1e provided at the
rear of the power supply for this ac output is· a nonstandard
connector designed to be used only for the IBM Monochrome
Display.
System Unit 1-25

Power Supply Connectors and Pin
Assignments
The power connector on the system board is a 12-pin male
connector that plugs into the power-supply connectors. The pin
configurations and locations are shown below:
c: c: c: c: c: c: c: c:
a:: a:: a:: a:: a:: a:: a:: a::
<II
Q)
.:::
...o
(.)
o
Q)
c:
Q)
o c:
III 0
t:
~
en
~ 0 E
Q) Q)
.~ t) ti :t:
Cl ~ > 0
(J)Q.
.s: c:
(.) 0
Eu
~ Q;
..., 0:t:
L!lQ.
Power Supply and Connectors
1-26 System Unit

Over-Voltage/Over-Current Protection
The system power supply employs protection features which are
described below.
Primary (Input)
The following table describes the primary (input voltage)
protection for the system-unit power supply.
Voltage (Nominal Vac) Type Protection Rating (Amps)
120 Fuse 2
Secondary (Output)
On over-voltage, the power supply is designed to shut down all
outputs when either the +5 Vdc or the +12 Vdc output exceeds
200% of its maximum rated voltage. On over-current, the supply
will turn off if any output exceeds 130% of its nominal value.
Power-Good Signal
When the power supply is turned on after it has been off for a
minimum of 5 seconds, it generates a power-good signal which
indicates that there is adequate power for processing. When the
four output voltages are above the minimum sense levels, as
described below, the signal sequences to a TTL-compatible up
level (2.4 Vdc to 5.5 Vdc), which is capable of sourcing 60 /LA.
When any of the four output voltages is below its minimum sense
level or above its maximum sense level, the power good signal will
be a TTL-compatible down level (0.0 Vdc to 0.4 Vdc) capable of
sourcing 500 /LA. The power good signal has a turn-on delay of
100 ms after the output voltages. have reached their respective
minimum sense levels.
System Unit 1-27

Output Under-Voltage Over-Voltage
Voltage Nominal Sense level Nominal Sense level
+5 Vdc +4.0 Vdc +5.9 Vdc

-5 Vdc -4.0 Vdc -5.9 Vdc
+12 Vdc +9.6 Vdc +14.2 Vdc
-12 Vdc -9.6 Vdc -14.2Vdc
Cassette Interface
The cassette interface is controlled through software. An output
from the 8253 timer controls the data to the cassette recorder
through pin 5 of the cassette DIN connector at the rear of the
system board. The cassette input data is read by an input port bit
of the 8255A-5 programmable peripheral interface (8255A-5
PPI). This data is received through pin 4 of the cassette
connector. Software algorithms are used to generate and read
cassette data. The cassette drive motor is controlled through pins
1 and 3 of the cassette connector. The drive motor on/off
switching is controlled by an 8255A-5 PPI output-port bit
(hex 61, bit 3). The 8255A-5 address and bit assignments are
defined in "I/O Address Map" earlier in this section.
A 2 by 2 Berg pin and a jumper are used on the cassette 'data out'
line. The jumper allows use of the 'data out' line as a O.075-Vdc
microphone input when placed across the M and C pins of the
Berg connector. A O.68-Vdc auxiliary input to the cassette
recorder is· available when the jumper is placed across the A and
C pins of the Berg connector. The "System Board Component
Diagram" shows the location of the cassette Berg pins.
M A M A
c c c c
Microphone Input Auxiliary Input
(0.075 Vdc) (0.68 Vdc)
1-28 System Unit

Cassette Circuit Block Diagrams
Circuit block diagrams for the cassette-interface read hardware,
write hardware, and motor control are illustrated below.
-5V
Silicon
GND Diode
Data From VIR=.4V Cathode
Cassette
Recorder
GND
Earphone
Jack
Cassette Interface Read Hardware Block Diagram
+5V
74lS38
8253 Timer # 2 t O
Output OR
o
0----------------.
0.678V
toAUX
Input
0----------------·
O.075V
to MIC
Input
GND
Cassette Interface Write Hardware Block Diagram
System Unit 1-29

+5V
I +5V
4.7k
Ohm SN75475 Relay
+5V- Clamp N/O

S Coil
C 1---4 t Cassette
~8 Motor
VCC r--
OR Control
In Out Coil
Motor-[O
On 0 Com
~
I
GND
VSS
Cassette Motor Control Block Diagram
1-30 System Unit

Rear Panel
5-Pin DIN Connector
Pin Signal Electrical Characteristics

1 Motor Control Common from Relay
2 Ground
3 Motor Control Relay N.O. (6 Vdc at 1A)
4 Data In 500nA at ±13V - at 1,000 - 2,000 Baud
5 Data Out (Microphone or 250 f.1A at 0.68 Vdc
Auxiliary) or **
0.075 Vdc
*AII voltages and currents are maximum ratings and should not be exceeded.
**Data out can be chosen using a jumper located on the system board.
(Auxiliary - 0.68 Vdc or Microphone - 0.075 Vdc).
Interchange of these voltages on the cassette recorder could lead to damage
of recorder inputs.
Cassette Interface Connector Specifications
System Unit 1-31

Notes:
1-32 System Unit

IBM Personal Computer Math
Coprocessor
The IBM Personal Computer Math Coprocessor enables the IBM

Personal Computer to perform high speed arithmetic, logarithmic
functions, and trigonometric operations with extreme accuracy.
The coprocessor works in parallel with the processor. The parallel

operation decreases operation time by allowing the coprocessor to
do mathematical calculations while the processor continues to do
other functions.
The first five bits of every instruction opcode for the coprocessor
are identical (11011 binary). When the processor and the
coprocessor see this instruction opcode, the processor calculates
the address, of any variables in memory, while the coprocessor
checks the instruction. The coprocessor will then take the memory
address from the processor if necessary. To access locations in
memory, the coprocessor takes the local bus from the processor
when the processor finishes its current instruction. When the
coprocessor is finished with the memory transfer, it returns the
local bus to the processor.
The IBM Math Coprocessor works with seven numeric data types
divided into the three classes listed below.
• Binary integers (3 types)
• Decimal integers (1 type)
• Real numbers (3 types)
Coprocessor 1-33
Programming Interface
The coprocessor extends the datatypes, registers, and instructions
to the processor.
The coprocessor has eight 80-bit registers which provide the

equivalent capacity of 40 16-bit registers found in the processor.
This register space allows constants and temporary results to be
held in regjsters during calculations, thus reducing memory access
and improving speed as well as bus availability. The register space
can be used as a stack or as a fIxed register set. When used as Ii
stack, only the top two stack elements are operated on: when used
as a fIxed register set, all registers are operated on. The Figure
below shows representations of large and small numbers in each
data type.
Data Type Bits Significant Approximate Range (decimal)

Digits (Decimal)
Word Integer 16 4 ·32,768o;;;;Xo;;;;+32,767
Sh ort Integer 32 9 ·2x10 9 O;;;;Xo;;;;+2x10 9
Long Integer 64 18 ·9x10 18 o;;;;Xo;;;;+9x10 18
Packed Decimal 80 18 ·99 ...99O;;;;Xo;;;;+99 ... 99 (18 digits)
Short Real* 32 6·7 8.43x1 0- 37 0;;;; IX 10;;;; 3.37x1 038
Long Real* 64 15-16 4.19x10- 307 o;;;;:X:o;;;;1.67x10 3ffi
Temporary Real 80 19 3.4x 10- 4932 0;;;; IX: 0;;;; 1.2x 104932
*The short and long real data types correspond to the single and double precision
data types
Data Types
1-34 Coprocessor
Hardware Interface
The coprocessor utilizes the same clock generator and system bus
interface components as the processor. The coprocessor is wired
directly into the processor, as shown in the coprocessor
interconnection diagram. The processor's queue status lines (QSO
and QS 1) enable the coprocessor to obtain and decode
instructions simultaneously with the processor. The coprocessor's
busy signal informs the processor that it is executing; the
processor's WAIT instruction forces the processor to wait until
the coprocessor is finished executing (wait for NOT BUSY).
When an incorrect instruction is sent to the coprocessor (for

example; divide by zero or load a full register), the coprocessor
can signal the processor with an interrupt. There are three
conditions that will disable the coprocessor interrupt to the
processor:
1. Exception and Interrupt Enable bits of the control word are

set to 1'so
2. System board switch block 1 switch 2 set in the On position.
3. NMI Mask REG is set to zero.
At power-on time the NMI Mask REG is cleared to disable the

NMI. Any software using the coprocessor's interrupt capability
must ensure that conditions 2 and 3 are never met during the
operation of the software or an "Endless Wait" will occur. An
"Endless Wait" will have the processor waiting for the "Not
Busy" signal from the coprocessor while the coprocessor is
waiting for the processor to interrupt.
Because a memory parity error may also cause an interrupt to the

8088 NMI line, the program should check that a parity error did
not occur (by reading the 8255 port), then clear exceptions by
executing the FNSAVE or the FNCLEX instruction. In most
cases, the status word would be looked at, and the exception
would be identified and acted upon.
Coprocessor 1-35
The NMI Mask REG and the coprocessors interrupt are tied to
the NMI line through the NMI interrupt logic. Minor conversions
of software designed for use with an 8087 must be made before
existing software will be compatible with the IBM Personal
Computer Math Coprocessor.
Memory NMI 1--""" NMI

and NMIINT
System Logic
Board 8088
INT Family Multimaster
Bus System
Interface Bus
Components
8284
Clock
Generator
ClKI--+-----'----'~ CLK Math
Coprocessor
'------lINT
RU/GTt
Coprocessor Interconnection
1-36 Coprocessor
Control Unit
The control unit (CU) of the coprocessor and the processor fetch
all instructions at the same time, as well as every byte of the
instruction stream at the same time. The simultaneous fetching
allows the coprocessor to know what the processor is doing at all
times. This is necessary to keep a coprocessor instruction from
going unnoticed. Coprocessor instructions are mixed with
processor instructions in a single data stream. To aid the
coprocessor in tracking the processor, nine status lines are
interconnected (Q80, Q81, and 80 through 86).
I
r-....&....--.I
I
I
I
I
Data"'-+-...-.l~
I
I
I
! I
Status
Addressing & ! Reg;"" Stack I
~
Bus Tracking
I I
Address
I I ~:~:~:::n 0 (D) I
r-- ----I
L _____ l __________ _ BO BIts J
Coprocessor Block Diagram
Coprocessor 1-37
Register Stack
Each of the eight registers in the coprocessor's register stack is 80
bits wide, and each is divided into the "fields" shown in the figure
below. The format in the figure below corresponds to the
coprocessor's temporary real data type that is used for all
calculations.
The ST field in the status word identifies the current top-of-stack

register. A load ("push") operation decreases ST by 1 and loads a
new value into the top register. A store operation stores the value
from the current top register and then increases ST by 1. Thus,
the coprocessor's register stack grows "down" toward
lower-addressed registers.
Instructions may address registers either implicitly or explicitly.

Instructions that operate at the top of the stack, implicitly address
the register pointed to by ST. The instruction, FSQRT, replaces
the number at the top with its square root; this instruction takes no
operands, because the top-of-stack register is implied as the
operand. Other instructions specify the register that is to be used.
Explicit register addressing is "top-relative." The expression, ST,
denotes the current stack top, and ST(i) refers to the ith register
from the ST in the stack. If ST contains "binary all" (register 3
is at the top ofthe stack), the instruction, FADD ST,ST(2),
would add registers 3 and 5.
Passing subroutine parameters to the register stack eliminates the

need for the subroutine to know which registers actually contain
the parameters. This allows different routines to call the same
subroutine without having to observe a convention for passing
parameters in dedicated registers. As long as the stack is not full,
each routine simply loads the parameters to the stack and calls the
subroutine.
79 64 63 o
I( Exponent Significand
Sign
Register Structure
1-38 Coprocessor
Status Word
The status word reflects the overall condition of the coprocessor.
It may be stored in memory with a coprocessor instruction then
inspected with a processor code. The status word is divided into
the fields shown in the figure below. Bit 15 (BUSY) indicates
when the coprocessor is executing an instruction (B= 1) or when it
is idle (B=O).
Several instructions (for example, the comparison instructions)

post their results to the condition code (bits 14 and 10 through 8
of the status word). The main use of the condition code is for
conditional branching. This may be accomplished by first
executing an instruction that sets the condition code, then storing
the status word in memory, and then examining the condition code
with processor instructions.
Bits 13 through 11 of the status word point to the coprocessor

register that is the current stack top (ST). Bit 7 is the interrupt
request field, and bits 5 through 0 are set to indicate that the
numeric execution unit has detected an exception while executing
the instruction.
15 7 0
ST [CZICllcoIIR[ IPEluEloEIZEloEllEI
-'-~ Exception Flags (1 = Exception Has Occurred)
IJ~
Invalid Operation
Denormalized Operand
Zerodivide
Overflow
Underflow
Precision
(Reserved)
Interrupt Request
Condition Code
Stack Top Pointer (1)
Busy
(11 ST values:
000 = register 0 is stack top
Status Word Format
Coprocessor 1-39
Control Word
The coprocessor provides several options that, are selected by
loading a control word register.
15 o
I I I I
-,-- -~ -,- Exception Masks (1 = Exception is Masked)
~
Invalid Operation
Oenormalized Operand
Zerodivide
Overflow
Underflow
Precision
(Reserved)
Interrupt-Enable Mask (1)
Precision Control(2)
Rounding Control(3)
Infinity Control(4)
(Reserved)
(1) Interrupt-Enable Mask:

0= Interrupts Enabled
1 = Interrupts Disabled (Masked)
(2) Precision Control:
00 = 24 bits
01 = (reserved)
10 = 53 bits
11 = 64 bits
(3) Rounding Control:
00 = Round to Nearest or Even
01 = Round Down (toward co)
10 = Round Up (toward co)
11 = Chop (Truncate Toward Zero)
(4) Infinity Control:
o= Projective
1 = Affine
Control Word Format
1-40 Coprocessor
Tag Word
The tag word marks the content of each register, as shown in the
Figure below. The main function of the tag word is to optimize the
coprocessor's performance under certain circumstances, and
programmers ordinarily need not be concerned with it.
Tag values:
00 = Valid (Normal or Unnormal)
01 = Zero (True)
10 = Special (Not-A-Number, 00, or Denormal)
11 = Empty
Tag Word Format
Exception Pointers
The exception pointers in the figure below are provided for
user-written exception handlers. When the coprocessor executes
an instruction, the control unit saves the instruction address and
the instruction opcode in the exception pointer registers. An
exception handler subroutine can store these pointers in memory
and determine which instruction caused the exception.
I OPERAND ADDRESS(1)
I INSTRUCTION OPCODE(2)
I INSTRUCTION ADDRESS(1)
10 o
(1 )20-bit physical address
(2) 11 least significant bits of opcode: 5 most significant bits are always
COPROCESSOR HOOK (110118)
Exception Pointers Format
Coprocessor 1-41
Number System
The figure below shows the basic coprocessor real number system
on a real number line (decimal numbers are shown for clarity,
although the coprocessor actually represents numbers in binary).
The dots indicate the subset of real numbers the coprocessor can
represent as data and final results of calculations. The
coprocessor's range is approximately +4.19x 10-307 to
+ 1.67x 10308 •
The coprocessor can represent a great many of, but not all, the
real numbers in its range. There is always a "gap" between two
adjacent coprocessor numbers, and the result of a calculation may
fall within this space. When this occurs, the coprocessor rounds
the true result to a number it can represent.
The coprocessor actually uses a number system that is a superset

of that shown in the figure below. The internal format (called
temporary real) extends the coprocessor's range to about
+3.4x 10-4932 to + 1.2x 10493 1, and its precision to about 19
(equivalent decimal) digits. This format is designed to provide
extra range and precision for constants and intermediate results,
and is not normally intended for data or final results.
I Negative Range I I Positive Range I

III
I
(Normalized) -I I ..
I (Normalized) 'II
, ,I
I
, ., .... , ,. ,
J L~9~
, .. , n I
I I
-5 -4 -3 -2 -1 4 5 I
L'
I
~ ., 0
-1.67xl0 308 -4.19xl0- 307 4.19xl0- 307

J
1.67xl0 308
-2
• • •
tQ 2.00000000000000000
(Not Representable)
1.99999999999999999
Coprocessor Number System
1-42 Coprocessor
Instruction Set
On the following pages are descriptions of the operation for the
coprocessor's 69 instructions.
An instruction has two basic types of operands - sources and

destinations. A source operand simply supplies one of the
"inputs" to an instruction; it is not altered by the instruction. A
destination operand may also provide an input to an instruction. It
is distinguished from a source operand, however, because its
content can be altered when it receives the result produced by that
operation; that is the destination is replaced by the result.
The operands of any instructions can be coded in more than one

way. For example, FADD (add real) may be written without
operands, with only a source, or with a destination and a source
operand. The instruction descriptions use the simple convention of
separating alternative operand forms with slashes; the slashes,
however, are not coded. Consecutive slashes indicate there are no
explicit operands. The operands for F ADD are thus described as:
source/destination, source
This means that F ADD may be written in any of three ways:
FADD
FADD source
F ADD destination,source
It is important to bear in mind that memory operands may be

coded with any of the processor's memory addressing modes.
Coprocessor 1-43
FABS
FABS (absolute value) changes the top stack element to its
absolute value by making its sign positive.
FABS (no operands) Exceptions: 1
Operands Execution Clocks Trans- Bytes Coding Example

fers
Typical Range 8088
(no operands) 14 10-17 0 2 FABS
FADD
Addition
F ADD / / source/destination,source
F ADDP destination,source
FIADD source
The addition instructions (add real, add real and pop, integer add)
add the source and destination operands and return the sum to the
destination. The operand at the stack top may be doubled by
coding FADD ST,ST(O).
FADD Exceptions: 1,0,0, U, P

Operands Execution Clocks Trans- Bytes
fers Coding Example
Typical Range 8088
IIST,ST(i)/ST(i),ST 85 70-100 0 2 FADD ST,ST(4)

short-real 105+EA 90-120+EA 4 2-4 FADD AI R_ TEMP [SIl
long-real 110+EA 95-125+EA 8 2-4 FADD [BX] ,MEAN
1-44 Coprocessor
FADDP Exceptions: I, D, 0, U, P
fers
Typical Range 8088
ST(I),ST 90 75-105 0 2 FADD ST(2), ST
FIADD Exceptions: I, D, 0, P
fers Coding Example
Typical Range 8088
word-integer 120+EA 102-137+EA 2 2-4 FIADD DISTANCE_TRAVELLED

short-integer 1125+EA 108-143+EA 4 2-4 FIADD PULSCCOUNT[SI]
FBLD
FBLD Source
FBLD (packed decimal BCD) load» converts the content of the

source operand from packed decimal to temporary real and loads
(pushes) the result onto the stack. The packed decimal digits of
the source are assumed to be in the range X 'O-9R'.
FBLD Exceptions: I
fers
Typical Range 8088
packed-decimal 300+EA 290-310+EA 10 2-4 FBLD YTD_SALES
Coprocessor 1-45
FBSTP
FBSTP destination
FBSTP (packed decimal (BCD) store and pop) performs the

inverse of FBLD, where the stack top is stored to the destination
in the packed-decimal data type.
FBSTP Exceptions: I
fers Coding Example
Typical Range 8088
packed-decimal 530+EA 520-542+EA 12 2-4 FBSTP [BXl.FORCAST
FCHS
FCHS (change sign) complements (reverses) the sign of the top
stack element.
FCHS (no operands) Exceptions: I

fers Coding Example
Typical Range 8088
(no operands) 15 10-17 0 2 FCHS
FCLEX/FNCLEX
FCLEX/FNCLEX (clear exceptions) clears all exception flags,
the interrupt request flag, and the busy flag in the status word.
FCLEX/FNCLEX (no operands) Exceptions: None

fers Coding Example
Typical Range 8088
(no operands) 5 2-8 0 2 FNCLEX
1-46 Coprocessor
FCOM
FCOM/ /source
FCOM (compare real) compares the stack top to the source

operand. This results in the setting of the condition code bits.
FCOM Exceptions: I, 0
Operands Execution Clocks Trans· Bytes
fers Coding Example
Typical Range 8088
IIST(i) 45 40·50 0 2 FCOM ST(1)
short·real 65+EA 63·70+EA 4 2·4 FCOM [BP.] UPPER_LIMIT
long·real 70+EA 65·75+EA 8 2·4 FCOM WAVELENGTH
C3 CO Order
0 0 ST >source
0 1 ST <source
1 0 ST = source
1 1 ST? source
NANS and 00 (projective) cannot be compared

and return C3=Co=1 as shown above.
FCOMP
FCOMP / /source
FCOMP (compare real and pop) operates like FCOM, and in

addition pops the stack
FCOMP Exceptions: I, 0
fers Coding Example
Typical R~nge 8088
IISTO) 47 42-52 0 2 FCOMP ST(2)
short-real 68+EA 63-73+EA 4 2-4 FCOMP [BP].N_REAOINGS
long-real 72+EA 67-77+EA 8 2-4 FCOMP DENSITY
Coprocessor 1-47
FCOMPP
FCOMPP/ /source
FCOMPP (compare real and pop twice) operates like FCOM

and, additionally, pops the stack twice, discarding both operands.
The comparison is of the stack top to ST( 1); no operands may be
explicitly coded.
FCOMPP (no operands) Exceptions: I, 0

fers Coding Example
Typical Range 8088
(no operands) 50 45-55 0 2 FCOMPP
FDECSTP
FDECSTP (decrement stack pointer) subtracts 1 from ST, the
stack top pointer in the status word.
FDECSTP (no operands) Exceptions: None

fers Coding Example
Typical Range 8088
(no operands) 9 6-12 0 2 FOECSTP
FDISI/FNDISI
FDISI/FNDISI (disable interrupts) sets the interrupt enable
mask in the control word.
FDISI/FNDISI (no operands) Exceptions: None

fers Coding Example
Typical Range 8088
(no operands) 5 2-8 0 2 FOISI
1-48 Coprocessor
FDIV
Normal division
FDIV / /source/ destination,source
FDIVP destination,source
FIDIV source
The normal division instructions (divide real, divide real and pop,
integer divide) divide the destination by the source and return the
quotient to the destination.
FDIV Exceptions: I, D, Z, D, U, P
fers Coding Example
Typical Range 8088
/lST(il.ST 198 193-203 0 2 FOIV
short-real 220+EA 215-225+EA 4 2-4 FOIV DISTANCE
long-real 225+EA 220-230+EA 8 2-4 FOIV ARC [011
FDIVP Exceptions: I, D, Z, D, U, P
fers Coding Example
Typical Range 8088
ST(i),ST 202 197-207 0 2 FOIVP ST(4), ST
FIDIV Exceptions: I, D, Z, D, U, P
fars Coding Example
Typical Range 8088
word-integer 230+EA 224-238+EA 2 2-4 FIOIV SURVEY_OBSERVATIONS
short-integer 236+EA 230-243+EA 4 2-4 FIOIV RELATIVE_ANGLE[OI)
Coprocessor 1-49
FDIVR
Reversed Division
FDIVR Iisourcel destination,source
FDIVRP destination,source
FIDIVR source
The reversed division instructions (divide real reversed, divide

real reversed and pop, integer divide reversed) divide the source
operand by the destination and return the quotient to the
destination.
FDIVR Exceptions: I, D, Z, 0, U, P
fers Coding Example
Typical Range 8088
//ST,STO)/ST(i),ST 199 194-204 0 2 FDIVR ST(2), ST
short-real 221+EA 216-226+EA 6 2-4 FDIVR [BX].PULSE_RATE
long-real 226+EA 221-231+EA 8 2-4 FDIVR RECDRDER.FREQUENCY
FDIVRP Exceptions: I, D, Z, 0, U, P
fers Coding Example
Typical Range 8088
STO),ST 203 198-208 0 2 FDIVRP sHU, ST
FIDIVR Exceptions: I, D, Z, 0, U, P
fers Coding Example
Typical Range 8088
word-integer 230+EA 225-239+EA 2 2-4 FIDIVR [BP].X_CDDRD
short-integer 237+EA 231-245+EA 4 24 FIDIVR FREQUENCY
1-50 Coprocessor
FENI/FNENI
FENI/FNENI (enable interrupts) clear the interrupt enable mask
in the control word.
FENI/FNENI (no operands) Exceptions: None

fers Coding Example
Typical Range 8088
(no operands) 5 2·8 0 2 FNENI
FFREE
FFREE destination
FFREE (free register) changes the destination register's tag to

empty; the content of the register is not affected.
FFREE Exceptions: None

fers Coding Example
Typical Range 8088
ST(O 186 9·16 0 2 FFREE ST(l)
FICOM
FICOM source
FICOM (integer compare) compares the source to the stack top.
FICOM Exceptions: 1,0

fers Coding Example
Typical Range 8088
word·integer 80+EA 72·86+EA 2 Z-4 FICOM TOQl.N_PASSES
short·integer 85+EA 78·g1tEA 2 2-4 FICOM [BP+41J.!'ARM_COUNT
Coprocessor 1-51
FICOMP
FICOMP source
FICOMP (integer compare and pop) operates the same as

FICOMand additionally pops the stack.
FICOMP Exceptions: I, D
fers Coding Example
Typical Range 8088
word-integer 82+EA 74-88+EA 2 2-4 FICOMP [BPl.LlMIT [SI)
short-inter 87+EA 80-93+EA 4 2-4 FICOMP N_SAMPLES
FILD
FILD source
FILD (integer load) loads (pushes) the source onto the stack.
flLD Exceptions: I
fers Coding Example
Typical Range 8088
word-integer 50+EA 46-54+EA 2 2-4 FI LD [BXl.SEQUENCE
short-integer 56+EA 52-60+EA 4 2-4 FILD STANDOFF[DI)
long-integer 64+EA 60-68+EA 8 2-4 FILD RESPONSE.COUNT
FINCSTP
FINCSTP (increment stack pointer) adds 1 to the stack top
pointer (ST) in the status word.
FINCSTP(no operands) Exceptions: None

fers Coding Example
Typical Range 8088
(no operands) 9 6-12 0 2 FINCSTP
1-52 Coprocessor
FINIT/FNINIT
FINIT/FNINIT (initialize processor) performs the functional
equivalent of a hardware RESET.
FINIT/FNINIT (no operands) Exceptions: None

fers Coding Example
Typical Range 8088
(no operands) 5 2·8 0 2 FINIT
Field Value Interpretation
Control Word
Infinity Control 0 Projective
Rounding Control 00 Round to nearest
Precision Control 11 64 bits
Interrupt-enable Mask 1 Interrupts disabled
Exception Masks 111111 All exceptions masked
Status Word
Busy 0 Not Busy
Condition Code ???? (Indeterminate)
Stack Top 000 Empty stack
Interrupt Request 0 No interrupt
Exception Flags 000000 No exceptions
Tag Word
Tags 11 Empty
Registers N.C. Not changed

Exception Pointers
Instruction Code N.C. Not changed
Instruction Address N.C. Not changed
Operand Address N.C. Not changed
Coprocessor 1-53
FIST
FIST destination
FIST (integer store) stores the stack top to the destination in the
integer format.
FIST ExceptiDns: I, P
fers Coding Example
Typical Range 8088
word·integer 86+EA 80·90+EA 4 2·4 FIST OBS.COUNT[SIl
short·integer 88+EA 82·92+EA 6 2-4 FIST [BP].FACTORED_PULSES
FISTP
FISTP destination
FISTP (integer store and pop) operates like FIST and also pops
the stack following the transfer. The destination may be any of the
binary integer data types.
FISTP ExceptiDns: I, P
fers Coding Example
Typical Range 8088
word·integer 88+EA 82·92+EA 4 2·4 FISTP [BX].ALPHA_COUNT[SIl
short·integer 90+EA 84·94+EA 6 2·4 FISTP CORRECTED_TIME
long·integer 100+EA 94·105+EA 10 2·4 FISTP PANEL.N_READINGS
1-54 Coprocessor
FLD
FLD source
FLD (load real) loads (pushes) the source operand onto the top of
the register stack.
FLD Exceptions: I, D
fers Coding Example
Typical Range BOB8
STOl 20 17-22 0 2 FLO ST(O)
short-real 43+EA 38-56+EA 4 2-4 FLO READING[SII.PRESSURE
long-real 46+EA 40-60+EA 8 2-4 FLO [BPI.TEMPERATURE
temp-real 57+EA 53-65+EA 10 2-4 FLO SAVEREADING
FLDCW
FLDCW source
FLDCW (load control word) replaces the current processor

control word with the word defined by the source operand.
FLDCW Exceptions: None

fers Coding Example
Typical Range B08B
2-bytes 10+EA 7-14+EA 2 2-4 FLDCW CONTROL_WORD
Coprocessor 1-55
FLDENV
FLDENV source
FLDENV (load environment) reloads the coprocessor

environment from the memory area defined by the source
operand.
FLDENV Exceptions: None

fers Coding Example
Typical Range 8088
14·bytes 40+EA 35·45+EA 14 2·4 FLOENV [BP+6]
FLDLG2
FLDLG2 (load log base 10 of 2) loads (pushes) the value of
LOG 102 onto the stack.
FLDLG2 (no operands) Exceptions: I

fers Coding Example
Typical Range 8088
(no operands) 21 18·24 0 2 FLDLG2
FLDLN2
FLDLN2 (load log base e of 2) loads (pushes) the value of
LOG) onto the stack.
FLDLN2 (no operands) Exceptions: I

fers Coding Example
Typical Range 8088
(no operands) 20 17·23 0 2 FLDLN2
1-56 Coprocessor
FLDL2E
FLDL2E (load log base 2 of e) loads (pushes) the value LOG 2e
onto the stack.
FLOL2E (no operands) Exceptions: I

fers Coding Example
Typical Range 8088
(no operands) 18 15-21 a 2 FLOL2E
FLDL2T
FLDL2T (load log base 2 of 10) loads (pushes) the value of
LOG210 onto the stack.
FLOL2T (no operands) Exceptions: I

fers Coding Example
Typical Range 8088
(no operands) 19 16-22 a 2 FLOL2T
FLDPI
FLD PI (load 1T) loads (pushes) 1T onto the stack.
FLOPI (no operands) Exceptions: I

fers Coding Example
Typical Range 8088
(no operands) 19 16-22 a 2 FLOPI
Coprocessor 1-57
FLDZ
FLDZ (load zero) loads (pushes) +0.0 onto the stack.
FLOZ (no operands) Exceptions: I

fers Coding Example
Typical Range 8088
(no operands) 14 11·17 0 2 FLOI
FLDI
FLD 1 (load one) loads (pushes) + 1.0 onto the stack.
FL01 (no operands) Exceptions: I

fers Coding Example
Typical Range 8088
(no operands) 18 15·21 0 2 FLOZ
1-58 Coprocessor
FMUL
Multiplication
FMUL / /source/destination,source
FMULP destination,source
FIMUL source
The multiplication instructions (multiply real, multiply real and

pop, integer multiply) multiply the source and destination
operands and return the product to the destination. Coding FMUL
ST,ST(O) square the content of the stack top.
FMUL Exceptions: I, D, 0, U, P
fers Coding Example
Typical Range 8088
/ /ST(i),ST/ST,ST(i) [ 97 90-105 0 2 FMU L ST,ST(3)
//ST(i),ST/ST,ST(i) 138 130-145 0 2 FMULST,ST(3)
short-real 118+EA 110-125+EA 4 2-4 FMU L SPEED_FACTOR
long-real I 120+EA 112-126+EA 8 2-4 FMUL [BP].HEIGHT
long-real 161+EA 154-168+EA 8 2-4 FMUL [BP]_HEIGHT
I occurs when one or both operands is "short" - it has 40 trailing zeros in its fraction.
FMULP Exceptions: I, D, 0, U, P
fers Coding Example
Typical Range 8088
STm,ST I 100 94-108 0 2 FMU LP ST(1 ),ST
ST(il.ST 142 134-148 0 2 FMULP ST(l).ST
I occurs when one or both operands is "short" - it has 40 trailing zeros in its fraction.
FIMUL Exceptions: I, D, 0, P
fers Coding Example
Typical Range 8088
word-integer 130+EA 124-138+EA 2 2-4 FIMUL BEARING
short-integer 136+EA 130-144+EA 4 2-4 FIMUL POSITION.LAXIS
Coprocessor 1·59
FNOP
FNOP (no operation) stores the stack top to the stack top (FST
ST,ST(O» and thus effectively performs no operation.
FNOP (no operands) Exceptions: None

fers Coding Example
Typical Range 8088
(no operands) 13 10-16 0 2 FNOP
FPATAN
FPATAN (partial arctangent) computes the function
() =ARCTAN (Y/X). X is taken from the top stack element and
Y from ST( 1). Y and X must observe the inequality O<Y <X < 00 •
The instruction pops the stack and returns () to the (new) stack
top, overwriting the Y operand.
FPATAN (no operands) Exceptions: U, P (operands not checked)

fers Coding Example
Typical Range 8088
(no operands) 650 250-800 0 2 FPATAN
FPREM
FPREM (partial remainder) performs modulo division on the top
stack element by the next stack element, that is, ST( 1) is the
modulus.
FPREM (no operands) Exceptions: I, D, U

fers Coding Example
Typical Range 8088
(no operands) 125 15-190 0 2 FPREM
1-60 Coprocessor © Copyright IBM Corp_ 1981, 1982, 1983

FPTAN
FPTAN (partial tangent) computes the function Y/X =TAN(O).
ois taken from the top stack element; it must lie in the range
O<O<rr/4. The result of the operation is a ratio; Y replaces 0 in
the stack and X is pushed, becoming the new stack top.
FPTAN Exceptions: I, P (operands not checked)

fers Coding Example
Typical Range 8088
(no operands) 450 30-540 0 2 FPTAN
FRNDINT
FRNDINT (round to integer) rounds the top stack element to an
integer.
FRNDINT (no operands) Exceptions: I, P

fers Coding Example
Typical Range 8088
(no operands) 45 16-50 0 2 FRNDINT
FRSTOR
FRS TOR source
FRSTOR (restore state) reloads the coprocessor from the 94-byte

memory area defined by the source operand.
FRSTOR Exceptions: None

fers Coding Example
Typical Range 8088
94-bytes 210+EA 205-215+EA 96 2-4 FRSTOR [BP]
© Copyright IBM Corp. 1981,1982,1983 Coprocessor 1-61

F SAVE/FNSAVE
FSAVE/FNSAVE destination
FSAVE/FNSAVE (save state) writes the full coprocessor state-

environment plus register stack - to the memory location defined
by the destination operand.
FSAVE/FNSAVE Exceptions: None

fers Coding Example
Typical Range 8088
94-bytes 210+EA 205-215+EA 94 2-4 FSAVE [BP]
FSCALE
FSCALE (scale) interprets the value contained in ST(1) as an
integer, and adds this value to the exponent of the number in ST.
This is equivalent to:
ST-- ST .2ST(I)
Thus, FSCALE provides rapid multiplication or division by

integral powers of 2.
FSCALE (no operands) Exceptions: 1,0, U

fers Coding Example
Typical Range 8088
(no operands) 35 32-38 0 2 FSCALE
FSQRT
FSQRT (square root) replaces the content of the top stack
element with its square root.
Note: the square root of -0 is defined to be -0.
FSORT (no operands) Exceptions: I, 0, P

fers Coding Example
Typical Range 8088
(no operands) 183 180-186 0 2 FSQRT
1-62 Coprocessor
FST
FST destination
FST (store real) transfers the stack top to the destination, which
may be another register on the stack or long real memory operand.
FST Exceptions: 1,0, U, P

fers Coding Example
Typical Range 8088
SliD 18 15-22 0 2 FST ST(3)

short-real 87+EA 84-90+EA 6 2-4 FST CORRELATION [01]
long-real 100+EA 96-104+EA 10 2-4 FST MEAN_READING
FSTCW/FNSTCW
FSTCW/FNSTCW destination
FSTCW/FNSTCW (store control word) writes the current

processor control word to the memory location defined by
the destination.
FSTCW/FNSTCW Exceptions: None

Operands Execution Clocks Trans- 8ytes
fers Coding Example
Typical Range 8088
2-bytes 15+EA 12-18+EA 4 2-4 FSTCW SAVE_CONTROL
Coprocessor 1-63
FSTENV/FNSTENV
FSTENV/FNSTENV destination
FSTENV/FNSTENV (store environment) writes the coprocessQf's

basic status - control, status and tag words, and exception pointers
- to the memory location defined by the destination operand.
FSTENV/FNSTENV Exceptions: None

fers Coding Example
Typical Range 8088
14-bytes 45+EA 40-50+EA 16 2-4 FSTENV [BP)
FSTP
FSTP destination
FSTP (store real and pop) operates the same as FST, except that
the stack is popped following the transfer.
FSTP Exceptions: 1,0, U, P

fers Coding Example
Typical Range 8088
ST(i) 20 17-24 0 2 FSTP ST(2)
short-real 89+EA 86-92+EA 6 2-4 FSTP [BX).ADJUSTEO_RPM
long-real 102+EA 98-106+EA 10 2-4 FSTP TOTAL_DOSAGE
temp-real 55+EA 52-58+EA 12 2-4 FSTP REG_SAVE[S!)
1-64 Coprocessor
FSTSW/FNSTSW
FSTSW/FNSTSW destination
FSTSW/FNSTSW (store status word) writes the current value of

the coprocessor status word to the destination operand in memory.
FSTSW/FNSTSW Exceptions: None

fers Coding Example
Typical Range 8088
2·bytes 14+EA 12·18+EA 4 2·4 FSTSW SAVE_STATUS
FSUB
Subtraction
FSUB / /source/destination,source
FSUBP destination,source
FISUB source
The normal subtraction instructions (subtract real, subtract real

and pop, integer subtract) subtract the source operand from the
destination and return the difference to the destination.
FSUB Exceptions: 1,0,0, U, P

fers Coding Example
Typical Range 8088
/IST,ST(j)/ST(il.ST 85 70·100 0 2 FSUB ST,ST(2)
shart·real 105+EA 90·120+EA 4 2·4 FSUB BASE_VALUE
lang·real 11O+EA 95·125+EA 8 2·4 FSUB COOROINATE.X
Coprocessor 1-65
FSUBP Exceptions: I, D, 0, U, P
fers Coding Example
Typical Range 8088
ST(i),ST 90 75-105 0 2 FSUBP ST(2),ST
FISUB Exceptions: I, D, 0, P
fers Coding Example
Typical Range 8088
word-i nteger 120+EA 102-137+EA 2 2-4 FISUB BASE_FREQUENCY
sh ort-i nteger 125+EA 108-143+EA 4 2-4 FISUB TRAIN_SIZE[DIl
FSUBR
Reversed Subtraction
FSUBR / /source/destination,source
FSUBRP destination,source
FISUBR source
The reversed subtraction instructions (subtract real reversed,

subtract real reversed and pop, integer subtract reversed) subtract
the destination from the source and return the difference to the
destination.
FSUBR Exceptions: I, D, 0, U, P
Operands Execution Clocks Trans- Bvtes
fers Coding Example
Typical Range 8088
//ST,ST(i)!ST(i),ST 87 70-100 0 2 FSUBR ST,ST(1)
short-real 105+EA 90-120+EA 4 2-4 FSUBR VECTOR[SI]
long-real 110+EA 95-125+EA 8 2-4 FSUBR [BXl.INDEX
1-66 Coprocessor
FSUBRP Exceptions: I, D, D, U, P
fers Coding Example
Typical Range 8088
ST(j),ST 90 75-105 0 2 FSUBRP ST(I),ST
FISUBR Exceptions: I, D, D, P
fers Coding Example
Typical Range 8088
word-integer 120+EA 103-139+EA 2 2-4 FISUBR FLOOR[BX] [SIl
short-integer 125+EA 109-144+EA 4 2-4 FISUBR BALANCE
FTST
FTST (test) tests the top stack element by comparing it to zero.
The result is posted to the condition codes.
FTST (no operands) Exceptions: I, D

fers Coding Example
Typical Range 8088
(no operands) 42 38-48 0 2 FTST
C3 CO Result
0 0 ST is positive and nonzero
0 1 ST is negative and nonzero
1 0 ST is zero (+ or -)
1 1 ST is not comparable (that
is, it is a NAN or projective 00)
Coprocessor 1-67
FWAIT
FWAIT (processor instruction)
FWAIT is not actually a coprocessor instruction, but an alternate

mnemonic for the processor WAIT instruction. The FWAIT
mnemonic should be coded whenever the programmer wants to
synchronize the processor to the coprocessor, that is, to suspend
further instruction decoding until the coprocessor has completed
the current instruction.
FWAIT (no operands) Exceptions: Non (CPU instruction)

fers Coding Example
Typical Ranga 8088
(no operands) 3+5n 3+5n 0 1 FWAIT
EXAM
FXAM (examine) reports the content of the top stack element as

positive/negative and NAN/unnormal/denormal/normal/zero, or
empty.
FXAM Exceptions: None

Oparands Execution Clocks Trans- Bytes
fars Coding Example
Typical Range 8088
(no operands) 17 12-23 0 2 FXAM
1-68 Coprocessor
Condition Code
Interpretation
C3 C2 Cl CO
0 0 0 0 + Unnormal
0 0 0 1 +NAN
0 0 1 0 - Unnormal
0 0 1 1 - NAN
0 1 0 0 + Normal
0 1 0 1 +00
0 1 1 0 - Normal
0 1 1 1 _00
1 0 0 0 +0
1 0 0 1 Empty
1 0 1 0 -0
1 0 1 1 Empty
1 1 0 0 + Denormal
1 1 0 1 Empty
1 1 1 0 - Denormal
1 1 1 1 Empty
FXCH
FXCH/ /destination
FXCH (exchange registers) swaps the contents of the destination

and the stack top registers. If the destination is not coded
explicitly, ST( 1) is used.
FXCH Exceptions: I
fers Coding Example
Typical Range 8088
//ST(j) 12 10·15 0 2 FXCH ST(2)
Coprocessor 1-69
FXTRACT
FXTRACT (extract exponent and significant) "decomposes" the
number in the stack top into two numbers that represent the actual
value of the operand's exponent and significand fields contained in
the stack top and ST(1).
FXTRACT Exceptions: I
ters Coding Example
Typical Range 8088
(no operands) 50 27-55 0 2 FXTRACT
FYL2X
FYL2X (Y log base 2 of X) calculates the function Z=Y.LOG 2 •
X is taken from the stack top and Y from ST( 1). The operands
must be in the ranges O<X < and - 00<Y< + The 00 00.
instruction pops the stack and returns Z at the (new) stack top,
replacing the Y operand.
FYl2X Exceptions: P (operands not checked)

ters Coding Example
Typical Range 8088
(no operands) 950 900-1100 0 2 FYL2X
1-70 Coprocessor
FYL2XPI
FYL2XP 1 (Y log base 2 of (X + 1» calculates the function
Z = y. LOG 2( X + 1). X is taken from the stack top and must be
in the range 0< IXI «1-(v'2/2». Y is taken from ST(1) and
must be in the range - <Y < 00 FYL2XP 1 pops the stack and
00 •
returns Z at the (new) stack top, replacing Y.
FYL2XPl Exceptions: P (operands not checked)

fers Coding Example
Typical Range 8088
(no operands) 850 700-1000 a 2 FYL2XPI
F2XMI
F2XMl (2 to the X minus 1) calculates the function Y=2x-1.
X is taken from the stack top and must be in the range O<X <0.5.
The result Y replaces the stack top.
This instruction is designed to produce a very accurate result even

when X is close to zero. To obtain Y=1', add 1 to the result
delivered by F2XMl.
F2XMl Exceptions: U, P (operands not checked)

fers Coding Example
Typical Range 8088
(no operands) 500 310-630 0 2 F2XMl
Coprocessor 1-71
Notes:
1-72 Coprocessor
IBM Keyboard
The keyboard has a permanently attached cable that connects to a

DIN connector at the rear of the system unit. This shielded
four-wire cable has power (+5 Vdc), ground, and two bidirectional
signal lines. The cable is approximately 6-feet long and is coiled,
like that of a telephone handset.
The keyboard uses a capacitive technology with a microcomputer

(Intel 8048) performing the keyboard scan function. The keyboard
has three tilt positions for operator comfort (5-, 7-, or 15-degree
tilt orientations).
The keyboard has 83 keys arranged in three major groupings. The

central portion of the keyboard is a standard typewriter keyboard
layout. On the left side are 10 function keys. These keys are
user-defined by the software. On the right is a 15-key keypad.
These keys are also defined by the software, but have legends for
the functions of numeric entry, cursor control, calculator pad, and
screen edit.
The keyboard interface is defined so that system software has

maximum flexibility in defining certain keyboard operations. This
is accomplished by having the keyboard return scan codes rather
than American Standard Code for Information Interchange
(ASCII) codes. In addition, all keys are typematic and generate
both a make and a break scan code. For example, key 1 produces
scan code hex 01 on make and code hex 81 on break. Break codes
are formed by adding hex 80 to make codes. The keyboard I/O
driver can define keyboard keys as shift keys or typematic, as
required by the application.
Keyboard 1-73
The microcomputer (Intel 8048) in the keyboard performs several
functions, including a power-on self-test when requested by the
system uilit .. This test checks the microcomputer ROM, tests
memory, and checks for stuck keys. Addition~l functions are:
keyboard scanning, buffering of up to 16 key scan codes,
maintaining bidirectional serial communications with the system
unit, and executing the hand-shake protocol required by each
scan-code transfer.
The following pages have figures that show the keyboard, the scan
codes, and the keyboard interface connector specifications.
1-74 Keyboard
8255A5 LS322
PAO OH OH'
PA1 OG
PA2 OF
PA3 OE
PA4 OD
PA5 OC
PA6 OB
PA7 QA
OE
D1
DO
PB7 CLR
PB6
Keyboard Clock 1 IR01

0
2
Keyboard Data 0
Reset 0
3 7407
GND 0 4
+5 V 0 5
LS175 LS175
PC LK --+-+-l
Keyboard Interface Block Diagram
Keyboard 1-7 5
-,
-J
0'1
a.~o
~
0.. ;;0\
59EJ60EJ 1n 2[] 31@l41#1 5[J 61%1 7Fl8r&l91*110f(l11f)l12~13r+TOQOOr;.:]OD [;
CD
<tr
o
...
I»
l 1 J lLJ1~ llLJlliJI! 1~1~1LtJ1~1LLJ1tL1u 1~ J LJ
F' F2 ~ ~ ~ ~:::'
a.
lEJrEJJ to§CiEJIEJI[]IEJr[)I[)lrJl[]l~I[)I[]llJ[]Ub1~I[]r~IEJJ
tDEOEJt[]lrJr[]l1:JrEJl[]I~l"[]IODiD~l"[]l'[r~
o
Qi'
te
ci
3 "lElrEJJ
6[EJIEJJ luE}ulDrDrEJrEJrEJr[]lEJIEJlEJt[JY[]JOEJDlBI[gllDrg. ll +
67EJ68
l !uj
F9
0 5DO'J[
~ LJU
57 rI~ capsOOrolOO~'
ill ~ ill ~ Lock
Note: Nomenclature is on both the top and front face of the keybutton as shown. The number to the upper left designates the button
position.
Key Position Scan Code in Hex Key Position Scan Code in Hex
1 01 43 2B
2 02 44 2C
3 03 45 2D
4 04 46 2E
5 05 47 2F
6 06 48 30
7 07 49 31
8 08 50 32
9 09 51 33
10 OA 52 34
11 OB 53 35
12 OC 54 36
13 OD 55 37
14 OE 56 38
15 OF 57 39
16 10 58 3A
17 11 59 3B
18 12 60 3C
19 13 61 3D
20 14 62 3E
21 15 63 3F
22 16 64 40
23 17 65 41
24 18 66 42
25 19 67 43
26 1A 68 44
27 1B 69 45
28 1C 70 46
29 1D 71 47
30 1E 72 48
31 1F 73 49
32 20 74 4A
33 21 75 4B
34 22 76 4C
35 23 77 4D
36 24 78 4E
37 25 79 4F
38 26 80 50
39 27 81 51
40 28 82 52
41 29 83 53
42 2A
Keyboard Scan Codes
Keyboard 1-77
Rear Panel
Connector
5-Pin DIN Connector
Pin TTL Signal Signal Level

1 +Keyboard Clock +5 Vdc
2 +Keyboard Data +5 Vdc
3 -Keyboard Reset (Not used by keyboard)
Power Supply Voltages Voltage
4 Ground 0
5 +5 Volts +5 Vdc
Keyboard Interface Connector Specifications
1-78 Keyboard
Expansion Unit
The expansion unit option upgrades the IBM Personal Computer

by adding expansion slots in a separate unit. This option consists
of an extender card, an expansion cable, and the expansion unit.
The expansion unit contains a power supply, an expansion board,
and a receiver card. This option utilizes one expansion slot in the
system unit to provide seven additional expansion slots in the
expansion unit.
Expansion Unit Cable

The expansion unit cable consists of a 56-wire, foil-shielded cable
terminated on each end with a 62-pin D-shell male connector.
Either end of the expansion unit cable can be plugged into the
extender card or the receiver card.
Expansion Board
The expansion board is a support board that carries the I/O
channel signals from the option adapters and receiver card. These
signals, except 'osc,' are carried over the expansion cable.
Because 'osc' is not sent over the expansion cable, a
14.31818-MHz signal is generated on the expansion board. This
signal may not be in phase with the 'osc' signal in the system unit.
Decoupling capacitors provided on the expansion board aid in

noise filtering.
Expansion Unit 1-79

I----
-
Expansion
Channel
Slot 1 Slot
-
2 I----
Slot
3
Slot ~
4
Slot
5 ~
Slot
6
Slot t--
7
Power
Slot Supply
8 Connector
Timing
---- Generation
(8284)
-
'---
----
---
14.31818
MHz Crystal
L.......
Expansion Board Block Diagram
1-80 Expansion Unit

Expansion Channel
All signals found on the system unit's I/O channel will be
provided to expansion slots in the expansion unit, with the
exception of the 'osc' signal and the voltages mentioned
previously.
A 'ready' line on the expansion channel makes it possible to

operate with slow I/O or memory devices. If the channel's 'I/O
ch rdy' line is not activated by an addressed device, all processor-
generated memory cycles take five processor clock cycles per byte
for memory in the expansion unit.
The following table contains a list of all the signals that are
redriven by the extender and receiver cards, and their associated
time delays. The delay times include the delay due to signal
propagation in the expansion cable. Assume a nominal cable
delay of 3 ns. As such, device access will be less than 260 ns.
Nominal Maximum
Delay Delay
Signal (ns) (ns) Direction (*)
AO - A19 27 39 Output
AEN 27 39 Output
DACKO - DACK3 27 39 Output
MEMR 27 39 Output
MEMW 51 75 Output
lOR 51 75 Output
lOW 27 39 Output
ALE 27 39 Output
ClK 27 39 Output
T/C 27 39 Output
RESET 27 39 Output
IRQ2 - IRQ7 36 (**) Input
DRQ1 - DRQ3 36 (**) Input
I/O CH RDY 36 51 Input
I/O CH CK 36 51 Input
DO - D7 (Read) 84 133 Input
DO - D7 (Write) 19 27 Output
(*) With respect to the system unit.
(**) Asynchronous nature of interrupts and other requests are more dependent on
processor recognition than electrical signal propagation through expansion
logic.
Expansion Unit 1-81

Power Supply
The expansion unit dc power supply is a 130-watt, 4 voltage level
switching regulator. It is integrated into the expansion unit and
supplies power for the expansion unit, and its options. The supply
provides 15 A of+5 Vdc, plus or minus 5%, 4.2A of+12 Vdc,
plus or minus 5%, 300 rnA of -5 Vdc, plus or minus 10%, and
250 rnA of -12 Vdc, plus or minus 10%. All power levels are
regulated with over-voltage and over-current protection. The input
is 120 Vac and fused. If dc over-load or over-voltage conditions
exist, the supply automatically shuts down until the condition is
corrected. The supply is designed for continuous operation at
130 watts.
The power supply is located at the right rear of the expansion unit.
It supplies operating voltages to the expansion board, and provides
two separate connections for power to the fixed disk drives. The
nominal power requirements and output voltages are listed in the
following tables:
Voltage Frequency Current

(Vac at 50/60 Hz) (Hz) (Amps)
Nominal I Minimum I Maximum +/- 3 Hz Maximum
110 I 90 I 137 50/60 4.1 at 90 Vac
Input Requirements
Voltage Current Regulation

(Vdc) (Amps) (Tolerance)
Nominal Minimum Maximum +% -%
+5.0 2.3 15.0 5 4
-5.0 0.0 0.3 10 8
+12.0 0.4 4.2 5 4
-12.0 0.0 0.25 10 9
Vdc Output
Voltage Current Voltage Limits

(Vac) (Amps) (Vac)
Nominal Minimum I Maximum Minimum I Maximum
120 0.0 I 1.0 88 I 137
Vac Output
1-82 Expansion Unit

Power Supply Connectors and Pin Assignments
The power connector on the expansion board is a 12-pin male
connector that plugs into the power-supply connectors. The pin
configurations and locations are shown below:
.tMN": .tMN": tt51ll<t·MN ...·tt5Ill.tMN..:

t: t: t: t: t: t: t: t: t: t: t: t: t: t: t: t: t: t: t: t:
C::C::C::C:: C::C::C::C:: c::c::c::c::c::c::c::c::c::c::c::c::
~~~I~~
::G
'"
....o
u
CIl
CIl t:
> c: t:
';: o 0
0<11
..>::
"'
,- ....
u
0
,- (.)
't:"
~ ;=
..
CIl
OCll >< 0
t: we..
'0 t:
........o
CIl 0
,~ (.)
u.. ..
~ CIl
'c ~
:::> t:
o ~ (S) c:t:
o 0
... e.. 'iii (.)
t: ..
0.;=
'" CIl
/~J.
~ 0
\..Y <ttl
C! ~
... t:
. 0
u(.)
~ a3
o ;=
NO
... e..
Power Supply and Connectors
Expansion Unit 1-83

Over-Voltage/Over-Current Protection
Voltage Nominal Vac Type Protection Rating Amps

110 Fuse 5
Power On/Off Cycle: When the supply is turned off for a

minimum of 1.0 second, and then turned on, the power-good
signal will be regenerated.
The power-good signal indicates that there is adequate power to

continue processing. If the power goes below the specified levels,
the power-good signal triggers a system shutdown.
This signal is the logical AND of the dc output-voltage sense

signal and the ac input voltage fail signal. This signal is
TTL-compatible up-level for normal operation or down-level for
fault conditions. The ac fail signal causes power-good to go to a
down-level when any output voltage falls below the regulation
limits.
The dc output-voltage sense signal holds the power-good signal at

a: down level (during power-on) until all output voltages have
reached their respective minimum sense levels. The power-good
signal has a tum-on delay of at least 100 ms but no greater than
500ms. .
The sense levels of the dc outputs are:
Output Minimum Sense Voltage Nominal Maximum

(Vdc) (Vdc) (Vdc) (Vdc)
+5 +4.5 +5.0 +5.5
-5 -4.3 -5.0 -5.5
+12 +10.8 +12.0 +13.2
-12 -10.2 -12.0 -13.2
1-84 Expansion Unit

Extender Card
The extender card is a four-plane card. The extender card redrives
the I/O channel to provide sufficient power to avoid capacitive
effects ofthe cable. The extender card presents only one load per
line of the I/O channel.
The extender card has a wait-state generator that inserts a

wait-state on 'memory read' and 'memory write' operations
(except refreshing) for all memory contained in the expansion
unit. The address range for wait-state generation is controlled by
switch settings on the extender card.
The DIP switch on the extender card should be set to indicate the
maximum contiguous read/write memory housed in the system
unit. The extender card switch settings are located in "Appendix
G: Switch Settings." Switch positions 1 through 4 correspond to
address bits hex A19 to hex A16, respectively.
The switch settings determine which address segments have a wait

state inserted during 'memory read' and 'memory write'
operations. Wait states are required for any memory, including
ROM on option adapters, in the expansion unit. Wait states are
not inserted in the highest segment, hex addresses FOOOO to
FFFFF (segment F).
Expansion Unit 1-85

Extender Card Programming Considerations
Several registers associated with the expansion option are
programmable and readable for diagnostic purposes. The
following figure indicates the locations and functions of the
registers on the extender card.
Location Function
Memory FXXXX(*) Write to memory to latch address bits
Port 210 Write to latch expansion bus data (EDO - ED7)
Port 210 Read to verify expansion bus data (EDO - ED7)
Port 211 Read high-order address bits (AB - A 15)
Port 211 Write to clear wait test latch
Port 212 Read low-order address bits (AO - A7)
Port 213 Write 00 to disable expansion unit
Port 213 Write 01 to enable expansion unit
Port 213 Read status of expansion unit
DO = enable/disable
D1 = wait-state request flag
D2-D3 = not used
D4-D7 = switch position
1 = Off
O=On
(*) Example: Write to memory location F123:4=00
Read Port 211 = 1 2
Read Port 212 = 34
(All values in hex)
The expansion unit is automatically enabled upon power-up. The

extender card and receiver card will both be written to, if the
expansion unit is not disabled when writing to FXXXX. However,
the system unit and the expansion unit are read back separately.
1-86 Expansion Unit

~ ~
Control Bus Control

'//. Z Bus '//////.
-
Buffer liD CH RDY
MEMW,MEMR,DACKO
A16-A~ ~o-~
Wait-State liD Address
-
G'."";'"~
Decode
~
~
~ ~
AO-A19
Address
~ l::
-h
I/) Buffer
~
::l a>
m r:-'
"tl
E 3'
~
I/) (")
> 0
Vl ::l
~
>' ::l
--.. Data Latch ~
<1>
!l
~
and Disable
?Z2 Circuits
DO-D7
I EXT DISABLE l
Data
'If,
Buffer
,.. T
DIR ENABLE
~ "", D;",•••
and Enable
I Control
---
Extender Card Block Diagram
-
Expansion Unit 1-87

Receiver Card
The receiver card is a four-plane card that fits in expansion slot 8
of the expansion unit. The receiver card redrives the I/O channel
to provide sufficient power for additional options and to avoid
capacitive effects. Directional control logic is contained on the
receiver card to resolve contention and direct data flow on the I/O
channel. Steering signals are transmitted back over the expansion
cable for use on the extender card.
Receiver Card Programming Considerations

Several registers associated with the expansion option are
programmable and readable for diagnostic purposes. The
following figure indicates the locations and functions of the
registers on the receiver card.
Location Function
Memory FXXXX(*) Write to memory to latch address bits
Port 214 Write to latch data bus bits (DO - 07)
Port 214 Read data bus bits (DO - 07)
Port 215 Read high-order address bits (AB - A15)
Port 216 Read low-order address bits (AO - A7)
(*) Example: Write to memory location F123:4=00
Read Port 215 =12
Read Port 21 6 =34
(All values in hex)
The expansion unit is automatically enabled upon power-up. The

expansion unit and the system unit will be written to, if the
expansion unit is not disabled when writing to FXXXX. However,
the system unit and the expansion unit are read back separately.
1-88 Expansion Unit

~~c~o~n~t~ro~I~B~U~S~~Controlbz22~2f~~~~CZ22222Z2Z22222222~~~~
t Bus ..
Buffer
00-07 Data
~u
.,
I:
Bus
Buffer
I:
o
U
I:
a::
N Data Latch
<Q
Circuit
Control Signal
AO-A19
Receiver Card Block Diagram
Expansion Unit 1-89

Expansion Unit Interface Information
The extender card and receiver card rear-panel connectors are the
same. Pin and signal assignments for the extender and receiver
cards are shown below.
2',(@ • • • • • • • • • • • • • • • • • • • @ )~1
42 @ • • • • • • • • • • • • • • • • • • • @ 22
62 @ • • • • • • • • • • • • • • • • • • @ 43
Pin Signal Pin Signal Pin Signal

1 +E IRQ6 22 +E D5 43 +E IRQ7
2 +E DRQ2 23 +E DRQ1 44 +E D6
3 +E DIR 24 +E DRQ3 45 +E I/O CH RDY
4 +E ENABLE 25 RESERVED 46 +E IRQ3
5 +E ClK 26 +E ALE 47 +E D7
6 -E MEM IN EXP 27 +E T/C 48 +E D1
7 +E A17 28 +E RESET 49 -E I/O CH CK
8 +E A16 29 +E AEN 50 +E IRQ2
9 +EA5 30 +E A19 51 +E DO
10 -E DACKO 31 +E A14 52 +E D2
11 +E A15 32 +E A12 53 +E D4
12 +E A11 33 +E A18 54 +E IRQ5
13 +E A10 34 -E MEMR 55 +E IRQ4
14 +EA9 35 -E MEMW 56 +E D3
15 +E A1 36 +EAO 57 GND
16 +EA3 37 -E DACK3 58 GND
17 -E DACK1 38 +E A6 59 GND
18 +EA4 39 -E lOR 60 GND
19 -E DACK2 40 +E A8 61 GND
20 -E lOW 41 +EA2 62 GND
21 +E A13 42 +EA7
E = Extended
Connector Specifications
1-90 Expansion Unit

IBM 80 CPS Printers
The IBM 80 CPS (characters-per-second) Printers are self-

powered, stand-alone, tabletop units. They attach to the system
unit through a parallel signal cable, 6 feet in length. The units
obtain ac power from a standard wall outlet (120 Vac). The
printers are 80 cps, bidirectional, wire-matrix devices. They print
characters in a 9 by 9 dot matrix with a 9-wire head. They can
print in a compressed mode of 132 characters per line, in a
standard mode of 80 characters per line, in a double width,
compressed mode of 66 characters per line, and in a double width
mode of 40 characters per line. The printers can print double-size
characters and double-strike characters. The printers print the
standard ASCII, 96-character, uppercase and lowercase character
sets. A printer without an extended character set also has a set of
64 special block graphic characters.
The IBM 80 CPS Graphics Printer has additional capabilities

including: an extended character set for intemationallanguages,
subscript, superscript, an underline mode, and programmable
graphics.
The printers can also accept commands setting the line-feed

control desired for the application. They attach to the system unit
through the printer adapter or the combination monochrome
display and printer adapter. The cable is a 25-lead shielded cable
with a 25-pin D-shell connector at the system unit end, and a
36-pin connector at the printer end.
Printers 1-91
(1 ) Print Method: Serial-impact dox matrix
(2) Print Speed: 80 cps
(3) Print Direction: Bidirectional with logical seeking
(4) Number of Pins in Head: 9
(5) Line Spacing: 1/16 inch (4.23 mm) or programmable
(6) Printing Characteristics
Matrix: 9x9
Character Set: Full 96-character ASCII with descenders
plus 9 international characters/symbols.
Graphic Character: See "Additional Printer Specifications'~
(7) Printing S.izes
Maximum
Characters characters
per inch per inch
Normal: 10 80
Double Width: 5 40
Compressed: 16.5 132
Double Width-Compressed: 8.25 66
(8) Media Handling
Paper Feed: Adjustable sprocket pin feed
Paper Width Range: 4 inch (101.6 mm) to 10 inch (254 mm)
Copies: One original plus two carbon copies (total
thickness not to exceed 0.012 inch (0.3
mm)). Minimum paper thickness is 0.0025
inch (0.064 mm).
Paper Path: Rear
(9) Interfaces
Standard: Parallel 8-bit
Data and Control Lines
(10) Inked Ribbon
Color: Black
Type: Cartridge
Life Expecta ncy: 3 million characters
(11 ) Environmental Conditions
Operating Temperature Range: 41 to 95° F (5 to 35° C)
Operating Humidity: 10 to 80% non-condensing
(12) Power Requirement
Voltage: 120 Vac, 60 Hz
Current: 1 A maximum
Power Consumption: 100 VA maximum
(13) Physical Characteristics
Height: 4.2 inches (107 mm)
Width: 14.7 inches (374 mm)
Depth: 12.0 inches (305 mm)
Weight: 12 pounds (5.5 kg)
Printer Specifications
1-92 Printers
IBM 80 CPS Matrix Printer
Graphics: 64 block characters.

IBM 80 CPS Graphics Printer Set 1
Extra Character Set: Additional ASCII numbers 160 to 175
contain European characters. Numbers 176
to 223 contain graphic characters. Numbers
224 to 239 contain selected Greek
characters. Numbers 240 to 255 contain
math and extra symbols.
Set 2
The difference in set 2 are ASCII numbers 3,
4,5,6, and 21. ASCII numbers 128 to 175
contain European characters.
Graphics: There are 20 block characters and
programmable graphics.
(7) Printing Sizes Maximum
Characters characters
per inch per line
Subscript: 10 80
Superscript: 10 80
Additional Printer Specifications
Printers 1-93
Setting the DIP Switches
There are two DIP switches on the control circuit board. In order
to satisfy the user's specific requirements, desired control modes
are selectable by the DIP switches. The functions of the switches
and their preset conditions at the time of shipment are as shown in
the following figures.
DIP Switch 2 DIP Switch 1
Location of Printer DIP Switches
Switch Factory-Set
Number Function On Off Condition
1-1 Not Applicable - - On
1-2 CR Print Only Print & On
Line Feed
1-3 Buffer Full Print Only Print & Off
Line Feed
1-4 Cancel Code Invalid Valid Off
1-5 Delete Code Invalid Valid On
1-6 Error Buzzer Sounds Does Not On
Sound
1-7 Character Generator N.A. Graphic Off
Patterns
Select
1-8 SLCT IN Signal Fixed Not Fixed On
Functions and Conditions of DIP Switch 1 (Matrix)
1-94 Printers
Switch Factory-Set
2-3 Auto Feed XT Signal Fixed Not Fixed Off
Internally Internally
2-4 Coding Table Select N.A. Standard Off
Functions and Conditions of DIP Switch 2 (Matrix)
Switch Factory-Set
1 -1 Not Applicable - - On
1-2 CR Print Only Print & On
Line Feed
1-3 Buffer Full Print Only Print & Off
Line Feed
1-4 Cancel Code Invalid Valid Off
1-6 Error Buzzer Sound Does Not On
Sound
1-7 Character Generator Set 2 Set 1 Off
1-8 SLCT IN Signal Fixed Not Fixed On
Functions and Conditions of DIP Switch 1 (Graphics)
Switch Factory-Set
2-1 Form Length 12 Inches 11 Inches Off
2-2 Line Spacing 1/8 Inch 1/6 Inch Off
2-3 Auto Feed XT Signal Fixed Not Fixed Off
2-4 1 Inch Skip Over Perforation Valid Not Valid Off
Functions and Conditions of DIP Switch 2 (Graphics)
Printers 1-95
Parallel Interface Description
Specifications:
• Data transfer rate: 1000 cps (maximum)
• Synchronization: By externally-supplied STROBE pulses.
• Handshaking ACKNLG or BUSY signals.
• Logic level: Input data and all interface control signals are
compatible with the TTL level.
Connector: Plug: 57-30360 (Amphenol)
Connector pin assignment and descriptions of respective interface

signals are provided on the following pages.
Data transfer sequence:
BUSy-----,
ACKNLG
0.5 flS (Minimum)
DATA--~
STROBE ---+-....
0.5 flS (Minimum)
0.5 flS (Minimum)
Parallel Interface Timing Diagram
1-96 Printers
Signal Return
Pin No. Pin No. Signal Direction Description
1 19 STROBE In STROBE pulse to read
data in. Pulse width must
be more than 0.5 /1S at
receiving terminal. The
signal level is normally
"high"; read-in of data is
performed at the "Iow "
level of this signal.
2 20 DATA 1 In These signals represent
3 21 DATA 2 In information of the 1 st to
4 22 DATA 3 In 8th bits of parallel data
5 23 DATA 4 In respectively. Each signal
6 24 DATA 5 In is at "high" level when
7 25 DATA 6 In data is logical "1" and
8 26 DATA 7 In "low" when logical "0."
9 27 DATA 8 In
10 28 ACKNLG Out Approximately 5 /1S pulse;
"low" indicates that data
has been received and
the pri nter is ready to
accept other data.
11 29 BUSY Out A "high" signal indicates
that the printer cannot
receive data. The signal
becomes "high" in the
following cases:
1. During data entry.
2. During printing
operation.
3. In "offline " state.
4. During printer error
status.
Connector Pin Assignment and Descriptions of Interface Signals

(Part 1 of 3)
Printers 1-97
Signal Return
12 30 PE Out A "high" signal indicates
that the printer is out of
paper.
13 - SLCT Out This signal indicates that
the printer is in the
se Iected state.
14 - AUTO In With this signal being at
FEED XT "low" level, the paper is
automatically fed one line
after printing. (The signal
level can be fixed to
"low" with DIP SW pin
2-3 provided on the
control circuit board.)
15 - NC Not used.
16 - OV Logic GND level.
17 - CHASSIS- - Printer chassis GND. In
GND the printer, the chassis
GND and the logic GND
are isolated from each
other.
18 - NC - Not used.
19-30 - GND - "Twisted-Pair Return"
signal; GND level.
31 - INIT In When the level of this
signal becomes "low" the
printer controller is reset
to its initial state and the
print buffer is cleared.
This signal is normally at
"high" level, and its
pulse width must be
more than 50 f.JS at the
receiving terminal.

(Part 2 of 3)
1-98 Printers
Signal Return
32 ERROR Out The level of this signal
becomes "Iow " when the
printer is in "Paper End"
state, "Offline" state and
"Error" state.
33 - GND - Same as with pin
numbers 19 to 30.
34 - NC - Not used.
35 Pulled up to +5 Vdc
through 4.7 k-ohms
resistance.
36 - SLCTIN In Data entry to the printer
is possible only when the
level of this signal is
"low." (Internal fixing can
be carried out with DIP
SW 1-8. The condition at
the time of shipment is
set "low" for this signaL)
Notes: 1. "Direction" refers to the direction of signal flow as viewed from

the printer.
2. "Return" denotes "Twisted-Pair Return" and is to be connected at
signal-ground level.
When wiring the interface, be sure to use a twisted-pair cable for
each signal and never fail to complete connection on the return
side. To prevent noise effectively, these cables should be shielded
and connected to the chassis of the system unit and printer,
respectively.
3. All interface conditions are based on TTL level. Both the rise and
fall times of each signal must be less than 0.2 j1S.
4. Data transfer must not be carried out by ignoring the ACKNLG or
BUSY signal. (Data transfer to this printer can be carried out only
after confirming the ACKNLG signal or when the level of the
BUSY signal is "low.")

(Part 3 of 3)
Printers 1-99
Printer Modes for the IBM 80 CPS
Printers
The IBM 80 CPS Graphics Printer can use any of the
combinations listed below, and the print mode can be changed at
any place within a line.
The IBM 80 CPS Matrix Printer cannot use the Subscript,

Superscript, or Underline print modes. The Double Width print
mode will affect the entire line with the matrix printer.
The allowed combinations of print modes that can be selected are

listed in the following table. Modes can be selected and combined
if they are in the same vertical column.
Printer Modes
Normal X X X
Compressed X X X
Emphasized X X X
Double Strike X X X
Subscript X X X
Superscript X X X
Double Width X X X X X X X X X
Underline X X X X X X X X X
1-100 Printers
Printer Control Codes
On the following pages you will find complete codes for printer
characters, controls, and graphics. You may want to keep them
handy for future reference. The printer codes are listed in ASCII
decimal numeric order (from NUL which is 0 to DEL which is
127). The examples given in the Printer Function descriptions are
written in the BASIC language. The "input" description is given
when more information is needed for programming considerations.
ASCII decimal values for the printer control codes can be found
under "Printer Character Sets."
The descriptions that follow assume that the printer DIP switches
have not been changed from their factory settings.
Printers 1-101
Printer
Code Printer Function
NUL Null
Used with ESC B and ESC D as a list terminator. NUL is also used
with other printer control codes to select options (for example,
ESC S).
Example:
LPRINT CHR$ (0);
BEL Bell
Sounds the printer buzzer for 1 second.
Example:
LPRINT CHR$ (7);
HT Horizontal Tab
Tabs to the next horizontal tap stop. Tab stops are set with ESC D.
No tab stops are set when the printer is powered on. (Graphics
Printer sets a tab stop every 8 columns when powered on.)
Example:
LPRINT CHR$ (9);
LF line Feed
Spaces the paper up one line. Line spacing is 116-inch unless
reset by ESC A, ESC 0, ESC 1, ESC 2 or ESC 3.
Example:
LPRINT CHR$(1 0);
VT Vertical Tab
Spaces the paper to the next vertical tab position. (Graphics Printer
does not allow vertical tabs to b.e set; therefore, the VT code is
treated as LF.)
Example:
LPRINT CHR$ (11);
FF Form Feed
Advances the paper to the top of the next page.
Note: The location of the paper, when the printer is powered on,
determines the top of the page. The next top of page is 11
inches from that position. ESC C can be used to change the
page length.
Example:
LPRINT CHR$ (12);
CR Carriage Return
Ends the line that the printer is on and prints the data remaining in
the printer buffer. (No Line Feed operation takes place.)
Note: IBM Personal Computer BASIC adds a Line Feed unless
128 is added [for example, CHR$ (141 )].
Example:
LPRINT CHR$ (13);
1-102 Printers
Printer
SO Shift Out (Double Width)
Changes the printer to the Double Width print mode.
Note: A Carriage Return, Line Feed or DC4 cancels Double Width
print mode.
Example:
LPRINT CHR$( 14);
SI Shift In (Compressed)
Changes the printer to the Compressed Character print mode.
Example:
LPRINT CHR$(15);
DC1 Device Control 1 (Printer Selected)
(Graphics Printer ignores DC1)
Printer accepts data from the system unit. Printer DIP switch 1-8
must be set to the Off position.
Example:
LPRINT CHR$(17);
DC2 Device Control 2 (Compressed Off)
Stops printing in the Compressed print mode.
Example:
LPRINT CHR(18);
DC3 Device Control 3 (Printer Deselected)
(Graphics Printer ignores DC3)
Printer does not accept data from the system unit. The system unit
must have the printer select line low, and DIP switch 1-8 must be in
the Off position.
Example:
LPRINT CHR$(19);
DC4 Device Control 4 (Double Width Off)

Stops printing in the Double Width print mode.
Example:
LPRINT CHR$(20);
CAN Cancel
Clears the printer buffer. Control codes, except SO, remain in effect.
Example:
LPRINT CHR$ (24);
ESC Escape
Lets the printer know that the next data sent is a printer command.
(See the following list of commands.)
Example:
LPRINT CHR$(27);
Printers 1-103
Printer
ESC- Escape Minus (Underline)
Format: ESC -;n;
(Graphics Printer only)
ESC - followed by a 1, prints all of the following data with an
underline.
ESC - followed by a 0 (zero), cancels the Underline print mode.
Example:
LPRINT CHR$(27);CHR$(45);CHR$(1);
ESC 0 Escape Zero (1 IS-Inch Line Feeding)
Changes paper feeding to 118 inch.
Example:
LPRINT CHR$(27);CHR$(48);
ESC 1 Escape 1 (7/72-lnch Line Feeding)
Changes paper feed to 7/72 inch.
Example:
ESC 2 Escape Two (Starts Variable Line Feeding)
ESC 2 is an execution command for ESC A. If no ESC A command
has been given, line feeding returns to 1/6-inch.
Example:
ESC 3 Escape Three (Variable Line Feeding)
Format: ESC 3;n;
Changes the·paper feeding to n/216-inch. The example below sets
the paper feeding to 54/216 (1/4) inch. The value of n must be
between 1 and 255.
Example:
LPRINT CHR$(27);CHR$(51 );CHR$(54);
ESC 6 Escape Six (Select Character Set 2)
Selects character set 2. (See "Printer Character Set 2. ")
Example:
ESC 7 Escape Seven (Select Character Set 1.)
Selects character set 1. (See "Printer Character Set 1.")
Character set 1 is selected when the printer is powered on or reset.
Example:
ESC 8 Escape Eight (Ignore Paper End)
Allows the printer to print to the end of the paper. The pri nter
ignores the Paper End switch.
Example:
1-1 04 Printers
Printer
ESC 9 Escape Nine (Cancel Ignore Paper End)
Cancels the Ignore Paper End command. ESC 9 is selected when
the printer is powered on or reset.
Example:
ESC < Escape Less Than (Home Head)
The print head will return to the left margin to print the line
following ESC <. This will occur for one line only.
Example:
ESCA Escape A (Sets Variable Line Feeding)

Format: ESC A;n;
Escape A sets the line-feed to n/72-inch. The example below tells
the printer to set line feeding to 24/72-inch. ESC 2 must be sent to
the printer before the line feeding will change. For example, ESC
A;24 (text) ESC 2 (text). The text following ESC A;24 will space at
the previously set line-feed increments. The text following ESC 2
will be printed with new line-feed increments of 24/72-inch. Any
increment between 1/72 and 85/72 may be used.
Example:
LPRINT CHR$(27);CHR$(65);CHR$(24);CHR$(27);CHR$(50);
ESC B Escape B (Set Vertical Tabs)

Format: ESC B;n, ;n 2 ; ... n k ;NUL;
(Graphics Printer ignores ESC B)
Sets vertical tab stop positions. Up to 64 vertical tab stop positions
are recognized by the printer. The n's, in the format above, are used
to indicate tab stop positions. Tab stop numbers must be received in
ascending numeric order. The tab stop numbers will not become
valid until the NUL code is entered. Once vertical tab stops are
established, they will be valid until new tab stops are specified. (If
the printer is reset or powered Off, set tab stops are cleared.) If no
tab stop is set, the Vertical Tab command behaves as a Line Feed
command. ESC B followed only by NUL will cancel tab stops. The
form length must be set by the ESC C command prior to setting
tabs.
Example:
LPRINT CH R$(27);CHR$(66);CHR$( 1O);CHR$(20);CH R$(40);CHR$(O);
Printers 1-105
Printer
ESCC Escape C (Set Lines per Page)
Format: ESC C;n;
Sets the page length. The ESC C command must have a value
following ino specify the length of page desired. (Maximum form
length for the printer is 127 lines.)
The example below sets the page length to 55 lines. The printer
defaults to 66 lines per page when powered on or reset.
Example:
Escape C (Set Inches per Page)
Format: ESC C;n;m;
Escape C sets the length of the page in inches. This command
requires a value of 0 (zero) for n, and a value between 1 and 22 for
m.
Example:
LPRINT CHR$(27);CHR$(67);CHR$(0);CHR$(12);
ESC D Escape D (Set Horizontal Tab Stops)

Format: ESC D;n,;n 2 ; ... n k;NUL;
Sets the horizontal tab stop positions. The example below shows
the horizontal tab stop positions set at printer column positions of
10,20, and 40. They are followed by CHR$(O), the NUL code. They
must also be in ascending numeric order as shown. Tab stops can
be set between 1 and 80. When in the Compressed print mode, tab
stops can be set up to 132.
The maximum number of tabs that can be set is 112. The Graphics
Printer can have a maxim.um of 28 tab stops. The HT (CHR$(9)) is
used to execute a tab operation.
Example:
LPRI NT CH R$(27);CH R$(68);CH R$( 10)CHR$(20)CHR$(40); CHR$(O);
ESC E Escape E (Emphasized)
Changes the printer to the Emphasized print mode. The speed of the
printer is reduced to half speed during the Emphasized print mode.
Example:
ESC F Escape F (Emphasized Off)
Stops printing in the Emphasized print mode.
Example:
ESCG Escape G (Double Strike)
Changes the printer to the Double Strike print mode. The paper is
spaced 1/216 of an inch before the second pass of the print head.
Example:
1-106 Printers
Printer
ESC H Escape H (Double Strike Off)
Stops printing in the Double Strike mode.
Example:
ESCJ Escape J (Set Variable Line Feeding)
Format: ESC J;n;
When ESC J is sent to the printer, the paper will feed in increments
of n/216 of an inch. The value of n must be between 1 and 255.
The example below gives a line feed of 50/216-inch. ESC J is
canceled after the line feed takes place.
Example:
ESC K Escape K (480 Bit-Image Graphics Mode)
Format ESC K;n,;n 2 ;v,;v 2 ; ... v k ;
Changes from the Text mode to the Bit-Image Graphics mode. n,
and n 2 are one byte, which specify the number of bit-image data
bytes to be tra nsferred. v, through vk are the bytes of the bit-image
data. The number of bit-image data bytes (k) is equal to n, +256n 2
and ca nnot exceed 480 bytes. At every horizonta I position, each
byte can print up to 8 vertical dots. Bit-image data may be mixed
with text data on the same line.
Note: Assign values to n, and n 2 as follows:
n, represents values from 0 - 255.
n 2 represents values from 0 - 1 x 256.
MSB is most significant bit and LSB is least significant bit.
I MSB LSB I
15 14 13 12 11 10 9 8
222 2 2 2 2 2
n,
I MSB LSB I
7 6 5 4 3 2 1 0
22222 222
Printers 1-107
Data sent to the printer.
Text (20 characters) T ESCTK Tn=360 TBit-image data I Next data I
In text mode, 20 characters in text mode correspond to 120 bit-image
positions (20 x 6 = 120). The printable portion left in Bit-Image mode is 360
dot positions (480 - 120 = 360).
Data sent to the printer.
Data A 1ESC K 1 n,1 n 2 1Data B 1 Data C 1 ESC 1 Kin, I n I Data D

2
Text Length of I Bit-

image
I Text I Length of
Bit-
I image
data data data data data data
1 - - - - - - - - - 4 8 0 bit-image dot positions --------.~I
Example:
TYPE B:GRAPH.TXT
1 'OPEN PRINTER IN RANDOM MODE WITH LENGTH OF 255
2 OPEN "LPn:" AS #1
3 WIDTH "LPT1",255
4 PRINT #1 ,CHR$(13);CHR$(1 0);
5 SLASH$=CHR$(1 )+CHR$(02)+CHR$(04)+CHR$(08)
6 SLASH$=SLASHS+CHR$(16)+CHR$(32)+CHR$(64)+CHR$(128)+CHR$(0)
7 GAP$=CHR$(O)+CHR$(O)+CHR$(O)
8 NDOTS=4HQ
9 'ESCKN1 N2
10 PRINT #1 ,CHR$(27);"K";CHR$(NDOTS MOD 256);CHR$(FIX (NDOTSI256});
11 ' SEND NDOTS NUMBER OF BIT IMAGE BYTES
12 FOR 1=1 TO NDOTS/12 'NUMBER OF SLASHES TO PRINT USING
GRAPHICS
13 PRINT #1 ,SLASH$;GAPS;
14 NEXT I
15 CLOSE
16 END
This example will give you a row of slashes printed in the 480 Bit-Image mode.
1-108 Printers
Printer
ESC L Escape L (960 Bit-Image Graphics Mode)
Format: ESC L;n1;n2;v1;v2; ... vk;
Changes from the Text mode to the Bit-Image Graphics mode. The
input is similar to ESC K. The 960 Bit-Image mode prints at half the
speed of the 480 Bit-Image Graphics mode, but can produce a
denser graphic image. The number of bytes of bit-image Data (k) is
n 1 + 256n 2 but cannot exceed 960. n 1 is in the range of 0 to 255.
ESC N Escape N (Set Skip Perforation)
Format ESC N;n;
Sets the Skip Perforation function. The number following ESC N
sets the value for the number of lines of Skip Perforation. The
example shows a 12-line skip perforation. This will print 54 lines
and feed the paper 12 lines. The value of n must be between 1 and
127. ESC N must be reset anytime the page length (ESC C) is
changed.
Example:
CHR$(27);CHR$(78);CHR$(12);
ESCO Escape 0 (Cancel Skip Perforation)

Cancels the Skip Perforation function.
Example:
ESC S Escape S (Subscript/Superscript)
Format: ESC S;n;
Changes the printer to the Subscript print mode when ESC S is
followed by a 1, as in the example below. When ESC S is followed
by a 0 (zero), the printer will print in the Superscript print mode.
Example:
ESCT Escape T (Subscript/Superscript Off)

The printer stops printing in the Subscript or Superscript print
mode.
Example:
ESC U Escape U (Unidirectional Printing)
Format: ESC U;n;
The printer will print from left to right following the input of ESC
U; 1. When ESC U is followed by a 0 (zero), the left to right printing
operation is canceled. The Unidirectional print mode (ESC U)
ensures a more accurate print-start position for better print quality.
Example:
Printers 1-109
Printer
ESCW Escape W (Double Width)
Format: ESC W;n;
Changes the printer to the Double Width print mode when ESC W is
followed by a 1. This mode is not canceled by a line-feed operation
and must be canceled with ESC W followed by a 0 (zero).
Example:
ESCY Escape Y (960 Bit-Image Graphics Mode Normal Speed)
Format: ESC Y n,;n 2 ;v,;v2 ; ... v k ;
Changes from the Text mode to the 960 Bit-Image Graphics mode.
The printer prints at normal speed during this operation and cannot
print dots on consecutive dot positions. The input of data is similar to
ESC L.
ESC Z Escape Z (1920 Bit-Image Graphics Mode)
Format: ESC Z;n,;n 2 ;v,;v2 ; ... v k;
Changes from the Text mode to the 1920 Bit-Image Graphics mode.
The input is similar to the other Bit-Image Graphics modes. ESC Z
can print only every third dot position.
DEL Delete (Clear Printer Buffer)
(Graphics Printer ignores DEL)
Clears the printer buffer. Control codes, except SO, still remain in
effect. DIP switch 1-5 must be in the Off position.
Example:
LPRINT CHR$(127);
1-110 Printers
Matrix Printer Character Set (Part 1 of 2)
Printers 1-111
Matrix Printer Character Set (Part 2 of 2)
1-112 Printers
Graphics Printer Character Set 1 (Part 1 of 2)
Printers 1-113
., XX' I « » :::: : ::
• • ii ii ! ~
r=-
---I·
--- ':-::-
1-114 Printers
Printers 1-115
130 131 132 133 134 135 136 137 138 139
e a a a.. a «; 0
e e e I
1-116 Printers
IBM Printer Adapter
The printer adapter is specifically designed to attach printers with

a parallel port interface, but it can be used as a general
input/output port for any device or application that matches its
input/output capabilities. It has 12 TTL-buffer output points,
which are latched and can be written and read under program
control using the processor In or Out instruction. The adapter also
has five steady-state input points that may be read using the
processor's In instructions.
In addition, one input can also be used to create a processor

interrupt. This interrupt can be enabled and disabled under
program control. Reset from the power-on circuit is also ORed
with a program output point, allowing a device to receive a
power-on reset when the processor is reset.
The input/output signals are made available at the back of the

adapter through a right-angled, PCB-mounted, 25-pin, D-shell
connector. This connector protrudes through the rear panel of the
system or expansion unit, where a cable may be attached.
When this adapter is used to attach a printer, data or printer

commands are loaded into an 8-bit, latched, output port, and the
strobe line is activated, writing-data to the printer. The program
then may read the input ports for printer status indicating when
the next character can be written, or it may use the interrupt line
to indicate "not busy" to the software.
The output ports may also be read at the card's interface for
diagnostic loop functions. This allows faults to be isolated
between the adapter and the attaching device.
This same function is also part of the combination IBM

Monochrome Display and Printer Adapter. A block diagram of
the printer adapter is on the next page.
Printer Adapter 1-117

8 25-Pin D-Shell
L:u, Buff..8 . Data Latch

Connector
.. 8
-. Enable
~ Clock
~ Trans-
ceiver
.... .
... 8 ..
r DIR
I DIR O.C.
Read Drivers SLCTIN
A.~ Data STROBE
Write Data AUTO
Command FD XT
Decoder Write Control INIT
Read Status
Read
Control
r-
Bus Control
Buffers Latch
~ Enable
~ 4 Clock -
5
4 Enable
... --.
r
Clear
- --
ERROR
SLCT
PE
ACK
R eset
BUSY
Printer Adapter Block Diagram
1-118 Printer Adapter

Programming Considerations
The printer adapter responds to five I/O instructions: two output
and three input. The output instructions transfer data into 2
latches whose outputs are presented on pins of a 25-pin D-shell
connector.
Two of the three input instructions allow the processor to read

back the contents of the two latches. The third allows the
processor to read the real time status of a group of pins on the
connector.
A description of each instruction follows.
IBM Monochrome Display &

Printer Adapter Printer Adapter
Output to address hex 3BC Output to address hex 378
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2
The instruction captures data from the data bus and is present on
the respective pins. These pins are each capable of sourcing
2.6 rnA and sinking 24 rnA.
It is essential that the external device not try to pull these lines to
ground.

Output to address hex 3BE Output to address hex 37 A
Bit 4
-
Bit 3 Bit 2
-Bit 1 - -
Bit 0
IRQ Pin 17 Pin 16 Pin 14 Pin 1

Enable

This instruction causes the latch to capture the five least
significant bits of the data bus. The four least significant bits
present their outputs, or inverted versions of their outputs, to the
respective pins shown above. If bit 4 is written as 1, the card will
interrupt the processor on the condition that pin 10 transitions
high to low.
These pins are driven by open collector drivers pulled to +5 Vdc

through 4.7 k-ohm resistors. They can each sink approximately
7 rnA and maintain 0.8 volts down-level.

Input from address hex 3BC Input from address hex 378
This command presents the processor with data present on the

pins associated with the out to hex 3BC. This should normally
reflect the exact value that was last written to hex 3BC. If an
external device should be driving data on these pins (in violation
of usage ground rules) at the time of an input, this data will be
ORed with the latch contents.

Input from address hex 3BD Input from address hex 379
This command presents realtime status to the processor from the

pins as follows.
I Bit 7 I Bit 6 Bit 5 I Bit 4 Bit 3 I Bit 2 I Bit 1 I Bit 0 I

I Pin 11 I Pin 10 Pin 12 I Pin 13 Pin 15 I - I I I

Input from address hex 3BE Input from address hex 37A
This instruction causes the data present on pins 1, 14, 16, 17, and
the IRQ bit to read by the processor. In the absence of external
drive applied to these pins, data read by the processor will exactly
match data last written to hex 3BE in the same bit positions. Note
that data bits 0-2 are not included. If external drivers are dotted
to these pins, that data will be ORed with data applied to the pins
by the hex 3BE latch.

IRQ
- -
Pin 17 Pin 16
- -
Pin 14
--
Pin 1
Enable
Por=O Por=1 Por=O Por=1 Por=1
These pins assume the states shown after a reset from the
processor.

25-Pin D-Shell
Connector
Rear Panel
0
14
• •
•
• •
•
• ••
•
•
•
25
Connector •
Note: All outputs are software-generated,
and all inputs are real-time signals
(not latched).
0
At Standard TTL Levels

Signal Adapter
N arne p.In N urn b er
-Strobe 1
+Data Bit 0 2
+Data Bit 1 3
+Data Bit 2 4
+Data Bit 3 5
+Data Bit 4 6
+Data Bit 5 7
+Data Bit 6 8
Printer +Data Bit 7 9 Printer
- Acknowledge 10 Adapter
+Busy 11
+P.End (out of paper) 12
+Select 13
-Auto Feed 14
- Error 15
-Initialize Printer 16
- Select Input 17
Ground 18-25

IBM Monochrome Display and
Printer Adapter
This chapter has two functions. The first is to provide the

interface to the IBM Monochrome Display. The second provides
a parallel interface for the IBM 80 CPS Printer. This second
function is fully discussed in the "IBM Printer Adapter" section.
The monitor adapter is designed around the Motorola 6845 CRT
controller module. There are 4K bytes of static memory on the
adapter which is used for the display buffer. This buffer has two
ports and may be accessed directly by the processor. No parity is
provided on the display buffer.
Two bytes are fetched from the display buffer in 553 ns, providing
a data rate of 1.8M bytes/second.
The monitor adapter supports 256 different character codes. An
8K-byte character generator contains the fonts for the character
codes. The characters, values, and screen characteristics are give:.}
in "Appendix C: Of Characters, Keystrokes, and Color."
This monitor adapter, when used with a display containing P39
phosphor, will not support a light pen.
Where possible, only one low-power Schottky (LS) load is
present on any I/O slot. Some of the address bus lines have two
LS loads. No signal has more than two LS loads.
Characteristics of the monitor adapter are listed below:
• 80 by 25 screen
• Direct-drive output
• 9 by 14 character box
• 7 by 9 character
• 18 kHz monitor
• Character attributes
Monochrome Adapter 1-123
Processor
Address ..
(12) ..
Memory
Address
(1~ Multiplexer (10) (10)
2K Memory
2K Memory
Character
Attribute
Code
(8)
Data 1.0.
Processor
Data
Bus
Gating
. (8)
Character
Clock 'F
I
~
(8)
BDO-7
MA Octal
Latch
1. Octal
Latch
. r--
AO .. (4)
RA
.. Character
Generator
Attribute
Decode
Chip MC6845
CRTC
Select DOTCLK
Timing
Signals
.. Shift
Register
Video
Process
Serial Dots Logic
r ..
HSYNC, VSYNC, CURSOR, DISPEN
Characte.r
Clock
I +
Monitor
Direct Drive
Outputs
IBM Monochrome Display Adapter Block Diagram
1-124 Monochrome Adapter

The following table summarizes the 6845 internal data registers,
their functions, and their parameters. For the IBM Monochrome
Display, the values must be programmed into the 6845 to ensure
proper initialization of the device.
IBM Monochrome
Register Register Program Display
Number File Unit (Address in hex)
RO Horizontal Total Characters 61

R1 Horizonta I Displayed Characters 50
R2 Horizontal Sync Position Characters 52
R3 Horizontal Sync Width Characters F
R4 Vertical Total Character Rows 19
R5 Vertical Total Adjust Scan Line 6
R6 Vertical Displayed Character Row 19
R7 Vertical Sync Position Character Row 19
R8 Interlace Mode -------- 02
R9 Maximum Scan Line Scan Line D
Address
R10 Cursor Start Scan Line B
R11 Cursor End Scan Line C
R12 Start Address (H) -------- 00
R13 Start Address (L) -------- 00
R14 Cursor (H) -------- 00
R15 Cursor (L) -------- 00
R16 Reserved -------- --
R17 Reserved -------- --
To ensure proper initialization, the first command issued to the

attachment must be to send to CRT control port 1 (hex 3B8), a
hex 01, to set the high-resolution mode. If this bit is not set, then
the processor access to the monochrome adapter must never
occur. If the high-resolution bit is not set, the processor will stop
running.
System configurations that have both an IBM Monochrome

Display Adapter and Printer Adapter, and an IBM
Color/Graphics Monitor Adapter, must ensure that both adapters
are properly initialized after a power-on reset. Damage to either
display may occur if not properly initialized.

The IBM Monochrome Display and Printer Adapter supports 256
different character codes. In the character set are alphanumerics
and block graphics. Each character in the display buffer has a
corresponding character attribute. The character code must be an
even address, and the attribute code must be an odd address in the
display buffer.
7 6 5 4 3 2 0
Character Code
Even Address (M)
7 6 5 4 3 2 0
Attribute Code
BL
I IG R I B II
I
R I
G
I
B I Odd Address (M+1)
I Foreground
~
Intensity
I I I Background
I Blink
The adapter decodes the character attribute byte as defined above.

The blink and intensity bits may be combined with the foreground
and background bits to further enhance the character attribute
functions listed below.
Background Foreground
R G B R G B Function
0 0 0 0 0 0 Non-Display
0 0 0 0 0 1 Underline
0 0 0 1 1 1 White Character IBlack Background
1 1 1 0 0 0 Reverse Video

The 4K display buffer supports one screen of 25 rows of 80
characters, plus a character attribute for each display character.
The starting address of the buffer is hex BOOOO. The display
buffer can be read from using DMA; however, at least one
wait-state will be inserted by the processor. The duration of the
wait-state will vary, because the processor/monitor access is
synchronized with the character clock on this adapter.
Interrupt level 7 is used on the parallel interface. Interrupts can be

enabled or disabled through the printer control port. The interrupt
is a high-level active signal.
The figure below breaks down the functions of the I/O address
decode for the adapter. The I/O address decode is from hex 3BO
through hex 3BF. The bit assignment for each I/O address
follows:
1/0 Register
Address Function
3BO Not Used
3B1 Not Used
3B2 Not Used
3B3 Not Used
3B4* 6845 Index Register
3B5* 6845 Data Register
3B6 Not Used
3B7 Not Used
3B8 CRT Control Port 1
3B9 Reserved
3BA CRT Status Port
3BB Reserved
3BC Parallel Data Port
3BD Printer Status Port
3BE Printer Control Port
3BF Not Used
*The 6845 Index and Data Registers are

used to program the CRT controller to
interface the high-resolution IBM
Monochrome Display.
I/O Address and Bit Map

Bit
Number Function
0 +High Resolution Mode
1 Not Used
2 Not Used
3 +Video Enable
4 Not Used
5 +Enable Blink
6,7 Not Used
6845 CRT Control Port 1 (Hex 3B8)
Bit
Number Function
0 +Horizontal Drive
1 Reserved
2 Reserved
3 +Black/White Video
6845 CRT Status Port (Hex 3BA)

9-Pin
Monochrome
Display
Connector
o
6
o
o
Connector

Ground 1
Ground 2
Not Used 3
Not Used 4 IBM
IBM
Not Used 5 Monochrome
Monochrome
Display and
Display +Intensity 6 Printer Adapter
+Video 7
+Horizontal 8
- Vertical 9
Note: Signal voltages are 0.0 to 0.6 Vdc at down level and +2.4 to 3.5
Vdc at high level.

Notes:

IBM Monochrome Display
The high-resolution IBM Monochrome Display attaches to the

system unit through two cables approximately 3 feet (914
millimeters) in length. One cable is a signal cable that contains the
direct drive interface from the IBM Monochrome Display and
Printer Adapter.
The second cable provides ac power to the display from the

system unit. This allows the system-unit power switch to also
control the display unit. An additional benefit is a reduction in the
requirements for wall outlets to power the system. The display
contains an ll-Yz inch (283 millimeters), diagonal 90 deflection
0
CRT. The CRT and analog circuits are packaged in an enclosure

so the display may either sit on top of the system unit or on a
nearby tabletop or desk. The unit has both brightness and
contrast adjustment controls on the front surface that are easily
accessible to the operator.
Screen
• High-persistence green phosphor (P 39).
• Etched surface to reduce glare.
• Size is 80 characters by 25 lines.
• Character box is 9 dots wide by 14 dots high.
Video Signal
• Maximum bandwidth of 16.257 MHz.
Monochrome Display 1-131

Vertical Drive
• Screen refreshed at 50 Hz with 350 lines of vertical resolution

and 720 lines of horizontal resolution.
Horizontal Drive
• Positive-level, TTL-compatibility at a frequency of

18.432 kHz.
1-132 Monochrome Display

IBM Color/Graphics Monitor
Adapter
The IBM Color/Graphics Monitor Adapter is designed to attach

to the IBM Color Display, to a variety of television-frequency
monitors, or to home television sets (user-supplied RF modulator
is required for home television sets). The adapter is capable of
operating in black-and-white or color. It provides three video
interfaces: a composite-video port, a direct-drive port, and a
connection interface for driving a user-supplied RF modulator. In
addition, a light pen interface is provided.
The adapter has two basic modes of operation: alphanumeric

(A/N) and all-points-addressable graphics (APA). Additional
modes are available within the A/N and APA modes. In the A/N
mode, the display can be operated in either a 40-column by
25-row mode for a low-resolution monitor or home television, or
in an 80-column by 25-row mode for high-resolution monitors. In
both modes, characters are defined in an 8-wide by 8-high
character box and are 7-wide by 7-high, with one line of
descender for lowercase characters. Both uppercase and lowercase
characters are supported in all modes.
The character attributes of reverse video, blinking, and

highlighting are available in the black-and-white mode. In the
color mode, sixteen foreground and eight background colors are
available for each character. In addition, blinking on a
per-character basis is available.
The monitor adapter contains 16K bytes of storage. As an

example, a 40-column by 25-row display screen uses 1000 bytes
to store character information, and 1000 bytes to store
attribute/color information. This would mean that up to eight
display screens can be stored in the adapter memory. Similarly, in
an 80-column by 25-row mode, four display screens may be
stored in the adapter. The entire 16K bytes of storage on the
display adapter are directly addressable by the processor, which
allows maximum software flexibility in managing the screen.
Color/Graphics Adapter 1-133

In A/N color modes, it is also possible to select the color of the
screen's border. One of sixteen colors can be selected.
In the AP A mode, there are two resolutions available: a

medium-resolution color graphics mode (320 PELs by 200 rows)
and a high-resolution black-and-white graphics mode (640 PELs
by 200 rows). In the medium-resolution mode, each picture
element (PEL) may have one of four colors. The background
color (color 0) may be any of the 16 possible colors. The
remaining three colors come from one of the two
software-selectable palettes. One palette contains green/red/
brown; the other contains cyan/magenta/white.
The high-resolution mode is available only in black-and-white

because the entire 16K bytes of storage in the adapter is used to
define the on or off of the PELs.
The adapter operates in noninterlace mode at either 7 or 14 MHz,

depending on the mode of operation selected.
In the A/N mode, characters are formed from a ROM character

generator. The character generator contains dot patterns for 256
different characters. The character set contains the following
major groupings of characters:
• 16 special characters for game support
• 15 characters for word-processing editing support
• 96 characters for the standard ASCII graphics set
• 48 characters for foreign-language support
• 48 characters for business block-graphics support (allowing

drawing of charts, boxes, and tables using single and double
lines)
• 16 selected Greek characters
• 15 selected scientific-notation characters
1-134 Color/Graphics Adapter

The color/graphics monitor adapter function is packaged on a
single card. The direct-drive and composite-video ports are
right-angle mounted connectors on the adapter, and extend
through the rear panel of the unit. The direct-drive video port is a
9-pin D-shell female connector. The composite-video port is a
standard female phono-jack.
The display adapter is implemented using a Motorola 6845 CRT

controller device. This adapter is highly programmable with
respect to raster and character parameters. Therefore, many
additional modes are possible with clever programming of the
adapter.

--
,
w
0'1
P rocessor
A ddress ...
... Address
Latch
....
~II."
Display
Buffer
(16K Bytes)
- Input
Buffer
....
..... ~
Processc
Data
~~
(')
• .
o V
0- Output
~ ~
-
o flrocessor Address Data Data
Latch
~ 6845 ~ f-
..
'0
t:r'
Data
...... CRT
Latch Latch Latch
(')
[Il
Controller
y Graphics
~ - •.... Serializer
-
~
(t
'"I
... Character ~R
rL:...
Alpha
Generator ~ ~G
Serializer
ROM Color
Encoder
Palettel
~B
. ~
4.....
Overscan
- --....
I ..... Vertical
Horizontal
Composite
4 Mode
Control ...
Timing
Generator
. Color
Generator
~
& Control
Color/Graphics Monitor Adapter Block Diagram

Descriptions of Major Components
Motorola 6845 CRT Controller

This device provides the necessary interface to drive a raster-scan
CRT.
Mode Set Register

This is a general-purpose, programmable, I/O register. It has I/O
ports that may be individually programmed. Its function in this
attachment is to provide mode selection and color selection in the
medium-resolution color-graphics mode.
Display Buffer
The display buffer resides in the processor-address space, starting
at address hex B8000. It provides 16K bytes of dynamic
read/write memory. A dual-ported implementation allows the
processor and the graphics control unit to access the buffer. The
processor and the CRT control unit have equal access to this
buffer during all modes of operation, except in the high-resolution
alphanumeric mode. In this mode, only the processor should
access to this buffer during the horizontal-retrace intervals. While
the processor may write to the required buffer at any time, a small
amount of display interference will result if this does not occur
during the horizontal-retrace intervals.
Character Generator
This attachment utilizes a ROM character generator. It consists of
8 K bytes of storage that cannot be read from or written to under
software control. This is a general-purpose ROM character
generator with three different character fonts. Two character fonts
are used on the color/graphics adapter: a 7-high by 7-wide
double-dot font and a 5-wide by 7-high single-dot font. The font is
selected by a jumper (P3). The single-dot font is selected by
inserting the jumper; the double-dot font is selected by removing
the jumper.

Timing Generator
This generator produces the timing signals used by the 6845 CRT
controller and by the dynamic memory. It also resolves the
processor/graphic controller contentions for accessing the display
buffer.
Composite Color Generator

This generator produces base band video color information.
Alphanumeric Mode
Every display-character position in the alphanumeric mode is
defined by two bytes in the regen buffer (a part of the monitor
adapter), not the system memory. Both the color/graphics and the
monochrome display adapter use the following 2-byte
character/attribute format.
Display-Character Code Byte Attribute Byte
7 6 5 4 3 2 o 7 6 5 4 3 2 o
The functions of the attribute byte are defined by the following

table:
Attribute Function Attribute Byte

7 6 5 4 3 2 1 0
B R G B I R G B
FG Background Foreground
Normal B 0 0 0 I 1 1 1
Reverse Video B 1 1 1 I 0 0 0
Nondisplay (Black) B 0 0 0 I 0 0 0
Nondisplay (White) B 1 1 1 I 1 1 1
I = Highlighted Foreground (Character)

B = Blinking Foreground (Character)

The attribute byte definitions are:
7 6 543 2 1 0
IBIR G Bill R G BI
Foreground Color
I
~
Intensity
I Background Color
I Blinking
In the alphanumeric mode, the display mode can be operated in

either a low-resolution mode or a high-resolution mode.
The low-resolution alphanumeric mode has the following features:
• Supports home color televisions or low-resolution monitors
• Displays up to 25 rows of 40 characters each
• ROM character generator that contains dot patterns for a

maximum of 256 different characters
• Requires 2,000 bytes of read/write memory (on the adapter)
• Character box is 8-high by 8-wide
• Two jumper-controlled character fonts are available:

5-wide by 7-high single-dot character font with one descender
7-wide by 7-high double-dot character font with one descender
• One character attribute for each character
The high-resolution alphanumeric mode has the following

features:
• Supports the IBM Color Display or other color monitor with

direct-drive input capability
• Supports a black-and-white composite-video monitor
• Displays up to 25 rows of 80 characters each

• ROM displays generator that contains dot patterns for a
maximum of 256 different characters
• Character box is 8-high by 8-wide
• Two jumper-controlled character fonts are available:

5-wide by 7-high single-dot character font with one descender
7-wide by 7-high double-dot character font with one descender
• One character attribute for each character
Monochrome vs Color/Graphics
Character Attributes
Foreground and background colors are defined by the attribute
byte of each character, whether using the IBM Monochrome
Display and Printer Adapter or the IBM Color/Graphics Monitor
Adapter. The following table describes the colors for each
adapter:
Attribute Byte Monochrome Color/Graphics

7 6 5 4 3 2 1 D Display Adapter Monitor Adapter
B R G B I R G B Background Character Background Character
FG Background Foreground Color Color Color Color
B 0 0 0 I 1 1 1 Black White Black White
B 1 1 1 I 0 0 0 White Black White Black
B 0 0 0 I 0 0 0 Black Black Black Black
B 1 1 1 I 1 1 1 White White White White
The monochrome display adapter will produce white characters

on a white background with any other code. The color/graphics
adapter will change foreground and background colors according
to the color value selected. The color values for the various red,
green, blue, and intensity bit settings are given in the following
table.

R G B I Color
0 0 0 0 Black
0 0 1 0 Blue
0 1 0 0 Green
0 1 1 0 Cyan
1 0 0 0 Red
1 0 1 0 Magenta
1 1 0 0 Brown
1 1 1 0 White
0 0 0 1 Gray
0 0 1 1 Light Blue
0 1 0 1 Light Green
0 1 1 1 Light Cyan
1 0 0 1 Light Red
1 0 1 1 Light Magenta
1 1 0 1 Yellow
1 1 1 1 White (High Intensity)
Code written with an underline attribute for the IBM

Monochrome Display, when executed on a color/graphics monitor
adapter, will result in a blue character where the underline
attribute is encountered. Also, code written on a color/graphics
monitor adapter with blue characters will be displayed as white
characters on a black background, with a white underline on the
IBM Monochrome Display.
Remember that not all monitors recognize the intensity (I) bit.
Graphics Mode
The IBM Color/Graphics Monitor Adapter has three modes
available within the graphics mode. They are low-resolution color
graphics, medium-resolution color graphics, and high-resolution
color graphics. However, only medium- and high-resolution
graphics are supported in ROM. The following table summarizes
the three modes.
Color/Graphics Adaptel 1-141

Mode Horizontal Vertical Number of Colors Available
(PEls) (Rows) (Includes Background Color)
Low Resolution 160 100 16 (Includes black-and-white)
Medium 320 200 4 Colors Total
Resolution 1 of 16 for Background and
1 of Green, Red, or Brown or
1 of Cyan, Magenta, or White
High Resolution 640 200 Black-and-white only
Low- Resolution Color-Graphics Mode

The low-resolution mode supports home television or color
monitors. This mode is not supported in ROM. It has the
following features:
• Contains a maximum of 100 rows of 160 PELs, with each

PEL being 2-high by 2-wide
• Specifies 1 of 16 colors for each PEL by the I, R, G, and

B bits
• Requires 16,000 bytes ofread/write memory (on the adapter)
• Uses memory-mapped graphics
Medium-Resolution Color-Graphics Mode

The medium-resolution mode supports home televisions or color
monitors. It has the following features:

PEL being I-high by I-wide
• Preselects one of four colors for each PEL
• Uses memory-mapped graphics

• Formats 4 PELs per byte in the following table:
7 6 5 4 3 2 o
C1 CO C1 CO C1 CO C1 CO
Fi rst Second Third Fourth
Display Display Display Display
PEL PEL PEL PEL
• Organizes graphics storage in two banks of 8,000 bytes, using

the following format:
Memory
Address
(in hex) Function
B8000
Even Scans
(0,2,4, .. 198)
8,000 bytes
B9F3F
Not Used
BAOOO
Odd Scans
( 1.3,5 .. 199)
8,000 Bytes
BBF3F
Not Used
BBFFF
Address hex B8000 contains PEL instruction for the upper-left

comer of the display area.
• Color selection is determined by the following logic:
C1 co Function
0 Dot takes on the color of 1 of 16 preselected background colors
0
°
1 Selects first color of preselected Color Set 1 or Color Set 2
1 0 Selects second color of preselected Color Set 1 or Color Set 2
1 1 Selects third color of preselected Color Set 1 or Color Set 2

Cl and CO will select 4 of 16 preselected colors. This color
selection (palette) is preloaded in an I/O port.
Tow two colors sets are:
Color Set 1 Color Set 2

Color 1 is Green Color 1 is Cyan
Color 2 is Red Color 2 is Magenta
Color 3 is Brown Color 3 is White
The background colors are the same basic 8 colors as defined

for low-resolution graphics, plus 8 alternate intensities dermed
by the intensity bit, for a total of 16 colors, including black and
white.
High-Resolution Black-and-White Graphics

Mode
The high-resolution mode supports color monitors. This mode has
the following features:

PEL being I-high by I-wide.
• Supports black-and-white mode only.
• Requires 16,000 bytes ofread/write memory (on the adapter).

• Addressing and mapping procedures are the same as
medium-resolution color graphics, but the data format is
different. In this mode, each bit in memory is mapped to a
PEL on the screen.
• Formats 8 PELs per byte in the following manner:
First Display PEL I

~
Second Display PEL I
Third Display PEL
Fourth Display PEL
II
Fifth Display PEL
Sixth Display PEL
Seventh Display PEL
Eighth Display PEL
Description of Basic Operations

In the alphanumeric mode, the adapter fetches character and
attribute information from its display buffer. The starting address
of the display buffer is programmable through the 6845, but it
must be an even address. The character codes and attributes are
then displayed according to their relative positions in the buffer.
Memory
Address
(in hex) Display Buffer
B8000
(Even) Character Code A
Starting B8001
Address Attribute A
B8002 (Example of a 40 by 25 Screen)
Character Code B
B8003 AB
Attribute B
X
B87CE
Character Code X Video Screen
Last B87CF
Address Attribute X

The processor and the display control unit have equal access to
the display buffer during all the operating modes, except the
high-resolution alphanumeric mode. During this mode, the
processor should access the display buffer during the vertical
retrace time. If it does not, the display will be affected with
random patterns as the processor is using the display buffer. In the
alphanumeric mode, the characters are displayed from a prestored
ROM character generator that contains the dot patterns of all the
displayable characters.
In the graphics mode, the displayed dots and colors (up to 16K
bytes) are also fetched from the display buffer. The bit
configuration for each graphics mode is explained in "Graphics
Mode."
I R G B Color
0 0 0 0 Black
0 0 0 1 Blue
0 0 1 0 Green
0 0 1 1 Cyan
0 1 0 0 Red
0 1 0 1 Magenta
0 1 1 0 Brown
0 1 1 1 White
1 0 0 0 Gray
1 0 0 1 Light Blue
1 0 1 0 Light Green
1 0 1 1 Light Cyan
1 1 0 0 Light Red
1 1 0 1 Light Magenta
1 1 1 0 Yellow
1 1 1 1 High Intensity White
Note: "I" provides extra luminance (brightness) to

each available shade. This results in the
light colors listed above, except for
monitors that do not recognize the "I" bit.
Summary of Available Colors

Programming the 6845 CRT Controller

The 6845 has 19 accessible internal registers, which are used to
define and control a raster-scan CRT display. One of these
registers, the Index register, is actually used as a pointer to the
other 18 registers. It is a write-only register, which is loaded from
the processor by executing an 'out' instruction to I/O address hex
3D4. The five least significant bits of the I/O bus are loaded into
the Index register.
In order to load any of the other 18 registers, the Index register is

first loaded with the necessary pointer; then the Data Register is
loaded with the information to be placed in the selected register.
The Data Register is loaded from the processor by executing an
Out instruction to I/O address hex 3D5.
The following table defines the values that must be loaded into the
6845 CRT Controller registers to control the different modes of
operation supported by the attachment:

40 by 25 80 by 25
Address Register Register Alpha- Alpha- Graphic
Register Number Type Units liD numeric numeric Modes
0 RO Horizontal Character Write 38 71 38
Total Only
1 R1 Horizontal Character Write 28 50 28
Displayed Only
2 R2 Horizontal Character Write 2D 5A 2D
SY,1C Position Only
3 R3 Horizontal Character Write OA OA OA
Sync Width Only
4 R4 Vertical Total Character Write 1F 1F 7F
Row Only
5 R5 Vertical Total Scan Write 06 06 06
Adjust Line Only
6 R6 Vertical Character Write 19 19 64
Displayed Row Only
7 R7 Vertical Character Write 1C 1C 70
Sync Position Row Only
8 R8 Interlace - Write 02 02 02
Mode Only
9 R9 Maximum Scan Write 07 07 01
Scan Line Line Only
Address
A R10 Cu rsor Start Scan Write 06 06 06
Line Only
B R11 Cursor End Scan Write 07 07 07
Line Only
C R12 Start - Write 00 00 00
Address (H) Only
D R13 Start - Write 00 00 00
Address (L) Only
E R14 Cursor - Read/ XX XX XX
Address (H) Write
F R15 Cursor - Read/ XX XX XX
Address (L) Write
10 R16 Li ght Pen (H) - Read XX XX XX
Only
11 R17 Light Pen (L) - Read XX XX XX
Only
Note: All register values are given in hexadecimal
6845 Register Description

Programming the Mode Control and Status
Register
The following I/O devices are defined on the color/graphics
adapter.
Hex
Address A9 AS A7 A6 A5 A4 A3 A2 Al AD Function of Register
308 1 1 1 1 0 1 1 0 0 0 Mode Control Register (DO)
309 1 1 1 1 0 1 1 0 0 1 Color Select Register (00)
30A 1 1 1 1 0 1 1 0 1 0 Status Register (01)
30B 1 1 1 1 0 1 1 0 1 1 Clear Light Pen Latch
3DC 1 1 1 1 0 1 1 1 0 0 Preset Light Pen Latch
3D4 1 1 1 1 0 1 0 Z Z 0 6845 Index Register
3D5 1 1 1 1 0 1 0 Z Z 1 6845 Data Register
3DO 1 1 1 1 0 1 0 Z Z 0 6845 Registers
3D1 1 1 1 1 0 1 0 Z Z 1 6845 Registers
Z = don't care condition
Color-Select Register
This is a 6-bit output-only register (cannot be read). Its I/O
address is hex 3D9, and it can be written to by using the 8088
I/O Out command.

Bit 0 Selects B (Blue) Border Color in 40 x 25 Alphanumeric Mode
Selects B (Blue) Background Color in 320 x 200 Graphics Mode
Selects B (Blue) Foreground Color in 640 x 200 Graphics Mode
Bit 1 Selects G (Green) Border Color in 40 x 25 Alphanumeric Mode
Selects G (Green) Background Color in 320 x 200 Graphics Mode
Selects G (Green) Foreground Color in 640 x 200 Graphics Mode
Bit 2 Selects R (Red) Border Color in 40 x 25 Alphanumeric Mode
Selects R (Red) Background Color in 320 x 200 Graphics Mode
Selects R (Red) Foreground Color in 640 x 200 Graphics Mode
Bit 3 Selects I (Intensified) Border Color in 40 x 25 Alphanumeric Mode
Selects I (Intensified) Background Color in 320 x 200 Graphics Mode
Selects I (Intensified) Foreground Color in 640 x 200 Graphics Mode
Bit 4 Selects Alternate, Intensified Set of Colors in Graphics Mode
Selects Background Colors in the Alphanumeric Mode
Bit 5 Selects Active Color Set in 320 x 200 Graphics Mode
Bit 6 Not Used
Bit 7 Not Used
Bits 0, 1, 2, 3 These bits select the screen's border color in the

40 by 25 alphanumeric mode. They select the
screen's background color (CO-Cl) in the
medium-resolution (320 by 200) color-graphics
mode.
Bits 4 This bit, when set, will select an alternate,

intensified set of colors. Selects background colors
in the alphanumeric mode.
Bit 5 This bit is only used in the medium-resolution

(320 by 200) color-graphics mode. It is used to
select the active set of screen colors for the
display.
When bit 5 is set to 1, colors are determined as follows:
C1 co Set Selected
0 0 Background (Defined by bits 0-3 of port hex 309)
0 1 Cyan
1 0 Magenta
1 1 White

When bit 5 is set to 0, colors are determined as follows:
C1 CO Set Selected
0 0 Background (Defined by bits 0-3 of port hex 3D9)
0 1 Green
1 0 Red
1 1 Brown
Mode- Select Register

This is a 6-bit output-only register (cannot be read). Its I/O
address is hex 3D8, and it can be written to using the 8088 I/O
Out command.
The following is a description of the register's functions:
Bit 0 80 x 25 Alphanumeric Mode

Bit 1 Graphics Select
Bit 2 Black/White Select
Bit 3 Enable Video Signal
Bit 4 High-Resolution (640 x 200) Black/White Mode
Bit 5 Change Background Intensity to Blink Bit
Bit 6 Not Used
Bit 7 Not Used
Bit 0 A 1 selects 80 by 25 alphanumeric mode

A 0 selects 40 by 25 alphanumeric mode
Bit 1 A 1 selects 320 by 200 graphics mode

A 0 selects alphanumeric mode
Bit 2 A 1 selects black-and-white mode

A 0 selects color mode
Bit 3 A 1 enables the video signal at certain times when modes

are being changed. The video signal should be disabled
when changing modes.

Bit 4 A 1 selects the high-resolution (640 by 200)
black-and-white graphics mode. One color of 8 can be
selected on direct-drive sets in this mode by using register
hex 3D9.
Bit 5 When on, this bit will change the character background
intensity to the blinking attribute function for
alphanumeric modes. When the high-order attribute bit is
not selected, 16 background colors (or intensified colors)
are available. For normal operation, this bit should be set
to 1 to allow the blinking function.
Mode Register Summary

Bits
0 1 2 3 4 5
0 0 1 1 0 1 40 x 25 Alphanumeric Black-and-White
0 0 0 1 0 1 40 x 25 Alphanumeric Color
1 0 1 1 0 1 80 x 25 Alphanumeric Black-and-White
1 0 0 1 0 1 80 x 25 Alphanumeric Color
0 1 1 1 0 z 320 x 200 Black-and-White Graphics
0 1 0 1 0 z 320 x 200 Color Graphics
0 1 1 1 1 z 640 x 200 Black-and-White Graphics
Enable Blink Attribute

640 x 200 Black-and-White
Enable Video Signal
Select Black-and-White Mode
Select 320 x 200 Graphics
80 x 25 Alphanumeric Select
z = don't care condition

Note: The low-resolution (160 by 100) mode requires special programming and is
set up as the 40 by 25 alphanumeric mode.

Status Register
The status register is a 4-bit read-only register. Its I/O address is
hex 3DA, and it can be read using the 8088 I/O In instruction.
The following is a description of the register functions:
Bit 0 Display Enable

Bit 1 Light-Pen Trigger Set
Bit 2 Light-Pen Switch Made
Bit 3 Vertica I Sync
Bit 4 Not Used
Bit 5 Not Used
Bit 6 Not Used
Bit 7 Not Used
Bit 0 This bit, when active, indicates that a regen buffer memory
access can be made without interfering with the display.
Bit 1 This bit, when active, indicates that a positive-going edge

from the light-pen has set the light pen's trigger. This
trigger is reset upon power-on and may also be cleared by
performing an I/O Out command to hex address 3DB. No
specific data setting is required; the action is
address-activated.
Bit 2 The light-pen switch status is reflected in this status bit.

The switch is not latched or debounced. A 0 indicates
that the switch is on.
Bit 3 This bit, when active, indicates that the raster is in a

vertical retrace mode. This is a good time to perform
screen-buffer updating.
Sequence of Events for Changing Modes

1. Determine the mode of operation.
2. Reset 'video enable' bit in mode-select register.
3. Program 6845 to select mode.
4. Program mode/color select registers including re-enabling

video.

Memory Requirements
The memory used by this adapter is self-contained. It consists of
16K bytes of memory without parity. This memory is used as
both a display buffer for alphanumeric data and as a bit map for
graphics data. The regen buffer's address starts at hex B8000.
Read/Write Memory
Address Space (in hex)
01000
System
Read/Write
Memory
AOOOO
B8000
Display Buffer 128K Reserved
(16K Bytes) Regen Area
BCOOO
COOOO

Rear Panel
• 6
•
• 9
o
Color Direct
Drive 9-Pin
D-Shell Connector
At Standard TTL levels

Ground 1
Ground 2
Red 3
Green 4
IBM Color D isplay Colo riG raphics
Blue 5
or other Dire ct-Drive Direct-D rive
Monitor Intensity 6 Adapter
Reserved 7
Horizontal Drive 8
Vertical Drive 9
Composite Phono Jack

Hookup to Monitor
Composite Video Signal of

Approximately 1.5 Volts
Video Color/G raphics
Monitor Peak to Peak Amplitude 1
Composi te Jack
Chassis Ground 2
Connector Specifications (Part 1 of 2)

P1 (4-Pin Berg Strip) P2 (6-Pin Berg Strip)
for RF Modulator for Light-Pen
Color/Graphics
Adapter
+12 Volts 1
(key) Not Used 2
RF Color/G raphics
Mo dulator Composite Video Output 3 Adapter
logic Ground 4
RF Modulator Interface
-light Pen Input 1

(key) Not Used 2
Lig ht - Light Pen Switch 3 Color/G raphics
Pe n Chassis Ground 4 Adapter
+5 Volts 5
+12 Volts 6
Light Pen Interface

IBM Color Display
The IBM Color Display attaches to the system unit by a signal

cable that is approximately 5 feet (1.5 meters) in length. This
signal cable provides a direct-drive interface from the IBM
Color/Graphics Monitor Adapter.
A second cable provides ac power to the display from a standard

wall outlet. The display has its own power control and indicator.
The display will accept either 120-volt 60-Hz, or 220-volt 50-Hz
power. The power supply in the display automatically switches to
match the applied power.
The display has a 13-inch (340 millimeters) CRT. The CRT and
analog circuits are packaged in an enclosure so the display may sit
either on top of the system unit or on a nearby tabletop or desk.
Front panel controls and indicators include: Power-On control,
Power-On indicator, Brightness and Contrast controls. Two
additional rear-panel controls are the Vertical Hold and Vertical
Size controls.
Screen
• High contrast (black) screen.
• Displays up to 16 colors, when used with the IBM

Color/Graphics Monitor Adapter.
• Characters defined in an 8-high by 8-wide matrix.
Video Signal
• Maximum video bandwidth of 14 MHz.
• Red, green, and blue video signals and intensity are all
independent.
Color Display 1-157

Vertical Drive
• Screen refreshed at 60 Hz with 200 vertical lines of

resolution.
Horizontal Drive
• Positive-level, TTL-compatibility, at a frequency of

15.75 kHz.
1-158 Color Display

IBM 5-1/4" Diskette Drive Adapter
The 5-1/4 inch diskette drive adapter fits into one of the
expansion slots in the system unit. It attaches to one or two
diskette drives through an internal, daisy-chained flat cable that
connects to one end of the drive adapter. The adapter has a
connector at the other end that extends through the rear panel of
the system unit. This connector has signals for two additional
external diskette drives; thus the 5-1/4 inch diskette drive adapter
can attach four 5-1/4 inch drives - two internal and two external.
The adapter is designed for double-density, MFM-coded, diskette

drives and uses write precompensation with an analog phase-lock
loop for clock and data recovery. The adapter is a general-purpose
device using the NEe ,u.PD765 compatible controller. Therefore,
the diskette drive parameters are programmable. In addition, the
attachment supports the diskette drive's write-protect feature. The
adapter is buffered on the I/O bus and uses the system board's
direct memory access (DMA) for record data transfers. An
interrupt level is also used to indicate when an operation is
complete and that a status condition requires processor attention.
In general, the 5-1/4 inch diskette drive adapter presents a

high-level command interface to software I/O drivers. A block
diagram of the 5-1/4 inch diskette drive adapter is on the
following page.
Diskette Adapter 1-159

--
, Clock
.. Write ~ Write Data
L"
0'1 and
Precompensate
o Timing
t:j
Circuit C;,,""
;;.
~
1
• .~
Write !'--
.. ~-
::+ Data Read Data
~ ...... Data I"""" <}- I I
:>
I"
VCO SyNC...... Separator f-
Q. STD. DATA
~
'0
.....
~
i"'Data Windovyj
I"""" ,reo
'"I NEC Step
Floppy ~
~ Buffer rv-
Direction
Disk
rv' Controller
V Write Enable
l/"" Head Select
~
Index
I"""" Write Protect
~'-J
i'" Track 0
.v"""1..
I""""
iRes~t I-- B l/""'"

Drive A Motor On
--"
Digital
~
I--C
Control Decoder ~D Drive A Select
~
Port 1/'"
r-B
t--C
INTR.
~
r r-D
5-1/4 Inch Diskette Drive Adapter Block Diagram

Functional Description
From a programming point of view, this attachment consists of an
8-bit digital-output register in parallel with an NEC ,uPD765 or
equivalent floppy disk controller (FDC).
In the following description, drive numbers 0, 1, 2, and 3 are

equivalent to drives A, B, C, and D.
Digital-Output Register
The digital-output register (DOR) is an output-only register used
to control drive motors, drive selection, and feature enable. All
bits are cleared by the I/O interface reset line. The bits have the
following functions:
Bits 0 and 1 These bits are decoded by the hardware to

select one drive if its motor is on:
Bit 1 0 Drive
o 0 o (A)
o 1 1 (B)
1 0 2 (C)
1 1 3 (D)
Bit 2 The FDC is held reset when this bit is clear.

It must be set by the program to enable the
FDC.
Bit 3 This bit allows the FDC interrupt and DMA

requests to be gated onto the I/O interface. If
this bit is cleared, the interrupt and DMA
request I/O interface drivers are disabled.
Bits 4, 5, 6, and 7 These bits control, respectively, the motors of

drives 0, 1, 2 (A, B, C), and 3 (D). If a bit is
clear, the associated motor is off, and the
drive cannot be selected.

Floppy Disk Controller
The floppy disk controller (FDC) contains two registers that may
be accessed by the main system processor: a status register and a
data register. The 8-bit main status register contains the status
information of the FDC and may be accessed at any time. The
8-bit data register (actually consisting of several registers in a
stack with only one register presented to the data bus at a time)
stores data, commands, parameters, and provides floppy disk
drive (FDD) status information. Data bytes are read from or
written to the data register in order to program or obtain results
after a particular command. The main status register may only be
read and is used to facilitate the transfer of data between the
processor and FDC.
The bits in the main status register (hex 34F) are dermed as
follows:
Bit
Number Name Symbol Description
DBO FDD A Busy DAB FDD number 0 is in the Seek mode.
DB' FDD B Busy DBB FDD number' is in the Seek mode.

DB2 FDD C Busy DCB ~DD number 2·is in the Seek mode.
DB3 FDD D Busy DDB FDD number 3 is in the Seek mode.
DB4 FDC Busy CB A read or write command is in process.
DB5 Non-DMA NDM The FDC is in the non-DMA mode.
Mode
DB6 Data Input! DIO Indicates direction of data transfer
Output between FDC and processor. If DID = '" ,"
then transfer is from FDC data register to
the processor. If DID = "0," then transfer
is from the processor to FDC data register.
DB7 Request for ROM Indicates data register is ready to send or
Master receive data to or from the processor. Both
bits DID and ROM should be used to
perform the handshaking functions of
"ready" and "direction" to the processor.
1-162 Diskette Adapter

The FDC is capable of performing 15 different commands. Each
command is initiated by a multi-byte transfer from the processor,
and the result after execution of the command may also be a
multi -byte transfer back to the processor. Because of this
multi-byte interchange of information between the FDC and the
processor, it is convenient to consider each command as
consisting of three phases:
Command Phase
The FDC receives all information required to perform a particular
operation from the processor.
Execution Phase
The FDC performs the operation it was instructed to do.
Result Phase
After completion of the operation, status and other housekeeping
information is made available to the processor.

The following tables define the symbols used in the command
summary, which follows.
Symbol Name Description
AO Address Line a AO controls selection of main status

register (AO = a) or data register (AO = 1).
C Cylinder Number C stands for the current/selected cylinder
(track) number of the medium.
D Data D stands for the data pattern that is going

to be written into a sector.
D7-00 Data Bus 8-bit data bus, where D7 sta nds for a
most significant bit, and DO stands for a
least significant bit.
DTL Data Length When N is defined as 00, DTL stands for
the data length that users are going to
read from or write to the sector.
EOT End of Track EOT stands for the final sector numbe'r on
a cylinder.
GPL Gap Length G PL sta nds for the length of gap 3
(spacing between sectors excluding VCO
sync field).
H Head Address H stands for head number a or 1, as

specified in ID field.
HD Head HD stands for a selected head number a

or 1. (H = HD in all command words.)
HLT Head Load Time HLT stands for the head load time in the
FDD (4 to 512 ms in 4-ms increments).
HUT Head Unload Time HUT stands for the head unload time after
a read or write operation has occurred (0
to 480 ms in 32-ms increments).
MF FM or MFM Mode If MF is low, FM mode is selected; if it is
high, MFM mode is selected only if MFM
is implemented.
MT Multi-Track If MT is high, a multi-track operation is to
be performed. (A cylinder under both HDO
and HD1 will be read or written.)
N Number N stands for the number of data bytes

written in a sector.
Symbol Descriptions (Part 1 of 2)

Symbol Name Description
NCN New Cylinder NCN stands for a new cylinder number,
Number which is going to be reached as a result
of the seek operation. (Desired position of
the head.)
NO Non-DMA Mode NO stands for operation in the non-DMA
mode.
PCN Present Cylinder PCN stands for cylinder number at the
Number completion of sense-interrupt-status
command indicating the position of the
head at present time.
R Record R stands for the sector number, which
will be read or written.
R/W Read/Write R/W stands for either read (R) or write
(W) signal.
SC Sector SC indicates the number of sectors per
cylinder.
SK Skip SK stands for skip deleted-data address
mark.
SRT Step Rate Time SRT stands for the stepping rate for the
FDD (2 to 32 ms in 2-ms increments).
STO Status 0 ST 0-3 stand for one of four registers that
ST 1 Status 1 store the status information after a
ST 2 Status 2 command has been executed. This
ST 3 Status 3 information is available during the result
phase after command execution. These
registers should not be confused with the
main status register (selected by AO =0).
ST 0-3 may be read only after a command
has been executed and contain
information releva nt to that particula r
command.
STP Scan Test During a scan operation, if STP =1, the
data in contiguous sectors is compared
byte-by-byte with data sent from the
processor (or DMA), and if STP =2, then
alternate sectors are read and compared.
usa, Unit Select US stands for a selected drive number
US1 encoded the same as bits 0 and 1 of the
digital output register (DOR).
Symbol Descriptions (Part 2 of 2)

Command Summary
In the following table, 0 indicates "logical 0" for that bit, 1 means
"logical 1," and X means "don't care."
Data Bus
Phase R/W D7 D6 D5 D4 D3 D2 D1 DO Remarks
Read Data
Command W MT MF SK 0 0 1 1 0 Command Codes
W X X X X X HD US1 usa
w C Sector ID information
W H prior to command
W R execution.
W N
W EOT
W GPL
W DTL
Execution Data tra nsfer
between the FDD
and main system.
Result R STO Status information
R ST 1 after command
R ST 2 execution.
R C Sector I D information
R H after command
R R execution.
R N
Read Deleted Data
Command W MT MF SK 0 1 1 0 0 Command Codes
W R execution.
W N
W EOT
W GPL
W DTL
between the FDD
and main system.
R ST 2 execution.
R C Sector ID information
R H after command
R R execution.
R N

Data Bus
Phase R/W D7 D6 D5 D4 D3 D2 D1 DO Remarks
Write Data
Command W MT MF a a a 1 a 1 Command Codes
w C Sector I D information
W H to command
W R execution.
W N
W EOT
W GPL
W DTL
between the main
system and FDD.
Result R STa Status information
R ST 2 execution.
R H after command
R R execution.
R N
Write Deleted Data
Command W MT MF a a 1 a a 1 Command Codes
W R execution.
W N
W EOT
W GPL
W DTL
between FDD and
main system.
Result R STa Status ID information
R ST 2 execution.
R H after command
R R execution.
R N

Data Bus
Phase R/W 07 06 05 04 03 02 01 DO Remarks
Read a Track
Command W a MF SK a a a 1 a Command Codes
W C Sector ID information
W R execution.
W N
W EOT
W GPL
W DTL
between the FDD
and main system.
FDC reads all of
cylinder's contents
from index hole to
EOT.
R ST 2 execution.
R C Sector I D information
R H after command
R R execution.
R N
Read 10
Command W a MF a a 1 a
1 a Command Codes
Execution The first correct ID
information on the
cylinder is stored in
data register.
R ST 2 execution.
R H during execution
R R phase.
R N

Oata Bus
Format a Track
Command W 0 MF 0 0 1 1 0 0 Command Codes
w N Bytes/Sector
W SC Sector /Track
W GPL Gap 3
W D filler byte.
Execution FDC formats an
entire cylinder.
R ST 2 execution.
R C In this case, the ID
R H information has no
R R meaning.
R N
Scan Equal
Command W MT MF SK 1 0 0 0 Command Codes
W R execution.
W N
W EOT
W GPL
W STP
Execution Data compared
between the FDD
and the main system.
R ST 2 execution.
R H after Command
R R execution.
R N

Data Bus
Command W MT MF SK , ,
Scan Low or Equal
0 0 , Command Codes
W X X X X X HD US, usa
W R execution.
W N
W EOT
W GPL
W STP
between the FDD
and main system.
R ST' after command
R ST 2 execution.
R H after command
R R execution.
R N
Command W MT MF SK , , ,
Scan High or Equal
0 , Command Codes
W X X X X X HD US, usa
W R execution.
W N
W EOT
W GPL
W STP
between the FDD
and main system.
R ST' after command
R ST 2 execution.
R H after command
R R execution.
R N

Data Bus
Recalibrate
Command W 0 0 0 0 0 1 1 1 Command Codes
W X X X X X 0 USl usa
Execution Head retracted to
No Result track 0
Phase
Sense Interrupt Status

Result R STO Status information at
R PCN the end of seek
operation about the
FOC
Specify
W -SRT HUT-
W ---HLT ND
No Result
Phase
Sense Drive Status
W X X X X X HD USl usa
Result R ST 3 Status information
about FDD.
Seek
W X X X X X HD USl usa
w NCN
Execution Head is positioned
over proper cylinder
on diskette.
No Result
Phase
Invalid
Command W Invalid Codes Invalid command
codes (NoOp - FDC
goes into standy
state).
Result R STO ST 0 = 80.

Bit
No. Name Symbol Description
07 07=Oand06=O
Interrupt IC Normal termination of command (NT).
Code Command was completed and properly
executed.
06 07 =Oand 06 = 1
Abnormal termination of command (AT).
Execution of command was started. but
was not successfully completed.
07 = 1 and 06 = 0
Invalid command issue (IC). Command
that was issued was never started.
07 = 1 and 06 = 1
Abnormal termination because. during
command execution. the ready signal
from FOO changed state.
05 Seek End SE When the FOC completes the seek
command. this flag is set to 1 (high),
04 Equipment EC If a fault signal is received from the
Check FOO. or if the track 0 signal fails to occur
after 77 step pulses (recalibrate
command). then this flag is set.
03 Not Ready NR When the FOO is in the not-ready state
and a read or write command is issued.
this flag is set. If a read or write command
is issued to side 1 of a single-sided drive.
then this flag is set.
02 Head Address HO This flag is used to indicate the state of
the head at interrupt.
01 Unit Select 1 US 1 These flags are used to indicate a drive
00 Unit Select 0 US 0 unit number at interrupt.
Command Status Register 0

Bit
D7 End of EN When the FDC tries to access a sector
Cylinder beyond the final sector of a cylinder, this
flag is set.
D6 - - Not used. This bit is always 0 (low).
D5 Data Error DE When the FDC detects a CRC error in
either the ID field or the data field, this
flag is set.
D4 Over Run OR If the FDC is not serviced by the main
system during data transfers within a
certain time interval, this flag is set.
D2 No Data ND During execution of a read data, write
deleted data, or scan command, if the
FDC cannot find the sector specified in
the ID register, this flag is set. During
execution of the read ID command, if the
FDC cannot read the ID field without an
error, then this flag is set. During the
execution of the read a cylinder
command, if the starting sector cannot be
found, then this flag is set.
D1 Not Writable NW During execution of a write data, write
deleted data, or format-a-cylinder
command, if the FDC detects a
write-protect signal from the FDD, then
this flag is set.
DO Missing MA If the FDC cannot detect the ID address
Address mark, this flag is set. Also, at the same
Mark time, the MD (missing address mark in
the data field) of status register 2 is set.

Bit
D6 Control Mark CM During execution of the read data or scan

command, if the FDC encounters a sector
that contains a deleted data address
mark, this flag is set.
D5 Data Error in DD If the FDC detects a CRC error in the data,
Data Field then this flag is set.
D4 Wrong WC This bit is related to the ND bit, and when
Cylinder the contents of C on the medium are
different from that stored in the ID
register, this flag is set.
D3 Scan Equal SH During execution of the scan command, if

Hit the condition of "equal" is satisfied, this
flag is set.
D2 Scan Not SN During execution of the scan command,
Satisfied if the FDC cannot find a sector on the
cylinder that meets the condition, then
this flag is set.
D1 Bad Cylinder BC This bit is related to the ND bit, and when
the contents of C on the medium are
different from that stored in the ID
register, and the contents of C is FF, then
this flag is set.
DO Missing MD When data is read from the medium, if
Address Mark the FDC cannot find a data address mark
in Data Field or deleted data address mark, then this
flag is set.

Bit
D7 Fault FT This bit is the status of the fault signal
from the FDD.
D6 Write WP This bit is the status of the
Protected write-protected signal from the FDD.
D5 Ready RY This bit is the status of the ready signal

from the FDD.
D4 Track 0 TO This bit is the status of the track 0 signal
from the FDD.
D3 Two Side TS Th is bit is the status of the two-side

signal from the FDD.
D2 Head Address HD This bit is the status of the side-select
D1 Unit Select 1 US 1 This bit is the status of the unit-select-1
DO Unit Select 0 US 0 This bit is the status of the unit-select-O
Programming Summary
FDC Data Register 1/0 Address Hex 3F5

FDC Main Status Register 1/0 Address Hex 3F4
Digital Output Register 1/0 Address Hex 3F2
Bit 0 Drive 00: DR #A 10: DR #C

1 Select 01: DR #B 11: DR #D
2 Not FDC Reset
3 Enable INT & DMA Requests
4 Drive A Motor Enable
5 Drive B Motor Enable
6 Drive C Motor Enable
7 Drive D Motor Enable
All bits cleared with channel reset.
OPC Registers

FDC Constants (in hex)
N: 02 GPL Format: 05
SC: 08 GPLR!W: 2A
HUT: F HLT: 01
SRT: C (6 ms track-to-track)
Drive Constants
Head Load 35 ms
Head Settle 15 ms
Motor Start 250ms
Comments
• Head loads with drive select, wait HD load before R/W.
• Following access, wait HD settle time before R/W.
• Drive motors should be off when not in use. Only A or Band

C or D may run simultaneously. Wait motor start time before
R/W.
• Motor must be on for drive to be selected.
• Data errors can occur while using a home television as the

system display. Locating the TV too close to the diskette area
can cause this to occur. To correct the problem, move the TV
away from, or to the opposite side of the system unit.
System I/O Channel Interface

All signals are TTL-compatible:
Most Positive Up Level 5.5 Vdc

Least Positive Up Level 2.7 Vdc
Most Positive Down Level 0.5 Vdc
Least Positive Down Level -0.5 Vdc

The following lines are used by this adapter.
+ DO-7 (Bidirectional, load: 1 74LS, driver: 74LS 3-state).

These eight lines form a bus by which all commands,
status, and data are transferred. Bit 0 is the low-order
bit.
+AO-9 (Adapter input, load: 1 74LS)

These ten lines form an address bus by which a
register is selected to receive or supply the byte
transferred through lines DO-7. Bit 0 is the low-order
bit.
+AEN (Adapter input, load: 1 74LS)

The content of lines AO-9 is ignored if this line is
active.
-lOW (Adapter input, load: 1 74LS)

The content of lines DO-7 is stored in the register
addressed by lines AO-9 or DACK2 at the trailing
edge of this signal.
-lOR (Adapter input, load: 1 74LS)

The content of the register addressed by lines AO-9
or DACK2 is gated onto lines DO-7 when this line is
active.
-DACK2 (Adapter input, load: 2 74LS)

This line being active degates output DRQ2, selects
the FDC data register as the source/destination of
bus DO-7, and indirectly gates T/C to IRQ6.
+T/C (Adapter input, load: 4 74LS)

This line and DACK2 being active indicates that the
byte of data for which the DMA count was initialized
is now being transferred.
+RESET (Adapter input, load: 1 74LS)

An up level aborts any operation in process and
clears the digital output register (DaR).

+DRQ2 (Adapter output, driver: 74LS 3-state)
This line is made active when the attachment is ready
to transfer a byte of data to or from main storage.
The line is made inactive by DACK2 becoming
active or an I/O read ofthe FDC data register.
+IRQ6 (Adapter output, driver: 74LS 3-state)

This line is made active when the FDC has
completed an operation. It results in an interrupt to a
routine which should examine the FDC result bytes
to reset the line and determine the ending condition.
Drive A and B Interface

All signals are TTL-compatible:
Most Positive Up Level 5.5 Vdc

Least Positive Up Level 2.4 Vdc
Most Positive Down Level 0.4 Vdc
Least Positive Down Level -0.5 Vdc
All adapter outputs are driven by open-collector gates. The

drive(s) must provide termination networks to Vcc (except motor
enable, which has a 2000-ohm resistor to Vcc).
Each adapter input is terminated with a I50-ohm resistor to Vcc.
Adapter Outputs
-Drive Select A and B (Driver: 7438)
These two lines are used by drives A
and B to degate all drivers to the
adapter and receivers from the
attachment (except motor enable) when
the line associated with a drive is
inactive.

-Motor Enable A and B (Driver: 7438)
The drive associated with each of these
lines must control its spindle motor
such that it starts when the line
becomes active and stops when the line
becomes inactive.
-Step (Driver: 7438)

The selected drive moves the
read/write head one cylinder in or out
per the direction line for each pulse
present on this line.
-Direction (Driver: 7438)

For each recognized pulse of the step
line, the read/write head moves one
cylinder toward the spindle if this line
is active, and away from the spindle if
inactive.
-Head Select (Driver: 7438)

Head 1 (upper head) will be selected
when this line is active (low).
-Write Data (Driver: 7438)

For each inactive to active transition of
this line while write enable is active,
the selected drive causes a flux change
to be stored on the diskette.
-Write Enable (Driver: 7438)

The drive disables write current in the
head unless this line is active.
Adapter Inputs
-Index The selected drive supplies one pulse
per diskette revolution on this line.
- Write Protect The selected drive makes this line

active if a write-protected diskette is
mounted in the drive.

-Track 0 The selected drive makes this line
active if the read/write head is over
track O.
-Read Data The selected drive supplies a pulse on

this line for each flux change
encountered on the diskette.

34-Pin Keyed
Edge Connector
Component
Side
Note: Lands 1-33 (odd numbers) are on the back of the

board. Lands 2-34 (even numbers) are on the front, or
component side.
At Standard TTL Levels Land Number

Ground-Odd Numbers 1-33
Unused 2,4,6
Index 8
Motor Enable A 10
Drive Select B 12
Drive Select A 14
Motor Enable B 16
Direction (Stepper Motor) 18
Diskette Step Pulse 20 Drive
Drives Adapte
Write Data 22
Write Enable 24
Track 0 26
Write Protect 28
Read Data 30
Select Head 1 32
Unused 34

37-Pin D-Shell
20
•
• ••
•
• ••
• ••
• •
•• ••
• •
•
•
•
• •
• • 37
•
o
Pin
At Standard TTL Levels Number
Unused 1-5
Index 6
Motor Enable C 7
Drive Select D 8
Drive Select C 9
Motor Enable D 10
Direction (Stepper Motor) 11
External Drive
Step Pulse 12
Drives Adapter
Write Data 13
Write Enable 14
Track 0 15
Write Protect 16
Read Data 17
Select Head 1 18
Ground 20-37

IBM 5-1/4" Diskette Drive
The system unit has space and power for one or two 5-1/4 inch
diskette drives. A drive can be single-sided or double-sided with
40 tracks for each side, is fully self-contained, and consists of a
spindle drive system, a read positioning system, and a
read/write/erase system.
The diskette drive uses modified frequency modulation (MFM) to

read and write digital data, with a track-to-track access time of 6
milliseconds.
To load a diskette, the operator raises the latch at the front of the
diskette drive and inserts the diskette into the slot. Plastic guides
in the slot ensure the diskette is in the correct position. Closing the
latch centers the diskette and clamps it to the drive hub. After 250
milliseconds, the servo-controlled dc drive motor starts and drives
the hub at a constant speed of 300 rpm. The head positioning
system, which consists of a 4-phase stepper-motor and band
assembly with its associated electronics, moves the magnetic head
so it comes in contact with the desired track of the diskette. The
stepper-motor and band assembly uses one-step rotation to cause
a one-track linear movement of the magnetic head. No operator
intervention is required during normal operation. During a write
operation, a 0.013-inch (0.33 millimeter) data track is recorded,
then tunnel-erased to 0.012 inch (0.030 millimeter). If the diskette
is write-protected, a write-protect sensor disables the drive's
circuitry, and an appropriate signal is sent to the interface.
Data is read from the diskette by the data-recovery circuitry,

which consists of a low-level read amplifier, differentiator,
zero-crossing detector, and digitizing circuits. All data decoding is
done by an adapter card.
The diskette drive also has the following sensor systems:
1. The track 00 switch, which senses when the head/carriage

assembly is at track 00.
Diskette Drive 1-183

2. The ind~x sensor, which consists of an LED light source and
phototransistor. This sensor is positioned so that when an
index hole is detected, a digital signal is generated.
3. The write-protect sensor disables the diskette drive's

electronics whenever a write-protect tab is applied to the
diskette.
For interface information, refer to "IBM 5-1/4" Diskette Drive

Adapter" earlier in this section.
Media Industry-compatible 5-1/4 inch diskette

Tracks per inch 48
Number of tracks 40
Dimensions
Height 3.38 inches (85.85 mm)
Width 5.87 inches (149.10 mm)
Depth 8.00 inches (203.2 mm)
Weight 4.50 pounds (2.04 kg)
Temperature
(Exclusive of media)
Operating 50 0 F to 11 2 0 F (1 0 0 C to 44 0 C)
Non operating -40 0 F to 140 0 F (-40 0 C to 60 0 C)
Relative humidity
(Exclusive of media)
Operating 20% to 80% (non condensing)
Non operating 5% to 95% (non condensing)
Seek Time 6 ms track-to-track
Head Settling Time 15 ms (last track addressed)
Error Rate 1 per 109 (recoverable)
1 per 1012 (non recoverable)
1 per 106 (seeks)
Head Life 20,000 hours (normal use)
Media Life 3.0 x 106 passes per track
Disk Speed 300 rpm +/- 1.5% (long term)
Instantaneous Speed Variation +/- 3.0%
Start/Stop Time 250 ms (maximum)
Transfer Rate 250K bits/sec
Recording Mode MFM
Power +12 Vdc +/- 0.6 V, 900 mA average
+5 Vdc +/- 0.25 V, 600 mA average
Mechanical and Electrical Specifications
1-184 Diskette Drive

Diskettes
The IBM 5-1/4" Diskette Drive uses a standard 5.25-inch

( 133 .4-millimeter) diskette. For programming considerations,
single-sided, double-density, soft-sectored diskettes are used for
single-sided drives. Double-sided drives use double-sided,
double-density, soft-sectored diskettes. The figure below is a
simplified drawing of the diskette used with the diskette drive.
This recording medium is a flexible magnetic disk enclosed in a
protective jacket. The protected disk, free to rotate within the
jacket, is continuously cleaned by the soft fabric lining of the
jacket during normal operation. Read/write/erase head access is
made through an opening in the jacket. Openings for the drive hub
and diskette index hole are also provided.
I
I
I
__ I
0.140 Inch -I L 0.25 ± 0.01 Inch
(~.56 mm) ~llf6.30 ± 0.25 mm)
J----c
Sealed
Protective
Jacket
Oxide Coated
Mylar Disk
....... ,
"-
\
.r: E
gE \
---(0, @
: : It) 5.25 Inch
66 1(133.4mm) I
I
I
+1 +1 /
o ~ Liner /
m COlO
C'l-
~
·co
'---5.25Inch-l
1~(133.4m~ Head
I Aperture
Recording Medium
Diskettes 1-185
Notes:
1-186 Diskettes
IBM Fixed Disk Drive Adapter
The fixed disk drive adapter attaches to one or two fixed disk
drive units, through an internal daisy-chained flat cable
(data/control cable). Each system supports a maximum of one
fixed disk drive adapter and two fixed disk drives.
The adapter is buffered on the I/O bus and uses the system board
direct memory access (DMA) for record data transfers. An
interrupt level also is used to indicate operation completion and
status conditions that require processor attention.
The fixed disk drive adapter provides automatic II-bit burst error
detection and correction in the form of 32-bit error checking and
correction (ECC).
The device level control for the fixed disk drive adapter is
contained on a ROM module on the adapter. A listing of this
device level control can be found in "Appendix A: ROM BIOS
Listings. "
WARNING: The last cylinder on the fixed disk drive is

reserved for diagnostic use. Diagnostic write
tests will destroy any data on this cylinder.
Fixed Disk Controller

The disk controller has two registers that may be accessed by the
main system processor: a status register and a data register. The
8-bit status register contains the status information of the disk
controller, and can be accessed at any time. The 8-bit data
register (actually consisting of several registers in a stack with
only one register presented to the data bus) stores data,
commands, parameters, and provides the disk controller's status
information. Data bytes are read from, or written to the data
register in order to program or obtain the results after a particular
command. The status register is a read-only register, and is used
to help the transfer of data between the processor and the disk
controller. The controller-select pulse is generated by writing to
port address hex 322.
Fixed Disk Adapter 1-187
--
,
00
00
"!1
~.
('I>
0.
o
iii·
Serializer I
Deserializer
~
J2
>
0. To
Data
~
....
Serdes
ECC Separator
) Drives
('I>
"" 1/0
Edge
Connector
Data Bus
DB7-DBO'
Control Sector
r-- Buffer
8-Bit
Processor
Fixed Disk Drive Adapter Block Diagram

Status Register
At the end of all commands from the system board, the disk
controller returns a completion status byte back to the system
board. This byte informs the system unit if an error occurred
during the execution of the command. The following shows the
format of this byte.
~I
6 5 4 3 2
o d o o o e
Bits 0, 1,2,3,4,6, 7 These bits are set to zero.
Bit 1 When set, this bit shows an error has

occurred during command execution.
Bit 5 This bit shows the logical unit number of

the drive.
If the interrupts are enabled, the controller sends an interrupt

when it is ready to transfer the status byte. Busy from the disk
controller is unasserted when the byte is transferred to complete
the command.
Sense Bytes
If the status register receives an error (bit 1 is set), then the disk
controller requests four bytes of sense data. The format for the
four bytes is as follows:
Bits 7 6 5 4 3 2 1 0
Byte 0 Address I 0 Error Type Error Code
Valid I I
Byte 1 0 0 d Head Number
Byte 2 Cylinder High Sector Number
Byte 3 Cylinder Low
Remarks
d = drive

Byte 0 Bits 0, 1,2,3 Error code.
Byte 0 Bits 4,5 Error type.
Byte 0 Bit 6 Set to 0 (spare).
Byte 0 Bit 7 The address valid bit. Set only when

the previous command required a disk
address, in which case it is returned
as a 1; otherwise, it is a O.
The following disk controller tables list the error types and error
codes found in byte 0:
Error Type Error Code

Bits 5 4 3 2 1 0 Description
0 0 0 0 0 0 The controller did not detect any error
during the execution of the previous
operation.
0 0 0 0 0 1 The controller did not detect an index signal
from the drive.
0 0 0 0 1 0 The controller did not get a seek-complete
signal from the drive after a seek operation
(for all non-buffered step seeks).
0 0 0 0 1 1 The controller detected a write fault from
the drive during the last operation.
0 0 0 1 0 0 After the controller selected the drive, the
drive did not respond with a ready signal.
0 0 0 1 0 1 Not used.
0 0 0 1 1 0 After stepping the maximum number of
cylinders, the controller did not receive the
track 00 signal from the drive.
0 0 0 1 1 1 Not used.
0 0 1 0 0 0 The drive is still seeking. This status is
reported by the Test Drive Ready command
for an overlap seek condition when the
drive has not completed the seek. No
time-out is measured by the controller for
the seek to complete.
1-190 Fixed Disk Adapter

0 1 0 0 0 0 ID Read Error: The controller detected an
ECC error in the target ID field on the disk.
0 1 0 0 0 1 Data Error: The controller detected an
uncorrectable ECC error in the target sector
during a read operation.
0 1 0 0 1 0 Address Mark: The controller did not detect
the target address mark (AM) on the disk.
0 1 0 0 1 1 Not used.
0 1 0 1 0 0 Sector Not Found: The controller found the
correct cylinder and head, but not the
target sector.
0 1 0 1 0 1 Seek Error: The cylinder or head address
(either or both) did not compare with the
expected target address as a result of a
seek.
0 1 0 1 1 0 Not used.
0 1 0 1 1 1 Not used.
0 1 1 0 0 0 Correctable Data Error: The controller
detected a correctable ECC error in the
target field.
0 1 1 0 0 1 Bad Track: The controller detected a bad
track flag during the last operation. No
retries are attempted on this error.

1 0 0 0 0 0 Invalid Command: The controller has
received an invalid command from the
system unit.
1 0 0 0 0 1 Illegal Disk Address: The controller

detected an address that is beyond the
maximum range.

1 1 0 0 0 0 RAM Error: The controller detected a data

error during the RAM sector-buffer
diagnostic test.
1 1 0 0 0 1 Program Memory Checksum Error: During
this internal diagnostic test, the controller
detected a program-memory checksum
error.
1 1 0 0 1 0 ECC Polynominal Error: During the
controller's internal diagnostic tests, the
hardware ECC generator failed its test.

Data Register
The processor specifies the operation by sending the 6-byte device
control block (DeB) to the controller. The figure below shows the
composition of the DeB, and defines the bytes that make up the
DeB.
Bit 7 6 5 4 3 2 1 0
Byte 0 Command Opcode
Class
Byte 1 0 0 d Head Number
Byte 2 Cylinder High
I Sector Number
Byte 3 Cylinder Low
Byte 4 Interleave or Block Count
Byte 5 Control Field
Byte 0 - Bits 7, 6, and 5 identify the class of the command.

Bits 4 through 0 contain the Opcode command.
Byte 1 - Bit 5 identifies the drive number.

Bits 4 through 0 contain the disk head number to be
selected.
Bits 6 and 7 are not used.
Byte 2 - Bits 6 and 7 contain the two most significant bits of the
cylinder number.
Bits 0 through 5 contain the sector number.
Byte 3 - Bits 0 through 7 are the eight least significant bits of the
cylinder number.
Byte 4 - Bits 0 through 7 specify the interleave or block count.
Byte 5 - Bits 0 through 7 contain the control field.

Control Byte
Byte 5 is the control field of the DCB and allows the user to select
options for several types of disk drives. The format of this byte is
as follows:
Bits 7 6 5 4 3 2 0 Remarks
I I a 0 0 0 s s s r = retries
s = step option
a = retry option on data ECC
error
Bit 7 Disables the four retries by the controller on all

disk-access commands. Set this bit only during the
evaluation of the performance of a disk drive.
Bit 6 If set to 0 during read commands, a reread is

attempted when an ECC error occurs. If no error
occurs during reread, the command will complete
with no error status. If this bit is set to 1, no reread is
attempted.
Bits 5,4,3 Set to O.
Bits 2, 1, 0 These bits define the type of drive and select the step
option. See the following figure.
Bits 2. 1. 0
0 0 0 This drive is not specified and defaults to 3 milliseconds per
step,
0 0 1 N/A
0 1 0 N/A
0 1 1 N/A
1 0 0 200 microseconds per step,
1 0 1 70 microseconds per step (specified by BIOS),
1 1 0 3 milliseconds per step,
1 1 1 3 milliseconds per step,

Command Summary
Command Data Control Block Remarks
Test Drive Bit 7 6 5 4 3 2 1 0 d= drive (0 or 1)

Ready Byte 0 0 0 010 0 0 0 0 x= don't care
(Class 0, Byte 1 0 0 dlx x x x x Bytes 2, 3, 4, 5 = don't
Opcode 00) care
Recalibrate Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1)

(Class 0, Byte 0 0 0 010 0 0 0 1 x = don't care
Opcode 01) Byte 1 0 0 dlx x x x x r = retries
Byte 5 r 0 0 0 0 s s s s = Step Option
Bytes 2, 3, 4 = don't
care
ch = cylinder high
Reserved This Opcode is not

(Class 0, used.
Opcode 02)
Request Sense Bit 7 6 5 4 3 2 1 0 d= drive (0 or 1 )
Status Byte 0 0 0 010 0 0 1 1 x= don't care
(Class 0, Byte 1 0 0 dlx x x x x Bytes 2, 3, 4, 5 = don't
Opcode 03) care
Format Drive Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

(Class 0, Byte 0 0 0 010 0 1 0 0 r = retries
Opcode 04) Byte 1 0 0 d I Head Number s = step option
Byte 2 ch 1·0 0 0 0 0 0 ch = cylinder high
Byte 3 Cylinder Low
Byte 4 0 0 01 Interleave Interleave: 1 to 16
Byte 5 r 0 0 0 0 s s s for 512-byte sectors.
Ready Verify Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1)

Opcode 05) Byte 1 0 0 d I Head Number s = step option
Byte 2 ch I Sector Number a = retry option on
Byte 3 Cylinder Low data ECC
Byte 4 Block Count ch = cylinder high
Byte 5 r a 0 0 0 s s s

Format Track Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

Opcode 06) Byte 1 0 0 I
d Head Number s = step option
Byte 2 ch 10 0 0 0 0 0 ch =cylinder high
Byte 3 Cylinder Low
Byte 5 r 0 0 0 0 s s s for 512-byte sectors
Format Bad Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

Track Byte 0 0 0 010 0 1 1 1 r = retries
(Class 0, Byte 1 0 0 d I Head Number s = step option
Opcode 07) Byte 2 ch 10 0 0 0 0 0 ch = cylinder high
Byte 3 Cylinder Low
Byte 5 r 0 0 0 0 s s s for 51 2-byte sectors
Read Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

Opcode 08) Byte 1 0 0 d I Head Number a = retry option on
Byte 2 ch I Sector Number data ECC error
Byte 3 Cylinder Low s = step option
Byte 5 r a 0 0 0 s s s ch =cylinder high

(Class 0, used
(Opcode 09)
Write Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1)

Opcode OA) Byte 1 0 0 I
d Head Number s = step option
Byte 2 ch I Sector Number ch = cylinder high
Byte 3 Cylinder Low
Byte 4 Block Count
Byte 5 r 0 0 0 0 s s s
Seek Bit 7 6 5 4 3 2 1 0 d = drive (0 or 1 )

Opcode OB) Byte 1 0 0 d I Head Number s = step option
Byte 2 ch 10 0 0 0 0 0 x = don"t care
Byte 3 Cylinder Low ch = cylinder high
Byte 4: x x x x x x x x
Byte 5 r 0 0 0 0 s s s

Initialize 1 Bit 17 6 5 4 3 2 1 01 Bytes 1,2, 3, 4, 5 =

Drive I Byte 0 10 0 01 0 1 1 0 01 don't care
Characteristics*
(Class 0,
Opcode OC)
Read ECC Burst I Bit I7 6 5 4 3 2 1 01 Bytes 1, 2, 3, 4, 5 =

Error Length I Byte 0 10 0 010 1 1 0 1 I don't care
(Class 0,
Opcode OD)
Read Data from 1 Bit 17 6 5 4 3 2 1 oj Bytes 1, 2, 3, 4, 5 =

Sector Buffer I Byte 0 10 0 01 0 1 1 1 OJ don't care
(Class 0,
Opcode OE)
Write Data to 1 Bit 17 6 5 4 3 2 1 01 Bytes 1, 2, 3,4,5 =

Sector Buffer I Byte 0 10 0 01 0 1 1 1 1 I don't care
(Class 0,
Opcode OF)
RAM I Bit 17 6 5 4 3 2 1 01 Bytes 1, 2, 3, 4, 5 =

Diagnostic I Byte 0 I 1 1 1 10 0 0 0 01 don't care
(Class 7,
Opcode 00)

(Class 7, used
Opcode 01)

(Class 7, used
Opcode 02)
*Initialize Drive Characteristics: The DCB must be followed by eight additional bytes.
Maximum number of cylinders (2 bytes)
Maximum number of heads (1 byte)
Start reduced write current cylinder (2 bytes)
Start write precompensation cylinder (2 bytes)
Maximum ECC data burst length (1 byte)

Drive Bit 7 6 5 4 3 2 1 a d = drive (0 or 1)

Diagnostic Byte a 1 1 1 Ia a a 1 1 s = step option
(Class 7, Byte 1 a a d Ix x x x x r = retries
Opcode 03) Byte 2 x x x x x x x x x = don't care
Byte 3 x x x x x x x x
Byte 4 x x x x x x x x
Byte 5 r a a a a s s s
Controller Bit 7 6 5 4 3 2 1 a Bytes 1, 2, 3,4,5 =

Internal Byte a 1 1 1 10 a 1 a a don't care
Diagnostics
(Class 7,
Opcode 04)
Read Long* Bit 7 6 5 4 3 2 1 a d = drive (0 or 1 )

(Class 7, Byte a 1 1 1 10 a 1 a 1 s = step option
Opcode 05) Byte 1 a a d I Head Number r = retries
Byte 3 Cylinder Low
Byte 4 Block Count
Write Long** Bit 7 6 5 4 3 2 1 a d = drive (0 or 1 )

(Class 7, Byte a 1 1 1 10 a 1 1 a s = step option
Opcode 06) Byte 1 a a d I Head Number r = retries
Byte 3 Cylinder Low
Byte 4 Block Count
*Returns 512 bytes plus 4 bytes of ECC data per sector.

**Requires 512 bytes plus 4 bytes of ECC data per sector.

Programming Summary
The two least-significant bits of the address bus are sent to the
system board's I/O port decoder, which has two sections. One
section is enabled by the I/O read signal (-lOR) and the other by
the I/O write signal (-lOW). The result is a total of four
read/write ports assigned to the disk controller board.
The address enable signal (AEN) is asserted by the system board

when DMA is controlling data transfer. When AEN is asserted,
the I/O port decoder is disabled.
The following figure is a table of the four read/write ports:
R/W Port Address Function
Read 320 Read data (from controller to system unit).

Write 320 Write data (from system unit to controller).
Read 321 Read controller hardware status.

Write 321 Controller reset.
Read 322 Reserved.
Write 322 Generate controller-select pulse.
Read 323 Not used.

Write 323 Write pattern to DMA and interrupt mask
register.

System I/O Channel Interface
The following lines are used by the disk controller:
AO-A19 Positive true 20-bit address. The least-significant 10

bits contain the I/O address within the range of hex
320 to hex 323 when an I/O read or write is
executed by the system unit. The full 20 bits are
decoded to address the read-only memory (ROM)
between the addresses of hex C8000 and C9FFF.
DO-D7 Positive 8-bit data bus over which data and status
information is passed between the system board and
the controller.
Negative true signal that is asserted when the system

board reads status or data from the controller under
either programmed I/O or DMA control.
Negative true signal that is asserted when the system

board sends a command or data to the controller
under either programmed I/O or DMA control.
AEN Positive true signal that is asserted when the DMA in

the system board is generating the I/O Read (-lOR)
or I/O Write (-lOW) signals and has control of the
address and data buses.
RESET Positive true signal that forces the disk controller to

its initial power-up condition.
IRQ 5 Positive true interrupt request signal that is asserted

by the controller, when enabled to interrupt the
system board on the return ending status byte from
the controller.

DRQ 3 Positive-true DMA-request signal that is asserted by
the controller when data is available for transfer to or
from the controller under DMA control. This signal
remains active until the system board's DMA
channel activates the DMA-acknowledge signal
(-DACK 3) in response.
DACK 3 This signal is true when negative, and is generated by

the system board DMA channel in response to a
DMA request (DRQ 3).

Pin 34
Pin 20
Pin 2
Signal Pin Number

Ground - Odd Numbers 1-33
Reserved 4,16,30,32
-Reduced Write Current 2
-Write Gate 6
-Seek Complete 8
-Track 00 10
D isk -Write Fault 12 Disk
D rive -Head Select 2 0 14 Adapter
C onnector -Head Select 21 18 Connect or
J1 J1
-Index 20
-Ready 22
-Step 24
-Drive Select 1 26
-Drive Select 2 28
-Direction In 34
Signal Pin Number

Ground 2,~~8, 12, 16,20
Drive Select 1
Reserved 3, 7
Spare 9, 10, 5 (No Pin)
D isk Ground 11 Disk
D rive MFM Write Data 13 Adapter
C onnector Connect or
-MFM Write Data 14
J2 orJ3 J2 or J3
Ground 15
MFM Read Data 17
-MFM Read Data 18
Ground 19
Fixed Disk Adapter Interface Specifications

IBM 10MB Fixed Disk Drive
The disk drive is a random-access storage device that uses two

non-removable 5-1/4 inch disks for storage. Each disk surface
employs one movable head to service 306 cylinders. The total
formatted capacity of the four heads and surfaces is 10 megabytes
(17 sectors per track with 512 bytes per sector and a total of
1224 tracks).
An impact-resistant enclosure provides mechanical and

contamination protection for the heads, actuator, and disks. A
self-contained recirculating system supplies clean air through a
0.3-micron filter. Thermal isolation of the stepper and spindle
motor assemblies from the disk enclosure results in a very low
temperature rise within the enclosure. This isolation provides a
greater off-track margin and the ability to perform read and write
operations immediately after power-up with no thermal
stabilization delay.
Scrubbing
Filter
sting
Disk
Fixed Disk Drive 1-203

Media Rigid media disk
Number of Tracks 1224
Track Density 345 tracks per inch
Dimensions
Height 3.25 inches (82.55 mm)
Width 5.75 inches (146.05 mm)
Depth 8.0 inches (203.2 mm)
Weight 4.6 Ib (2.08 kg)
Temperature
Operating 40°F to 122°F (4°C to 50°C)
Non operating -40° F to 140° F (-40° C to 60° C)
Relative Humidity
Operating 8% to 80% (non condensing)
Maximum Wet Bulb 78°F (26°C)
Shock
Operating 10 Gs
Non operating 20 Gs
Access Time 3 ms track-to-track
Average Latency 8.33 ms
Error Rates
Soft Read Errors 1 per 10 10 bits read
Hard Read Errors 1 per 10 12 bits read
Seek Errors 1 per 106 seeks
Design Life 5-years (8,000 hours MTF)
Disk Speed 3600 rpm ±1 %
Tra nsfer Rate 5.0 M bits/sec
Recording Mode MFM
Power +12 Vdc ± 5% 1.8 A (4.5 A maximum)
+5 Vdc ± 5% 0.7 A (1.0 A maximum)
Maximum Ripple 1 % with equivalent resistive load
Mechanical and Electrical Specifications
1-204 Fixed Disk Drive

IBM Memory Expansion Options
Three memory expansion options (32KB, 64KB, and 64/256KB)

and two memory module kits (16KB and 64KB) are available for
the IBM Personal Computer. Memory expansion is described in
the following chart:
Number of Number of Memory

Minimum Maximum 16K Memory 64K Memory Module
Memory Memory Module Kits Module Kits Type
16/64K 16K 64K 1,2, or 3 16K by 1 Bit,

System Board 16 pin
64/256K 64K 256K 1,2, Or 3 64K by 1 Bit,

System Board 16 pin
64/256K 64K 256K 1,2, or 3 64K by 1 Bit,

Memory Option 16 pin
32K 32K 16K by 1 Bit,

Memory Option 16 pin
64K 64K Stacked 32K

Memory Option by 1 Bit,
18 pin
The system board must be fully populated before any memory

expansion options can be installed. An expansion option must be
configured to reside at a sequential 32K or 64K memory address
boundary within the system address space. This is done by setting
the DIP switches on the option.
All memory expansion options are parity checked. If a parity

error is detected, a latch is set and an I/O channel check line is
activated, indicating an error to the processor.
Memory Expansion Options 1-205

In addition to the memory modules, the memory expansion
options contain the following circuits: bus buffering, dynamic
memory timing generation, address multiplexing, and card-select
decode logic.
Dynamic-memory refresh timing and address generation are

functions performed on the system board and made available in
the I/O channel for all devices.
To allow the system to address 32K, 64K, or 64/256K memory

expansion options, refer to "Appendix G: Switch Settings" for the
proper memory expansion option switch settings.
The system board operates at a frequency of 4.77 MHz, which
results in a clock cycle of 210 ns.
Normally four clock cycles are required for a bus cycle so that an
840-ns memory cycle time is achieved. Memory-write and
memory-read cycles both take four clock cycles, or 840 ns.
General specifications for memory used on all cards are:
16K by 1 Bit 32K by 1 Bit 64K by 1 Bit
Access 250 ns 250 ns 200 ns

Cycle 410 ns 410 ns 345 ns
Memory Module Description

Both the 32K and the 64K options contain 18 dynamic memory
modules. The 32K memory expansion option utilizes 16K by 1
bit modules, and the 64K memory expansion option utilizes 32K
by 1 bit modules.
1-206 Memory Expansion Options

The 64/256K option has four banks of 9 pluggable sockets. Each
bank will accept a 64K memory module kit, consisting of 9 (64K
by 1) modules. The kits must be installed sequentially into banks
1,2, and 3. The base 64/256K option comes with modules
installed in bank 0, providing 64K of memory. One, two, or three
64K bits may be added, upgrading the option to 128K, 192K, or
256K of memory.
The 16K by 1 and the 32K by 1 modules require three voltage

levels: +5 Vdc, -5 Vdc, and + 12 Vdc. The 64K by 1 modules
require only one voltage level of +5 Vdc. All three memory
modules require 128 refresh cycles every 2 ns. Absolute
maximum access times are:
16K by 1 Bit 32K by 1 Bit 64K by 1 Bit
From RAS 250 ns 250 ns 200 ns

From
-
CAS 165 ns 165 ns 115 ns
16K by 1 Bit Module 32K by 1 Bit Module 64K by 1 Bit Module

Pin (used on 32K option (used on 64K option) (used on 64/256K option
and 16/64K and 64/256K
system board) system board)
1 -5 Vdc -5 Vdc N/C

2 Data In** Data In** Data In***
3 -Write -Write -Write
4 -RAS -RAS 0 -RAS
5 AO -RAS 1 AO
6 A2 AO A2
7 A1 A2 A1
8 +12 Vdc A1 +5 Vdc
9 +5 Vdc +12 Vdc A7
10 A5 +5 Vdc A5
11 A4 A5 A4
12 A3 A4 A3
13 A6 A3 A6
14 Data Out** A6 Data Out***
15 -CAS Data Out** -CAS
16 GND -CAS 1 GND
17 * -CAS 0 *
18 * GND *
*16K by 1 and 64K by 1 bit modules have 16 pins.

**Data In and Data Out are tied together (three-state bus),
***Data In and Data Out are tied together on Data Bits 0-7 (three-state bus).
Memory Module Pin Configuration
Memory Expansion Options 1- 207

Switch-Configurable Start Address
Each card has a small DIP module, that contains eight switches.
The switches are used to set the card start address as follows:
Number 32K and 64K Options 64/256K Options

1 ON: A 19=0; OFF: A 19=1 ON: A 19=0; OFF: A 19=1
2 ON: A18=0; OFF: A18=1 ON: A 18=0; OFF: A 18=1
3 ON:A17=0; OFF: A17=1 ON:A17=0;OFF:A17=1
4 ON:A16=0:OFF:A16=1 ON:A16=0;OFF:A16=1
5 ON:A15=0;OFF:A15=1* ON: Select 64K
6 Not used ON: Select 128K
7 Not used ON: Select 192K
8 Used only in 64K RAM Card* ON: Select 256K
*Switch 8 may be set on the 64K memory expansion option to use only half the
memory on the card (that is, 32K). If switch 8 is on, all 64K is accessible. If
switch 8 is off, address bit A 15 (as set by switch 5) is used to determine which
32K are accessible, and the 64K option behaves as a 32K option.
DIP Module Start Address
Memory Option Switch Settings

Switch settings for all memory expansion options are located in
"Appendix G: Switch Settings."

The following method can be used to determine the switch settings for the 32K
memory expansion option.
Starting Address = xxxK

=Decimal value
32K IxxxK
Convert decimal value to binary
Bit ........ 4 3 2 1 0
Bit value ... 16 8 4 2
Switch
bit
'-----0
1..------- 2 (off = logical 1 )

'-------3
'--------4
The following method can be used to determine the switch settings for the 64K
memory expansion option.

=Decimal value
64K IxxxK
Bit ........ 3 2 0
Bit value ... 8 4 2
Switch
rn hlr 00001
bit
L------O
' - - - - - - - - 2 (off = logical 1)

L-._ _ _ _ _ _ _ _ 3
Memory Expansion Options 1-209

The following method can be used to determine the switch settings for the
64/256K memory expansion option.

=Decimal value
64K IxxxK
Bit ........ 3 2 0
Bit value ... 8 4 2
Switch
Amount of memory
installed on option
' - - - - 256K
' - - - - - 192K (on = logical 1)
' - - - - - - 128K
64K
bit
'-------0
' - - - - - - - - - 2 (off = logical 1 )

.......-------3

IBM Game Control Adapter
The game control adapter allows up to four paddles or two joy

sticks to be attached to the system. This card fits into one of the
system board's or expansion board's expansion slots. The game
control interface cable attaches to the rear ofthe adapter. In
addition, four inputs for switches are provided. Paddle and joy
stick positions are determined by changing resistive values sent to
the adapter. The adapter plus system software converts the
present resistive value to a relative paddle or joy stick position.
On receipt of an output signal, four timing circuits are started. By
determining the time required for the circuit to time-out (a
function of the resistance), the paddle position can be determined.
This adapter could be used as a general purpose I/O card with
four analog (resistive) inputs plus four digital input points.
A9 AO - ... .
I 10 )
r
Convert
AResistive Input
AEN Instruction Resistance
F
Digital K.. 4 I
lOW ..
F
Decode
Pulse
lOR ..... - ~
4--
Typical Frequency
D7-DO 833 Hz
A A
. 8 Data Bus
Buffer/
Driver
(
...
4
..... Digital Inputs
K. 4 J
Game Control Adapter Block Diagram
Game Control Adapter 1-211

Address Decode
The select on the game control adapter is generated by two
74LS138s as an address decoder. AEN must be inactive while
the address is hex 201 in order to generate the select. The select
allows a write to fire the one-shots or a read to give the values of
the trigger buttons and one-shot outputs.
Data Bus Buffer/Driver

The data bus is buffered by a 74LS244 buffer/driver. For an In
from address hex 201, the game control adapter will drive the data
bus; at all other times, the buffer is left in the high impedance
state.
Trigger Buttons
The trigger button inputs are read by an In from address hex 201.
A trigger button is on each joy stick or paddle. These values are
seen on data bits 7 through 4. These buttons default to an open
state and are read as "1." When a button is pressed, it is read as
"0." Software should be aware that these buttons are not
debounced in hardware.
Joy Stick Positions

The joy stick position is indicated by a potentiometer for each
coordinate. Each potentiometer has a range from 0 to 100 k-ohms
that varies the time constant for each ofthe four one-shots. As this
time constant is set at different values, the output of the one-shot
will be of varying durations.
All four one-shots are fired at once by an Out to address hex 201.
All four one-shot outputs will go true after the fire pulse and will
remain high for varying times depending on where each
potentiometer is set.
These four one-shot outputs are read by an In from address hex

201 and are seen on data bits 3 through O.
1-212 Game Control Adapter
I/O Channel Description
A9-AO: Address lines 9 through 0 are used
to address the game control adapter.
D7-DO: Data lines 7 through 0 are the data

bus.
lOR, lOW: I/O read and I/O write are used

when reading from or writing to an
adapter (In, Out).
AEN: When active, the adapter must be

inactive and the data bus driver
inactive.
+5 Vdc: Power for the game control adapter.
GND: Common ground.
AI9-AI0: Unused.
MEMR,MEMW: Unused.
DACKO-DACK3: Unused.
IRQ7-IRQ2: Unused.
DRQ3-DRQ1: Unused.
ALE, TIC: Unused.
CLK,OSC: Unused.
I/O CHCK: Unused.
I/O CHRDY: Unused.
RESETDRV: Unused.
-5 Vdc, +12 Vdc, -12 Vdc: Unused.

Interface Description
The game control adapter has eight input lines, four of which are
digital inputs and 4 of which are resistive inputs. The inputs are
read with one In from address hex 201.
The four digital inputs each have a 1 k-ohm pullup resistor

+5 Vdc. With no drives on these inputs, a 1 is read. For a 0
reading, the inputs must be pulled to ground.
The four resistive pullups, measured to +5 Vdc, will be converted

to a digital pulse with a duration proportional to the resistive load,
according to the following equation:
Time = 24.2 fLsec + 0.011 (r) fLsec

The user must first begin the conversation by an Out to address
hex 201. An In from address hex 201 will show the digital pulse
go high and remain high for the duration according to the
resistance value. All four bits (bit 3-bit 0) function in the same
manner; their digital pulse will all go high simultaneously and will
reset independently according to the input resistance value.
Bit 7 Bit 6 I Bit 5 Bit 4 Bit 3 Bit 2 I Bit 1 Bit 0
Digital Inputs Resistive Inputs
The typical input to the game control adapter is a set of joy sticks
or game paddles.
The joy sticks will typically be a set of two (A and B). These will
have one or two buttons each with two variable resistances each,
with a range from 0 to 100 k-ohms. One variable resistance will
indicate the X-coordinate and the other variable resistance will
indicate the Y-coordinate. This should be attached to give the
following input data:

B-#2 B-#1 A-#2 A-#1 B-Y B-X A-Y A-X
Button Button Button Button Coordinate Coordinate Coordinate Coordinate

The game paddles will have a set of two (A and B) or four (A, B,
C, and D) paddles. These will have one button each and one
variable resistance each, with a range of 0 to 100 k-ohms. This
should be attached to give the following input data:

D C BAD C B A
Button Button Button Button Coordinate Coordinate Coordinate Coordinate
Refer to "Joy Stick Schematic Diagram" for attaching game

controllers.
15-Pin Male D-Shell

Connector
Joy Stick B __ -<j'\ r ____J~~~~~_A___ ~

r---------------,
I /--- ~--+---------------~
r----------------I----!-I"9 2 I I X-Coordinate
X.Coordinate ....}-- I
I • I ~ r-Button
Butto~J :'0 i-+- I ~
1'---1-_-,-1~11.. ! ! i I
Y -Coordinate I 12 5 I
I • I Y-Coordin;lte
oil I I • 6 I
I 11 3 • I
I I. I
I 114 7 I
I
I I • I I
I. 8 I I
IL _____________ JI (15 • L_____________ J
'-- -----.",
Note: Potentiometer for X- and Y -Coordinates has a range of 0
to 100 k-ohms. Button is normally open; closed when
pressed.
Joy Stick Schematic Diagram

15-Pin D-Shell
Connector
0
• • 9
• •
• •
8 •
G
• •
G
• •
G
• • 15
8 •
G
~ G 0

Adapter
Voltage Pin No.
+5Vdc 1
Button 4 2
Position 0 3
Ground 4
Ground 5
Position 1 6
Button 5 7
External +5Vdc 8 Game Control
Devices +5 Vdc 9 Adapte
Button 6 10
Position 2 11
Ground 12
Position 3 13
Button 7 14
+5 Vdc 15

IBM Prototype Card
The prototype card is 4.2 inches (106.7 millimeters) high by 13.2

inches (335.3 millimeters) long and plugs into an expansion unit
or system unit expansion slot. All system control signals and
voltage requirements are provided through a 2 by 31 position
card-edge tab.
The card contains a voltage bus (+5 Vdc) and a ground bus (0
Vdc). Each bus borders the card, with the voltage bus on the back
(pin side) and the ground bus on the front (component side). A
system interface design is also provided on the prototype card.
The prototype card can also accommodate a D-shell connector if

it is needed. The connector size can range from a 9 to a 37
position connector.
Note: Install all components on the component side of the

prototype card. The total width of the card including components
should not exceed 0.500 inch (12.7 millimeters). If these
specifications are not met, components on the prototype card may
touch other cards plugged into adjacent slots.
Prototype Card 1-217

8
Bit 0- 7 Data Bus
Data Bus
Buffer
Transceiver
Bus Direction
DIR G Data
Bus
I/O Read/Write
Memory Read/Write
Spare-E18
Address Bit 0 Buffered
Address
Addrets Bit 2
Lines
Address Bit 3 E2
Addrest Bit 9 Address E5
Buffer
1--I6t..-_ _-I1/0 Address
Address Enabl Decode
t-t-----i Logic
H .... --1. E11
L...-_ _- - '
-I/O Decode
(Hex 300 - 31 F Inclusive)
Prototype Card Block Diagram
1-218 Prototype Card

I/O Channel Interface
The prototype card has two layers screened onto it (one on the
front and one on the back). It also has 3,909 plated through-holes
that are 0.040 inch (10.1 millimeters) in size and have a 0.060
inch (1.52 millimeters) pad, which is located on a 0.10 inch (2.54
millimeters) grid. There are 37 plated through-holes that are
0.048 inch (1.22 millimeters) in size. These holes are located at
the rear of the card (viewed as if installed in the machine). These
37 holes are used for a 9 to 37 position D-shell connector. The
card also has 5 holes that are 0.125 inch (3.18 millimeters) in
size. One hole is located just above the two rows of D-shell
connector holes, and the other four are located in the comers of
the board (one in each comer).
Prototype Card Layout

The component side has the ground bus [0.05 inch (1.27
millimeters) wide] screened on it and card-edge tabs that are
labeled Al through A31.
Ground Bus
2~l
O-Shell Connector
Pin Positions
!
Card-Edge Tabs
Hole for Option
Retaining Bracket
Component Side

The component side also has a silk screen printed on it that is
used as a component guide for the I/O interface.
Component Side
The pin side has a +5 Vdc bus [0.05 inch (1.27 millimeters)
wide] screened onto it and card-edge tabs that are labeled B 1
through B31.
Hole for Option +5 Vdc Bus

Retaining Bracket
Pin Positions
Hole for Option Card-Edge Tabs

Retaining Bracket
Pin Side

Each card-edged tab is connected to a plated through-hole by a
O.012-inch (O.3-millimeter) land. There are three ground tabs
connected to the ground bus by three O.012-inch (O.3-millimeter)
lands. Also, there are two +5 Vdc tabs connected to the voltage
bus by two O.012-inch (O.3-millimeter) lands.
For additional interfacing information, refer to "I/O Channel

Description" and "I/O Channel Diagram" in this manual. Also,
the "Prototype Card Interface Logic Diagram" is in Appendix D
of this manual. If the recommended interface logic is used, the list
of TTL type numbers listed below will help you select the
necessary components.
Component TTL Number Description

Ul 74LS245 acta I Bus Tra nsceiver
U2,U5 74LS244 Octal Buffers Line Driver/Line Receivers
U4 74LS04 Hex Inverters
U3 74LS08 Quadruple 2 - Input
Positive - AND Gate
U6 74LS02 Quadruple 2 - Input
Positive - NOR Gate
U7 74LS21 Dual 4 - Input
Positive - AND Gate
C1 10.0 f.1F Tantalum Capacitor
C2,C3,C4 0.047 f.1F Ceramic Capacitor
System Loading and Power Limitations

Because of the number of options that may be installed in the
system, the I/O bus loading should be limited to one Schottky
TTL load. If the interface circuitry on the card is used, then this
requirement is met.
Refer to the power supply information in this manual for the

power limitations to be observed.

Prototype Card External Interface
If a connector is required for the card function, then you should
purchase one of the recommended connectors (manufactured by
Amp) or equivalent listed below:
Connector Size Part Number (Amp)

9-pin D-shell (Male) 205865-1
9-pin D-shell (Female) 205866-1
25-pin D-shell (Male 205857-1
The following example shows a 1S-pin, D-shell, female connector

attached to a prototype card.
Option Retaining
Bracket
~
•
• • 9
• •
• •
• •
• •
• •
• 15
~
8
0
15-Pin D-Shell
Female Connector
Component Side

IBM Asynchronous
Communications Adapter
The asynchronous communications adapter system control signals

and voltage requirements are provided through a 2 by 31 position
card-edge tab. Two jumper modules are provided on the adapter.
One jumper module selects either RS-232C or current-loop
operation. The other jumper module selects one of two addresses
for the adapter, so two adapters may be used in one system.
The adapter is fully programmable and supports asynchronous

communications only. It will add and remove start bits, stop bits,
and parity bits. A programmable baud rate generator allows
operation from 50 baud to 9600 baud. Five, six, seven or eight bit
characters with 1, 1-1/2, or 2 stop bits are supported. A fully
prioritized interrupt system controls transmit, receive, error, line
status and data set interrupts. Diagnostic capabilities provide
loopback functions of transmit/receive and input/output signals.
The heart of the adapter is a INS8250 LSI chip or functional

equivalent. Features in addition to those listed above are:
• Full double buffering eliminates need for precise

synchronization.
• Independent receiver clock input.
• Modem control functions: clear to send (CTS), request to

send (RTS), data set ready (DSR), data terminal ready
(DTR), ring indicator (RI), and carrier detect.
• False-start bit detection.
• Line-break generation and detection.
All communications protocol is a function of the system

microcode and must be loaded before the adapter is operational.
All pacing of the interface and control signal status must be
handled by the system software. The following figure is a block
diagram of the asynchronous communications adapter.
Asynchronous Adapter 1-223

Address Chip
Address Bus
""'""-'--
,--_D_ec_o_d_e_.J Select ......
Data Bus
-----~ln~te~r~ru~p~t----~8250
...--__ ;::;::====::::;---~ Asynchronous

Communications
1 - - - -...... Element
Current Loop
25-Pin D-Shell
Connector
Asynchronous Communications Adapter Block Diagram
Modes of Operation
The different modes of operation are selected by programming the
8250 asynchronous communications element. This is done by
selecting the I/O address (hex 3F8 to 3FF primary, and hex 2F8
to 2FF secondary) and writing data out to the card. Address bits
AO, AI, and A2 select the different registers that define the modes
of operation. Also, the divisor latch access bit (bit 7) of the line
control register is used to select certain registers.
1-224 Asynchronous Adapter

I/O Decode (in Hex)
Primary Alternate
Adapter Adapter Register Selected DLAB State
3F8 2F8 TX Buffer DLAB=O (Write)
3F8 2F8 RX Buffer DLAB=O (Read)
3F8 2F8 Divisor Latch LSB DLAB=l
3F9 2F9 Divisor Latch MSB DLAB=l
3F9 2F9 Interrupt Enable Register
3FA 2FA Interrupt Identification Registers
3FB 2FB Line Control Register
3FC 2FC Modem Control Register
3FD 2FD Line Status Register
3FE 2FE Modem Status Register
I/O Decodes
Hex Address 3F8 to 3FF and 2F8 to 2FF

A9 A8 A7 A6 AS A4 A3 A2 A1 AO DLAB Register
1 1/0 1 1 1 1 1 x x x
0 0 0 0 Receive Buffer (read).

Transmit
Holding Reg. (write)
0 0 1 0 Interrupt Enable
0 1 0 x Interrupt Identification
0 1 1 x Line Control
1 0 0 x Modem Control
1 0 1 x Line Status
1 1 0 x Modem Status
1 1 1 x None
0 0 0 1 Divisor Latch (LSB)
0 0 1 1 Divisor Latch (MSB)
Note: Bit 8 will be logical 1 for the adapter designated as primary or a logical 0
for the adapter designated as alternate (as defined by the address jumper
module on the adapter).
A2, Aland AO bits are "don't cares" and are used to select the different
register of the communications chip.
Address Bits

Interrupts
One interrupt line is provided to the system. This interrupt is
IRQ4 for a primary adapter or IRQ3 for an alternate adapt~r, and
is positive active. To allow the communications card to send
interrupts to the system, bit 3 of the modem control register must
be set to 1 (high). At this point, any interrupts allowed by the
interrupt enable register will cause an interrupt.
The data format will be as follows:
00 01 02 05 06 07
Transmit Start Parity Stop

Oata Marking Bit Bit Bits
Data bit 0 is the first bit to be transmitted or received. The

adapter automatically inserts the start bit, the correct parity bit if
programmed to do so, and the stop bit (1, 1-1/2, or 2 depending
on the command in the line-control register).
Interface Description
The communications adapter provides an EIA RS-232C-like
interface. One 25-pin D-shell, male type connector is provided to
attach various peripheral devices. In addition, a current loop
interface is also located in this same connector. A jumper block is
provided to manually select either the voltage interface, or the
current loop interface.
The current loop interface is provided to attach certain printers

provided by IBM that use this particular type of interface.
Pin 18 + receive current loop data

Pin 25 - receive current loop return
Pin 9 + transmit current loop return
Pin 11 - transmit current loop data

+5Vdc
I
T" ..m" C;re"" I
~~~
~ 49.9 Ohm
Pin 9
Tx Data _ _ _....,~2vO'hm
L.._- - - - - - - - . :
_ Pin 11
+5Vdc
I Receive Circuit
5.6 k-Ohm
OPTO Isolator
Pin 18 X J I - - - - - Rx Data
Pin 25 ...--+-.....
+5Vdc
Current Loop Interface
The voltage interface is a serial interface. It supports certain data

and control signals, as listed below.
Pin 2 Transmitted Data

Pin 3 Received Data
Pin 4 Request to Send
Pin 5 Clear to Send
Pin 6 Data Set Ready
Pin 7 Signal Ground
Pin 8 Carrier Detect
Pin 20 Data Terminal Ready
Pin 22 Ring Indicator
The adapter converts these signals to/from TTL levels to EIA

voltage levels. These signals are sampled or generated by the
communications control chip. These signals can then be sensed by
the system software to determine the state of the interface or
peripheral device.

Voltage Interchange Information
Interface
Interchange Voltage Binary State Signal Condition Control Function
Positive Voltage = Binary (0) = Spacing =On
Negative Voltage = Binary (1) = Marking =Off
Invalid Levels
+15 Vdc
On Function
+3 Vdc
o Vdc Invalid Levels
-3 Vdc
Off Function
-15 Vdc
Invalid Levels
The signal will be considered in the "marking" condition when the

voltage on the interchange circuit, measured at the interface point,
is more negative than - 3 Vdc with respect to signal ground. The
signal will be considered in the "spacing" condition when the
voltage is more positive than + 3 Vdc with respect to signal
ground. The region between +3 Vdc and -3 Vdc is defined as the
transition region, and considered an invalid level. The voltage that
is more negative than -15 Vdc or more positive than + 15 Vdc
will also be considered an invalid level.
During the transmission of data, the "marking" condition will be

used to denote the binary state" 1" and "spacing" condition will
be used to denote the binary state "0."
Forinterface control circuits, the function is "on" when the

voltage is more positive than + 3 Vdc with respect to signal ground
and is "off" when the voltage is more negative than - 3 Vdc with
respect to signal ground.

INS8250 Functional Pin Description
The following describes the function of all INS8250 input/output
pins. Some of these descriptions reference internal circuits.
Note: In the following descriptions, a low represents a logical 0

(0 Vdc nominal) and a high represents a logical 1 (+2.4 Vdc
nominal).
Input Signals
Chip Select (CSO, CS1, CS2), Pins 12-14: When CSO and
CSI are high and CS2 is low, the chip is selected. Chip selection
is complete when the decoded chip select signal is latched with an
active (low) address strobe (ADS) input. This enables
communications between the INS8250 and the processor.
Data Input Strobe (DISTR, DISTR) Pins 22 and 21: When

DISTR is high or DISTR is low while the chip is selected, allows
the processor to read status information or data from a selected
register of the INS8250.
Note: Only an active DISTR or DISTR input is required to

transfer data from the INS8250 during a read operation.
Therefore, tie either the DISTR input permanently low or the
DISTR input permanently high, if not used.
Data Output Strobe (DOSTR, DOSTR), Pins 19 and

18: When DOSTR is high or DOSTR is low while the chip is
selected, allows the processor to write data or control words into a
selected register of the INS8250.
Note: Only an active DOSTR or DOSTR input is required to

transfer data to the INS8250 during a write operation. Therefore,
tie either the DOSTR input permanently low or the DOSTR input
permanently high, if not used.

Address Strobe (ADS), Pin 25: When low, provides latching
for the register select (AO, AI, A2) and chip select (CSO, CSl,
CS2) signals.
Note: An active ADS input is required when the register select

(AO, AI, A2) signals are not stable for the duration of a read or
write operation. If not required, tie the ADS input permanently
low.
Register Select (AO, At, A2), Pins 26-28: These three inputs
are used during a read or write operation to select an INS8250
register to read from or write to as indicated in the table below.
Note that the state of the divisor latch access bit (DLAB), which
is the most significant bit of the line control register, affects the
selection of certain INS8250 registers. The DLAB must be set
high by the system software to access the baud generator divisor
latches.
DLAB A2 A1 AO Register
0 0 0 0 Receiver Buffer (Read), Transmitter
Holding Register (Write)
0 0 0 1 Interrupt Enable
,
X 0 1 0 Interrupt Identification (Read Only)
X 0 1 1 Li ne Control
X 1 0 0 Modem Control
X 1 0 1 Line Status
X 1 1 0 Modem Control Status
X 1 1 1 None
1 0 0 0 Divisor Latch (Least Significant Bit)
1 0 0 1 Divisor Latch (Most Significant Bit)
Master Reset (MR), Pin 35: When high, clears all the registers
(except the receiver buffer, transmitter holding, and divisor
latches), and the control logic of the INS8250. Also, the state of
various output signals (SOUT, INTRPT, OUT 1, OUT 2, RTS,
DTR) are affected by an active MR input. Refer to the
"Asynchronous Communications Reset Functions" table.
Receiver Clock (RCLK), Pin 9: This input is the 16 x baud

rate clock for the receiver section of the chip.

Serial Input (SIN), Pin 10: Serial data input from the
communications link (peripheral device, modem, or data set).
Clear to Send (CTS), Pin 36: The CTS signal is a modem

control function input whose condition can be tested by the
processor by reading bit 4 (CTS) of the modem status register. Bit
o (DCTS) of the modem status register indicates whether the CTS
input has changed state since the previous reading of the modem
status register.
Note: Whenever the CTS bit of the modem status register

changes state, an interrupt is generated if the modem status
interrupt is enabled.
Data Set Ready (DSR), Pin 37: When low, indicates that the
modem or data set is ready to establish the communications
link and transfer data with the INS8250. The DSR signal is a
modem-control function input whose condition can be tested by
the processor by reading bit 5 (DSR) of the modem status register.
Bit 1 (DDSR) of the modem status register indicates whether the
DSR input has changed since the previous reading of the modem
status register.
Note: Whenever the DSR bit of the modem status register

Received Line Signal Detect (RLSD), Pin 38: When low,

indicates that the data carrier had been detected by the modem or
data set. The RLSD signal is a modem-control function input
whose condition can be tested by the processor by reading bit 7
(RLSD) of the modem status register. Bit 3 (DRLSD) of the
modem status register indicates whether the RLSD input has
changed state since the previous reading of the modem status
register.
Note: Whenever the RLSD bit of the modem status register


Ring Indicator (RI), Pin 39: When low, indicates that a
telephone ringing signal has been received by the modem or data
set. The RI signal is a modem-control function input whose
conditon can be tested by the processor by reading bit 6 (RI) of
the modem status register. Bit 2 (TERI) of the modem status
register indicates whether the RI input has changed from a low to
high state since the previous reading of the modem status register.
Note: Whenever the RI bit of the modem status register changes

from a high to a low state, an interrupt is generated if the modem
status register interrupt is enabled.
vee, Pin 40: +5 Vdc supply.
VSS, Pin 20: Ground (0 Vdc) reference.
Output Signals
Data Terminal Ready (DTR), Pin 33: When low, informs the
modem or data set that the INS8250 is ready to communicate.
The DTR output signal can be set to an active low by
programming bit 0 (DTR) of the modem control register to a high
level. The DTR signal is set high upon a master reset operation.
Request to Send (RTS), Pin 32: When low, informs the modem
or data set that the INS8250 is ready to transmit data. The RTS
output signal can be set to an active low by programming bit 1
(RTS) of the modem control register. The RTS signal is set high
upon a master reset operation.
Output 1 (OUT 1), Pin 34: User-designated output that can be

set to an active low by programming bit 2 (OUT 1) of the modem
control register to a high level. The OUT 1 signal is set high upon
a master reset operation.
Output 2 (OUT 2), Pin 31: User-designated output that can be

set to an active low by programming bit 3 (OUT 2) of the modem
control register to a high level. The OUT 2 signal is set high upon
a master reset operation.

Chip Select Out (CSOUT), Pin 24: When high, indicates that
the chip has been selected by active CSO, CSl, and CS2 inputs.
No data transfer can be initiated until the CSOUT signal is a
logical 1.
Driver Disable (DDIS), Pin 23: Goes low whenever the

processor is reading data from the INS8250. A high-level DDIS
output can be used to disable an external transceiver (if used
between the processor and INS8250 on the D7-DO data bus) at
all times, except when the processor is reading data.
Baud Out (BAUDOUT), Pin 15: 16 x clock signal for the

transmitter section of the INS8250. The clock rate is equal to the
main reference oscillator frequency divided by the specified
divisor in the baud generator divisor latches. The BAUDOUT
may also be used for the receiver section by typing this output to
the RCLK input of the chip.
Interrupt (INTRPT), Pin 30: Goes high whenever anyone of

the following interrupt types has an active high condition and is
enabled through the IER: receiver error flag, received data
available, transmitter holding register empty, or modem status.
The INTRPT signal is reset low upon the appropriate interrupt
service or a master reset operation.
Serial Output (SOUT), Pin 11: Composite serial data output to

the communications link (peripheral, modem, or data set). The
SOUT signal is set to the marking (logical 1) state upon a master
reset operation.
Input/Output Signals
Data Bus (D7-DO), Pins 1-8: This bus comprises eight tri-state
input/output lines. The bus provides bidirectional communications
between the INS8250 and the processor. Data, control words,
and status information are transferred through the D7-DO data
bus.
External Clock Input/Output (XTALl, XTAL2), Pins 16 and

17: These two pins connect the main timing reference (crystal or
signal clock) to the INS8250.

The INS8250 has a number of accessible registers. The system
programmer may access or control any of the INS8250 registers
through the processor. These registers are used to control
INS8250 operations and to transmit and receive data. A table
listing and description of the accessible registers follows.
Register /Signal Reset Control Reset State

Interrupt Enable Register M a ste r Reset All Bits Low (0-3 Forced and
4-7 Permanent)
Interrupt Identification Master Reset Bit 0 is High, Bits 1 and 2 Low
Register Bits 3-7 are Permanently Low
Line Control Register Master Reset All Bits Low
Modem Control Register Master Reset All Bits Low
Line Status Register Master Reset Except Bits 5 and 6 are High
Modem Status Register Master Reset Bits 0-3 Low
Bits 4-7 - Input Signal
SOUT Master Reset High
INTRPT (RCVR Errors) Read LSR/MR Low
INTRPT (RCVR Data Ready) Read RBR/MR Low
INTRPT (RCVR Data Ready) Read IIR/ Low
Write THR/MR
INTRPT (Modem Status Read MSR/MR Low
Changes)
OUT 2 Master Reset High
RTS Master Reset High
DTR Master Reset High
OUT 1 Master Reset High
Asynchronous Communications Reset Functions

Line-Control Register
The system programmer specifies the format of the asynchronous
data communications exchange through the line-control register.
In addition to controlling the format, the programmer may retrieve
the contents of the line-control register for inspection. This feature
simplifies system programming and eliminates the need for
separate storage in system memory of the line characteristics. The
contents of the line-control register are indicated and described
below.
Bit 7 6 5 4 3 2 0
Word Length Select Bit 0 (WLSO)

Word Length Select Bit 1 (WLS 1)
Number of Stop Bits (STB)
Parity Enable (PEN)
Even Parity Select (EPS)
Stick Parity
Set Break
Divisor Latch Access Bit(DLAB)
Line-Control Register (LCR)
Bits 0 and 1: These two bits specify the number of bits in each
transmitted or received serial character. The encoding of bits 0
and 1 is as follows:
Bit 1 Bit 0 Word Length

0 0 5 Bits
0 1 6 Bits
1 0 7 Bits
1 1 8 Bits

Bit 2: This bit specifies the number of stop bits in each
transmitted or received serial character. If bit 2 is a logical 0, one
stop bit is generated or checked in the transmit or receive data,
respectively. If bit 2 is logical 1 when a 5-bit word length is
selected through bits 0 and 1, 1-1/2 stop bits are generated or
checked. If bit 2 is logical 1 when either a 6-, 7-, or 8-bit word
length is selected, two stop bits are generated or checked.
Bit 3: This bit is the parity enable bit. When bit 3 is a logical 1,
a parity bit is generated (transmit data) or checked (receive data)
between the last data word bit and stop bit of the serial data. (The
parity bit is used to produce an even or odd number of l's when
the data word bits and the parity bit are summed.)
Bit 4: This bit is the even parity select bit. When bit 3 is a
logical 1 and bit 4 is a logical 0, an odd number of logical 1's is
transmitted or checked in the data word bits and parity bit. When
bit 3 is a logical 1 and bit 4 is a logical 1, an even number of bits
is transmitted or checked.
Bit 5: This bit is the stick parity bit. When bit 3 is a logical 1
and bit 5 is a logical 1, the parity bit is transmitted and then
detected by the receiver as a logical 0 if bit 4 is a logical 1, or as a
logical 1 if bit 4 is a logical O.
Bit 6: This bit is the set break control bit. When bit 6 is a logical
1, the serial output (SOUT) is forced to the spacing (logical 0)
state and remains there regardless of other transmitter activity.
The set break is disabled by setting bit 6 to a logical O. This
feature enables the processor to alert a terminal in a computer
communications system.
Bit 7: This bit is the divisor latch access bit (DLAB). It must be
set high (logical 1) to access the divisor latches of the baud rate
generator during a read or write operation. It must be set low
(logical 0) to access the receiver buffer, the transmitter holding
register, or the interrupt enable register.

Programmable Baud Rate Generator
The INS8250 contains a programmable baud rate generator that
is capable oftaking the clock input (1.8432 MHz) and dividing it
by any divisor from 1 to (2 16 -1). The output frequency of the
baud generator is 16 x the baud rate [divisor # = (frequency
input)/(baud rate x 16)]. Two 8-bit latches store the divisor in a
16-bit binary format. These divisor latches must be loaded during
initialization in order to ensure desired operation of the baud rate
generator. Upon loading either of the divisor latches, a 16-bit
baud counter is immediately loaded. This prevents long counts on
initial load.
Hex Address 3F8 DLAB = 1

a
L:
Bit 7 6 5 4 3 2
I I~Bitl
.,,0
Bit 2
L...-_ _ _ _ _ _ ~ Bit 3
1....-_ _ _ _ _ _ _ _ _ Bit 4
L...-_ _ _ _ _ _ _ _ _ _ ~ Bit 5
L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ Bit 6
1....-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Bit 7
Divisor Latch Least Significant Bit (DLL)

Hex Address 3F9 DLAB = ,.
1_:
Bit 7 6 5 4 3 2 o
I I~Bit9 B;>8
Bit 10
I..-_ _ _ _ _ _ _ ~ Bit 11
'--------------1~ Bit 12
' - - - - - - - - - - - - - - - Bit 13
' - - - - - - - - - - - - - - - - + - Bit 14
1..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.... Bit 15
Divisor Latch Most Significant Bit (DLM)
The following figure illustrates the use of the baud rate generator
with a frequency of 1.8432 MHz,. For baud rates of 9600 and
below, the error obtained is minimal.
Note: The maximum operating frequency of the baud generator

is 3.1 MHz. In no case should the data rate be greater than 9600
baud.
Desired Divisor Used Percent Error

Baud to Generate Difference Between
Rate 16x Clock Desired and Actual
(Decimal) (Hex)
50 2304 900 -
75 1536 600 -
110 1047 417 0.026
134.5 857 359 0.058
150 768 300 -
300 384 180 -
600 192 OCO -
1200 96 060 -
1800 64 040 -
2000 58 03A 0.69
2400 48 030 -
3600 32 020 -
4800 24 018 -
7200 16 010 -
9600 12 OOC -
Baud Rate at 1.843 MHz

Line Status Register
This 8-bit register provides status information on the processor
concerning the data transfer. The contents of the line status
register are indicated and described below:
Hex Address 3FD

Bit 7 6 5 4 3 2 o
I I 1_: 0,., R"dy (DR,

Overrun Error (OR)
Parity Error (PE)
' - - - - - - - - _ Framing Error (FE)
'----------~ Break Interrupt (BI)
'------------~ Transmitter Holding
Register Empty
(THRE)
'--------------~ Tx Shift Register
Empty (TSRE)
~---------------=O
Line Status Register (LSR)
Bit 0: This bit is the receiver data ready (DR) indicator. Bit 0 is
set to a logical 1 whenever a complete incoming character has
been received and transferred into the receiver buffer register. Bit
o may be reset to a logical 0 either by the processor reading the
data in the receiver buffer register or by writing a logical 0 into it
from the processor.
Bit 1: This bit is the overrun error (OE) indicator. Bit 1

indicates that data in the receiver buffer register was not read by
the processor before the next character was transferred into the
receiver buffer register, thereby destroying the previous character.
The OE indicator is reset whenever the processor reads the
contents of the line status register.
Bit 2: This bit is the parity error (PE) indicator .. Bit 2 indicates
that the received data character does not have the correct even or
odd parity, as selected by the even parity-select bit. The PE bit is
set to a logical 1 upon detection of a parity error and is reset to a
logical 0 whenever the processor reads the contents of the line
status register.

Bit 3: This bit is the framing error (FE) indicator. Bit 3
indicates that the received character did not have a valid stop bit.
Bit 3 is set to a logical 1 whenever the stop bit following the last
data bit or parity is detected as a zero bit (spacing level).
Bit 4: This bit is the break interrupt (BI) indicator. Bit 4 is set to
a logical 1 whenever the received data input is held in the spacing
(logical 0) state for longer than a full word transmission time (that
is, the total time of start bit + data bits + parity +stop bits).
Note: Bits 1 through 4 are the error conditions that produce a

receiver line status interrupt whenever any of the corresponding
conditions are detected.
Bit 5: This bit is the transmitter holding register empty (THRE)

indicator. Bit 5 indicates that the INS8250 is ready to accept a
new character for transmission. In addition, this bit causes the
INS8250 to issue an interrupt to the processor when the transmit
holding register empty interrupt enable is set high. The THRE bit
is set to a logical 1 when a character is transferred from the
transmitter holding register into the transmitter shift register. The
bit is reset to logical 0 concurrently with the loading of the
transmitter holding register by the processor.
Bit 6: This bit is the transmitter shift register empty (TSRE)

indicator. Bit 6 is set to a logical 1 whenever the transmitter shift
register is idle. It is reset to logical 0 upon a data transfer from the
transmitter holding register to the transmitter shift register. Bit 6 is
a read-only bit.
Bit 7: This bit is permanently set to logical O.
Interrupt Identification Register

The INS8250 has an on-chip interrupt capability that allows for
complete flexibility in interfacing to all the popular
microprocessors presently available. In order to provide minimum
software overhead during data character transfers, the INS8250
prioritizes interrupts into four levels: receiver line status (priority
1), received data ready (priority 2), transmitter holding register
empty (priority 3), and modem status (priority 4).

Information indicating that a prioritized interrupt is pending and
the type of prioritized interrupt is stored in the interrupt
identification register. Refer to the "Interrupt Control
Functions" table. The interrupt identification register (IIR), when
addressed during chip-select time, freezes the highest priority
interrupt pending, and no other interrupts are acknowledged until
that particular interrupt is serviced by the processor. The contents
of the IIR are indicated and described below.
Hex Address 3FA

Bit 7 6 543 2 a
[I L~
I~ 0 If 'oW,"p' P, odi0 9
Interrupt 10 Bit (0)
Interrupt 10 Bit (1)
=0
1....-_ _ _ _ _ _ = a
I....--------~ = a
1....-_ _ _ _ _ _ _ _- . . = a
L...-_ _ _ _ _ _ _ _ _ _..... = a
Interrupt Identification Register OIR)
Bit 0: This bit can be used in either a hard-wired prioritized or

polled environment to indicate whether an interrupt is pending and
the IIR contents may be used as a pointer to the appropriate
interrupt service routine. When bit 0 is a logical 1, no interrupt is
pending and polling (if used) is continued.
Bits 1 and 2: These two bits of the IIR are used to identify the
highest priority interrupt pending as indicated in the "Interrupt
Control Functions" table.
Bits 3 through 7: These five bits of the IIR are always logical O.

Interrupt 10
Register Interrupt Set and Reset Functions
Priority Interrupt Interrupt Interrupt
Bit 2 Bit 1 Bit 0 Level Type Source Reset Control
0 0 1 - None None -
1 1 0 Highest Receiver Overrun Error Reading the
Line Status or Line Status
Parity Error Register
or
Fra mi ng Error
or
Break Interrupt
1 0 0 Second Received Receiver Reading the
Data Available Data Available Receiver Buffer
Register
0 1 0 Third Transmitter Transmitter Reading the IIR
Holding Holding Register (if
Register Register source of
Empty Empty interrupt)
or
Writing into the
Transmitter
Holding Register
0 0 0 Fourth Modem Clear to Send Reading the
Status or Modem Status
Data Set Ready Register
or
Ring Indicator
or
Received Line
Signal Direct
Interrupt Control Functions

Interrupt Enable Register
This eight-bit register enables the four types of interrupt of the
INS8250 to separately activate the chip interrupt (INTRPT)
output signal. It is possible to totally disable the interrupt system
by resetting bits 0 through 3 of the interrupt enable register.
Similarly, by setting the appropriate bits of this register to a
logical 1, selected interrupts can be enabled. Disabling the
interrupt system inhibits the interrupt identification register and
the active (high) INTRPT output from the chip. All other system
functions operate in their normal manner, including the setting of
the line status and modem status registers. The contents of the
interrupt enable register are indicated and described below:
Hex Address 3F9 DLAB = a

Bit 7 6 543 2 a
~
L 1 = Enable Data
Available Interrupt
1 = Enable Tx Holding Register
Empty Interrupt
1 = Enable Receive Line
Status Interrupt
L...-_ _ _ _~ 1 = Enable Modem Status
Interrupt
L...------~·=O
'---------~ = a
' - - - - - - - - - -..... = a
' - - - - - - - - - - - -. . . = a
Interrupt Enable Register (IER)
Bit 0: This bit enables the received data available interrupt when
set to logical 1.
Bit 1: This bit enables the transmitter holding register empty

interrupt when set to logical 1.
Bit 2: This bit enables the receiver line status interrupt when set
to logical 1.

Bit 3: This bit enables the modem status interrupt when set to
logical 1.
Bits 4 through 7: These four bits are always logical O.
Modem Control Register

This eight-bit register controls the interface with the modem or
data set (or peripheral device emulating a modem). The contents
of the modem control register are indicated and described below:
Hex Address 3FC

Bit 7 6 543 2 a
III I ~ Do<, Toem'''' R"dy,DTR,

Request to Send (RTS)
Out 1
Out 2
L...-_ _ _ _ _• Loop
L...-_ _ _ _ _ _ _ = a
L...-_ _ _ _ _ _ _ _• = a
L...-_ _ _ _ _ _ _ _ _ _ _ = a
Modem Control Register (MCR)
Bit 0: This bit controls the data terminal ready (DTR) output.
When bit 0 is set to logical 1, the DTR output is forced to a
logical O. When bit 0 is reset to a logical 0, the DTR output is
forced to a logical 1.
Note: The DTR output ofthe INS8250 may be applied to an

EIA inverting line driver (such as the DS 1488) to obtain the
proper polarity input at the succeeding modem or data set.
Bit 1: This bit controls the request to send (RTS) output. Bit 1
affects the RTS output in a manner identical to that described
above for bit O.

Bit 2: This bit controls the output 1 (OUT 1) signal, which is an
auxiliary user-designated output. Bit 2 affects the OUT 1 output
in a manner identical to that described above for bit O.
Bit 3: This bit controls the output 2 (OUT 2) signal, which is an

auxiliary user-designated output. Bit 3 affects the OUT 2 output
in a manner identical to that described above for bit O.
Bit 4: This bit provides a loopback feature for diagnostic testing

of the INS8250. When bit 4 is set to logical 1, the following
occurs: the transmitter serial output (SOUT) is set to the marking
(logical 1) state; the receiver serial input (SIN) is disconnected;
the output of the transmitter shift register is "looped back" into
the receiver shift register input; the four modem control inputs
(CTS, DRS, RLSD, and RI) are disconnected; and the four
modem control outputs (DTR, RTS, OUT 1, and OUT 2) are
internally connected to the four modem control inputs. In the
diagnostic mode, data that is transmitted is immediately received.
This feature allows the processor to verify the transmit- and
receive-data paths of the INS8250.
In the diagnostic mode, the receiver and transmitter interrupts are

fully operational. The modem control interrupts are also
operational but the interrupts' sources are now the lower four bits
of the modem control register instead of the four modem control
inputs. The interrupts are still controlled by the interrupt enable
register.
The INS8250 interrupt system can be tested by writing into the

lower four bits of the modem status register. Setting any of these
bits to a logical 1 generates the appropriate interrupt (if enabled).
The resetting of these interrupts is the same as in normal
INS8250 operation. To return to normal operation, the registers
must be reprogrammed for normal operation and then bit 4 of the
modem control register must be reset to logical O.
Bits 5 through 7: These bits are permanently set to logical O.

Modem Status Register
This eight-bit register provides the current state of the control
lines from the modem (or peripheral device) to the processor. In
addition to this current-state information, four bits of the modem
status register provide change information. These bits are set to a
logical I whenever a control input from the modem changes state.
They are reset to logical 0 whenever the processor reads the
modem status register.
The content of the modem status register are indicated and

described below:
Hex Address 3FE

Bit 7 6 543 2
II I:
o
De", CI,,, '" Seod ,DCTSI
Delta Data Set Ready (DDSR)
Trailing Edge Ring
Indicator (TERI)
L -_ _ _ _~ Delta Rx Line Signal
Detect (DRLSD)
'-------~ Clear to Send (CTS)
'----------....,~ Data Set Ready (DSR)
' - - - - - - - - - - - Ring Indicator (RI)
' - - - - - - - - - - - - , . . Receive Line Signal
Detect (RLSD)
Modem Status Register (MSR)
Bit 0: This bit is the delta clear to send (DCTS) indicator. Bit 0
indicates that the CTS input to the chip has changed state since
the last time it was read by the processor.
Bit I: This bit is the delta data set ready (DDSR) indicator. Bit
I indicates that the DRS input to the chip has changed since the
last time it was read by the processor.
Bit 2: This bit is the trailing edge of ring indicator (TERI)

detector. Bit 2 indicates that the RI input to the chip has changed
from an on (logical I) to an off (logical 0) condition.

Bit 3: This bit is the delta received line signal detector
(DRLSD) indicator. Bit 3 indicates that the RLSD input to the
chip has changed state.
Note: Whenever bit 0, 1, 2, or 3 is set to a logical 1, a modem

status interrupt is generated.
Bit 4: This bit is the complement of the clear to send (CTS)

input. If bit 4 (LOOP) of the MCR is set to a logical 1, this is
equivalent to RTS in the MCR.
Bit 5: This bit is the complement of the data set ready (DSR)
input. If bit 4 of the MeR is set to a logical 1, this bit is
equivalent to DTR in the MeR.
Bit 6: This bit is the complement of the ring indicator (RI) input.
If bit 4 of the MeR is set to a logical 1, this bit is equivalent to
OUT 1 in the MeR.
Bit 7: This bit is the complement of the received line signal

detect (RLSD) input. If bit 4 of the MeR is set to a logical 1, this
bit is equivalent to OUT 2 of the MeR.
Receiver Buffer Register

The receiver buffer register contains the received character as
defined below:
Hex Address 3F8 DLAB = 0 Read Only

Bit 7 6 5 4 3 2 o
~
I ~ Data Bit 0
~ Data Bit 1
Data Bit 2
Data Bit 3
' - - - - - - - _ Data Bit 4
' - - - - - - - -__~ Data Bit 5
1--_ _ _ _ _ _ _ _..... Data Bit 6
'---------------l~ Data Bit 7
Receiver Buffer Register (R BR)
Bit °
is the least significant bit and is the first bit serially received.

Transmitter Holding Register
The transmitter holding register contains the character to be
serially transmitted and is defined below:
Hex Address 3F8 DLAB = 0 Write Only

Bit 7 654 3 2 o
~
I '-- Data Bit 0
~ Data Bitl
Data Bit 2
Data Bit 3
'----------1~ Data Bit 4
' - - - - - - - - -.... Data Bit 5
' - - - - - - - - - -....... Data Bit 6
' - - - - - - - - - - - -.... Data Bit 7
Transmitter Holding Register (THR)
Bit 0 is the least significant bit and is the first bit serially
transmitted.

Selecting the Interface Format and
Adapter Address
The voltage or current loop interface and adapter address are
selected by plugging the programmed shunt modules with the
locator dots up or down. See the figure below for the
configurations.
Module Position Module Position

for Primary Asynchronous for Alternate Asynchronous
Adapter Adapter
D
D
o
D
Asynchronous
Communications
A d a pte r u.J.J..LJ...L..L.U..!..J.jI-l.U..L.L.L..JL.J.J.J..LJ...L..L..L.f.J.J..L.J...U..J
Current Loop Voltage Interface

Interface Socket Dot Up
Dot Down

Rear Panel
25-Pin D-Shell
Connector
o
25
•
•
•
14
o
At standard RS-232C Levels
(with exception of current loops)
Description Pin
NC 1
Transmitted Data 2
Received Data 3
Request to Send 4
Clear to Send 5
Data Set Ready 6
Signal Ground 7
Received Line Signal Detector 8
+Transmit Current Loop Data 9
NC 10
-Transmit Current Loop Data 11
NC 12 Asynchr onous
External NC 13 Commu nications
Device Adapter
NC 14
(RS-232 C)
NC 15
NC 16
NC 17
+Receive Current Loop Data 18
NC 19
Data Terminal Ready 20
NC 21
Ring Indicator 22
NC 23
NC 24
-Receive Current Loop Return 25
Note: To avoid inducing voltage surges on interchange circuits. signals from

interchange circuits shall be used to drive inductive devices. such as
relay coils.
Binary Synchronous
Communications Adapter
The binary synchronous communication (BSC) adapter is a

4-inch high by 7 .5-inch wide card that provides an
RS232C-compatible communication interface for the IBM
Personal Computer. All system control, voltage, and data signals
are provided through a 2- by 31-position card-edge tab. External
interface is in the form of EIA drivers and receivers connected to
an RS232C, standard 25-pin, D-shell connector.
The adapter is programmed by communication software to

operate in binary synchronous mode. Maximum transmission rate
is 9600 bits per second (bps). The heart of the adapter is an
Intel 8251A Universal Synchronous/Asynchronous
Receiver/Transmitter (USART). An Intel 8255A-5
programmable peripheral interface (PPI) is also used for an
expanded modem interface, and an Intel 8253-5 programmable
interval timer provides time-outs and generates interrupts.
The following is a block diagram of the BSC adapter.
TIMER
EIA
Drivers/
8253 Receivers
- Data
System Comm unication
Bus Equip ment
'
I
I Data p:L 'i
:L:L
Bus I I
I I
I I
r
I I Control USART
I I
I I I
I I /, I
I I
I 8251A I I
I r- '------ I
I I I
I Address t Programmable I I
I
L....J Peripheral L....J
Interface
~
[;j r-----
~
V;
~'--
'/); 8255A5
Bse Adapter Block Diagram

BSC Adapter 1-251
8251A Universal Synchronous/Asynchronous

Receiver/Transmitter
The 8251A operational characteristics are programmed by the
system unit's software, and it can support virtually any form of
synchronous data technique currently in use. In the configuration
being described, the 8251A is used for IBM's binary synchronous
communications (BSC) protocol in half-duplex mode.
Operation of the 8251 A is started by programming the

communications format, then entering commands to tell the
8251A what operation is to be performed. In addition, the 8251A
can pass device status to the system unit by doing a Status Read
operation. The sequence of events to accomplish this are mode
instruction, command instruction, and status read. Mode
instruction must follow a master reset operation. Commands can
be issued in the data block at any time during operation of the
8251A.
A block diagram of the 8251A follows:
TxD
TxRDY
TxE
TxC
RxD
RxRDY
RxC
INTERNAL
SYNDET
DATA BUS
8251A Block Diagram
1-252 BSC Adapter

Data Bus Buffer
The system unit's data bus interfaces the 8251A through the data
bus buffer. Data is transferred or received by the buffer upon
execution of input or output instructions from the system unit.
Control words, command words, and status information are also
transferred through the data bus buffer.
ReadIWrite Control Logic

The read/write control logic controls the transfer of information
between the system unit and the 8251A. It consists of pins
designated as RESET, CLK, WR, RD, C/D, and CS.
RESET: The Reset pin is gated by Port B, bit 4 of the 8255,

and performs a master reset of the 8251A. The minimum reset
pulse width is 6 clock cycles. Clock-cycle duration is determined
by the oscillator speed of the processor.
CLK (Clock): The clock generates internal device timing. No

external inputs or outputs are referenced to CLK. The input is the
system board's bus clock of 4.77 MHz.
WR (Write): An input to WR informs the 8251A that the

system unit is writing data or control words to it. The input is the
WR signal from the system-unit bus.
RD (Read): An input to RD informs the 8251A that the

processing unit is reading data or status information from it. The
input is the RD signal from the system-unit bus.
C/D (Control/Data): An input on this pin, in conjunction with

the WR and RD inputs, informs the 8251A that the word on the
data bus is either a data character, a control word, or status
information. The input is the low-order address bit from the
system board's address bus.
CS (Chip Select): A low on the input selects the 8251A. No

reading or writing will occur unless the device is selected. An
input is decoded at the adapter from the address information on
the system-unit bus.
BSC Adapter 1-253

Modem Control
The 8251A has the following input and output control signals
which are used to interface the transmission equipment selected
by the user.
DSR (Data Set Ready): The DSR input port is a

general-purpose, I-bit, inverting input port. The 8251A can test
its condition with a Status Read operation.
CTS (Clear to Send): A low on this input enables the 825lA

to transfer serial data if the TxEnable bit in the command byte is
set to 1. If either a TxEnable off or CTS off condition occurs
while the transmitter is in operation, the transmitter will send all
the data in the USART that was written prior to the TxDisable
command, before shutting down.
DTR (Data Terminal Ready): The DTR output port is a

general-purpose, I-bit, inverting output port. It can be set low by
programming the appropriate bit in the command instruction
word.
RTS (Request to Send): The RTS output signal is a

general-purpose, I-bit, inverting output port. It can be set low by
programming the appropriate bit in the Command Instruction
word.
Transmitter Buffer
The transmitter buffer accepts parallel data from the data-bus
buffer, converts it to a serial bit stream, and inserts the
appropriate characters or bits for the BSC protocol. The output
from the transmit buffer is a composite serial stream of data on the
falling edge of Transmit Clock. The transmitter will begin
transferring data upon being enabled, if CTS = 0 (active). The
transmit data (TxD) line will be set in the marking state upon
receipt of a master reset, or when transmit enable/CTS is off and
the transmitter is empty (TxEmpty).
1-254 BSC Adapter

Transmitter Control
Transmitter control manages all activities associated with the
transfer of serial data. It accepts and issues the following signals,
both externally and internally, to accomplish this function:
TxRDY (Transmitter Ready): This output signals the system

unit that the transmitter is ready to accept a data character. The
TxRDY output pin is used as an interrupt to the system unit
(Level 4) and is masked by turning off Transmit Enable. TxRDY
is automatically reset by the leading edge of a WR input signal
when a data character is loaded from the system unit.
TxE (Transmitter Empty): This signal is used only as a status

register input.
TxC (Transmit Clock): The Transmit Clock controls the rate

at which the character is to be transmitted. In synchronous mode,
the bit-per-second rate is equal to the TxC frequency. The falling
edge of TxC shifts the serial data out of the 8251A.
Receiver Buffer
The receiver accepts serial data, converts it to parallel format,
checks for bits or characters that are unique to the communication
technique, and sends an "assembled" character to the system unit.
Serial data input is received on the RxD (Receive Data) pin, and
is clocked in on the rising edge of RxC (Receive Clock).
Receiver Control
This control manages all receiver-related activites. The
parity-toggle and parity-error flip-flop circuits are used for
parity-error detection, and set the corresponding status bit.
BSC Adapter 1-255

RxRDY (Receiver Ready): This output indicates that the
8251A has a character that is ready to be received by the system
unit. RxRDY is connected to the interrupt structure of the system
unit (Interrupt Level 3). With Receive Enable off, RxRDY is
masked and held in the reset mode. To set RxRDY, the receiver
must be enabled, and a character must finish assembly and be
transferred to the data output register. Failure to read the received
character from the RxData output register before the assembly of
the next RxData character will set an overrun-condition error, and
the previous character will be lost.
RxC (Receiver Clock): The receiver clock controls the rate at

which the character is to be received. The bit rate is equal to the
actual frequency of RxC.
SYNDET (Synchronization Detect): This pin is used for

synchronization detection and may be used as either input or
output, programmable through the control word. It is reset to
output-mode-low upon reset. When used as an output (internal
synchronization mode), the SYNDET pin will go to 1 to indicate
that the 8251A has found the synchronization character in the
receive mode. If the 8251A is programmed to use double
synchronization characters (bisynchronization as in this
application), the SYNDET pin will go to 1 in the middle of the
last bit of the second synchronization character. SYNDET is
automatically reset for a Status Read operation.
8255A-5 Programmable Peripheral Interface

The 8255A-5 is used on the BSC adapter to provide an expanded
modem interface and for internal gating and control functions. It
has three 8-bit ports, which are defined by the system during
initialization of the adapter. All levels are considered plus active
unless otherwise indicated. A detailed description of the ports is in
"Programming Considerations" in this section.
1-256 BSC Adapter

8253-5 Programmable Interval Timer
The 8253-5 is driven by a divided-by-two system-clock signal. Its
outputs are used as clocking signals and to generate inactivity
timeout interrupts. These level 4 interrupts occur when either of
the timers reaches its programmed terminal counts. The 8253-5
has the following outputs:
Timer 0: Not used for synchronous-mode operation.
Timer 1: Connected to port A, bit 7 of the 8255 and Interrupt

Level 4.
Timer 2: Connected to port A, bit 6 of the 8255 and Interrupt

Level 4.
Operation
The complete functional definition of the BSC adapter is
programmed by the system software. Initialization and control
words are sent out by the system to initialize the adapter and
program the communications format in which it operates. Once
programmed, the BSC Adapter is ready to perform its
communication functions.
Transmit
In synchronous transmission, the TxD output is continuously at a
mark level until the system sends its first character, which is a
synchronization character to the 8251A. When the CTS line goes
on, the first character is serially transmitted. All bits are shifted
out on the falling edge of TxC. When the 8251A is ready to
receive another character from the system for transmission, it
raises TxRDY, which causes a level-4 interrupt.
BSC Adapter 1-257

Once transmission has started, the data stream at the TxD output
must continue at the TxC rate. If the system does not provide the
8251A with a data character before the 8251A transmit buffers
become empty, the synchronization characters will be
automatically inserted in the TxD data stream. In this case, the
TxE bit in the status register is raised high to signal that the
8251A is empty and that synchronization characters are being
sent out. (Note that this TxE bit is in the status register, and is not
the TxE pin on the 8251A). TxE does not go low when SYNC is
being shifted out. The TxE status bit is internally reset by a data
character being written to the 8251A.
Receive
In synchronous reception, the 8251A will achieve character
synchronization, because the hardware design of the BSC adapter
is intended for internal synchronization. Therefore, the SYNDET
pin on the 8251A is not connected to the adapter circuits. For
internal synchronization, the Enter Hunt command should be
included in the first command instruction word written. Data on
the RxD pin is then sampled in on the rising edge of RxC. The
content of the RxD buffer is compared at every bit boundary with
the first SYNC character until a match occurs. Because the
8251A has been programmed for two synchronization characters
(bisynchronization), the next received character is also compared.
When both SYNC characters have been detected, the 8251A
ends the hunt mode and is in character synchronization. The
SYNDET bit in the status register (not the SYNDET pin) is then
set high, and is reset automatically by a Status Read.
Once synchronization has occurred, the 8251A begins to

assemble received data bytes. When a character is assembled and
ready to be transferred to memory from the 8251A, it raises
RxRDY, causing an interrupt level 3 to the system.
If the system has not fetched a previous character by the time

another received character is assembled (and an interrupt-level 3
issued by the adapter), the old character will be overwritten, and
the overrun error flag will be raised. All error flags can be reset by
an error reset operation.
1-258 BSC Adapter

Before starting data transmission or reception, the BSC adapter
is programmed by the system unit to define control and gating
ports, timer functions and counts, and the communication
environment in which it is to operate.
Typical Programming Sequence

The 8255A-5 programmable peripheral interface (PPI) is
initialized for the proper mode by selecting address hex 3A3 and
writing the control word. This defines port A as an input, port B
as an output for modem control and gating, and port C for 4-bit
input and 4-bit output. The bit descriptions for the 8255A-5 are
shown in the following figures. Using an output to port C, the
adapter is then set to wrap mode, disallow interrupts, and gate
external clocks (address=3A2H, data=ODH). The adapter is
now isolated from the communication interface, and initialization
continues.
Through bit 4 of 8255 Port B, the 8251A reset pin is brought

high, held, then dropped. This resets the internal registers of the
8251A.
BSC Adapter 1-259

8255 Port A Assignments Address: hex 3AO for BSC
Input Port hex 380 for Alternate BSC
Bit 7 6543210
IIII -
I_I~
L - - I ___L. ~ : Ei~::t~~~~:~~~~;{:s:~ E~~~~ertace
: 0 = Clear-to-Send is on from Interface
' - - - - - - - - - _ Oscillating = Receive Clock Active
1 = TxROY Active
' - - - - - - - - - - - - -__ 1 = Timer 2 Output Active
' - - - - - - - - - - - - - - - _ + _ 1 = Timer 1 Output Active
8255 Port B Assignments Address: hex 3A 1 for BSC

Output Port hex 381 for Alternate BSC
Bit 7 6 5 4 3 2 o
I I I ~ 0 ~ To," "" 0•• Si,",IA,OS,'oc,",
0= Turn on Select Standby
0= Turn on Test
1 = Not Used
' - -_ _ _ _ _ _ __ + _ 1 = Reset 8251 A
' - - - - - - - - - - - - . - 1 = Gate Timer 2

' - - - - - - - - - - - - -__ 1 = Gate Timer 1
' - - - - - - - - - - - - - - - - 1 = Gate Timers 1 and 2 to Interrupt Level 4
8255 Port C Assignments Address: hex 3A2 for BSC

hex 382 for Alternate BSC
1_:
Bit 7 6 4 3 2 1 0
I
I L-- 1 = Gate Internal Clock (Output Bit)
1 = Gate External Clock (Output Bit)
I
,-,- - - - _ - 1 = Electronic Wrap (Output Bit)
' - - - - - -__ 0 = Enable Timer 1 and 2, Interrupt 6 and
Receive Interrupt 3
' - - - - - - - - - _ _ + _ Oscillating = Receive Data (Input Bit)
'--_ _ _ _ _ _ _ _ _ _ Oscillating = Timer 0 Output (Input Bit)
' - - - - - - - - - - - - -__ 0 = Test Indicate Active (Input Bit)
' - - - - - - - - - - - - - - - _ _ . 0 = BSC Adapter
The 8253-5 programmable interval timer is used in the

synchronous mode to provide inactivity time-outs to interrupt the
system unit after a preselected period of time has elapsed from the
start of a communication operation. Counter a is not used for
synchronous operation. Counters 1 and 2 are connected to
interrupt-level 4, and are programmed to terminal-count values,
which will provide the desired time delay before a level-4 interrupt
is generated. These interrupts will indicate to the system software
that a predetermined period of time has elapsed without a TxRDY
(level 4) or RxRDY (level 3) interrupt being sent to the system
unit.
1-260 BSC Adapter
The modes for each counter are programmed by selecting each
timer-register address and writing the correct control word for
counter operation to the adapter. The mode for counters 1 and 2 is
set to O. The terminal-count values are loaded using control-word
bits D4 and D5 to select "load." The 8253-5 Control Word
format is shown in the following chart.
Control Word Format Address hex 3A7

D7 D6 D5 D4 D3 D2 D1 DO
I SC1 I sca I RL 1 I RLa I M2

I
M1 I Ma I BCDI
Definition of Control
SC - Select Counter:
SC1 SCO
a a Select Cou nter a
a 1 Select Counter 1
1 a Select Counter 2
1 1 Illegal
RL - Read/Load:
RL1 RLO
a a Cou nter Latch i ng operation
1 a Read/Load most significant byte only
a 1 Read/Load least significant byte only
1 1 Read/Load least significant byte first,

then most significant byte
M - Mode:
M2 M1 MO
I I I I I Terminal Count
a a a Mode a
Interrupt
BCD:
a Binary Counter 16-bits
1 Binary Coded Decimal (BCD) Counter

(4 Decades)
8253-5 Control Word Format
BSC Adapter 1-261

8251A Programming Procedures
After the support devices on the BSC adapter are programmed,
the 8251A is loaded with a set of control words that define the
communication environment. The control words are split into two
formats, mode instruction, and command instruction.
Both the mode and command instructions must conform to a

specified sequence for proper device operation. The mode
instruction must be inserted immediately after a reset operation,
before using the 8251A for data communications. The required
synchronization characters for the defined communications
technique are next loaded into the 8251A (usually hex 32 for
BSC). All control words written to the 8251A after the mode
instruction will load the command instruction. Command
instructions can be written to the 8251A at any time in the data
block during the operation of the 8251A. To return to the mode
instruction format, the master reset bit in the command instruction
word can be set to start an internal reset operation which
automatically places the 8251A back into the mode instruction
format. Command instructions must follow the mode instructions
or synchronization characters. The following diagram is a typical
data block, showing the mode instruction and command
instruction.
3A9 C/O = 1 Mode Instruction 1
3A9 C/O = 1 SYNC Character 1
3A9 C/O = 1 SYNC Character 2
3A9 cliS = 1 Command Instruction
J
3AB c/o = 0 Oata
3A9 C/O = 1 Command Instruction
3AB C/O = 0 " Oata
3A9 C/O = 1 Command Instruction
Typical Data Block
1-262 BSC Adapter

Mode Instruction Definition
The mode instruction defines the general operational
characteristics of the 8251A. It follows a reset operation (internal
or external). Once the mode instruction has been written to the
8251A by the system unit, synchronization characters or
command instructions may be written to the device. The following
figure shows the format for the mode instruction.
Mode Instruction Format Address: Hex 3A9 for BSe

Hex 389 for Alternate BSe
II
Bit 7 6 5 4 3 2 1 0
I ~ N",","dlAI~" 01
I
Not Used (Always 0)
Character Length Bit - - - - - - .,
Character Length Bit - - - - - 1 I
1I = ~"" '",bI, 5 Bits

0
Even Parity
1 = SYNDET is an Input 0 1 6 Bits
0= Double SYNC Character 1 0 7 Bits
1 1 8 Bits
Bit 0 Not used; always = 0
Bit 1 Not used; always = 0
Bit 2 These two bits are used together to define the character
and length. With 0 and 1 as inputs on bits 2 and 3,
Bit 3 character lengths of 5,6, 7, and 8 bits can be
established, as shown in the preceding figure.
Bit 4 In the synchronous mode, parity is enabled from this

bit. A 1 on this bit sets parity enable.
Bit 5 The parity generation/check is set from this bit. For

BSC, even parity is used by having bit 5 = 1.
Bit 6 External synchronization is set by this bit. A Ion this

bit establishes synchronization detection as an input.
Bit 7 This bit establishes the mode of character

synchronization. A 0 is set on this bit to give double
character synchronization.
BSC Adapter 1-263

Command-Instruction Format
The command-instruction format defines a status word that is
used to control the actual operation of the 8251A. Once the mode
instruction has been written to the 8251A, and SYNC characters
loaded, all further "Control Writes" to I/O address hex 3A9 or
hex 389 will load a command instruction.
Data is transferred by accessing two I/O ports on the 8251A,

ports 3A8 and 388. A byte of data can be read from port 3A8 and
can be written to port 388.
Address: Hex 3A9 for BSe

Bit 7 6 5 4 3 2 1 0
~
Transmit Enable
I I Data Terminal Ready

Receive Enable
I Send Break Character
I Error Reset
Request to Send
Internal Reset
Enter Hunt Mode
Command Instruction Format
Bit 0 The Transmit Enable bit sets the function of the 8251A
to either enabled (1) or disabled (0).
Bit 1 The Data Terminal Ready bit, when set to 1 will force
the data terminal output to O. This is a one-bit inverting
output port.
Bit 2 The Receive Enable bit sets the function to either

enable the bit (1), or to disable the bit (0).
Bit 3 The Send Break Character bit is set to 0 for normal

BSC operation.
Bit 4 The Error Reset bit is set to 1 to reset error flags from
the command instruction.
Bit 5 A 1 on the Request to Send bit will set the output to O.

This is a one-bit inverting output port.
1-264 BSC Adapter
Bit 6 The Internal Reset bit when set to 1 returns the 8251A
to mode-instruction format.
Bit 7 The Enter Hunt bit is set to 1 for BSC to enable a

search for synchronization characters.
Status Read Definition

In telecommunication systems, the status of the active device must
often be checked to determine if errors or other conditions have
occurred that require the processor's attention. The 8251A has a
status read facility that allows the system software to read the
status of the device at anytime during the functional operation. A
normal read command is issued by the processor with I/O address
hex 3A9 for BSC, and hex 389 for Alternate BSC to perform a
status read operation.
The format for a status read word is shown in the figure below.
Some of the bits in the status read format have the same meanings
as external output pins so the 8251A can be used in a completely
polled environment or in an interrupt-driven environment.
Address: Hex 3A9 for sse

Bits 0 ~ TxR DY (See Note Below)

1 • RxRDY
2 ~ TxEmpty
3 _ Parity Error (PE Flag On when a Parity Error Occurs)
4 ~ Overrun Error (OE Flag On when Overrun Error Occurs)
5 ~ Framing Error (Not Used for Synchronous Communications)
6 ~ SYNDET
7 ~ Data Set Ready (Indicates that DSR is at 0 Level)
Note: TxRDY status bit does not have the same meaning as the 8251A
TxR DY output pin. The former is not conditioned by CTS and TxEnable.
The latter is conditioned by both CTS and TxEnable.
Status Read Format
Bit 0 See the Note in the preceding chart.
Bit 1 An output on this bit means a character is ready to be

received by the computers 8088 microprocessor.
BSC Adapter 1-265

Bit 2 A 1 on this bit indicates the 8251A has no characters to
transmit.
Bit 3 The Parity Error bit sets a flag when errors are
detected. It is reset by the error reset in the command
instruction.
Bit 4 This bit sets a flag when the computers 8088

microprocessor does not read a character before another
one is presented. The 8251A operation is not inhibited
by this flag, but the overrun character will be lost.
Bit 5 Not used
Bit 6 SYNDET goes to 1 when the synchronization character

is found in receive mode. For BSC, SYNDET goes
high in the middle of the last bit of the second
synchronization character.
Bit 7 The Data Set Ready bit is a one bit inverting input. It
is used to check modem conditions, such as data-set
ready.
Interface Signal Information

The BSC adapter conforms to interface signal levels standardized
by the Electronics Industry Association (EIA) RS232C Standard.
These levels are shown in the following figure.
Additional lines, not standardized by the EIA, are pins 11, 18,
and 25 on the interface connector. These lines are designated as
Select Standby, Test, and Test Indicate. Select Standby is used to
support the switched network backup facility of a modem that
provides this option. Test and Test Indicate support a modem
wrap function on modems that are designated for
business-machine, controlled-modem wraps.
1-266 BSC Adapter

Driver EIA RS232C/CCITT V24-V28 Signal Levels
+15 Vdc - - - - - - - - - - - - - ,
Active/Data =0
+5 Vdc
+5 Vdc
Invalid Level
-5 Vdc
-5 Vdc
Inactive/Data = 1
-15Vdc
Receiver EIA RS232C/CCITT V24-V28 Signal Levels
+25Vdc .--------------------,
Active/Data =0
+3 Vdc
+3 Vdc
I nval id Level
-3 Vdc
-3 Vdc
Inactive/Data = 1
-25 Vdc
Interface Voltage Levels
BSC Adapter 1-267

Interrupt Information
Interrupt Level 4: Transmitter Ready
Counter 1
Counter 2
Interrupt Level 3: Receiver Ready
Hex Address
Device Register Name Function
Primary Alternate
3AO 380 8255 Port A Data I nternal/External Sensing

3A1 381 8255 Port B Data External Modem Interface
3A2 382 8255 Port C Data I nternal Control
3A3 383 8255 Mode Set 8255 Mode Initialization
3A4 384 8253 Counter 0 LSB Not Used in Synch Mode
3A4 384 8253 Counter 0 MSB Not Used in Synch Mode
3A5 385 8253 Counter 1 LSB I nactivity Time-Outs
3A5 385 8253 Counter 1 MSB I nactivity Time-Outs
3A6 386 8253 Counter 2 LSB I nactivity Time-Outs
3A6 386 8253 Counter 2 MSB I nactivity Time-Outs
3A7 387 8253 Mode Register 8253 Mode Set
3A8 388 8251 Data Select Data
3A9 389 8251 Command/Status Mode/Command
USART Status
Device Address Summary
1-268 BSC Adapter

25-Pin D-Shell
Connector
• 25
• •
C'J •
•
•
•
•
C'J eC'J •
•
•
• •
C'~C'J
• •
•
J •
•
•
• 14
Signal Name - Description Pin

No Connection 1
Transmitted Data 2
Received Data 3
Request to Send 4
Clear to Send 5
Data Set Ready 6
Signal Ground 7
No Connection 9
No Connection 10 Binary
External Select Standby* 11 Synchron ous
Device No Connection 12 Communi cations
No Connection· 13 Adapter
No Connection 14
Transmitter Signal Element Timing 15
No Connection 16
Receiver Signal Element Timing 17
Test (IBM Modems Only)- 18
No Connection 19
No Connection 21
Ring Indicator 22
Data Signal Rate Selector 23
No Connection 24
Test Indicate (IBM Modems Only)- 25
-Not standardized by EIA (Electronics Industry Association).
BSC Adapter 1-269

Notes:
1·270 BSC Adapter

IBM Synchronous Data Link Control
(SDLC) Communications Adapter
The SDLC communications adapter system control, voltage, and

data signals are provided through a 2 by 31 position card edge
tab. Modem interface is in the form of EIA drivers and receivers
connecting to an RS232C standard 25-pin, D-shell, male
connector.
The adapter is programmed by communications software to
operate in a half-duplex synchronous mode. Maximum
transmission rate is 9600 bits per second, as generated by the
attached modem or other data communication equipment.
The SDLC adapter utilizes an Intel 8273 SDLC protocol

controller and an Intel 8255A-5 programmable peripheral
interface for an expanded external modem interface. An Intel
8253 programmable interval timer is also provided to generate
timing and interrupt signals. Internal test loop capability is
provided for diagnostic purposes.
The figure below is a block diagram of the SDLC communications

adapter.
Data ~--::,...---~ 8255A·5

Bus
Buffer
System EIA
Bus Drivers DCE
Receivers
Address
Address Decode
Modem
logic Status
L - -_ _ _~ Controller Change
logic
SDLC Communications Adapter Block Diagram

SDLC Adapter 1-271
The 8273 SDLC protocol control module has the following key
features:
• Automatic frame check sequence generation and checking.
• Automatic zero bit insertion and deletion.
• TTL compatibility.
• Dual internal processor architecture, allowing frame level

command structure and control of data channel with minimal
system processor intervention.
The 8273 SDLC protocol controller operations, whether

transmission, reception, or port read, are each comprised of three
phases:
Command Commands and/or parameters for the required

operation are issued by the processor.
Execution Executes the command, manages the data link, and

may transfer data to or from memory utilizing direct
memory access (DMA), thus freezing the processor
except for minimal interruptions.
Result Returns the outcome of the command by returning

interrupt results.
Support of the controller operational phases is through internal

registers and control blocks of the 8273 controller.
1-272 SDLC Adapter

8273 Protocol Controller Structure
The 8273 module consists of two major interfaces: the processor
interface and the modem interface. A block diagram of the 8273
protocol controller module follows.
Registers
Txl/R Command
Rxl/R Parameter
Reset Status
Result
Data
Bus
Buffer
TxD
TxC
TxDRQ
TxDACK
i5PLL
32 x CLK
RxDRQ
RTS
RxDACK
PB 1 _4
TxlNT
CTS
RxlNT
CD
RD Read
Write
WR
DMA
Ao Control
Logic
A1
RESET RxD
RxC
CS---...J
CLK--------' L..-_ _+_ FLAG DET
Internal Data Bus--
Processor Interface Modem Interface
8273 SDLC Protocol Control Block Diagram
SDLC Adapter 1-273

Processor Interface
The processor interface consists of four major blocks: the
control/read/write logic (C/R/W), internal registers, data transfer
logic, and data bus buffers.
Control/Read/Write Logic
The control/read/write logic is used by the processor to issue

commands to the 8273. Once the 8273 receives and executes a
command, it returns the results using the C/R/W logic. The logic
is supported by seven registers which are addressed by AO, A I,
RD, and WR, in addition to cs. AO and Al are the two
low-order bits of the adapter address-byte. RD and WR are the
processor read and write signals present on the system control
bus. CS is the chip select, also decoded by the adapter address
logic. The table below shows the address of each register using the
C/R/W logic.
Address Inputs Control Inputs Register

AO A1 CS WR RD
0 0 0 0 1 Command
0 0 0 1 0 Status
0 1 0 0 1 Parameter
0 1 0 1 0 Result
1 0 0 0 1 Reset
1 0 0 1 0 Txl/R
1 1 0 0 1 None
1 1 0 1 0 Rxl/R
8273 SOLC Protocol Controller Register Selection
1-274 SDLC Adapter

8273 Control/ReadlWrite Registers
Command Operations are initialized by writing the
appropriate command byte into this register.
Status This register provides the general status of

the 8273. The status register supplies the
processor/adapter handshaking necessary
during various phases of the 8273 operation.
Parameter Additional information that is required to

process the command is written into this
register. Some commands require more than
one parameter.
Immediate Result Commands that execute immediately

(Result) produce a result byte in this register, to be
read by the processor.
Transmit Interrupt Results of transmit operations are passed to

Results (TxIIR) the processor from this register. This result
generates an interrupt to the processor when
the result becomes available.
Receiver Interrupt Results of receive operations are passed to

Results (Rx/l/R) the processor from this register. This result
generates an interrupt to the processor when
the result becomes available.
Reset This register provides a software reset

function for the 8273.
The other elements of the C/R/W logic are the interrupt lines
(RxINT and TxINT). Interrupt priorities are listed in the
"Interrupt Information" table in this section. These lines signal
the processor that either the transmitter or the receiver requires
service (results should be read from the appropriate register), or a
data transfer is required. The status of each interrupt line is also
reflected by a bit in the status register, so non-interrupt driven
operation is also possible by the communication software
examining these bits periodically.
SDLC Adapter 1-275

Data Interfaces
The 8273 supports two independent data interfaces through the
data transfer logic: received data and transmitted data. These
interfaces are programmable for either DMA or non-DMA data
transfers. Speeds below 9600 bits-per-second mayor may not
require DMA, depending on the task load and interrupt response
time of the processor. The processor DMA controller is used for
management of DMA data transfer timing and addressing. The
8273 handles the transfer requests and actual counts of data-block
lengths. DMA level 1 is used to transmit and receive data
transfers. Dual DMA support is not provided.
Elements of Data Transfer Interface

TxDRQIRxDRQ This line requests a DMA to or from
memory and is asserted by the 8273.
TxDACKIRxDACK This line notifies the 8273 that a request

has been granted and provides access to
data regions. This line is returned by the
DMA controller (DACKI on the system
unit control bus is connected to
TxDACK/RxDACK on the 8273).
RD (Read) This line indicates data is to be read from

the 8273 and placed in memory. It is
controlled by the processor DMA
controller.
WR (Write) This line indicates if data is to be written to

the 8273 from memory and is controlled
by the processor DMA controller.
To request a DMA transfer, the 8273 raises the DMA request

line. Once the DMA controller obtains control ofthe system bus,
it notifies the 8273 that the DRQ is granted by returning DACK,
and WR or RD, for a transmit or receive operation, respectively.
The DACK and WR or RD signals transfer data between the
8273 and memory, independent of the 8273 chip-select pin (CS).
This "hard select" of data into the transmitter or out of the
receiver alleviates the need for the normal transmit and receive
data registers, addressed bya combination of address lines, CS,
and WRorRD.
1-276 SDLC Adapter
Modem Interface
The modem interface of the 8273 consists of two major blocks:
the modem control block and the serial data timing block.
Modem Control Block

The modem control block provides both dedicated and
user-defined modem control function. EIA inverting drivers and
receivers are used to convert TTL levels to EIA levels.
Port A is a modem control input port. Bits PAD and PAl have
dedicated functions.
8273 Port A (Modem Control Input Port)

Bit PA 7 6 5 4 321 0
II~
PAO Clear to Send
PA 1 Carrier Detect
PA2 Data Set Ready
PA3 CTS Change
PA4 DSR Change
Not Used
Bit PAD This bit reflects the logical state of the clear to
send (CTS) pin. The 8273 waits until CTS is
active before it starts transmitting a frame. If
CTS goes inactive while transmitting, the frame
is aborted and the processor is interrupted. A
CTS failure will be indicated in the appropriate
interrupt-result register.
Bit PAl This bit reflects the logical state of the carrier
detect pin (CD). CD must be active in
sufficient time for reception of a frame's
address field. If CD is lost (goes inactive) while
receiving a frame, an interrupt is generated with
a CD failure result.
Bit PA2 This bit is a sense bit for data set ready (DSR).
Bit PA3 This bit is a sense bit to detect a change in

CTS.
SDLC Adapter 1-277
Bit PA4 This bit is a sense bit to detect a change in data
set ready.
Bits PAS to P A 7 These bits are not used and each is read as a 1
for a read port A command.
Port B is a modem control output port. Bits PBO and PBS are
dedicated function pins.
8273 Port B (Modem Control Output Port)

Bit PB 7 6 5 4 3 2 1 0
1- ~
II I~ PBO Re,,"" '" Seod
PB 1 - Reserved
PB2 - Data Terminal Ready
PB3 - Reserved
' - - - - - - - _ PB4 - Reserved
'--------~ PB5 - Flag Detect
'-----------~ PB6 - Not Used
' - - - - - - - - - - - - - - . . PB7 - Not Used
Bit PBO This bit represents the logical state of request to send
(RTS). This function is handled automatically by the
8273.
Bit PB 1 Reserved.
Bit PB2 Used for data terminal ready.
Bit PB3 Reserved.
Bit PB4 Reserved.
Bit PBS This bit reflects the state of the flag detect pin. This pin
is activated whenever an active receiver sees a flag
character.
Bit PB6 Not used.
Bit PB7 Not used.
1-278 SDLC Adapter

Serial Data Timing Block
The serial data timing block is comprised of two sections: the
serial data logic and the digital phase locked loop (DPLL).
Elements of the serial data logic section are the data pins TxD
(transmitted data output) and RxD (received data input), and the
respective clocks. The leading edge of TxC generates new
transmitted data and the trailing edge of RxC is used to capture
the received data. The figure below shows the timing for these
signals.
TxC
TxD
RxC
RxD
8273 SOLC Protocol Controller Transmit/Receive Timing
The digital phase locked loop provided on the 8273 controller

module is utilized to capture looped data in proper
synchronization during wrap operations performed by diagnostics.
SDLC Adapter 1-279

8255A-5 Programmable Peripheral
Interface
The 8255A-5 contains three 8-bit ports. Descriptions of each bit
of these ports are as follows:
8255A-5 Port A Assignments* Hex Address 380
Bit 7 6 5 4 3 2 1 0
~
0= Ring Indicator is on from Interface
0= Data Carrier Detect is on from Interface
Oscillating = Transmit Clock Active
0= Clear to Send is on from Interface
Oscillating = Receive Clock Active
1 = Modem Status Changed
1 = Timer 2 Output Active
1 = Timer 1 Output Active
*Port A is defined as an input port
8255A-5 Port B Assignments* Hex Address 381
Bit 7 6 5 4 3 2 1 0
II ~ ~ 0 Tom 00 0". Sigo.IR", S,I,ct"

Modem Interface
0= Turn On Select Standby at Modem
Interface
0= Turn On Test
1 = Reset Modem Status Changed Logic
1 = Reset 8273
1 = Gate Timer 2
1 = Gate Timer 1
1 = Enable Level 4 Interrupt
*Port B is defined as an output port
1-280 SDLC Adapter

8255A-5 Port C Assignments' Hex Address 382
Bit 7 6 5 4 3 2 1 0
III ~ ~ 1 G." 100em" Clook ,0",,", .,,'

1 = Gate External Clock (Output Bit)
1 = Electronic Wrap (Output Bit)
0= Gate Interrupts 3 and 4 (Output Bit)
Oscillating = Receive Data (Input Bit)
Oscillating = Timer 0 Output (Input bit)
0= Test Indicate Active (Input Bit)
Not Used
'Port C is defined for internal control and gating functions. It has three input
and four output bits. The four output bits are defined during initialization, but
only three are used.
8253-5 Programmable Interval Timer

The 8253-5 is driven by a processor clock signal divided by two_
It has the following output:
Timer 0 Programmed to generate a square wave signal, used as

an input to timer 2. Also connected to 8253 port C,
bit 5.
Timer 1 Connected to 8255 port A, bit 7, and interrupt level 4.
Timer 2 Connected to 8255 port A, bit 6, and interrupt level 4.
The software aspects ofthe 8273 involve the communication of
both commands from the processor to the 8273 and the return of
results of those commands from the 8273 to the processor. Due to
the internal processor architecture of the 8273, this system
unit/8273 communication is basically a form of interprocessor
communication, and must be considered when programming for
the SDLC communications adapter.
SDLC Adapter 1-281

The protocol for this interprocessor communication is
implemented through use of handshaking supplied in the 8273
status register. The bit defintions of this register are shown below.
8273 Status Register Format Hex Address 388
Bit 7 6 5 4 3 2 1 0
III~~ T.IRA 1 = TdNT R""''',,iI,bI,

RxlRA 1 = RxlNT Result Available
TxlNT 1 = Tx Interrupt
RxlNT 1 = Rx Interrupt
L -_ _ _ _ _ CRBF 1 = Command Result Buffer Full
' - - - - - - - - CPBF 1 = Command Parameter Buffer Full
' - - - - - - - - - CBF 1 = Command Buffer Full
' - - - - - - - - - CBSY 1 = Command Busy
Bit 0 This bit is the transmitter interrupt result available

(TxlRA) bit. This bit is set when the 8273 places an
interrupt-result byte in the TxI/R register, and reset
when the processor reads the TxI/R register.
Bit 1 This bit is the receiver interrupt result available

(RxlRA) bit. It is the corresponding result-available bit
for the receiver. It is set when the 8273 places an
interrupt-result byte in the Rxl/R register and reset
when the processor reads the register.
Bit 2 This bit is the transmitter interrupt (TxINT) bit and

reflects the state of the TxINT pin. TxINT is set by the
8273 whenever the transmitter needs servicing, and
reset when the processor reads the result or performs
the data transfer.
Bit 3 This bit is the receiver interrupt (RxINT) bit and is

identical to the TxINT, except action is initiated based
on receiver interrupt-sources.
Bit 4 This bit is the command result buffer full (CRBF) bit.
It is set when the 8273 places a result from an
immediate-type command in the result register, and
reset when the processor reads the result or performs
the data transfer.
1-282 SDLC Adapter

Bit 5 This bit is the command parameter buffer full (CPBF)
bit and indicates that the parameter register contains a
parameter. It is set when the processor deposits a
parameter in the parameter register, and reset when the
8273 accepts the parameter.
Bit 6 This bit is the command buffer full (CBF) bit and, when
set, it indicates that a byte is present in the command
register. This bit is normally not used.
Bit 7 This bit is the command busy (CBSY) bit and indicates
when the 8273 is in the command phase. It is set when
the processor writes a command into the command
register, starting the command phase. It is reset when
the last parameter is deposited in the parameter register
and accepted by the 8273, completing the command
phase.
Initializing the Adapter (Typical Sequence)

Before initialization of the 8273 protocol controller, the support
devices on the card must be initialized to the proper modes of
operation.
Configuration of the 825 5A -5 programmable peripheral interface

is accomplished by selecting the mode-set address for the 8255
(see the "SDLC Communications Adapter Device Addresses"
table later in this section) and writing the appropriate control word
to the device (hex 98) to set ports A, B, and C to the modes
described previously in this section.
Next, a bit pattern is output to port C which disallows interrupts,

sets wrap mode on, and gates the external clock pins (address =
hex 382, data = hex OD). The adapter is now isolated from the
communications interface.
Using bit 4 of port B, the 8273 reset line is brought high, held and
then dropped. This resets the internal registers of the 8273.
SDLC Adapter 1-283

The 8253-5's counter 1 and 2 tenninal-count values are now set
to values which will provide the desired time delay before a level
4 interrupt is generated. These interrupts may be used to indicate
to the communication software that a pre-detennined period of
time has elapsed without a result interrupt (interrupt level 3).
The tenninal count-values for these counters are set for any time
delay which the programmer requires. Counter 0 is also set at this
time to mode 3 (generates square wave signal, used to drive
counter 2 input).
To setup the counter modes, the address for the 8253 counter
mode register is selected (see the "SDLC Communications
Adapter Device Addresses" table, later in this section), and the
control word for each individual counter is written to the device
separately. The control-word fonnat and bit definitions for the
8253 are shown below. Note that the two most-significant bits of
the control word select each individual counter, and each counter
mode is defined separately.
Once the support devices have been initialized to the proper

modes and the 8273 has been reset, the 8273 protocol controller
is ready to be configured for the operating mode that defines the
communications environment in which it will be used.
1-284 SDLC Adapter

Control Word Format
D,
I SCl sca RL 1 RLa M2 Ml Ma BCD
Definitions of Control
SC - Select Counter:
SCl sca
a a Select Counter a
a 1 Select Counter 1
1 a Select Counter 2
1 1 Illegal
RL - Read/Load:
RL 1 RLO
a a Counter Latching operation
1 a Read/Load most significant byte (MSB)
a 1 Read/Load least significant byte (LSB)
1 1 Read/Load least significant byte first,
then most significant byte.
M - Mode:
M2 Ml Ma Mode
a a a Modea
a a 1 Mode 1
X 1 a Mode 2
X 1 1 Mode 3
1 a a Mode 4
1 a 1 Mode 5
BCD:
Binary Counter l6-bits
Binary Coded Decimal (BCD) Counter (4 Decades)
8253·5 Programmable Interval Timer Control Word
SDLC Adapter 1-285

Initialization/Configuration Commands
The initialization/configuration commands manipulate internal
registers of the 8273, which define operating modes. After chip
reset, the 8273 defaults to alII's in the mode registers. The
initialization/configuration commands either set or reset specified
bits in the registers depending on the type of command. One
parameter is required with the commands. The parameter is
actually the bit pattern (mask) used by the set or reset command
to manipulate the register bits.
Set commands perform a logical OR operation of the parameter

(mask) of the internal register. This mask contains l's where
register bits are to be set. Zero (O's) in the mask cause no change
to the corresponding register bit.
Reset commands perform a logical AND operation of the

parameter (mask) and internal register. The mask 0 is reset to
register bit, and 1 to cause no change.
The following are descriptions of each bit of the operating, serial

I/O, one-bit delay, and data transfer mode registers.
Operating Mode Register
8273 Operating Mode Register Format

Bit 7 6 5 4 3 2 1 0
~
I L 1 = Flag Stream Mode
~1 = Two Preframe Sync Characters
1 = Buffered Mode
1 = Enable Early Tx Interrupt
'-----~ 1 = EOP Interrupt Enable
'------~ 1 = HDLC Abort Enable
' - - - - - - - Not Used
'---------~ Not Used
1-286 SDLC Adapter

Bit 0 If bit 0 is set to aI, flags are sent immediately if the
transmitter was idle when the bit was set. If a transmit
or transmit-transparent command was active, flags are
sent immediately after transmit completion. This mode
is ignored if loop transmit is active or the one-bit-delay
mode register is set for one-bit delay. If bit 0 is reset (to
0), the transmitter sends idles on the next character
boundary if idle or, after transmission is complete, if the
transmitter was active at bit-O reset time.
Bit 1 If bit 1 is set to aI, the 8273 sends two characters

before the first flag of a frame. These characters are hex
00 ifNRZI is set or hex 55 ifNRZI is not set. (See
"Serial I/O Mode Register," for NRZI encoding mode
format.)
Bit 2 If bit 2 is set to a 1, the 8273 buffers the first two bytes
of a received frame (the bytes are not passed to
memory). Resetting this bit (to 0) causes these bytes to
be passed to and from memory.
Bit 3 This bit indicates to the 8273 when to generate an

end-of-frame interrupt. If bit 3 is set, an early interrupt
is generated when the last data character has been
passed to the 8273. If the processor responds to the
early interrupt with another transmit command before
the final flag is sent, the final-flag interrupt will not be
generated and a new frame will begin when the current
frame is complete. Thus, frames may be sent separated
by a single flag. A reset condition causes an interrupt to
be generated only following a final flag.
Bit 4 This is the EOP-interrupt-mode function and is not used

on the SDLC communications adapter. This bit should
always be in the reset condition.
Bit 5 This bit is always reset for SDLC operation, which

causes the 8273 protocol controller to recognize eight
ones (0 1 1 1 1 1 1 1 1) as an abort character.
SDLC Adapter 1-287

Serial I/O Mode Register
8273 Serial 1/0 Mode Register Format

Bit 7 6 5 4 3 2 1 0
~
I L 1 = NRZI Mode
~ 1 = Clock Loopback
1 = Data Loopback
Not Used
'-----~ Not Used
' - - - - - -.... Not Used
' - - - - - - - _ Not Used
' - - - - - - - -.... Not Used
Bit 0 Set to 1, this bit specifies NRZI encoding and decoding.

Resetting this bit specifies that transmit and receive
data be treated as a normal positive-logic bit stream.
Bit 1 When bit 1 is set to 1, the transmit clock is internally

routed to the receive-clock circuitry. It is normally used
with the loopback bit (bit 2). The reset condition causes
the transmit and receive clocks to be routed to their
respective 8273 I/O pins.
Bit 2 When bit 2 is set, the transmitted data is internally

routed to the received data circuitry. The reset
condition causes the transmitted and received data to be
routed to their respective 8273 I/O pins.
Data Transfer Mode Register
8273 Data Transfer Mode Register Format

Bit 7 6 5 4 3 2 1 0
I I I II I IL
L--L--L.---1-.-1--1--1-----;.~
1 = Interrupt Data Transfers
Not Used
1-288 SDLC Adapter

When the data transfer mode register is set, the 8273 protocol
controller will interrupt when data bytes are required for
transmission, or are available from a reception. If a transmit or
receive interrupt occurs and the status register indicates that there
is no transmit or receive interrupt result, the interrupt is a transmit
or receive data request, respectively. Reset of this register causes
DMA requests to be performed with no interrupts to the
processor.
One-Bit Delay Mode Register
8273 One-Bit Delay Mode Register Format

Bit 7 6 5 4 3 2 1 0
I I I I I I
L---------I_~
I: Not Used
1 = One-Bit Delay Enable
When one-bit delay is set, the 8273 retransmits the received data
stream one-bit delayed. Reset of this bit stops the one-bit delay
mode.
The table below is a summary of all set and reset commands

associated with the 8273 mode registers. The set or reset mask
used to define individual bits is treated as a single parameter. No
result or interrupt is generated by the 8273 after execution of
these commands.
Hex
Register Command Code Parameter
One-Bit Delay Mode Set A4 Set Mask
Reset 64 Reset Mask
Data Transfer Mode Set 97 Set Mask
Reset 57 Reset Mask
Operating Mode Set 91 Set Mask
Reset 51 Reset Mask
Serial 1/0 Mode Set AO Set Mask
Reset 60 Reset Mask
8273 SDLC Protocol Controller Mode Register Commands
SDLC Adapter 1-289

Command Phase
Although the 8273 is a full duplex device, there is only one
command register. Thus, the command register must be used for
only one command sequence at a time and the transmitter and
receiver may never be simultaneously in a command phase.
The system software starts the command phase by selecting the

8273 command register address and writing a command byte into
the register. The following table lists command and parameter
information for the 8273 protocol controller. If further information
is required by the 8273 prior to execution of the command, the
system software must write this information into the parameter
register.
1-290 SDLC Adapter

Command Result Completion
Command Description (Hex) Parameter Results Port Interrupt
Set One-Bit Delay A4 Set Mask None - No
Reset One-Bit Delay 64 Reset Mask None - No
Set Data Transfer 97 Set Mask None - No
Mode
Reset Data Transfer 57 Reset Mask None - No
Mode
Set Operating Mode 91 Set Mask None - No
Reset Operating Mode 51 Reset Mask None - No
Set Serial 110 Mode AO Set Mask None - No
Reset Serial 1/0 Mode 60 Reset Mask None - No
General Receive CO 80,81 RIC,RO,R1, RXI/R Yes
A,C
Selective Receive C1 80,81,A1, RIC,RO,R1, RXI/R Yes
A2 A,C
Receive Disable C5 None None - No
Transmit Frame C8 LO,L1,A,C TIC TXI/R Yes
Transmit Transparent C9 LO,L1 TIC TXI/R Yes
Abort Transmit Frame CC None TIC TXI/R Yes
Abort Transmit CD None TIC TXI/R Yes
Transparent
Read Port A 22 None Port Value Result No
Read Port B 23 None Port Value Result No
Set Port B Bit A3 Set Mask None - No
Reset Port B Bit 63 Reset Mask None - No
8273 Command Summary Key

80 - Least significant byte of the receiver buffer length.
81 - Most significant byte of the receiver buffer length.
LO - Least sig nificant byte of the Tx frame length.
11 - Most significant byte of the Tx frame length.
Al - Receive frame address match field one.
A2 - Receive frame address match field two.
A - Address field of received frame. If non-buffered mode is specified, this
result is not provided.
C - Control field of received frame. If non-buffered mode is specified, this
result is not provided.
RXI/R - Receive interrupt result register.
TXI/R - Transmit interrupt result register.
RO - Least significant byte of the length of the frame received.
Rl - Most significant byte of the length of the frame received.
RIC - Receiver interrupt result code.
TIC - Transmitter interrupt result code.
8273 SDLC Protocol Controller Commands

SDLC Adapter 1-291
A flowchart of the command phase is shown below. Handshaking
of the command and parameter bytes is accomplished by the
CBSY and CPBF bits of the status register. A command may not
be written if the 8273 is busy (CBSY = 1). The original command
will be overwritten if a second command is issued while
CBSY = 1. The flowchart also indicates a parameter buffer full
check. The processor must wait until CPBF = 0 before writing a
parameter to the parameter register. Previous parameters are
overwritten and lost if a parameter is written while CPBF = 1.
No
End of Command Phase
8273 SOLC Protocol Controller Command Phase Flowchart
1-292 SDLC Adapter

Execution Phase
During the execution phase, the operation specified by the
command phase is performed. If DMA is utilized for data
transfers, no processor involvement is required.
For interrupt-driven transfers the 8273 raises the appropriate INT

pin (TxINT or RxINT). When the processor responds to the
interrupt, it must determine the cause by examining the status
register and the associated IRA (interrupt result available) bit of
the status register. If IRA = 0, the interrupt is a data transfer
request. If IRA = 1, an operation is complete and the associated
interrupt result register must be read to determine completion
status.
Result Phase
During the result phase, the 8273 notifies the processor of the
outcome of a command execution. This phase is initiated by
either a successful completion or error detection during execution.
Some commands such as reading or writing the I/O ports provide

immediate results. These results are made available to the
processor in the 8273 result register. Presence of a valid
immediate result is indicated by the CRBF (command result
buffer full) bit of the status register.
Non-immediate results deal with the transmitter and receiver.

These results are provided in the TxIIR (transmit interrupt result)
or RxIIR (receiver interrupt result) registers, respectively. The
8273 notifies the processor that a result is available with the
TxIRA and RxIRA bits of the status register. Results consist of
one-byte result interrupt code indicating the condition for the
interrupt and, if required, one or more bytes supplying additional
information. The "Result Code Summary" table later in this
section provides information on the format and decode of the
transmitter and receiver results.
The following are typical frame transmit and receive sequences.

These examples assume DMA is utilized for data transfer
operations.
SDLC Adapter 1-293

Transmit
Before a frame can be transmitted, the DMA controller is
supplied, by the communication software, the starting address for
the desired information field. The 8273 is then commanded to
transmit a frame (by issuing a transmit frame command).
After a command, but before transmission begins, the 8273 needs

some more information (parameters). Four parameters are
required for the transmit frame command; the frame address field
byte, the frame control field byte, and two bytes which are the
least significant and most significant bytes of the information field
byte length. Once all four parameters are loaded, the 8273 makes
RTS (request to send) active and waits for CTS (clear to send) to
go active from the modem interface. Once CTS is active, the 8273
starts the frame transmission. While the 8273 is transmitting the
opening flag, address field, and control field, it starts making
transmitter DMA requests. These requests continue at character
(byte) boundaries until the pre-loaded number of bytes of
information field have been transmitted. At this point, the requests
stop, the FCS (frame check sequence) and closing flag are
transmitted, and the TxINT line is raised, signaling the processor
the frame transmission is complete and the result should be read.
Note that after the initial command and parameter loading, no
processor intervention was required (since DMA is used for data
transfers) until the entire frame was transmitted.
General Receive
Receiver operation is very similar. Like the initial transmit
sequence, the processor's DMA controller is loaded with a
starting address for a receive data buffer and the 8273 is
commanded to receive. Unlike the transmitter, there are two
different receive commands; a general receive, where all received
frames are transferred to memory, and selective receive, where
only frames having an address field matching one of two
preprogrammed 827 3 address fields are transferred to memory.
1-294 SDLC Adapter

(This example covers a general receive operation.) After the
receive command, two parameters are required before the receiver
becomes active; the least significant and most significant bytes of
the receiver buffer length. Once these bytes are loaded, the
receiver is active and the processor may return to other tasks. The
next frame appearing at the receiver input is transferred to
memory using receiver DMA requests. When the closing flag is
received, the 8273 checks the FCS and raises its RxINT line. The
processor can then read the results, which indicate if the frame
was error-free or not. (If the received frame had been longer than
the pre-loaded buffer length, the processor would have been
notified of that occurrence earlier with a receiver error interrupt.
Like the transmit example, after the initial command, the
processor is free for other tasks until a frame is completely
received.
Selective Receive
In selective receive, two parameters (AI and A2) are required in
addition to those for general receive. These parameters are two
address match bytes. When commanded to selective receive, the
8273 passes to memory or the processor only those frames having
an address field matching either A I or A2. This command is
usually used for secondary stations with A I designating the
secondary address and A2 being the "all parties" address. If only
one match byte is needed, Al and A2 should be equal. As in
general receive, the 8273 counts the incoming data bytes and
interrupts the processor if the received frame is larger than the
preset receive buffer length.
SDLC Adapter 1-295

Result Code Summary
Hex Code Result Status After Interrupt
T OC Early Transmit Interrupt Transmitter Active

r 00 Frame Transmit Complete Idle or Flags
a OE DMA Underrun Abort
n OF Clear to Send Error Abort
s 10 Abort Complete Idle or Flags
m
i
t
XO A 1 Match or General Receive Active
R X1 A2 Match Active
e 03 CRC Error Active
c 04 Abort Detected Active
e 05 Idle Detected Disabled
i 06 EOP Detected Disabled
v 07 Frame Less Than 32 Bits Active
e 08 DMA Overrun Disabled
09 Memory Buffer Overflow Disabled
OA Carrier Detect Failure Disabled
OB Receiver Interrupt Overrun Disabled
Note: X decodes to number of bits in partial byte received.
The first two codes in the receive result code table result from the
error free reception of a frame. Since SD LC allows frames of
arbitrary length (> 32 bits), the high order bits of the receive result
report the number of valid received bits in the last received
information field byte. The chart below shows the decode of this
receive result bit.
X Bits Received in Last Byte

E All Eig ht Bits of Last Byte
0 BitO Only
8 Bit1-BitO
4 Bit2-BitO
C Bit3-BitO
2 Bit4-BitO
A Bit5-BitO
6 Bit6-BitO
1-296 SDLC Adapter

Address and Interrupt Information
The following tables provide address and interrupt information for
the SDLC adapter:
Hex Code Device Register Name Function

380 8255 Port A Data Internal/External Sensing
381 8255 Port B Data External Modem Interface
382 8255 Port C Data Internal Control
383 8255 Mode Set 8255 Mode Initialization
384 8253 Counter 0 LSB Square Wave Generator
384 8253 Counter 0 MSB Square Wave Generator
385 8253 Counter 1 LSB Inactivity Time-Outs
385 8253 Counter 1 MSB Inactivity Time-Outs
386 8253 Counter 2 LSB Inactivity Time-Outs
386 8253 Counter 2 MSB Inactivity Time-Outs
387 8253 Mode Register 8253 Mode Set
388 8273 Command/Status Out=Command In=Status
389 8273 Para meter /Result Out=Parameter In=Status
38A 8273 Transmit INT Status DMA/INT
38B 8273 Receive I NT Status DMA/INT
38C 8273 Data DPC (Direct Program Control)
SDLC Communications Adapter Device Addresses
Interrupt Level 3 Transmit/Receive Interrupt

Interrupt Level 4 Ti mer 1 Interrupt
Timer 2 Interrupt
Clear to Send Changed
Data Set Ready Changed
DMA Level One is used for Transmit and Receive
Interrupt Information
SDLC Adapter 1-297

Interface Information
The SDLC communications adapter conforms to interface signal
levels standardized by the Electronics Industries Association
RS-232C Standard. These levels are shown in the figure below.
Additional lines used but not standardized by EIA are pins 11,
18, and 25. These lines are designated as select standby, test and
test indicate, respectively. Select Standby is used to support the
switched network backup facility of a modem providing this
option. Test and test indicate support a modem wrap function on
modems which are designed for business machine controlled
modem wraps. Two jumpers on the adapter (PI and P2) are used
to connect test and test indicate to the interface, if required (see
Appendix D for these jumpers).
C
Drivers Receivers
+15VdC~ +25VdC
Active Level: Data = 0
+5Vdc - +3 Vdc
-5Vdc ~
Invalid Level
Inactive Level: Data = 1 C - 3 VdC
-15VdC- -25 Vdc
1-298 SDLC Adapter

25-Pin D-Shell
Connector
Signal Name - Description Pin

No Connection 1
Transmitted Data 2
Received Data 3
Request to Send 4
Clear to Send 5
Data Set Ready 6
Signal Ground 7
No Connection 9
No Connection 10 Synchro nous
External Select Standby* 11 Data Lin k
Device No Connection 12 Control
No Connection Commun ications
13
Adapter
No Connection 14
Transmitter Signal Element Timing 15
No Connection 16
Receiver Signal Element Timing 17
Test (IBM Modems Only)* 18
No Connection 19
No Connection 21
Ring Indicator 22
Data Signal Rate Selector 23
No Connection 24
Test Indicate (IBM Modems Only)* 25
*Not standardized by EIA (Electronics Industry Association).
SDLC Adapter 1-299

Notes:
1-300 SDLC Adapter

IBM Communications Adapter Cable
The IBM Communications Adapter Cable is a ten foot cable for

connection of an IBM communications adapter to a modem or
other RS-232C DCE (data communications equipment). It is fully
shielded and provides a high quality, low noise channel for
interface between the communications adapter and DCE.
The connector ends are 25-pin D-shell connectors. All pin

connections conform with the EIA RS-232C standard. In addition,
connection is provided on pins 11, 18 and 25. These pins are
designated as select standby, test and test indicate, respectively,
on some modems. Select standby is used to support the switched
network backup facility, if applicable. Test and test indicate
support a modem wrap function on modems designed for business
machine controlled modem wraps.
Communications Cable 1-301

The IBM Communications Adapter Cable connects the following
pins on the 25-pin D-shell connectors.
14
14
Communications Modem
Adapter Connector
·· .. Connector
·.
13 25 25 13
Communications Modem
Adapter Connector Connector
Pin # Name Pin #
NC Outer Cable Shield 1
2 Transmitted Data 2
3 Received Data 3
4 Request to Send 4
5 Clear to Send 5
6 Data Set Ready 6
7 Signal Ground (Inner Lead Shields) 7
8 Received Line Signal Detector 8
NC NC
NC NC
11 Select Standby 11
NC NC
NC NC
NC NC
15 Transmitter Signal Element Timing 15
NC NC
17 Receiver Signal Element Timing 17
18 Test 18
NC NC
20 Data Terminal Ready 20
NC NC
22 Ring Indicator 22
23 Data Signal Rate Selector 23
NC NC
25 Test Indicate 25
1-302 Communications Cable

SECTION 2: ROM BIOS AND
SYSTEM USAGE
ROM BIOS ........................................ 2-2

Keyboard Encoding and Usage ....................... 2-11
BIOS Cassette Logic ................................ 2-21
ROM BIOS 2-1

Notes:
2·2 ROM BIOS

ROM BIOS
The basic input/output system (BIOS) resides in ROM on the

system board and provides device level control for the major I/O
devices in the system. Additional ROM modules may be located
on option adapters to provide device level control for that option
adapter. BIOS routines enable the assembly language programmer
to perform block (disk and diskette) or character-level I/O
operations without concern for device address and operating
characteristics. System services, such as time-of-day and memory
size determination, are provided by the BIOS.
The goal is to provide an operational interface to the system and

relieve the programmer of the concern about the characteristics of
hardware devices. The BIOS interface insulates the user from the
hardware, thus allowing new devices to be added to the system,
yet retaining the BIOS level interface to the device. In this
manner, user programs become transparent to hardware
modifications and enhancements.
The IBM Personal Computer MACRO Assembler manual and

the IBM Personal Computer Disk Operating System (DOS)
manual provide useful programming information related to this
section. A complete listing of the BIOS is given in Appendix A.
Use of BIOS
Access to BIOS is through the 8088 software interrupts. Each
BIOS entry point is available through its own interrupt, which can
be found in the "8088 Software Interrupt Listing."
The software interrupts, hex 10 through hex lA, each access a

different BIOS routine. For example, to determine the amount of
memory available in the system,
INT 12H
will invoke the BIOS routine for determining memory size and
will return the value to the caller.
ROM BIOS 2-3

Parameter Passing
All parameters passed to and from the BIOS routines go through
the 8088 registers. The prolog of each BIOS function indicates the
registers used on the call and the return. For the memory size
example, no parameters are passed. The memory size, in lK byte
increments, is returned in the AX register.
If a BIOS function has several possible operations, the AR

register is used at input to indicate the desired operation. For
example, to set the time of day, the following code is required:
MOV AH,l ;function is to set time of day.

MOV CX,RIG~COUNT ;establish the current time.
MOV DX,LOW~COUNT
INT lAR ;set the time.
To read the time of day:
MOV AH,O ;function is to read time of

day.
INT lAR ;read the timer.
Generally, the BIOS routines save all registers except for AX and
the flags. Other registers are modified on return only if they are
returning a value to the caller. The exact register usage can be
seen in the prolog of each BIOS function.
2-4 ROM BIOS

Address Interrupt
(Hex) Number Name BIOS Entry
0-3 0 Divide by Zero D_EOI
4-7 1 Single Step D_EOI
8-B 2 Nonmaskable NMUNT
C-F 3 Breakpoint P_EOI
10-13 4 Overflow D_EOI
14-17 5 Print Screen PRINT_SCREEN
18-1 B 6 Reserved D_EOI
1 D-1 F 7 Reserved D_EOI
20-23 8 Time of Day TIMERJNT
24-27 9 Keyboard KBJNT
28-2B A Reserved D_EOI
2C-2F B Communications D_EOI
30-33 C Communications D_EOI
34-37 D Disk D_EOI
38-3B E Diskette DISKJNT
3C-3F F Printer D_EOI
40-43 10 Video VIDEO_IO
44-47 11 Equipment Check EQUIPMENT
48-4B 12 Memory MEMORY_SIZE_DETERMINE
4C-4F 13 Diskette/Disk DISKETTEJO
50-53 14 Communications RS232JO
54-57 15 Cassette CASSETTEJO
58-5B 16 Keyboard KEYBOARD_IO
5C-5F 17 Printer PRINTERjO
60-63 18 Resident BASIC F600:0000
64-67 19 Bootstrap BOOT_STRAP
68-6B 1A Time of Day TIME_OF_DAY
6C-6F 1B Keyboard Break DUMMY_RETURN
70-73 1C Timer Tick DUMMY_RETURN
74-77 1D Video Initialization VIDEO_PARMS
78-7B 1E Diskette Parameters DISK_BASE
7C-7F 1F Video Graphics Chars 0
8088 Software Interrupt Listing
ROM BIOS 2-5

Vectors with Special Meanings
Interrupt Hex 1B - Keyboard Break Address

This vector points to the code to be exercised when the Ctrl and
Break keys are pressed on the keyboard. The vector is invoked
while responding !o the keyboard interrupt, and control should be
returned through an IRET instruction. The power-on routines
initialize this vector to point to an IRET instruction, so that
nothing will occur when the Ctrl and Break keys are pressed
unless the application program sets a different value.
Control may be retained by this routine, with the following

problems. The Break may have occurred during interrupt
processing, so that one or more End of Interrupt commands must
be sent to the 8259 controller. Also, all I/O devices should be
reset in case an operation was underway at that time.
Interrupt Hex 1C - Timer Tick

This vector points to the code to be executed on every system-
clock tick. This vector is invoked while responding to the timer
interrupt, and control should be returned through an IRET
instruction. The power-on routines initialize this vector to point to
an IRET instruction, so that nothing will occur unless the
application modifies the pointer. It is the responsibility of the
application to save and restore all registers that will be modified.
Interrupt Hex ID - Video Parameters

This vector points to a data region containing the parameters
required for the initialization of the 6845 on the video card. Note
that there are four separate tables, and all four must be
reproduced if all modes of operation are to be supported. The
power-on routines initialize this vector to point to the parameters
contained in the ROM video routines.
2-6 ROM BIOS

Interrupt Hex 1E - Diskette Parameters
required for the diskette drive. The power-on routines initialize the
vector to point to the parameters contained in the ROM diskette
routine. These default parameters represent the specified values
for any IBM drives attached to the machine. Changing this
parameter block may be necessary to reflect the specifications of
the other drives attached.
Interrupt Hex 1F - Graphics Character Extensions

When operating in the graphics modes of the IBM Color/Graphics
Monitor Adapter (320 by 200 or 640 by 200), the read/write
character interface will form the character from the ASCII code
point, using a set of dot patterns. The dot patterns for the first 128
code points are contained in ROM. To access the second 128
code points, this vector must be established to point at a table of
up to 1K bytes, where each code point is represented by eight
bytes of graphic information. At power-on, this vector is
initialized to 000:0, and it is the responsibility of the user to
change this vector if the additional code points are required.
Interrupt Hex 40 - Reserved

When an IBM Fixed Disk Drive Adapter is installed, the BIOS
routines use interrupt hex 40 to revector the diskette pointer.
Interrupt Hex 41 - Fixed Disk Parameters

required for the fixed disk drive. The power-on routines initialize
the vector to point to the parameters contained in the ROM disk
routine. These default parameters represent the specified values
for any IBM Fixed Disk Drives attached to the machine.
Changing this parameter block may be necessary to reflect the
specifications of the other fixed disk drives attached.
ROM BIOS 2-7

Other ReadIWrite Memory Usage
The IBM BIOS routines use 256 bytes of memory starting at
absolute hex 400 to hex 4FF. Locations hex 400 to 407 contain
the base addresses of any RS-232C cards attached to the system.
Locations hex 408 to 40F contain the base addresses of the
printer adapter.
Memory locations hex 300 to 3FF are used as a stack area during
the power-on initialization, and bootstrap, when control is passed
to it from power-on. If the user desires the stack in a different
area, the area must be set by the application.
Address Interrupt
(Hex) (Hex) Function
80-83 20 DOS Program Terminate
84-87 21 DOS Function Call
88-8B 22 DOS Terminate Address
8C-8F 23 DOS Ctrl Break Exit Address
90-93 24 DOS Fatal Error Vector
94-97 25 DOS Absolute Disk Read
98-9B 26 DOS Absolute Disk Write
9C-9F 27 DOS Terminate, Fix In Storage
AO-FF 28-3F Reserved for DOS
100-17F 40-5F Reserved
180-19F 60-67 Reserved for User Software Interrupts
1AO-1FF 68-7F Not Used
200-217 80-85 Reserved by BASIC
218-3C3 86-FO Used by BASIC Interpreter while BASIC is
running
3C4-3FF F1-FF Not Used
BASIC and DOS Reserved Interrupts
2-8 ROM BIOS

Address
(Hex) Mode Function
400-48F ROM BIOS See BIOS Listing
490-4EF Reserved
4FO-4FF Reserved as Intra-Application
Communication Area for any application
500-5FF Reserved for DOS and BASIC
500 DOS Print Screen Status Flag Store
O-Print Screen Not Active or Successful
Print Screen Operation
1-Print Screen In Progress
255-Error Encountered during Print Screen
Operation
504 DOS Single Drive Mode Status Byte
510-511 BASIC BASIC's Segment Address Store
512-515 BASIC Clock Interrupt Vector Segment: Offset Store
516-519 BASIC Break Key Interrupt Vector Segment: Offset
Store
51A-51D BASIC Disk Error Interrupt Vector Segment: Offset
Store
Reserved Memory Locations
If you do DEF SEG (Default workspace segment):
Offset
(Hex Value) Length
Line number of current line being executed 2E 2
Line number of last error 347 2
Offset into segment of start of program text 30 2
Offset into segment of start of variables 358 2
(end of program text 1-1)
Keyboard buffer contents 6A 1
if O-no characters in buffer
if 1-characters in buffer
Character color in graphics mode 4E 1
Set to 1, 2, or 3 to get text in colors 1 to 3.
Do not set to O.
(Default = 3)
Example
100 Print PEEK (&H2E) + 256*PEEK (&H2F)
~ L H
100
I Hex 64
I Hex 00
I
BASIC Workspace Variables
ROM BIOS 2-9

Starting Address in Hex
00000 BIOS
Interrupt
Vectors
00080 Available
Interrupt
Vectors
00400 BIOS
Data
Area
00500 User
Read/Write
Memory
C8000 Disk
Adapter
FOOOO Read
Only
Memory
FEOOO Bios
Program
Area
BIOS Memory Map
BIOS Programming Hints

The BIOS code is invoked through software interrupts. The
programmer should not "hard code" BIOS addresses into
applications. The internal workings and absolute addresses within
BIOS are subject to change without notice.
If an error is reported by the disk or diskette code, you should

reset the drive adapter and retry the operation. A specified
number of retries should be required on diskette reads to ensure
the problem is not due to motor start-up.
When altering I/O port bit values, the programmer should change
only those bits which are necessary to the current task. Upon
completion, the programmer should restore the original
environment. Failure to adhere to this practice may be
incompatible with present and future applications.
2-10 ROM BIOS

Adapter Cards with System-Accessible
ROM Modules
The ROM BIOS provides a facility to integrate adapter cards with
on board ROM code into the system. During the POST, interrupt
vectors are established for the BIOS calls. After the default
vectors are in place, a scan for additional ROM modules takes
place. At this point, a ROM routine on the adapter card may gain
control. The routine may establish or intercept interrupt vectors to
hook themselves into the system.
The absolute addresses hex C8000 through hex F4000 are

scanned in 2K blocks in search of a valid adapter card ROM.
A valid ROM is defined as follows:
Byte 0: Hex 55
Byte 1: HexAA
Byte 2: A length indicator representing the number of 512 byte
blocks in the ROM (length/512).
A checksum is also done to test the integrity of the
ROM module. Each byte in the defined ROM is
summed modulo hex 100. This sum must be 0 for
the module to be deemed valid.
When the POST identifies a valid ROM, it does a far call to byte
3 of the ROM (which should be executable code). The adapter
card may now perform its power-on initialization tasks. The feature
ROM should return control to the BIOS routines by executing a
far return.
ROM BIOS 2-11

Notes:
2-12 ROM BIOS

Keyboard Encoding and Usage
Encoding
The keyboard routine provided by IBM in the ROM BIOS is
responsible for converting the keyboard scan codes into what will
be termed "Extended ASCII."
Extended ASCII encompasses one-byte character codes with

possible values of 0 to 255, an extended code for certain extended
keyboard functions, and functions handled within the keyboard
routine or through interrupts.
Character Codes
The following character codes are passed through the BIOS
keyboard routine to the system or application program. A "-1"
means the combination is suppressed in the keyboard routine. The
codes are returned in AL. See Appendix C for the exact codes.
Also, see "Keyboard Scan Code Diagram" in Section 1.
Key
Number Base Case Upper Case Ctrl Alt
1 Esc Esc Esc -1
2 1 ! -1 Note 1
3 2 @ Nul (000) Note 1 Note 1
4 3 # -1 Note 1
5 4 $ -1 Note 1
6 5 % -1 Note 1
7 6 A RS(030) Note 1
8 7 & -1 Note 1
9 8 * -1 Note 1
10 9 ( -1 Note 1
11 0 ) -1 Note 1
12 - - US(031) Note 1
13 = + -1 Note 1
14 Backspace (008) Backspace (008) Del (127) -1
15 -1(009) I--(Note 1) -1 -1
16 q Q DCl (017) Note 1
17 w W ETB (023) Note 1
Character Codes (Part 1 of 3)

Keyboard Encoding 2-13
Key
18 e E ENQ (005) Note 1
19 r R DC2 (018) Note 1
20 t T DC4 (020) Note 1
21 y Y EM (025) Note 1
22 u U NAK (021) Note 1
23 i I HT (009) Note 1
24 a 0 SI (015) Note 1
25 p P DLE (016) Note 1
26 [ 1 Esc (027) -1
27 1 I GS (029 -1
28 CR CR LF (010) -1
29 Ctrl -1 -1 -1 -1
30 a A SOH (001) Note 1
31 s S DC3 (019) Note 1
32 d D EOT (004) Note 1
33 f F ACK (006) Note 1
34 9 G BEL (007) Note 1
35 h H BS (008) Note 1
36 j J LF (010) Note 1
37 k K VT (011) Note 1
38 I L FF (012) Note 1
39 -1 -1
40 " -1 -1
41 ~
-1 -1
42 Shift -1 -1 -1 -1
I
43 \ I FS (028) -1
44 z Z SUB (026) Note 1
45 x X CAN (024) Note 1
46 c C ETX (003) Note 1
47 v V SYN (022) Note 1
48 b B STX (002) Note 1
49 n N SO (014) Note 1
50 m M CR (013) Note 1
51 < -1 -1
52 > -1 -1
53 / ? -1 -1
54 Shift -1 -1 -1 -1
55 * (Note 2) (Note 1) -1
56 Alt -1 -1 -1 -1
57 SP SP SP SP
58 Caps Lock -1 -1 -1 -1
59 Nul (Note 1) Nul (Note 1) Nul (Note 1) Nul (Note 1)
2-14 Keyboard Encoding

Key
69 Num lock -1 -1 Pause (Note 2) -1
70 Scroll lock -1 -1 Break (Note 2) -1
Notes: 1. Refer to "Extended Codes" in this section.

2. Refer to "Special Handling" in this section.
Keys 71 to 83 have meaning only in base case, in Num Lock (or

shifted) states, or in Ctrl state. It should be noted that the shift key
temporarily reverses the current Num Lock state.
Key Num
Number lock Base Case Alt Ctrl
71 7 Home (Note 1) -1 Clear Screen
72
73
8
9
t (Note 1)
Page Up (Note 1)
-1
-1
-1
Top of Text and Home
74 - - - -- -- -- - ---- - ---- --- -1 -1
75 4 -(Note 1) -1 Reverse Word (Note 1)
76 5 -1 -1 -1
77 6 -(Note 1) -1 Advance Word (Note 1)
78 + + -1 -1
79 1 End (Note 1) -1 Erase to EOl (Note 1)
80
81
2
3
~ (Note 1)
Page Down (Note 1)
-1
-1
-1
Erase to EOS (Note 1)
82 0 Ins -1 -1
83 Del (Notes 1,2) Note 2 Note 2
Notes: 1. Refer to "Extended Codes" in this section.
2. Refer to "Special Handling" in this section.

Extended Codes
Extended Functions
F or certain functions that cannot be represented in the standard
ASCII code, an extended code is used. A character code of 000
(Nul) is returned in AL. This indicates that the system or
application program should examine a second code that will
indicate the actual function. Usually, but not always, this second
code is the scan code of the primary key that was pressed. This
code is returned in AH.
Second Code Function

3
15
16-25
-
Nul Character
Alt Q, W, E, R, T, Y, U, I, 0, P
30-38 Alt A, S, D, F, G, H, J, K, L
44-50 Alt Z, X, C, V, B, N, M
59-68 F1 to F1 0 Function Keys Base Case
71 Home
72 t
79
73
75
77
--
Page Up and Home Cursor
End
80
81
l
Page Down and Home Cursor
82 Ins (Insert)
83 Del (Delete)
84-93 F11 to F20 (Uppercase F1 to F1 0)
94-103 F21 to F30 (Ctrl F1 to F1 0)
104-113 F31 to F40 (Alt F1 to F1 0)
114 Ctrl PrtSc (Start/Stop Echo to Printer)
115 Ctrl-(Reverse Word)
116 Ctrl-(Advance Word)
117 Ctrl End [Erase to End of Line (EOL)]
118 Ctrl PgDn [Erase to End of Screen (EOS)]
119 Ctrl Home (Clear Screen and Home)
120-131 Alt 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, -, = (Keys 2-1 3)
132 Ctrl PgUp (Top 25 Lines of Text and Home Cursor)
Keyboard Extended Functions

Shift States
Most shift states are handled within the keyboard routine,
transparent to the system or application program. In any case, the
current set of active shift states are available by calling an entry
point in the ROM keyboard routine. The following keys result in
altered shift states:
Shift
This key temporarily shifts keys 2-13,15-27,30-41,43-53,55,
and 59-68 to upper case (base case ifin Caps Lock state). Also,
the Shift key temporarily reverses the Num Lock or non-Num-Lock
state of keys 71-73,75,77, and 79-83.
Ctrl
This key temporarily shifts keys 3, 7, 12, 14, 16-28, 30-38,43-50,
55,59-71, 73, 75, 77, 79, and 81 to the Ctrl state. Also, the Ctrl
key is used with the Alt and Del keys to cause the "system reset"
function, with the Scroll Lock key to cause the "break" function,
and with the Num Lock key to cause the "pause" function. The
system reset, break, and pause functions are described in "Special
Handling" on the following pages.
Alt
This key temporarily shifts keys 2-13, 16-25,30-38,44-50, and
59-68 to the Alt state. Also, the Alt key is used with the Ctrl and
Del keys to cause the "system reset" function described in
"Special Handling" on the following pages.
°
The Alt key has another use. This key allows the user to enter any
character code from to 255 into the system from the keyboard.
The user holds down the Alt key and types the decimal value of
the characters desired using the numeric keypad (keys 71-73,
75-77, and 79-82). The Alt key is then released. If more than
three digits are typed, a modulo-256 result is created. These three
digits are interpreted as a character code and are transmitted
through the keyboard routine to the system or application
program. Alt is handled internal to the keyboard routine.
Caps Lock
This key shifts keys 16-25, 30-38, and 44-50 to upper case. A
second depression of the Caps Lock key reverses the action. Caps
Lock is handled internal to the keyboard routine.
Scroll Lock
This key is interpreted by appropriate application programs as
indicating use of the cursor-control keys should cause windowing
over the text rather than cursor movement. A second depression
of the Scroll Lock key reverses the action. The keyboard routine
simply records the current shift state of the Scroll Lock key. It is
the responsibility of the system or application program to perform
the function.
Shift Key Priorities and Combinations

If combinations of the Alt, Ctrl, and Shift keys are pressed and
only one is valid, the precedence is as follows: the Alt key is first,
the Ctrl key is second, and the Shift key is third. The only valid
combination is Alt and Ctrl, which is used in the "system reset"
function.
Special Handling
System Reset
The combination of the Alt, Ctrl, and Del keys will result in the
keyboard routine initiating the equivalent of a "system reset" or
"reboot." System reset is handled internal to the keyboard.

Break
The combination of the Ctrl and Break keys will result in the
keyboard routine signaling interrupt hex 1A. Also, the extended
characters (AL = hex 00, AH = hex 00) will be returned.
Pause
The combination of the Ctrl and Num Lock keys will cause the
keyboard interrupt routine to loop, waiting for any key except the
Num Lock key to be pressed. This provides a system- or
application-transparent method of temporarily suspending list,
print, and so on, and then resuming the operation. The "unpause"
key is thrown away. Pause is handled internal to the keyboard
routine.
Print Screen
The combination of the Shift and PrtSc (key 55) keys will result
in an interrupt invoking the print screen routine. This routine
works in the alphanumeric or graphics mode, with unrecognizable
characters printing as blanks.
Other Characteristics
The keyboard routine does its own buffering. The keyboard buffer
is large enough to support a fast typist. However, if a key is
entered when the buffer is full, the key will be ignored and the
"bell" will be sounded.
Also, the keyboard routine suppresses the typematic action of the

following keys: Ctrl, Shift, Alt, Num Lock, Scroll Lock, Caps
Lock, and Ins.

Keyboard Usage
This section is intended to outline a set of guidelines of key usage
when performing commonly used functions.
Function KeY(5) Comment

Home Cursor Home Editors; word processors
Return to outermost menu Home Menu driven applications
Move cursor up t Full screen editor, word processor
Page up, scroll backward 25 PgUp Editors; word processors
lines and home
Move cursor left _Key 75 Text, command entry
Move cursor right
Scroll to end of text
-
End
Text, command entry
Editors; word processors
Place cursor at end of line
Move cursor down ~ Full screen editor, word processor
Page down, scroll forward Pg Dn Editors; word processors
25 lines and home
Start/Stop insert text at cursor, Ins Text, command entry
shift text right in buffer
Delete character at cursor Del Text, command entry
Destructive backspace -Key 14 Text, command entry
Tab forward -t Text entry

Tab reverse I- Text entry
Clear screen and home Ctrl Home Command entry
Scroll up
,t In scroll lock mode
In scroll lock mode
--
Scroll down
Scroll left In scroll lock mode
Scroll right In scroll lock mode
Delete from cursor to EOL Ctrl End Text, command entry
Exit/Escape Esc Editor, 1 level of menu, and so on
Start/Stop Echo screen to Ctrl Prt Sc Any time
printer (Key 55)
Delete from cursor to EOS Ctrl PgDn Text, command entry
Advance word Ctrl- Text entry
Reverse word Ctrl- Text entry
Window Right Ctrl- When text is too wide to fit screen
Window Left Ctrl- When text is too wide to fit screen
Enter insert mode Ins Line editor
Keyboard - Commonly Used Functions (Part 1 of 2)

Function Key(s) Comment
Exit insert mode Ins Line editor
Cancel current line Esc Command entry, text entry
Suspend system (pause) Ctrl Stop list, stop program, and so on
Num Lock Resumes on any key
Break interrupt Ctrl Break Interrupt current process
System reset Alt Ctrl Reboot
Del
Top of document and home Ctrl PgUp Ed itors, word processors
cursor
Standard function keys F1-F10 Primary function keys
°°
Secondary function keys Shift F1-F1 Extra function keys if 10 are not
Ctrl F1-F1 sufficient
Alt F1-F1 °
Extra function keys Alt Keys Used when stickers are put along
2-13 top of keyboa rd
(1-9,0,-,=)
Extra function keys Alt A-Z Used when function starts with
same letter as one of the alpha
keys
Keyboard· Commonly Used Functions (Part 2 of 2)

Function Key
Carriage return ~
Line feed Ctrl~

Bell Ctrl G
Home Home
Cursor up
.t
Cursor down
Cursor left
Cursor right
Advance one word
--
Ctrl -
Reverse one word Ctrl-
Insert Ins
Delete Del
Clear screen Ctrl Home
Freeze output Ctrl Num Lock
Tab advance -t
Stop execution (break) Ctrl Break
Delete current line Esc
Delete to end of line Ctrl End
Position cursor to end of line End
BASIC Screen Editor Special Functions
Function Key
Suspend Ctrl Num Lock

Echo to printer Ctrl PrtSc
(Key 55 any case)
Stop echo to printer Ctrl PrtSc
(Key 55 any case)
Exit current function Ctrl
(break) Break
Backspace - Key 14
Line feed Ctrl .--J
Cancel line Esc
Copy character F10r_
Copy until match F2
Copy remaining F3
Skip character Del
Skip until match F4
Enter skip mode Ins
Exit insert mode Ins
Make new line the template F5
String separator in REPLACE F6
End of file in keyboard input F6
DOS Special Functions

BIOS Cassette Logic
Software Algorithms - Interrupt Hex 15

The cassette routine will be called by the request type in AH. The
address of the bytes to be read from or written to the tape will be
specified by ES:BX and the number of bytes to be read or written
will be specified by ex. The actual number of bytes read will be
returned in DX. The read block and write block will automatically
tum the cassette motor on at the start and off at the end. The
request types in AH and the cassette status descriptions follow:
Request Type Function

AH =0 Turn Cassette Motor On
AH = 1 Turn Cassette Motor Off
AH =2 Read Tape Block
Read CX bytes into memory starting at Address ES:BX
Return actual number of bytes read in DX
Return Cassette Status in AH
AH =3 Write Tape Block
Write CX bytes onto cassette starting at Address DS:BX
Return Cassette Status in AH
Cassette Status Description

AH =00 No Errors
AH =01 Cyclic Redundancy Check (CRC) Error in Read Block
AH =02 No Data Transitions
AH =04 No Leader
AH =80 Invalid Command
Note: The carry flag will be set on any error.

Cassette Write
The write-block routine writes a tape block onto the cassette tape.
The block is described in "Data Record Architecture" later in this
section.
The write-block routine turns on the cassette drive motor and a

synchronization bit (0) and then writes the leader (256 bytes of all
1's) to the tape. Next, the routine writes the number of data blocks
specified by CX. After each data block of 256 bytes, a 2-byte
cyclic redundancy check (CRC) is written. The data bytes are
taken from the memory location pointed at by ES.
The write-byte routine disassembles and writes the byte a bit at a

time to the cassette. The method used is to set Timer 2 to the
period of the desired data bit. The timer is set to a period of 1.0
millisecond for a 1 bit and 0.5 millisecond for a 0 bit.
The timer is set to mode 3, which means the timer outputs a

square wave with a period given by its counter register. The
timer's period is changed on the fly for each data bit written to the
cassette. If the number of data bytes to be written is not an
integral mUltiple of 256, then, after the last desired data byte from
memory has been written, the data block is extended to 256 bytes
of writing multiples of the last data byte. The last block is closed
with two CRC bytes as usual. After the last data block, a trailer
consisting of four bytes of all 1 bits is written. Finally, the cassette
motor is turned off, if there are no errors reported by the routine.
~250f.1s-+l
Zero Bit
1414--- 500 f.1S ----.t.1
l...-_ _ _ _ _ _ _ _ --JI One Bit

~14~--------1000f.1S--------~·1
2-24 BIOS Cassette

Cassette Read
The read-block routine turns on the cassette drive motor and then
delays for approximately 0.5 second to allow the motor to come
up to speed.
The read-block routine then searches for the leader and must
detect all 1 bits for approximately 1/4 of the leader length before
it can look for the sync (0) bit. After the sync bit is detected, the
sync byte (ASCII character hex 16) is read. If the sync byte is
read correctly, the data portion can be read. If a correct sync byte
is not found, the routine goes back and searches for the leader
again. The data is read a bit at a time and assembled into bytes.
After each byte is assembled, it is written into memory at location
ES:BX and BX is incremented by 1.
After each multiple of 256 data bytes is read, the CRC is read and
compared to the CRC generated. If a CRC error is detected, the
routine will exit with the carry flag set to indicate an error and the
status of AH set to hex 01. DX will contain the number of bytes
written memory.
The time of day interrupt (IRQO) is disabled during the cassette-

read operation.
BIOS Cassette 2-25

Data Record Architecture
The write-block routine uses the following format to record a tape
block onto a cassette tape:
Motor Motor
On Off
Component Description
Leader 256 Bytes (of All 1 's)
Sync Bit One 0 Bit
Sync Byte ASCII Character Hex 16
Data Blocks 256 Bytes in Length
CRC 2 Bytes for each Data Block
Data Record Components
Error Recovery
Error recovery is handled through software. A eRe is used to
detect errors. The polynomial used is G(X) = X16 + X12 + Xs + 1,
which is the polynomial used by the synchronous data link control
interface. Essentially, as bits are written to or read from the
cassette tape, they are passed through the eRe register in
software. After a block of data is written, the complemented value
of the calculcated eRe register is written on the tape. Upon
reading the cassette data, the eRe bytes are read and compared
to the generated eRe value. If the read eRe does not equal the
generated eRe, the processor's carry flag is set and the status of
AH is set to hex 01, which indicates a eRe error has occurred.
Also, the routine is exited on a eRe error.
2-26 BIOS Cassette

APPENDIX A: ROM BIOS
LISTINGS
Line
Page Number
System ROM BIOS

Equates .............................. . A-2 12
8088 Interrupt Locations ............... . A-2 34
Stack ................................ . A-2 66
Data Areas ........................... . A-2 74
Power-On Self-Test .................... . A-5 229
Boot Strap Loader ..................... . A-21 1493
I/O Support
Asynchronous Communications
(RS-232C) ......................... . A-22 1551
Keyboard .......................... . A-26 1818
Diskette ............................ . A-36 2426
Printer ............................. . A-46 3201
Display ............................ . A-47 3327
System Configuration Analysis
Memory Size Determination .......... . A-73 5177
Equipment Determination ............. . A-73 5208
Cassette I/O Support ................... . A-74 5253
Graphics Character Generator ........... . A-80 5769
Time of Day .......................... . A-82 5903
Print Screen .......................... . A-84 6077
Fixed Disk ROM BIOS

Fixed Disk I/O Interface ................ A-87 1
Boot Strap Loader ...................... A-92 399
System BIOS A-I

LOC OBJ LINE SOURCE
$UTlE(BIOS t=OR IBM PERSONAL COHPUTER)
; --------------- --------------------- -- ------------- -- ---- -------

THE BIOS ROUTINES ARE MEANT TO BE ACCESSED THROUGH
SOFTWARE INTERRUPTS ONLY. ANY ADDRESSES PRESENT IN
THE LISTINGS ARE INCLUDED ONL. Y fOR COMPLETENESS.
NOT FOR REFERENCE. APPLltATIONS WHICH REFERENCE
ABSOLUTE ADDRESSES WITHIN THE CODe SEGMENT
VIOLATE THE STRUCTURe AND DESIGN OF BIOS.
10 ; ----------------------------------------------------------------
11
12 ~ ----------------------------------------
13 EQUATES
1.
0060 15 PORT_A EOU 60H j 62:55 PORT A AoDR
0061 16 PORT_B EOU 61H ; 62:55 PORT B ADDR
0062 17 PORT_C EOU 62H , 62:55 PORT C ADDR
0063 18 CMD_PORT EOU 63H
0020 19 INTAOO EOU 20H ; 62:59 PORT
0021 20 INTAOI EOU 21H i 82:59 PORT
0020 21 EO! EOU 20H
0040 22 TIMER EOU 40H
0043 23 TIM_CTL EOU 43H ; 8253 TIMER CONTROL PORT ADDR
0040 24 TIHERO EOU 40H j 6253 TIMER/CNTER 0 PORT ADDR
0001 25 TMINT EOU 01 ; TIMER 0 INTR RECVO MASK
0006 26 DMA06 EOU o. ; DMA STATUS REG PORT ADDR
0000 27 DMA EOU 00 ; DMA CHANNEL 0 ADDR REG PORT ADDR
0540 2. MAXj'ERIOO EOU S40H
0410 29 MIN_PERIOD EOU 410H
0060 30 KBD_IN EOU 60H J KEYBOARD DATA IN ADOR PORT
0002: 31 KBDINT EOU 02 j KEYBOARD INTR MASK
0060 32 KB_DATA EOU 60H j KEYBOARD SCAN CODE PORT
0061 33 KB_CTL EOU 61H i CONTROL BITS FOR KB SENSE DATA
34 ; ....---------------------------------------
35 6088 INTERRUPT LOCAnONS
36 ; ----------------------------------------
37 ABSO SEGMENT AT 0
0000 38 STG_LOCO LABEL BYTE
0008 39 ORG 2"
0008 40 NHI_PTR LABEL WORD
0014 41 ORG
...
5'4
0014 42 INT5_PTR LABEL WORD
0020 43 ORG
0020 44 INT_ADDR LABEL WORD
0020 45 INT_PTR LABEL DWORD
0040 46 ORG 10H*4
0040 .7 VIDEO_IHT LABEL WORO
0074 48 ORG lOH*4
0074 49 PARM_PTR LABEL aWaRD ; POINTER TO VIDEO PARMS
0060 50 ORG 18H*4
0060 51 BASIC_PTR LABEL WORD j ENTRY POINT FOR CASSETTE BASIC
0078 52 ORG 01EH*4 ; INTERRUPT 1EH
0078 53 DISK_POINTER LABEL OWORD
007C
007C
54
55 EXT_PTR lABEL
"".
DWORD
01FH*4 J LOCATION OF POINTER
J POINTER TO EXTENSION
0100 56 ORG 04QH*4 ; ROUTINE
0100 11?1 57 IO_ROM_INIT ow
0102 ?11? 58 IO_ROM_SEG ow j OPTIONAL ROM SEGMENT
0400 59 ORG 400H
0400 60 DATA_AREA LABEL BYTE I ABSOLUTE LOCATION OF DATA SEGMENT
0400 61 DATA_WORD LABEL WORD
7COO 62 ORG 7COOH
7COO 63 BOOT_LOCN LABEL "R
6. ABSO ENOS
65
66 I --- --------------------- - - - - -- ------- --- - --- - - - - - -- -----
67 STACK -- USED DURING INITIALIZATION ONLY
68 I --- --------------- - -- ----- - - - - -- ---- - --- - - - - - - - - -- - - - ---
69 STACK SEGMENT AT 30H
0000 1128 70 OW 128 OUPI? I
0100 71 TDS LABEL WORD

72 STACK ENOS
7.
74 ; --- ------ -- - - --- - - --- ------- --- - ---- ----
75 ROM BIOS DATA AREAS
76 ; ----------------------------------------
77 DATA SEGMENT AT 40H
A-2 System BIOS

LaC OBJ LINE SOURCE
0000 (4 78 ow 4 DUP(?) I ADDRESSES OF RS232: ADAPTERS
0008 (4 7. it DUP(?) I ADDRESSES OF PRINTERS
0010 ???? 80 OW I INSTALLED HARDWARE

0012 ?? 81 MFG_TST D. ; INITIALIZATION FLAG
0013 ???? 82 MEMORY_SIZE ow I MEMORY SIZE IN K BYTES
0015 7??? 83 IO_RAM_SIZE ow I MEMORY IN I/O CHANNE L
84 ;------------------------------ --- -------
85 KEYBOARD DATA AREAS
86 1----------------------------------------
0017 ?? 87 KBJLAG DB
88
89 ; ----- SHIFT FLAG EQUATES WITHIN KBJLAG
.0
ooao 91 INS_STATE EQU 80H I INSERT STATE IS ACTIVE
0040 92 CAPS_STATE EQU 40H I CAPS LOCK STATE HAS BEEN TOGGLED
0020
0010
9'94 NutCSTATE
SCROLL_STATE
EQU
EQU
20H
lOH
; HUH LOCK STATE HAS BEEN TOGGLED
J SCROLL LOCK STATE HAS BEEN TOGGLED
oooa 95 Al T_SHIFT EQU 08H ; ALTERNATE SHIFT KEY DEPRESSED
0004 96 ClL_SHIFT EQU 04H I CONTROL SHIFT KEY DEPRESSED
0002 97 lEFT_SHIFT EQU O2H ; LEFT SHIFT KEY DEPRESSED
0001 98 RIGHT_SHIFT EQU O1H I RIGHT SHIFT KEY DEPRESSED
0018 ??
9'
100 DB ; SECOND BYTE OF KEYBOARD STATUS
101
0080 10' INS_SHIFT EQU 80H I INSERT KEY IS DEPRESSED
0040 10' CAPS_SHIFT EQU 40H I CAPS LOCK KEY IS DEPRESSED
0020 104 NUtCSHIFT EQU 20H ; NUtl LOCK KEY IS DEPRESSED
0010 105 SCROLL_SHIFT EQU lOH ; SCF<OLl LOCK KEY IS DEPRESSED
0008 106 HOLD_STATE EQU 08H I SUSPEND KEY HAS BEEN TOGGLED
107
0019 ?1 108 ALI_INPUT DB I STORAGE FOR ALTERNATE KEYPAD ENTRY
OOIA ?1?1 109 BUFFER_HEAD 0" I POINTER TO HEAD OF KEYBOARD BUFFER
ODIC ???? 110 BUFFER_TAIL DW ; POINTER TO TAIL OF KEYBOARD BUFFER
DOlE (16 III KB_BUFFER D" 16 DUP(?) I ROOM FOR 15 ENTRIES
003E ll2
"'
114 ;----- HEAD = TAIL INDICATES THAT THE BUFFER IS EHPTY
ll5
0045 ll6 NUMJEY EQU 6. ; SCAN CODE FOR NUt1BER LOCK
0046 ll7 SCROLl.-KEY EOU 70 I SCROLL LOCK KEY
0038 ll8 ALT_KEY EOU 56 I ALTERNATE SHIFT KEY SCAN CODE
0010
003A
".
120
CTl_KEY
CAPS_KEY
EOU
EOU
29
58
; SCAN CODE FOR CONTROL KEY
; SCAN CODE FOR SHIFT LOCK
002A 121 LEFT_KEY EOU 42 I SCAN COOE FOR LEFT SHIFT
0036 122 RIGHT_KEY EOU 54 ; SCAN CODE FOR RIGHT SHIFT
0052 123 INS_KEY EOU 82 I SCAN CODE FOR INSERT KEY
0053 124 DEL_KEY EOU 8. I SCAN CODE FOR DElETE KEY
125
126 ; ----------------------------------------
127 DISKETTE DATA AREAS
128 1----------------------------------------
003E ?? 129 SEEK_STATUS DB ; DRIVE RECALIBRATION STATUS
130 BIT 3-0 = DRIVE 3-0 NEEDS RECAL BEFORE
m NEXT SEEK IF BIT IS :: 0
ooao 132 INTJLAG EQU 080H ; INTERRUPT OCCURRENCE flAG
003F ?? 133 MOTOR_STATUS DB I MOTOR STATUS
13' BIT 3-0 :: DRIVE 3-0 IS CURRENTLY RUNNING
135 BIT 7 :: CURRENT OP IS A WRITE. REQUIRES DELAY
0040 ?? 136 HOTOR_COUNT D. ; TIME OUT COUNTER FOR DRIVE Tlnm OFF
0025 137 MOTOR_WAIT EQU 37 ; TWO SEC OF COUNT FOR MOTOR TlIRN OFF
138
0041 11 13' DISKETTE_STATUS DB J BYTE OF RETURN CODE INFO FOR STATUS
0080 140 TIME_OUT EQU 80H ; ATTACHMENT FAILED TO RESPOND
0040 141 BAD_SEEK EQU 40H I SEEK OPERATION FAILED
0020 142 BAD_NEC EQU 20H ; NEC CONTROllER HAS FAILED
0010 14. BAD_CRC EQU lOH ; BAD CRC ON DISKETTE READ
0009 144 DNA_BOUNDARY EQU O'H ; ATTENPT TO DNA ACROSS 641< BOUNDARY
0006 145 BAD_DHA EQU D8H ; OMA OVERRUN ON OPERATION
0004
0003
0002 ..
146
147
,
RECORD_NOT_FND
WRITE_PROTECT
BAD_ADDR_MARK
EQU
EQU
EQU
04H
OJH
O2H
; REQUESTED SECTOR NOT FOUND
I WRITE ATTEMPTED ON WRITE PROT DISK
I ADDRESS HARt( NOT FOUND
System BIOS A-3

LOC OBJ LINE SOURCE
0001
'"
15.
E.... .," I BAD COMtlAND PASSED TO DISKETTE 110
0042 (7 lSI DB 7 DUP(?) I STATUS BYTES FROM NEt
152
153 1----.. ----- - ------.. -- ---------- ----- -----
154 VIDEO DISPLAY DATA AREA
1S5 ; ----------- - --- --- ----- ------- ----- -- .. --
0049 11 IS. CRT_HOOf DB I CLRRENT CRT tIODE
004A ???? 157 CRT_COLS DW J tU1BER OF COLlR1NS ON SCREEN
D04C ???? 158 CRT_LEN DW f LENGTH OF REGEN IN BYTES
004E ???? IS. CRT.START DW ; STARTING ADDRESS IN REGEN BUFFER
0050 (8 I •• CURSOR.POSH DW e DUP(?) ; CURSOR FOR EACH OF UP TO 8 PAGES
????
0060 1??? ,., CURSOR_HODE DW J CURRENT CURSOR MODE SETTING

0062 ?? ,.2 ACTIVE. PAGE DB I CURRENT PAGE BEING DISPLAYED
0063 ???? I.' ADDR_684S DW J BASE ADDRESS FOR ACTIVE DISPLAY CARD
0065 11
0066 ??
I.'
,.5
CRT.MODE_SET
CRT_PALETTE
DB
DB
; CURRENT SETTING OF THE 3X8 REGISTER
; CURRENT PALETTE SETTING COLOR CARD
I ••
167 ; ----------------------------------------
168 CASSETTE DATA AREA
I •• J ----------- - -------- - - ---- .--- ------- - --
0067 ???? 17. EDGE_CNT OW J TIME ccurr AT DATA EDGE
0069 ???? 171 CRC_REG OW ; CRC REGISTER
0068 11 17. LAST_VAL DB ; LAST INPUT VALUE
17>
174 ; ----------------------------------------
175 TIMER DATA AREA
17.
D06t 1111 171 TIMER_lOW DW ; LOW WORD OF TIMER COUNT
006E ???? 178 TIMER_HIGH DW J HIGH WORD OF TIMER COUNT
0070 ?1 17. TIMER_OFl DB , TIMER HAS ROLLED OVER SINCE LAST READ
18. ;COUNTS_SEC EQU 18
181 ; COUNTS_MIN EQU 1092
182 ; COUNTS_HOUR EQU 65543
I.' ;COUNTS_DAY EQU 1573040 = 1800BOH
I.'
185 ; - - --- --- - - ------ - -- - ----- -- -- - -- - - ------
186 SYSTEM DATA AREA
187 ; ------------ ------ -------------- - -- -- - --
0071 11 188 BIOS_BREAK DB J BIT 7 = 1 IF BREAK KEY WAS DEPRESSED
0072 111? 18. RESET]lAG DW ; WORD = 1234H IF KB RESET UNDERWAY
190 ; ----------------------------------------
191 FIXED DISK DATA AREA
192 J ----------------------------------------
0074 1111 19> DW
0076 ???? I •• DW
195 J -------.--------------------------------
196 PRINTER AND RS232 TIMEOUT CTRS :
197 ;- ---------------------------------------
0078 (4 198 PRINT_ TIH....0UT DB 4 DUP(?) ; PRINTER TIME OUT COUNTER
I
007C (4 I •• '" DUP(?) J RS232 TIME OUT COUNTER
200 ; ---------- ---------- ------ --------------

201 EXTRA KEYBOARD DATA AREA
2.2 ;------------------ ------------- ---------
0080 ???? 2.3 BUFFER_START OW
0082 1111 2.4 DW
205 DATA ENDS
206 J ------------------ - ---- -----------------
207 EXTRA DATA AREA
208 i ------------ ------ - ----- ----------------
209 XXDATA SEGHENT AT SOH
0000 ??
".
211
DB
ENDS
212
213 1----------------------------------------
214 VIDEO DISPLAY BUFFER
215 ,----------------------------------------
216 VIDEO_RAM SEGMENT AT oeaOOH
A-4 System BIOS

LaC OBJ LINE SOURCE
0000 217 REGEN LABEL BYTE

0000 218 REGENW LABEL WORD
0000 (16384 219 DB 16384 CUP!? J
'NDS
2: 21 ; ------ -- - -- - - -- -- -------- --- --- --- ------
222 ROM RESIDENT CODE
223 1----------------------------------------
224 CODE SEGMENT AT OFOOOH
0000 (57344 225 DB 57344 aUPI? 1 ~ FILL LOWEST 56K
226
EOOD 31353031343736 227 DB '1501476 COPR. IBM 1~~1' ; COPYRIGHT NOTICE
20434F50522EZO
49424020313938
32
228
2: 2: 9 1--- --------------- - - ---- ----- ---- -- - - - --------- - -- --- --- - - -- - ---
230 INITIAL RElIABILITY TESTS -- PHASE 1
231 ;----------------------------------------------------------------
232 ASSUME CS:COOE ,SS:CODE .ES:ABSO .DS:DATA
233 1----------------------------------------
234 DATA DEFINITIONS
235 ; ----------------------------------------
E016 DIED 236 C1 OW Cll ; RETURN ADDRESS
237
238 J -- - --- --------- - - - - -- -- ------ ---- - - - - - ------- - - - -- - ---------------- - ----
239 THIS SUBROUTINE PERFORMS A READ/WRITE STORAGE TEST ON
240 A 16K BLOCK OF STORAGE.
241 1 ENTRY REQUIREMENTS:
242 ES = ADDRESS OF STORAGE SEGMENT BEING TESTED
243 OS = ADDRESS OF STORAGE SEGMENT BEING TESTED
244 WHEN ENTERING AT STGTST_CNT, CX MUST BE LOADED WITH
245 THE BYTE COUNT.
246 ; EXIT PARAMETERS:
247 ZERO FLAG:: 0 IF STORAGE ERROR {DATA COMPARE OR PARITY CHECK.
248 AL ;: 0 DENOTES A PARITY CHECK. ELSE AL;:XOR'ED BIT
Z49 PATIERN OF THE EXPECTED DATA PATTERN VS THE
250 ACTUAL DATA. READ.
251 AX,BX,CX,DX.DI, AND SI ARE ALL DESTROYED.
252 ; -- - ----- ------- - - ---- - -- ----- - ------ - - - - - - - -- - - - - - - -- - ------------------
253
E018 254 STGTST PRDC NEAR
E018 890040 255 MOV CX,4000H ; SETUP CNT TO TEST A 16K BLK
EOIB 256 STGTST_CNT:
EOIB Fe 257 ClD i SET oIR flAG TO INCREMENT
EDIt 8809 258 I10V BX,ex ; SAVE BYTE CNT (4K FOR YIDEO OR 16K)
fOIE BBAAAA 259 MOV AX,OAAAAH ; GET DATA PATTERN TO WRITE
EOZI BA55FF 260 MaY' DX,OFF55H ; SETUP OTHER DATA. PATTERNS TO USE
E024 2BFF 261 SUB 01,01 ; 01 = OFFSET 0 RELATIVE TO ES REG
E026 f3 262 REP STOSB ; WRITE STORAGE LOCATIONS
E027 AA
E028 263 C3: , STSOI
E028 4F 264 DEC DI ; POINT TO LAST BYTE JUST WRITTEN
E029 FD 265 STD I SET OIR FLAG TO GO BACKWARDS
EOlA 266 C4:
EOlA 8BF7 267 MOV SI,DI
foze 86ce 268 NOV CX,BX ; SETUP BYTE CNT
f02E 269 C5: I INNER TEST LOOP
EDa AC 270 LOOSB ; READ OLD TST BYTE FROM STORAGE [SI)+
E02F 32C4 271 XOR .H,AH ; DATA READ AS EXPECTED?
E031 7525 272 JNE C7 ; NO - GO TO ERROR ROUTINE
E033 BAC2 273 MOV AL,OL I GET NEXT DATA PATTERN TO WRITE
E035 AA 274 STOSB I WRITE INTO LOCATION JUST READ [011+
E036 E2F6 275 LOOP C5 , DECREMENT BYTE COUNT AND LOOP CX
276
E038 22E4 277 AND AH,AH I ENDING ZERO PATTERN WRITTEN TO STG l'
E03A 7416 278 JZ C6X I YES - RETURN TO CALLER WITH Al::O
E03e BAEO 279 MDV AH,AL ; SETUP NEW VALUE FOR COMPARE
E03E e6F2 280 XCHG DH.OL ; MOVE NEXT DATA PATTERN TO OL
E040 22E4 281 AND AH.AH I READING ZERO PATTERN THIS PASS?
E042 7504 282 JHZ C6 I CONTINUE TEST SEqUENCE TILL ZERO DATA.
E044 8AD4 283 MDV DL,AH ELSE SET ZERO FOR END READ PATTERN
E046 EBED 284 JMP C3 ; ANO MAKE FINAL BACKWARDS PASS
'ooa 285 C6:
System BIOS A-5

LOC OBJ LINE SOURCE
E048 Fe 286 CLD ; SET OIR FLAG TO GO FORWARD

E049 47 287 INC DI • SET POINTER TO BEG lOCATION
E04A 74DE 288 JZ C4 ; READMRITE fORWARO IN STG
E04C 4F 289 DEC OI ; ADJUST POINTER
E040 8AOI00 290 MOV OX.OOOOlH I SETUP 01 fOR PARITY BIT
291 ; AHO 00 FOR END
E050 EB06 292 JMP C3 ; REAO/WRITE BACKWARD IN STG
E052 293 C6X:
E052 E462 294 IN AL.PORT_C ; 010 A PARITY ERROR OCCUR ?
E054 24CO 295 ANIl AL.OCOH 1 ZERO FLAG WILL BE OFF PARITY ERROR
E056 BODO 296 MOV AL.OOOH 1 AL=O DATA COMPARE OK
EOS8 297 C7:
E058 Fe 298 CLO ; SET DEFAULT DIRCTN flAG BACK TO INC
E059 C3 299 RET
300 STGTST EtilP
30I 1----------------------------------------------------------------
302 8088 PROCESSOR TEST
303 ; DESCRIPTION
304 VERIFY 8088 FLAGS. REGISTERS AHO COHOITIONAL JUMPS
305 1----------------------------------------------------------------
306 ASSUME tS :CODE .DS:NOTHING. ES: NOTHING,SS:NOTHIHG
E05B 307 DRG OE05BH
E058 308 RESET LABel FAR
E05B 309 START:
E05B FA 310 tLI I DISABLE INTERRUPTS
EOSC 8405 311 MOV AH.OD5H I SET SF. CF. ZF. AND AF FLAGS ON
EOSE 9E 312 SAHF
E05F 734C 313 JNC ERROl ; GO TO ERR ROUTINE IF CF NOT SET
E061 754.4. 314 JNZ ERROl I GO TO ERR ROUTINE IF ZF NOT SET
E063 7848 315 JHP ERROl ; GO TO ERR ROUTINE IF PF NOT SET
f065 7946 316 JNS ERROl ; GO TO ERR ROUTINE IF SF NOT SET
ED67 9F 317 LAHF I LOAD FLAG IMAGE TO AH
E06S BIOS 318 MOV CL.S ; LOAD tNT REG WITH SHIFT tNT
E06A D2EC 319 SHR AH.Cl ; SHIFT AF INTO CARRY BIT POS
EObC 733F 320 JNC ERROl ; GO TO ERR ROUTINE IF AF NOT SET
ED6E 6040 321 MOV AL,40H ; SET THE OF F LAG ON
E070 ODED 322 SHL AL,I i SETUP FOR TESTING
f072 7139 323 JNO ERROl ; GO TO ERR ROUTINE IF OF NOT SET
E074 32E4 324 XOR AH.AH ISETAH=O
f076 9E 325 SAHF i CLEAR SF. Cf. ZF. ANtI Pf
E077 7634 326 JBE ERROl ; GO TO ERR ROUTINE IF CF ON
327 ; OR TO TO ERR ROUTINE IF ZF ON
E079 7832 328 JS ERROl ; GO TO ERR ROUTINE IF SF ON
E07B 7A30 329 JP ERROl ; GO TO ERR ROUTINE IF PF ON
f070 9F 330 LAHF LOAD F LAG IMAGE TO AH
E07E 6105 331 MOV CL,S I LOAD tNT REG WITH SHIFT CNT
E060 02EC 332 SHR AH,CL ; SHIFT 'AF' INTO CARRY BIT POS
E082 7229 333 Je ERROl ; GO TO ERR ROUTINE IF ON
E084 00E4 334 SHL AH,l I CHECK THAT 'OF' IS CLEAR
E086 702:5 335 JO ERROl ; GO TO ERR ROUTINE IF ON
336
337 i----- READ/WRITE THE 8088 GENERAL AND SEGMENTATION REGISTERS
338 WITH ALL ONE'S AND ZEROES'S.
339
ED86 B8FFFF 340 MOV AX.OFFFFH I SETUP ONE'S PATTERN IN AX
E08B F9 341 STC
Eoec 342 C8:
Eoac 8E06 343 HOV DS.AX I WRITE PATTERN TO ALL REGS
EoeE 8coe 344 HOV BX.OS
E090 SEC3 345 MOV ES.BX
E092 eCCI 346 MOV CX,ES
E094 SED! 347 HOV sS,ex
E096 8e02: 348 HOV DX.5S
E096 8BE2 349 HOV SP,DX
E09.4. 8BEt 350 MOV BP,SP
E09C BBfS 351 HOV SI.BP
E09E SBFE 352 HOV DI.SI
EOAO 7307 353 JNC C9 I TSTlA
EOA2 33C7 354 XQR AX.DI I PATTERN HAKE IT THRU ALL REGS
EO.6.4 7507 355 JNZ ERROl I NO - GO TO ERR ROUTINE
fOA6 Fe 356 CLC
EDA7 EBE3 357 JHP C8
EOA9 358 C9: I TsnA
EOA9 DBC7 359 OR AX.DI I ZERO PATTERN MAKE IT THRU?
EDAB 7401 360 JZ C10 I YES - GO TO NEXT TEST
EDAD F4 361 ERROl: HLT I HALT SYSTEM
362 1--------------------------------------------------------
A-6 System BIOS

LaC OBJ LINE SOURCE
363 ROS CHECKSUM TEST I

364 I DESCRIPTION
36' A CHECKSUM IS DONE FOR THE 8K ROS HOOUlE
366 CONTAINING POD ANO BIOS.
367 1--------------------------------------------------------
EOAE 366 CIa:
369 ; ZERO IN .l.l ALREADY
EOAE E6AO 370 OUT OAOH,AL I DISABLE Nt1I INTERRUPTS
EOBO E683 371 OUT 63H,AL I INITIALZE DMA PAGE REG
EOBZ BA0803 372 MOV OX.30SH
EOB5 EE 373 OUT OX,AL I DISABLE COLOR VIDEO
EOB6 FEeD 374 INC Al
EOB8 8288 37' I10V Cl,DBBH
EOBA EE 376 OUT OX.At I DISABLE B/W VIDEO,EN HIGH RES
EOBB 8099 377 MOV AL.99H I SET 8255 A.e-INPUT .S-OUTPUT
EOBO E663 376 OUT tHO_PORT,AL I WRITE 8255 tHO/MODE REG
EOSF BOFt 379 MOV AL,OFtH ; DISABLE PARITY CHECKERS AND
EOCI E661 360 OUT PORT_B,AL I GATE SNS SWS,CASS MOTOR OFF
Eoe3 8CC8 361 MOV AX,es ; SETUP SS SEG REG
EOt5 8EOD 382 MOV 55,AX
Eoe7 8E08 383 MOV OS,AX I SET UP QATA SEG TO POINT TO
384 I RON ADDRESS
38' ASSUME SS:CODE
Eoe9 B7EO 386 MOV BH.OEOH ; SETIJP STARTING ROS ADDR (EOOOO)
EOCB 6C16EO 387 MOV SP,OFFSET Cl I SETUP RETURN ADDRESS
EDCE E9780B 388 JMP ROS_CHECKSUM
EOOI 389 ell:
EOOI 750.4. 390 JNE ERROl I HALT SYSTEM IF ERROR
391 1----------------------------------------------------------------
392 82:37 DHA INITIALIZATION CHANNEL REGISTER TEST
393 I DESCRIPTION
394 DISABLE THE 8237 DHA CONTROLLER. VERIFY THAT TINER 1
39' FUNCTIONS OK. IomITEI'REAO THE CURRENT ADDRESS AND WORD
396 COUNT REGISTERS fOR ALL CHANNELS. INITIALIZE AND
397 START DHA FOR MEMORY REFRESH.
396 1----------------------------------------------------------------
E003 8004 399 MOV AL,04 ; DISABLE DHA CONTROLLER
EOD5 E608 400 OUT OMAoe,Al
401
402 ; ----- VERIFY THAT TIMER 1. FUNCTIONS OK
403
E007 6054 404 MOV Al.54H I SEl TINER I, LSB,MOOE 2:
E009 E643 40' OUT TIMER+3.AL
EOOS 8ACI 406 MaV AL,CL I SET INITIAL TIMER CNT TO 0
EODO E641 407 OUT TIMER+l,AL
EODF 408 C12: I TIMERl_BITS_DN
EODF 8040 409 MaV AL.40H I LATCH TIMER 1 COUNT
EOEI E643 410 OUT TIHER+3.AL
Eon 80FBFF 411 CMP BL.OFFH I YES - SEE IF ALL BITS GO OFF
EOE6 7407 412 JE C13 ; TIMERl_BITS_OFF
EOE8 E441 413 IN AL, TIMER+1 I READ TIMER 1 COUNT
EOEA OAD8 414 OR 8L,AL ; ALL BITS ON IN TIMER
EOEC E2Fl 41' lOOP C12 ; TIHERI_BITS_ON
EOEE ,4 416 HlT I TIMER 1 FAILURE. HALT SYS
EOEF 417 C13: I TIHERl_BITS_OFF
EOEF 8AC3 418 MaV AL,BL I SET TIMER 1 CNT
EOFl 2BC9 419 SUB CX,CX
EOF3 E641 420 OUT TIMER+l.AL
EOF5 421 C14: I TIMER_LOOP
EOF5 8040 422 MOV AL,40H I LATCH TIMER 1 COUNT
EOF7 E643 423 OUT TIMER+3.AL
EOF9 90 424 NOP I DELAY FOR TIMER
EOFA 90 425 NOP
EOFB E441 426 IN AL, TIMER+l I READ TIMER 1 COUNT
EOFO 2208 427 AND BL,AL
EOFF 7403 426 JZ C1' I GO TO WRAP_DHA_REG
EIOI E2F2 429 LOOP C14 ; TIMER_LOOP
EI03 F4 430 HlT I TIMER ERROR - HALT SYSTEH
431
432 1----- INITIALIZE TIHER 1 TO REFRESH HEMORY
433
EI04 434 CIS: I WRAP_DHA_REG
EI04 B012 435 MOV AL.18 I SETUP DIVISOR FOR REFRESH
EI06 E641 436 OUT TIMER+l,AL ; WRITE TIMER 1 CNT REG
EI06 E600 437 OUT DMA+ODH,AL ; SEND MASTER CLEAR TO DMA
438
System BIOS A-7

LaC OBJ LINE SOURCE
439 1----- WRAP OHA CH~ELS ADDRESS AND COUNT REGISTERS

440
EIOA BOFF 441 HOY At,OFFH ;0 WRITE PATTERN FF TO ALL REGS
EIOC 44, C16:
EIOC 8A08 44> HOY BL,Al I SAVE PATTERN FOR COMPARE
flOE 8AFS 444 MOY BH,AL
E110 890800 44S HOY eX,6 I SETUP lOOP tNT
E113 l8D2 44. sue oX,OX ; SETUP 110 PORT AOCR OF REG (0000)
EllS 447 e17:
EllS EE 448 OUT OX,Al ; WRITE PATTERN TO REG, LSB
£116 50 449 PUSH AX
E1l7 EE 450 OUT DX.AL I MSB OF 16 BIT REG
El18 880101 451 HOY AX.OIOIH ; AX TO ANOTHER PAT BEFORE RD
E1l8 EC 4,. IN AL,OX ; READ 16-BIT DHA CH REG, LSB
EUC 8AEO 453 MOY AH,Al ; SAVE lSB OF 16-BIT REG
EllE EC 454 IN AL,DX I READ "5B OF OMA CH REG
EllF 3806 455 C"P aX,AX I PATTERN READ AS WRITTEN?
E121 7401 45. J' C18 I YES - CHECK NEXT REG
E123 F4 457 HLT I NO - HALT THE SYSTEM
£124 458 C18: I NXT_DMA_CH
E124 42 459 INC OX I SET I/O PORT TO NEXT CH REG
E125 E2EE 4.0 LOOP C17 ; WRITE PATTERN TO NEXT REG
E127 FEtD 4.1 INC AL I SET PATTERN TO 0
£129 74El 4.' JZ C1. I WRITE TO CH.t.t+-IEl REGS
463
4.4 ;----- INITIALIZE AND START OMA FOR MEMORY REFRESH.
4.5
E128 8EOB 4 •• HOY OS,BX ; SET UP ABSO INTO as AtIl ES
E120 SEC3 4.7 HOY ES,6X
4.8 ASSUHE os: .1.650. ES:ABSO
4.9
El2:F BOFF 470 MOY At.OFFH l SET CNT OF 64K FOR RAM REFRESH
E131 E601 471 OUT DHA+l,At
E133 50 472 PUSH AX
E134 E601 473 OUT DMA+l.AL
E136 B20B 474 HOY DL,OBH I OX=0006
E138 BOS8 475 HOY At.058H J SET DHA MOOE,CH O.READ,AUTOINT
E13A EE 47. OUT OX,AL I WRITE OMA MODE REG
El3B BOOO 477 MOV AL.O ; ENABLE DMA CONTROLLER
E130 £608 478 OUT DMA+8.AL ; S~TUP OMA CQMHAHD REG
E13F 50 479 PUSH AX
E140 E60A 480 OUT DHA+I0.AL ; ENABLE CHANNEL 0 FOR REFRESH
El42 B103 481 MOY CL.3
E144 8041 48' HOY AL,41H 1 SET HODE FOR CHANNE L 1
El46 483 CI8A:
El46 EE 484 OUT DX.AL
E147 FECO 485 INC AL I POINT TO NEXT CHANNEL
E149 E2FB 48. LOOP CIBA
487 1- - - - - -- - --- --- - - - - -- -- - - - -------- --- -- - ------ --- ----- -- -- -- -- -.-
488 I BASE 16K REAOIWRITE STORAGE TEST
48. I DESCRIPTION
4'0 WRITEIREAD/vERIFY DATA PATTERNS FF.55.AA,Ol. AND 00
491 TO 1ST 16K OF STORAGE. VERIFY STORAGE ADDRESSABILITY.
49' INITIALIZE THE B259 INTERRUPT CONTROLLER CHIP FOR
4'3 CHECKING MANUFACTURING TEST 2 MODE.
494 ; ----------.----_._---- .. ----------------------------------------
495
49. j----- DETERMINE MEMORY SIZE AND FILL MEMORY WITH DATA
497
E14B BA1302 498 HOY DX,0213H 1 ENABLE EXPANSION BOX
E14E B001 4'9 HOY AL.OlH
E150 EE 500 OUT DX.Al
ElSI BS2E72:04 501 HOY BP ,DATA_WORD{ OFFSET RESET_F LAG] J SAVE 'RESET_flAG' IN SP
E155 BIFD3412 50, C"P BP.1234H ; WARM START?
E159 740A 503 J" CIBB ; BYPASS STG TST.
ElSB BC41F090 504 HOY 5P.OFF5ET C2
E15f E986fE 505 JMP STGT5T
E162 50. C24:
E162 7401 507 J' CIBS ; PROCEED IF 5TGTST OK
E164 f4 508 HLT ; HALT IF NOT
E165 509 CIBS:
E165 2BFF 510 SUB CI.DI
E167 E460 511 IN AL,PORT_A I DETERMINE BASE RAM SIZE
E169 240C 5" AND AL,OCH I ISOLATE RAM SIZE SWS
E168 0404 513 ADD AL, 4 I CALCULATE MEMORY SIZE
E16D BlOC 514 MOY CL, 12
A-8 System BIOS

LOC OBJ LINE SOURCE
E16F 03£0 515 SHL AX. CL

EI7l 88C& 516 HOV ex. AX
E173 Fe 517 OLD , SET DIR FLAG TO INtR
E174 518 C19:
E174 AA 51' SIOSB ; FILL BASE RAM WITH DATA
E175 E2FD 520 lOOP C19 ; LOOP TIL ALL ZERO
fl77 892E7204 521 HOV OATA_WORO[OFFSET RESETJLAGJ.BP
522
523 1----- DETERMINE 10 CHANNEL RAM SIZE
524
El7B SOFa 525 MOV AL,OF8H , ENABLE SWITCH 5
El7D E661 52. OUT PORT_B,AL
E17F E462 527 IN AL,PORT_C ; READ SWITCHES
El81 2401 528 AND AL.OOOOOOOIB ; ISOLATE SWITCH 5
E183 BlOC 52. MOV CL,l20
E185 03CO 530 ROL AX,CL
EI87 BOFt 5Jl HOV AL,OFCH I DISABLE SW. 5
E189 E661 532 OUT PORT_B,AL
E 188 E462: 533 IN AL,PORT_C
EleD 240F 534 AND AL,OFH
fIeF OAC4 535 OR AL,AH ; COMBINE SWITCH VALUES
fI9l BAD8 536 HOV BL,AL ; SAVE
E193 6420 537 MOV AH,32
EI95 F6E4 53B HUL AH , CALC. LENGTH
E197 A31504 53' HOV DATA_WORD I OFFSET IO_RAM_SIZE I,AX ,SAVE IT
E19A 7418 540 JZ 021
E19C BADOIO 541 HOV DX,IOOOH , SEGMENT FOR I/O RAM
E19F BAED 542 MOV AH,AL
EIAI BODO 543 MOV AL,O
EtAJ 544 C20: FILL..IO:
EtA] 8EC2 545 MOV ES,OX
ElAS 890080 546 HOV eX.BOOOH FILL 32K BYTES
flAB 2BFF 547 SUB 01,01
ElAA F3 548 REP STOSB
ElAB AA
ElAC 81C20008 54' ADO OX,BOOH ; NEXT SEGMENT VALUE
ElBO FEes 550 DEC BL
E182 75EF 551 JNZ 020
552 ;----------------------------------------------------------------
553 INITIALIZE THE 8259 INTERRUPT CONTROLLER CHIP
554 i ------------------------------------------ ----------------------
EIB4 555 C21:
EIB4 8013 55. HOV AL,13H ; ICWI - EDGE, SNGL, ICW4
ElB6 E&20 557 OUT INTAOO,AL
EIB8 B008 558 HOV AL,8 I SETUP ICW2 - INT TYPE 8 (8-F I
ElBA E621 55' OUT INTAOl,AL
EISC 8009 5.0 HOV AL,9 ; SETUP ICW4 - eUFFRO,8086 MODE
ElSE E621 561 OLT INTAOl,AL
EICO 28tO 5.2 SUB AX,AX I POINT ES TO BEGIN
EIC2 BEtD 563 HOV ES,AX ; OF RIW STORAGE
564 ; ---------------------------------------------------------------------------
565 CHECK FOR MAWFACTURING TEST 2 TO LOAD TEST PROGRAMS FROM KEYBOARD.:
566 ; ---------------------------------------------------------------------------
567
568 ; ----- SETUP STACK SEG AND SP
56'
EIC4 B83000 570 MOV AX,STACK ; GET STACK VALUE
EIC7 8EOO 571 HOV S5,AX I SET THE STACK UP
EIC9 BCOOOI 572 MOV SP. OFFSET TOS ; STACK IS READY TO GO
Elee BIFD3412 573 OHP BP,1234H ; RESETJLAG SET?
ElDO 7425 574 JE 025 I YES - SKIP MFG TEST
fl02 2BFF 575 SUB 01,01
EI04 BEDF 576 HOV OS, 01
flD6 682400 577 HOV ex, 24H
EI09 C70747FF 57B MOV WORD PTR {BXl,OFFSET 011 ; SET UP KB INTERRUPT
EIDO 43 57' INC BX
flOE 43 580 INC ax
flOF BeOF 581 MOV [BXI,CS
E1El E85F04 5B2 CALL KBD_RESET ; READ IN KB RESET CODE TO Bl
EIE4 eDfB65 5B3 CMP BL,065H ; IS THIS MANUFACTURING TEST 2?
EIE7 750E 5B. JNZ C25 ; JUMP IF NOT NAN. TEST
EIE9 BUF 585 MOV DL,255 I READ IN TEST PROGRAM
ElEB 58. C22:
flEe E86204 587 CALL SP _TEST
flEE BAC3 588 MOV AL.Bl
ElFO AA 58. STOSS
System BIOS A-9

LOC OBJ LINE SOURCE
EIFl FECA 590 DEC OL

Eln 75F6 591 JNZ CZ< I JUMP IF NOT DONE YET
EIFS COlE 592 INT lEH I SET IHTERRUPT TYPE 62 ADDRESS F8H
EIF7 593 C25:
594
595 ;----- SET UP THE BIOS INTERRUPT VECTORS TO TEMP INTERRUPT
596
EIF7 892000 597 HOV CX.32. j FILL ALL 32 INTERRUPTS
ElFA 2BFF 598 sue 01,01 I fIRST INTERRUPT LOCATOIN
ElFC 599 03:
ElFC B847FF 600 HeV AX,OFFSET 011 , MOVE ADoR OF INTR PROC TO TBL
EIFF AB 601 STOSW
E200 ecce 602 HOV AX.CS , GET ADDR OF INTR PROC SEG
E202 AB 603 STOSW
E203 E2F7 604 LOOP D3 j VECTBLO
605
606 1----- SET UP OTllER INTERRUPTS AS NECESSARY
607
E205 C7060800C3E2 608 HOV NMI_PTR,OFFSET NMI_INT j NMI INTERRUPT
E20B C706140054FF 609 HOV IHTS_PTR,OFFSET PRINT_SCREEN ; PRINT SCREEN
E211 C70662:DOOOF6 610 HOV BASIC]TR+2.,OF600H ; SEGMENT FOR CASSETTE BASIC
611
612 1------- - - - -- --- - -- - - - - ------- ------- - - --- - --- ---- - ---- --- -- -----
613 8259 INTERRUPT CPHTROLlER TEST
614 ; DESCRIPTION
615 REAOIWRITE THE INTERRUPT MASK REGISTER IIMR} WITH ALL
616 ONES AND ZEROES. ENABLE SYSTEM INTERRUPTS. MASK DEVICE:
617 INTERRUPTS OFF. CHECK FOR HOT INTERRUPTS (UNEXPECTEDI. :
618 ,----------------------------------------------------------------
619
62.0 ;----- TEST THE IMR REGISTER
621
E217 8A2:IOO 622 HOV DX.OO21H j POINT INTR. CHIP AODR. 21
E2lA BODO 623 HOV AL.O J SET IHR TO ZERO
EHC EE 624 OUT OX,Al
E2:10 EC 625 IN AL,OX j READ IHR
EllE DACO 626 OR AL.AL ; INR = O?
E220 7515 627 JNZ 06 j GO TO ERR ROUTINE IF HOT 0
E222 BOFF 628 HOV AL.OFFH I DISABLE DEVICE INTERRUPTS
E224 EE 629 OUT DX,AL ; WRITE TO II'fR
E225 EC 630 IN AL,OX ; READ II1R
E226 0401 631 AOO AL.I ; ALL 111R BIT ON?
E228 7500 632 JNZ 06 ; NO - GO TO ERR ROUTINE
633
634 j----- CHECK FOR HOT INTERRUPTS
635
636 ;----- INTERRUPTS ARE MASKED OFF. CHECK THAT NO INTERRUPTS OCCUR.
637
E22:A 32E4 638 XOR AH,AH j CLEAR AH REG
E22C FB 639 STI ; ENABLtI EXTERNAL INTERRUPTS
E220 2BC9 640 SUB CX,CX ; WAIT 1 SEC FOR ANY INTRS THAT
E22F 641 04:
E22F E2FE 642 LOOP 04 , MIGHT OCCUR
[231 643 05:
E231 E2FE 644 LOOP 05
E233 0.4.E4 645 OR AH,AH , DID ANY INTERRUPTS OCCUR?
E235 7408 646 JZ 07 ; NO - GO TO NEXT TEST
E237 647 06:
En7 BAOIOI 648 HeV DX.I01H j BEEP SPEAKER IF ERROR
E23A E89203 649 CAll ERR_BEEP ; GO TO BEEP SUBROUTINE
E230 FA 650 CLI
E23E F4 651 HLT , HALT THE SYSTEM
652 I - ----- - - - - ---- - -- - - - ----- ----- ---- -- - ----- ------
653 8253 TIMER CHECKOUT
654 ; DESCRIPTION
655 VERIFY THAT THE SYSTEM TIMER (0)
656 DOESH' T COUNT TOO FAST OR TOO SLOW.
657 1------------------------------------------------
E23F 658 07:
E2.3F BOFE 659 HOV AL.OFEH ; MASK ALL INTRS EXCEPT lVl 0
E2.41 EE 660 O\JT DX,Al I WRITE THE 82.59 IHR
E242 BOlO 661 HOV AL,OOOIOOOOB J SEl TIM 0, LSB. NOOE O. BINARY
E244 E643 002 OUT TIM_CTL,AL I WRITE TIMER CONTROL MODE REG
E2:46 B91600 663 tIOV CX,16H , SET PGM LOOP CNT
E2:49 8ACI 664 NOV Al,CL J SET TIMER 0 CHT REG
E2:4B E640 665 OUT TIMERO,Al J WR:j:TE TIMER 0 CNT REG
A-lO System BIOS

LOC OBJ LINE SOURCE
E240 666 08:

E240 FbC4FF 667 TEST AH.OFFH I DID TIMER 0 INTERRUPT OCCUR?
E250 7504 668 JHZ 09 J YES - CHECK TIMER OP FOR SLOW TIME
E2:52 E2F9 669 LOOP 08 I !<IAIT FOR INTR FOR SPECIFIED TIME
E2:54 EBEI 670 J"P 06 J TIMER 0 INTR DIDN'T OCCUR - ERR
E2:56 671 09:
E256 9112 672 HOV CL,lS I SET PGM LOOP eNT
E2:58 BOFF 673 "OV At,OFFH I WRITE TIMER 0 CNT REG
E25A E640 674 OUT TlHERO,AL
E2se e8FEOO 67' "OV AX,OFEH
E25F EE 676 OUT OX.At
E2:60 677 010:
E260 F6C4FF 67& TEST AH.OFFH , DID TIMER 0 INTERRUPT OCCUR?
E263 7502: 679 JHZ 06 J YES - TIMER CNTING TOO FAST, ERR
E2:65 E2F9 680 lOOP 010 I WAIT FOR ItrrR FOR SPECIFIED TIME
6&1
6&2 1----- ESTABLISH BIOS SUBROUTINE CALL INTERRUPT VECTORS
6&3
E267 IE 684 PlSH OS I SAVE POINTER TO DATA AREA
E268 BF4000 68. "OV 01,OFFSET VIDEO_INT ; SETUP ADDR TO INTR AREA
E2:68 DE 6&6 PlSH CS
E26C If 687 POP OS , SETUP ADDR OF VECTOR TABLE
E2:60 BE03FF90 68& "OV SI,OFFSET VECTDR_TABlE+l6 I START WITH VIDEO ENTRY
E2:71 891000 689 MOV CX,I6
690
691 ;----- SETUP TIMER 0 TO MODE 3
692
E2:74 BOFF 693 MOV AL,OFFH I DISABLE ALL DEVICE INTERRUPTS
E2:76 EE 694 OlIT OX,AL
E2:77 B036 69. MOV AL,36H ; SEL TIM O,LSB,I1SB,MODE 3
E2:79 E643 696 OUT TIHER+3,AL ; WRITE TIMER MODE REG
E2:78 BODO 697 "OV AL,O
E2:7D E640 69& OUT TIMER,AL • WRITE LSB TO TIMER 0 REG
E2:7F 699 EIA:
E2:7F AS 700 MOVSW f HOVE VECTOR TABLE TO RAM
E2:80 47 701 INC 01 ; MOVE PAST SEGMENT POINTER
E2:81 47 702 INC 01
E2:82 E2:FB 703 LOOP ElA
E284 E640 704 OUT TIMER,AL I WRITE I1SB TO TIMER 0 REG
E286 IF 70' POP OS I RECOVER DATA SEG POINTER
706
707 ;----- SETUP TIMER 0 TO BLINK LED IF MANUFACTURING TEST MODE
708
E287 E8B903 709 CAll KBD_RESET I SEND SOFTWARE RESET TO KEYBRO
E28A 80FBAA 719 C"P BL,OAAH I SCAN CODE • AA' RETURNED?
E2:8D 741E 711 JE E6 ; YES - CONTINUE (NON HFG HOOE)
E28F B03C 712 "OV AL.3CH I EN KBD. SET KBD CLK LINE LOW
E291 E661 713 OUT PORT_B.AL ; WRITE 8255 PORT B
E293 90 714 NOP
E294 90 71' NOP
E295 E460 716 IN AL,PORT_A I WAS A BIT CLOCKED IN?
E297 24FF 717 AtIll AL,OFFH
E299 750E 71& JNZ E2 I YES - CONTINUE (NON HFG MODE)
E298 FE061Z04 719 INC DATA_AREA[OFFSET MFG_TSTJ ; ELSE SET SW FOR MFG TEST HOOE
E29F C7062:0006DE6 720 MOV INT_ADDR.OFFSET BLINK.....INT I SETUP TIMER INTR TO BLINK LED
E2:A5 BOFE 721 MOV Al,OFEH ; ENABLE TIMER INTERRUPT
E2A7 E621 722 OUT INTAOl,AL
E2A9 723 £2:: 1 JUHPER_NOT_IN:
E2A9 BOCC 724 "OV AL.DCCK ; RESET THE KEYBOARD
E2AB E661 725 OUT PORT_B,AL
726
7" ;--------------------------------------------------------
,,& INITIALIZE AND START CRT CONTROllER (6845)
"9 TEST VIDEO REAO/WRITE STORAGE.
730 ; DESCRIPTION
731 RESET THE VIDEO ENABLE SIGNAL.
732 SELECT ALPHANUMERIC MODE. 40 * 25. B & W.
733 REAOIWRITE DATA PATTERNS TO STG. CHECK STG
734 ADORESSABILITY.
735 1--------------- -- - - - -- - - - ---- ------ - - ---- - --------------
E2AD 736 £6:
E2AD E460 737 IH Al.PORT_A I READ SENSE SWITCHES
E2AF B400 738 MOV AH.O
E2Bl A31004 739 "OV DATA_WORD[OFFSET EQUIPJLAG),~X I STORE SENSE SW INFO
E2:B4 740 E6... :
E2B4 2430 741 AND AL,30H I ISOLATE VIDEO SillS
E256 7529 742 JNZ E7 1 VIDEO SWS SET TO 01
System BIOS A-ll

LOC OBJ LINE SOURCE
E2B8 C7064000S3FF 74, MOV

E,BE E9.6.200 744 JMP ; SKIP VIDEO TESTS FOR BURN-IN
745
E2C3 74. OR. OElC3H
He] 747 t"lI_INT PROC NEAR
E2C3 50 746 PUSH AX I SAVE ORIG CONTENTS OF AX
E2(4 E462 749 IN AL,PORT_C
E2C6 A6CO 750 TEST Al, OCOH ; PARITY CHECK?
EZCB 7415 751 JZ 014 I NO, EXIT FROM ROUTINE
EleA BEOAFF90 752 HOV SI. OFFSET 01 ; AOOR OF ERROR MSG
ElCE .6.840 753 TEST Al,40H ; I/O PARITY CHECK
E2DO 7504 754 JNZ DB I DISPLAY ERROR MSG
E202 BE23FF90 755 MOV 51 ,OFFSET DZ ; MUST BE PLANAR
E206 75. 013:
E206 2BCO 757 SUB AX,AX ; INIT AND SET MOOE FOR VIDEO
E208 COlO 756 INT 10H ; CALL VIDEO_IO PROCEDURE
E,DA E8Do03 759 CALL P_MSG ; PRINT ERROR MSG
ElDD fA 7.0 eLI
ElOE F4 7.1 HLT ; HALT SYSTEM
E20F 7., 014:
E,OF 58 7., pop AX I RESTORE ORIG CONTENTS OF AX
E2EO CF 764 IRET
E2El 7 •• E7: i TEST_VIDEO:

E2El 3e30 707 eMP AL,30H ; B/W CARD ATIACHED?
E2E3 7408 7'6 JE E8 ; YES - SET MODE FOR B/w CARD
E2E5 fEC4 7.9 INC AH ; SET COLOR MODE FOR COLOR CD
E2E7 X2D 770 eMP AL,20H ; 60X25 MODE SElECTED?
E2E9 7502 771 JHE E6 ; NO - SET MODE FOR 40X25
ElEB 8403 77' MOV AH.3 I SET MODE FOR 80X25
E2:ED 77' E8:
EZEO 86EO 774 XCHG AM,AL ; SET_MODE
EZEF 50 775 PUSH AX ; SAVE VIDEO HODE ON STACK
E2FO 2AE4 77. SUB AH,AH ; INITIALIZE TO ALPHAHUt1ERIC I1D
ElF2 COlO 777 IHT 10H i CALL VIDEO_IO
E2F4 58 776 POP AX ; RESTORE VIDEO SENSE SWS IN AH
ElFS 50 779 PUSH AX I RESAVE VALUE
E2FEo S80080 760 MOV BX,OBOOOH ; BEG VIDEO RAM ADoR B/w CD
E2F9 8A6803 761 MOV OX,398M ; MODE REG FOR B/Jol
E2Fe 890010 76' MOV CX.4096 ; RAM BYTE CNT FOR B/W CO
E2FF 8001 76' NOV AL.l ; SET MODE FOR BW CARD
£301 60FC30 764 CMP AH,30H I B/W VIDEO CARD ATTACHED?
£304 7408 765 JE E9 I yes - GO TEST VIDEO STS
E306 87BB 76' HOV BH,OB8H ; BEG VIDEO RAM ADDR COLOR CD
E308 8208 767 MOV OL,OD8H ; MODE REG FOR COLOR CD
E30A 8540 766 MOV CH,40H I RAM BYTE CNT FOR COLOR CD
noe FECB 769 OEC AL I SET HOOE TO 0 FOR COLOR CO
ElOE 790 E9: ; TEST_VIDEO_STG:
nOE EE 791 OUT DX,AL ; DISABLE VIDEO FOR COLOR CO
E30F BIFD3412 792 CMP BP.IZ34H ; POD INITIATED BY KBD RESET?
E313 8EC3 795 HOV ES,BX ; POINT ES TO VIDEO RAM STG
£315 7407 794 JE EIO ; YES - SKIP VIDEO RAM TEST
£317 8E08 795 HOV OS, BX ; POINT OS TO VIDEO RAM STG
79. ASSUME OS: NOTHING. ES: NOTHING
E319 E8FFFC 797 CALL STGTST_CNT I GO TEST VIDEO R/W STS
niC 7532 796 JHE El7 ; R/Jol STG FAILURE - BEEP SPK
799 1----------------------------------------------------------------
600 I SETUP VIDEO DATA ON SCREEN FOR VIDEO LINE TEST.
801 ; DESCRIPTION
802 ENABLE VIDEO SIGNAL ANO SET MODE.
803 DISPLAY A HORIZONTAL BAR ON SCREEN.
604 1----------------------------------------------------------------
E31E 605 EIO:
E31E 58 60. POP AX I GET VIDEO SENSE SWS (AH)
E31F 50 607 PUSH AX I SAVE IT
£320 8400 806 MOV AH.O I ENABLE VIDEO AtI) SET MODE
£322 COlO 609 INT 10M I VIDEO
E324 B82070 610 HOV AX.7020H ; WRT BLANKS IN REVERSE VIDEO
E327 2BFF 611 SUB 01.01 I SETUP STARTING LOC
E329 892800 612 HOV CX.40 i NO. OF BLANKS TO DISPLAY
E32C F3
E320 AB
6" REP STasw I WRITE VIDEO STORAGE
814 ; ------------------------------------------- -------------

815 CRT INTERFACE LINES TEST
816 ; DESCRIPTION
817 SENSE ON/OFF TRANSITION OF THE VIDEO ENABLE
A-12 System BIOS

LOC OSJ LINE SOURCE
818 AND HORIZONTAL SYNC LINES.

819 I - - ------ --------- - ----------- ------- --- --- --- - - - ---- ----
E32E 58 8" pop AX ; GET VIDEO SENSE SW INFO
E32:F 50 821 PUSH AX ; SAVE IT
E330 aOFC30 822 eMP AH,30H ; BIN CARD ATTACHED?
E333 BABAD3 823 MOV OX,03SAH I SETUP AOoR OF ew STATUS PORT
E336 7402 824 JE Ell ; YES - GO TEST LINES
E338 BlDA 825 MOV al,OOAH ; COLOR CARD IS ATTACHED
E33A 82. Ell: I LINE_1ST:
E33A 8408 827 MaV AH,B
E33C 828 E12: I OFLOOP_CNT:
E33C 2:BC'il 829 SUB CX,CX
E33E 830 En:
E31E EC 831 IN AL,OX I READ CRT STATUS PORT
E33F 22C4 832 AND Al,AH I CHECK VIDEOIHORZ LINE
E341 7504 8" JHZ E14 I ITS ON - CHECK IF IT GOES OFF
£343 E2F9 834 LOOP E13 ; LOOP TILL ON OR TIMEOUT
E345 EB09 835 JMP SHORT E17 I GO PRINT ERROR MSG
E347 83. E14:
£347 2BC9 837 SUB eX,ex
1:349 838 1:15:
E349 EC 839 IN AL,OX I READ CRT STATUS PORT
E34A 2:2C4 840 ANO AL,AH I CHECK VIDEO/HORZ LINE
E34C 7404 841 JZ E1. I ITS ON - CHECK NEXT LINE
E34E E2F9 842 LOOP E15 LOOP IF OFF TIll IT GOES ON
E35D 843 E17: , CRT_ERR
E350 BA0201 844 MOV DX,l02H
E353 E87902 845 CALL ERR_8EEP ; GO BEEP SPEAKER
E356 EB06 84. JMP SHORT E18
E358 847 El6: f NXT_LINE
E358 B103 848 MOV CL,3 I GET NEXT BIT TO CHECK
E35A 02:EC 849 SHR AH,CL
E35C 75DE a50 JHZ E12 • GO CHECK HORIZONTAL LINE
E35E 851 E18: , DISPLAY_CURSOR:
E35E 58 852 POP AX ; GET VIDEO SENSE SWS (AM)
E35F B400 853 MOV AH,D ; SET HaDE AND DISPLAY CURSOR
E361 COlO 854 'NT IOH i CAll VIDEO I/O PROCEDURE
855
E363 85. EI8_1:
E363 BAOOCO 857 MOV DX,OCOOOH
£366 858 E18A:
£366 BEDA 859 MaV DS,DX
E368 2BDB 8.0 SUB BX,BX
E36A 8B07 8.1 MOV AX,laXJ I GET FIRST 2: LOCATIONS
E36C 53 8.2 PUSH BX
E36C 5B a.3 POP BX ; LET BUS SETTLE
E36E 3C55AA 8.4 eMP AX,OAAS5H J PRESENT?
E371 7505 8.5 JHZ E18B j HO? GO LOOK FOR OTHER t10DULES
E373 E80E03 8 •• CALL ROM_CHECK I GO SCAN MODULE
£376 EB04 8.7 JMP SHORT E18C
E378 8.8 E18B:
E378 81C2800C 8.9 ADO DX,0080H I POINT TO NEXT 2K BLOCK
E37C 870 E18C:
E37C 81FAooea 871 eMP OX,DeaoaH I TOP OF VIDEo ROH AREA YET?
E380 7CE4 a72 JL El8A ; GO seAN FOR ANOTHER MODULE
873 ;----------------------------------------------------------------
874 I EXPANSION I/O BOX TEST
a75 CHECK TO SEE IF EXPANSION BOX PRESENT - IF INSTALLED,
87. TEST DATA AND ADDRESS BUSES TO 1/0 BOX.
877 ; ERROR='180l'
878 1----- - ---- - -------- ------ -- --- - - - - - - - - - - - ----- ----- - -- - - ---- ----
879
880 ; ----- DETERMINE IF BOX IS PRESENT
881
E382: 882 EXP_10: , (CARD WAS ENABLED EARLIER)
E382: 8,6,1002: 883 MOV DX,0210H I CONTROL PORT ADDRESS
E385 B85555 884 MaV AX,5555H i SET DATA PATTERN
E388 EE 885 01lT DX,At
£389 BOOI 88. MOV AL,OlH
E38B EC 887 'H AL,DX J RECOVER DATA
E38C 3AC4 888 eMP AL,AH I REPLY?
E38E 7534 889 JHE E19 I NO RESPONSE, GO TO NEXT TEST
E390 F7QO 890 HOT AX f HAKE DATA=AAAA
E392: EE 891 01lT DX,Al
El9] aOOl a92 MaV AL,OlH
E395 EC 8" 'H AL,OX I RECOVER DATA
E396 ]AC4- a.. C11P Al,AH
System BIOS A-13

LOC OBJ LINE SOURCE
E398 752.4. 895 JHE £19 I NO AHSWER=NEXT TEST

896
897 ;----- CHECK ADDRESS AND DATA BUS
898
E39A 899 EXPl:
E39.4. 8608 900 MOV BX,AX
E39C BA1402 901 MaV OX,OZ14H I LOAD DATA REG ADDRESS
E39F 2E8807 902 MOV cs:[eX],Al I WRITE ADDRESS FOOOO+BX
E3A2 EE 903 OUT DX.AL I WRITE DATA
E3.4.3 90 904 HOP
E3.4.4 EC 905 IN AL,OX I READ DATA
E3AS 3AC7 90. CMP AL,BH
EJ.A.7 7514 907 JHE EXP _ERR
nA9 42 908 INC ox ; DX=Z ISH (ADDR. HI REG I
E3AA EC 909 IN AL,DX
nAB 3AC4 910 CMP AL.AH I COMPARE TO HI ADDRESS
nAD 750£ 911 JHE EXP _ERR
E3AF 42 912 INC ox ; DX-Z16H {AODR. LOW REG)
f3BD EC 913 IH Al.DX
nBI 3AC4 914 CMP AL,AH ; ADDR. LOW OK?
BBl 7508 915 JHE EXP _ERR
nBS F700 916 HOT AX I INVERT AX
BB7 3CAA 917 CMP AL,OAAH ; BACK TO STARTING VALUE CUAA I YET
E3B9 7409 918 JE £19 ; GO ON TO NEXT TEST IF SO
ElBB EBOD 919 JMP EXPI ; LOOP BACK THROUGH WITll DATA OF 5555
nBD 920
E3BD BEEDFE90 921 MOV 51. OFFSET F3B
E3el E8F6.02 922 CAll P_MSG
9Z3 J ----------------------------------------------------------------
924 ADDITIONAL READ/WRITE STORAGE TEST
925 ; DESCRIPTION
926 WRITEI'READ DATA PATIERNS TO ANY READ/WRITE STORAGE
927 AFTER THE BASIC 16K. STORAGE ADDRESSABILITY IS CHECKED.
928 ;----------------------------------------------------------------
929 ASSUME DS:DATA
E3e4 930 E19:
931
932 ;----- DETERMINE RAM SIZE ON PLANAR BOARD
933
Be4 E87718 934 CALL DDS
nC7 AOI000 935 MOV AL.BYTE PTR EQUIP]LAG I GET SENSE SWS INFO
BeA 240C 936 AHil AL,OtH ; ISOLATE RAM SIZE SWS
nee 8404 937 MOV AH.4
neE F6E4 938 NUL AH
noD 0410 939 ADO AL.16 I ADD BASIC 16K
£302 8BOO 940 MOV OX.AX ; SAVE PLANAR RAM SIZE IN ox
E304 8B08 941 MOV
942
943 J ----- DETERMINE 10 CHANNEL RAM SIZE
944
E306 A11500 945 NOV I GET 10 CHANNE l RAM SIZE
E309 83FB40 946 CMP BX.40H ; PLANAR RAM SIZE::: 64K?
noe 7402
E30E 28CO
947
948
JE
SUB
"0
AX,AX
; YES - ADD 10 CHN RAM SIZE
; NO - DON'T ADD ANY 10 RAM
nED 949 E20:
E3EO 0"3e3 950 ADO AX,BX I SUM TOTAL RAM SIZE
E3E2 A31300 951 MOV MEMORY_SIZE,AX ; SETUP MEMORY SIZE PARM
E3£5 81FD3412 952 CMP BP.1234H ; POD INITIATED BY KBD RESET?
nE9 IE 953 PUSH OS ; SAVE DATA SEGMENT
nEil. 744F 954 JE TSTl2 ; YES - SKIP MEMORY TEST
955
956 1----- TEST ANY OTHER READIWRITE STORAGE AVAILABLE
957
E3Ee 880004 958 MOV BX,400H
E3EF B91000 959 MOV tX,16
ElFl 960 EZ1:
E3F2 3801 961 CMP OX,CX 1 ANY MORE STG TO BE TESTED?
E3F4 7620 962 JBE "3 ; NO - GO TO NEXT TEST
E3F6 8E08 963 MOV OS,BX ; SETUP STG ADOR IN OS Mil ES
E3FB 8EC3 964 MDV ES,BX
E3FA 6leIlO 965 ADD CX,16 I INCREMENT STG BYTE COUNTER
E3FD 81C30004 966 ADD BX.400H ; SET POINTER TO NEXT 16K BlK
E401 51 967 PUSH CX I SAVE REGS
E402 53 968 PUSH ex
E403 52 969 PUSH OX
E404 E811Ft 970 tAll STGTST ; GO TEST A. 16K BlK OF STG
E407 SA 971 POP OX
A-14 System BIOS

LOC OBJ LINE SOURCE
E408 58 972 POP ex • RESTORE REGS

E409 59 973 POP ex
E40A 74E6 974 J' ,,1 I CHECK IF I'IORE STG TO TEST
97S
976 1----- PRINT FAILING ADDRESS AND XOR'ED PATTERN IF DATA COMPARE ERROR
977
E40C aCDA 978 MOV DX,OS ; COtNERT FAILING HIGH-ORDER
E40E 8Af8 979 HOV CH.AL I SAVE FAILING BIT PATTERN
E410 8AC6 980 HOV AL,DH I GET FAILING ADOR
E412. f81002 981 CALL XPC_BYTE J CONVERT ANO PRINT CODE
E415 8AC5 982 HOV AL.CH ; GET FAILING BIT PATTERN
E417 f8DB02 98' CALL XPC_BYTE ; CONVERT AND PRINT CODE
E41A BE67FA90 984 MOV SI.OFFSET El ; SETUP ADDRESS OF ERROR MSG
E41E E89902 98S CALL P_MSG ; PRINT ERROR MSG
E421 98. E22:
E421 E818 987 JMP SHORT TST12 ; GO TO NEXT TEST
E423 988 E23: ; STG_TEST_DONE
E42:3 IF 989 POP OS I POIHT OS TO DATA SEGMENT
E424 IE 990 PUSH OS
E425 86161500 991 HOV OX, IO_RAM_SIZE ; GET 10 CHANNEL RAM SIZE
E429 OB02 992 OR OX,DX ; SET FLAG RESULT
E42B 740E 99' JZ TSTl2 ; NO !O RAM. GO TO NEXT TEST
E420 890000 994 HOV CX,O
E430 aIFBDOIO 99S CHP BX,lOOOH I HAS 10 RAM BEEN TESTED
E434 7705 996 JA TSTI2 ; YES - GO TO NEXT TEST
E436 B80010 997 HOV BX.IOOOH I SETUP BEG LaC FOR 10 RAM
E439 EBB7 998 JMP E21 ; GO TEST 10 CHANNEL RAM
999 1----------- ---- ----- - - - ------------- - - - -- - ---- -- - - - - -- --
1000 I KEYBOARD TEST
1001 ; DESCRIPTION
1002: RESET THE KEYBOARD ANO CHECK THAT SCAN CODE
1003 'M' IS RETURNED TO THE CPU. CHECK FOR STUCK
1004 KEYS.
1005 ; --------------------------------------------------------
100b ASSUME DS:DATA
E43B 1007 TSTl2:
E438 IF 1008 POP D.
E43C 603E120001 1009 eMP MfG_TST.l ; MANUFACTURING TEST MODE?
E441 742.0. 1010 J' F7 ; YES - SKIP KEYBOARD TEST
E443 E8FDOl 1011 CALL KBD_RESET ISSUE SOFTWARE RESET TO KEYBRD
E446 ElIE 1012 JCXZ Fb PRINT ERR MSG IF NO INTERRUPT
E448 B040 1013 MOV AL.40H I ENABLE KEYBOARD
E44A E661 1014 OUT PORT_B,AL
E44C aOFBAA 1015 CHP BL.OAAH I SCAN CODE AS EXPECTED?
E44F 7515 1016 JNE F6 ; NO - DISPLAY ERROR MSG
1017
1018 ;----- CHECK FOO STUCK KEYS
1019
E451 Boce 102:0 MaV AL.OCCH I elR KBD, SET CLK LINE HIGH
E453 E661 102:1 OUT PORT_B.AL
E455 B04e 102:2: MDV AL,4CH I ENABLE KBD.CLK IN NEXT BYTE
E457 E661 102:3 OUT PORT_B,AL
E459 28C9 1024 SUB CX.CX
E458 102:5 F5: I KBD_WAIT
E45B E2FE 102:b lOOP F5 ; DELAY FOR A WHILE
E450 E460 1027 I CHECK FOR STUCK KEYS
E45F 3COO 1028 CHP AL.O ; SCAN CODE = O?
E461 740.0. 1029 JE F7 ; YES - CONTINUE TESTING
E463 E8BFDI 1030 CALL XPC_BYTE ; CONVERT AND PRINT
E466 BE33FF90 1031 MOV 51 ,OFFSET Fl I GET MSG AODR
E46A E84002 1032 CAll P_MSG ; PRINT MSG ON SCREEN
1033
1034 ;----- SETUP IHTERRUPT VECTOR TABLE
1035
E460 103b F7:
E460 26CO 1037 .UB AX,AX
E46F 8Eeo 1038 MDV ES.AX
E471 890800 1039 MOV CX.8 ; GET VECTOR CNT
E474 IE 1040 PUSH OS I SAVE DATA SEGMENT
E475 DE 1041 PUSH CS ; SETUP OS SEG REG
E476 IF 1042 POP OS
E477 BEF3FE90 1043 HOV SI.OFFSET VECTOR_TABLE
E47B BF2000 1044 MDV
E47E ID45 F7A:
E47E AS 1046 MQV5W
E47F 47 1047 INC 01 I SKIP OVER SEGHEHT
£480 ,,7 1048 INC 01
System BIOS A-I5

LOC OBJ LINE SOURCE
E461 E2FB 1049 LOOP F7...

1 050 ; ~------- - ------ - -- --------------- - - ---------------------
1051 i CASSETTE DATA WRAP TEST
1052 ; DESCRIPTION
1053 1'\MH CASSETTE MOTOR OFF. WRITE A BIT OUT TO THE
1054 CASSETTE DATA BUS. VERIFY THAT CASSETTE OATA
1055 READ IS WITHIN A VALID RANGE.
1056 1--------------------------------------------------------
1057
1058 ;----- T\JRH THE CASSETTE HOTOR OFF
1059
E483 1060 TST13:
E483 IF 1061 pop OS
£484 IE 1062 PUSH OS
E485 8040 10b3 MaV Al,04DH I SET TINER 2 SPI{ OUT. AND CASST
E487 E661 1064 O\JT PORT.B.,U ; OUT BITS ON. CASSETTE NOT OFF
1065
10660 ;----- WRITE A BIT
1067
£489 BOFF 10608 MOV Al,OFFH I DISABLE TINER INTERRUPTS
E48e £621 1069 OUT INTAOl,At
E480 80BE> 1070 HOV Al,OB6H ; SEL TIM 2, LSB, MSB. MD 3
E4Sf £643 1071 OUT TIMER+3,Al ; WRITE 8253 CMDIMODE REG
E491 880304 1072 HOV AX,1235 ; SET TIMER 2 CNT FOR 1000 USEC
£494 £642 1073 OUT TINER+2.Al , WRITE TIMER 2 COUNTER REG
£496 SAC4 1074 MOV Al.AH ; WRITE NSB
£498 £642 1075 O\JT TIMER+2.AL
1076
1077 ;----- READ CASSETTE INPUT
1078
£494 £462 1079 IN AL,PORT_C I READ VALUE OF CASS IN BIT
E49C 2410 1080 AND AL.IOH ; ISOLATE FROM OTHER BITS
£49£ A26800 1081 MaV LAST_VAl.Al
E4Al £80514 1082 CALL READ.HALF.BIT
E4A4 £60214 1083 CALL READ.HALF _BIT
E4A7 f30C 1084 Jexz .8
£449 61FB400S 10B5 eMP BX.NA),-PERIOD
E4AD 730E> 1086 JNe .8
E4AF BIFBI004 1087 eMP BX.MIN_PERIOD
E483 7307 1088 JHe ROM.SCAN I GO TO NEXT TEST IF OK
E4S5- 1089 F8: I CAS_ERR
E4S5 BE39Ff90 1090 MaV SI.OFFSET F2 ; CASSETTE WRAP FAILED
£489 ESFED! 1091 CAll P.MSG ; GO PRINT ERROR MSG
1092 1- ------ - - ------ ----- - ------------ -.- - -- - -- - - - - - - -.- - -- - ---- - - - -- -- ------
1093 CHECK FOR OPTIONAL ROM fROM C8000->F4000 IN 2K INCREMENTS
1094 (A VALID tKIDULE HAS '55"'" IN THE fIRST 2 LOCATIONS, LENGTH
1095 INDICATOR {LENGTH/512) IN THE 3RD LOCATION AND TEST/INIT.
1096 CDOE STARTING IN THE 4TH LOCATION.)
1097 ;------------------------------------------------------------------------
E4BC 1096 ROM_SCAN:
E4BC BAOOt8 1099 MOV OX,OC800H ; SET BEGINNING ADDRESS
E48f 1100 ROM.SCAN_1 :
E48F BED ... 1101 MOV DS,DX
E4Cl 2BOB 1102 SUB BX,BX 1 SET BX=OOOO
E4C3 6B07 1103 MOV AX.[BX) ; GET 1ST WORD FROI1 NODULE
£4t5 30SSA-' 1104 eMP AX,OAASSH I = TO ID WORD?
E4C8 7505 1105 JHZ NEXT_ROM J PROCEED TO NEXT ROM IF NOT
E4CA £88701 1106 CAll ROM_CHECK ; GO 00 CHECKSUM AND CALL
E4eD £804 1107 JMP SHORT ARE_WE_DONE ; CHECK FOR EICI OF RDt1 SPACE
E4CF 1108 NEXT_RDM:
E4CF 81C28000 1109 ADO OX,ooaOH I POINT TO NEXT 2K ADDRESS
E403 1110 ARE_WE_DONE:
E403 81FAOOF6 1111 eMP DX,OF600H ; AT F6000 YET?
E4D7 7C£6 1112 JL RON.SCAN_l ; GO CHECK ANOTHER ADD. If NOT
E409 £801"'0 1113 JMP BASE_ROM_CHK J GO CHECK BASIC ROM
1114 ; ------------------------------------------------
1115 ROS CHECKSUM I I
1116 ; DESCRIPTION
1117 A CHECKSUM IS DDNE FOR THE 4 RDS
1118 MODULES CONTAINING BASIC CODE
1119 ;------------------------------------------------
E40e 1120 BASE_ROM_CHK:
E40e 1121 E4:
E40t ZBOB 1122 SUB BX,BX J SETUP STARTING ROS ADDR
E4DE BEDA 1123 HOV DS,OX
E'tEO £86907 1124 CAll ROS_CHECKSU1 f CHECK ROS
A-16 System BIOS

LOC OBJ LINE SOURCE
E4E3 7403 1125 JE E5 I CONTINUE IF OK

E4E5 E82103 1126 CALL ROM_ERR I POST ERROR
E4E8 1127 E5:
E4E8 80C60, 112.8 ADD DH.02H I POINT TO NEXT 8K HOCDULE
E4EB 80FEFE 1129 CMP OH,OFEH
E4EE 75Et 1130 JNZ E4 I YES - CONTINUE
E4FO IF 1131 PDP OS ; RECOVER DATA SEG PTR
1132 ; ------------------------------------------------------------------------
1133 I DISKETTE ATTACHMENT TEST
1134 I DESCRIPTION
1135 CHECK IF IPL DISKETTE DRIVE IS ATTACHED TO SYSTEM. IF ATTACHED,
1136 VERIFY STATUS OF NEe FOC AFTER A RESET. ISSUE A RECAL AND SEEK
1137 tHO TO FOC AND CHECK STATUS. COMPLETE SYSTEM INITIALIZATION
1138 THEN PASS CONTROL TO THE BOOT LOADER PROGRAM.
1139 ; ------------------------------------------------------------------------
E4Fl 1140 F9:
E4F1 MIOOO 1141 MOV AL,BYTE PTR EQUIPJUG I GET SENSE SWS INFO
E4F4 ABOI 114Z TEST AL,OIH ; IPL DISKETTE DRIVE AnCH?
E4F6 750A 1143 JHZ flO ; NO -SKIP THIS TEST
E4F8 e03ElZOOOl 1144 CMP MFG_TST,l ; I1ANUFACTURING TEST MODE?
E4FD 7530 1145 JNE F15A ; NO - GO TO BOOT LOADER
E4FF E959FB 1146 JMP START ; YES - LOOP POWER-ON-DlAGS
E502 1147 FlO:
E50Z E4Z1 1148 IN AL,INTAOI ; DISK_TEST
E504 Z4BF 1149 AND AL,OBFH ; ENABLE DISKETTE INTERRUPTS
E506 E621 1150 OUT INTA01,AL
E508 B400 1151 MOV AH,O ; RESET NEC FOC
E50A BA04 115Z MDV OL,AH I (POINT TO DISKETTE I
E50C C013 1153 INT 13H ; VERIFY STATUS AFTER RESET
E50E 72:Z1 1154 JC F13
1155
1156 ; ----- TURN DRIVE 0 MOTOR ON
1157
E510 BAF203 1158 MDV DX,03F2H ; GET ADDR OF FDC CARD
E513 52 1159 pUSH OX I SAVE lT
E514 BOlC 1160 MOV AL,ICH ; TURN MOTOR ON, EN DMA/INT
E516 EE
E517 2BC9
1161
1162 ,..,
!XJT DX,AL
CX,CX
; WRITE FOC CONTROL REG
E519 1163 F11: I MOTOR_WAlT:

E519 E2FE 1164 LOOP F11 I WAlT FOR 1 SECotm
E518 1165 F12: ; MOTOR_WAIT 1 :
E51B E2FE 1166 LOOP F12
E51D 3302 1167 XOR OX,DX ; SELECT DRIVE 0
ESIF 6501 1168 MOV CH,I I SE LEtT TRACK 1
E521 88163EOO 1169 MOV SEEK_STATUS,DL
E525 E85509 1170 CALL SEEK I RECALIBRATE DISKETTE
E528 72:07 1171 JC Fl' ; GO TO ERR SUBROUTINE IF ERR
E52A 8522 1172 MOV CH,34 ; SELECT TRACK 34
E52C E84E09 1173 tALL SEEK I SEEK TO TRACK 34
E52F 7307 1174 JNC Fl4 ; OK, TURN MOTOR OFF
E531 1175 FB: ; DSK_ERR:
E531 BEEAFF90 1176 MOV SI,OFFSET F3 ; GET ADOR OF MSG
E535 E88201 1177 CALL P_MSG ; GO PRINT ERROR HSG
1178
1179 1----- TURN DRIVE 0 MOTOR OFF
1180
E536 1181 F14: I ORO_OFF:
E538 BOOC 1182 NOV AL.OCH ; TURN DRIVE 0 MOTOR OFF
E53A SA 1183 PDP OX I RECOVER FDC CTL ADDRESS
E538 EE 1184 OUT OX.Al
1185
1186 1----- SETUP PRINTER AND RS232 BASE ADDRESSES IF DEVICE ATTACHED
1187
E53C 1168 FlSA:
E53C BEIEOO 1189 MDV 51. OFFSET KB_BUFFER
E53F 89361AQQ 1190 MOV BUFFER_HEAD ,51 I SETUP KEYBOARD PARAMETERS
E543 89361COO 1191 MOV BUFFER_TAIL.SI
E547 89368000 1192 MOV BUFFER_STARl,SI I DEFAULT TO STAt.ilARD BUFFER
E548 83C6Z0 1193 ADD 51,32 J (3;: BYTES LONG)
E54E 89366200 1194 MDV BUFFER_Et-I>.SI
E552 E421 1195 IN Al,INTAOl
E554 24FC 1196 AND AL,OFCH 1 Et-IABLE TIMER AND KBD INTS
E556 E621 1197 OUT INTA01,AL
E556 B03OE690 1198 MDV BP,OFFSET F4 I PRT_SRC_TBL
Esse 2BF6 1199 SUB 51,51
ESSE 1200 F16: ; PRT_BASE:
ESSE 2£885600 1201 MDV DX,CS:[BP] I GET PRINTER BASE ADDR
System BIOS A-17

LaC OBJ LINE SOURCE
E562 BOAA 1202 HOV Al,OAAH I WRITE DATA TO PORT A

E564 EE 12:03 OUT DX.AL
£565 52 1204 PUSH OX
E566 EC 12:05 IN AL,DX I READ PORT A
£567 SA 12:06 POP ox
E568 3CAA 1207 CHP Al,OAAH J DATA PATIERH SAME
£561. 7505 1208 JHE F17 • NO - CHECK NEXT PRT CD
ES6C a95408 1209 HOV PRINTER_BASE[ 51) .OX ; YES - STORE PRT BASE ADOR
E56F 46 1210 INC SI ; INCREMENT TO NEXT WORD
E570 46 1211 INC SI
E571 1212 f17: I NO_STORE:
E571 45 12:13 INC BP ; POINT TO NEXT BASE ADDR
E572 45 1214 INC BP
E573 81FD43E6 1215 CHP BP,OFFSET F4E
Fl. ,
I ALL POSSIBLE ADDRS CHECKED?
£577 75E5
E579 ZBDS
1216
1217
JHE
SUB eX,ex , PRT_BASE
POINTER TO R5232 TABLE
ES7S SAFA03 1216 HOV DX,3FAH I CHECK IF RS232 CD 1 AntH?
E57E EC 1219 IN Al,DX ; READ INTI? 10 REG
E57f ABFa 1220 TEST AL,OFaH
E561 7506 1221 JHZ Fl8
E583 C707F803 1222 HOV RS232_BASE[BX J .3F8H ; SETUP RS232 CD 11 AODR
E587 43 1223 INC BX
E568 43 1224 INC BX
E589 1225 F18:
E569 8602 1226 MOV OH,02H I CHECK IF RS232 CO 2 ATTCH (AT 2FAI
E58B EC 1227 IN AL,OX ; READ INTERRUPT 10 REG
TEST AL.OF6H
E56C A6F6
E56E 7506
1226
1229 JHZ Fl. , BASE_END
£590 C707F602 1230 HOV RS232_BASE( BX] ,2F8H ; SETUP RS232 CO 12
E594 43 1231 INC BX
E595 43 1232 IHC BX
1233
1234 ;----- SET UP EQUIP FLAG TO INDICATE NUMBER OF PRINTERS AND RSC!3C! CARDS
1235
E596 1236 F!9: ; BASE_END:
E596 8BC6 1237 HOV AX.SI ; 51 HAS 2* NUMBER OF RS232
E596 B103 1236 HOV CL,3 ; SHIFT COUNT
E59A 02ca 1239 000 AL.eL ; ROTATE RIGHT 3 POSITIONS
E59C OAC3 1240 OR AL,BL ; OR IN THE PRINTER COUNT
E59E A21100 1241 HOV BYTE PTR EQUIP_FLAG+l.,u ; STORE AS SECOND BYTE
E5Al B201 1242 HOV OL.OIH ; DX=201
E5A3 EC 1243 IN AL.OX
E5A4 A80F 1244 TEST AL.OFH
E5A6 7505 1245 JNZ FlO I NO_GAME_CARO
E5A8 800Ell0010 1246 00 BYTE PTR EQUIP_FLAG+l.16
E5AO 1247 flO:
1248
1249 ;----- SET DEFAULT TIMEOUT VALUES FOR PRINTER At.I) RS232
ESAD
E5AE 07
,. 1250
1251
1252
PUSH
POP
OS
ES
E5AF BF7800 1253 MOV OI.OFFSET PRINT_TIM_OUT
E5B2 681414 1254 HOV AX,1414H ; PRINTER DEFAULTS (COUNT=20)
E565 AB 1255 STOSW
E586 AB 1256 STOSW
E587 B60101 1257 MOV AX,OIDIH ; RS232 OEFAULTS=OI
E5BA AB 1256 STOSW
ESBB A6 1259 STOSW
1260
U~61 ;----- ENABLE NHI INTERRUPTS
1262
E5BC 8080 1263 HOV AL , 60H , ENABLE NHI INTERRUPTS
ESBE E6AO 1264 OUT OAOH,AL
CMP MFG_TST,1 , MFG MODE?
ESCO 803E120001
E5C5 7406
1265
1266 JE F21 , LOAP_BOOT_STRAP
E5C7 BAOI00 1267 HOV DX,l
E5CA E60200 1268 CALL EIU'_BEEP ; BEEP 1 SHORT TONE
1269
ESCD 1270 F21: , LOAD_BOOT_STRAP:
ESCO C019 1271 IHT 19M , BOOTSTRAP
1272
1273 ;--------------------------------------------------------
1274 INITIAL RELIABILITY TEST -- SUBROUTINES
1275 ;--------------------------------------------------------
1276 ASSUME CS:CODE,DS:DATA.
1277 ; --- --------------------------------------- --------------------
1278 ; SUBROUTINES FOR POWER ON DIAGNOSTICS
A-I8 System BIOS

LOC OBJ LINE SOURCE
1279 THIS PROCEDURE WILL ISSUE ONE LONG TONE (3 SECS) AI«) ONE OR
12:80 MORE SHORT TONES 11 SEC) TO INDICATE A FAIllRE ON THE Pl.ANAR
1281 BOARD. A BAD RAM MODULE, OR A PROBLEI1 WInt THE CRT.
1282 I ENTRY PARAMETERS:
1263 OH = HUMBER OF LONG TONES TO BEEP
1284 Dt = NUt1BER OF SHORT TONES TO BEEP
12:85 I---------~--------------------------------------------------------------
ESC' 1286 ERR_BEEP PROC NEAR

E5CF 9C 1267 PUSH' I SAVE FLAGS
£500 FA 12:88 ClI I DISABLE SYSTEM INTERRUPTS
ESDI IE 12:89 PUSH OS J SAVE OS REG CONTENTS
£502 E86919 1290 CALL DDS
E50S OAF6 1291 DR DH,DH I ANY LONG ONES TO BEEP
E507 7418 1292 JZ G3 ; NO. DO THE SHORT ONES
E509 1293 Gl: I LONG_BEEP:
£509 B106 1294 MaV Bl.b I COUNTER FOR BEEPS
ESOB £62500 1295 CALL BEEP I 00 THE BEEP
ESDE E2FE 1296 G2: lOOP G2 ; DELAY BETWEEN BEEPS
E5EO FEtE 1297 DEC OH J ... NY HORE TO DO
£5E2 75F5 1298 JHZ G1 I DO IT
E5E4 803E120001 1299 CMP HFG_TST,1 I MFG TEST MODE?
ESE9 7506 1300 JNE G3 I YES - CONTINUE BEEPING SPEAKER
ESEB BOCD 1301 MOV Al.OCDH I STOP BLIt-I<ING LED
ESED E661 1302: OUT PORT_B.AL
ESEF EBES 1303 JMP SHORT 61
ESFI 1304 63: I SHORT_BEEP:
ESFl B301 1305 MOV BL,1 I COlNTER FOR A SHORT BEEP
ESF! E60000 1306 CALL BEEP ; DO THE SOUND
ESF6 1307 G4:
ESF6 E2FE 1308 lOOP G4 ; DELAY BETWEEN BEEPS
E5F8 fECA 1309 DEC Ol I DONE WITH SHORTS
ESFA 75F5 1310 JNZ G3 ; DO SOME MOR E
ESFC
ESFC E2FE
ESFE
E5FE E2fE
1311
1312
1313
1314
.
&5:
,
LOOP
lOOP
GS
GO
I lONG DELAY BEFORE RE~N
E600 IF 1315 POP OS J RESTORE ORIG CONTENTS OF OS

E601 90 1316 POPF I RESTORE FLAGS TO ORIG SETTINGS
E602 C3 1317 RET I RETl.JRN TO CALLER
1318 ERR_BEEP ENDP
1319
1320 ; ----- ROUTINE TO SOlH) BEEPER
1321
E603 1322 BEEP PROC NEAR
E603 BOB6 1323 ttOY Al,lOIIDl108 ; SEL TII1 2,lSB,HSB,BIHARY
E605 E643 1324 OUT TIMER-t3.Al ; WRITE THE TIMER HOOE REG
E607 B83305 1325 MOV AX.533H ; DIVISOR FOR 1000 HZ
E60A E642 1326 OUT TIMER-t2,Al ; WRITE TIMER 2 CNT - lSB
E60C 8AC4 1327 MOV Al.AH
E60E E642 1328 OUT TIMER-t2.Al J WRITE TIMER 2 CNT - MSB
E610 E461 1329 IN Al,PORT_B J GET CURRENT SETIING OF PORT
E612 6AEO 1330 MOV AH,Al I SAVE THAT SETIING
E614 oe03 1331 OR Al,03 I TURN SPEAKER ON
E616 E661 1332: OUT PORT_B.At
E618 2BC9 1333 SUB CX.CX ; SET CNT TO WAIT 500 I1S
E61A
E61A E2FE
E61C FEeB
1334
1335
1336
G7:
lOOP
DEC
.7
Bl
I DELAY BEFORE TI.lRNING Off
• DELAY CNT EXPIREO?
E61E 75FA 1337 JNZ .7 ; NO - CONTINUE BEEPING SPK
E62:0 8AC4 1338 HOV Al,AH I RECOVER VALUE OF PORT
E622 E661 1339 OUT PORT_B.AL
E624 C3 1340 RET ; RE~N TO CAlLER
1341 BEEP ENDP
1342
1343 ; -------- --------------------------------------
--
1344 I CONVERT AND PRINT ASCII CODE
1345 Al MUST CONTAIN tu1BER TO BE COtNERTED. ,
1346 AX AND BX DESTROYED.
1347 ; ------------------------------------------------
E625 1348 XPC_BYTE PROC NEAR
E625 50 1349 PUSH AX I RESAVE FOR lOW NIBBLE DISPLAY
E626 BI04 1350 MOV Cl,4 ; SHIFT COUNT
E626 02:E8 1351 SHR Al,CL ; NIBBLE SWAP
E62A E80300 1352: CAll XlAT_PR ; DO THE HIGH NIBBLE DISPLAY
E620 58 1353 POP AX I RECOVER THE NIBBLE
E62E 24OF 1354 AND AL,OFH I ISOLATE TO LOW NIBBLE
1355 I FAll INTO LOW NIBBLE CONVERSION
System BIOS A-19

LOC OBJ LINE SOURCE
E630 1356 XLAT_PR PROC NEAR J CONVERT ~O-Of' TO ASCII CHARACTER

E630 0490 1357 ADD AL,090H ; ADD FIRST CONVERSION FACTOR
E632 27 1358 .AA I ADJUST FOR NUMERIC AND ALPHA RANGE
E633 1440 1359 ADC AL.040H I ADD CONVERSION AND ADJUST LOW NIBBLE
E635 27 1360 DAA ; ADJUST HI NIBBLE TO ASCII RANGE
E636 1361 PRT_HEX PROC NEAR
E636 840E 1362 MOV AH,14 ; DISPLAY CHAR. IN AL
E638 B700 1363 HOV SH,O
E63A COlO 1364 INT lOH
E63C C3 1365 RET
1366 PRT_HEX EHOP
1367 XLAT]R EHOP
1368 XPC_BYTE ENDP
1369
E630 1370 F4 LABEL WORD ; PRINTER SOURCE TABLE
E630 BC03 1371 OW 3BCH
E63F 7803 1372 OW 378H
E641 7802 1373 OW 278H
E643 1374 F4E LABEL WORD
1375
1376 ; -----------------------------------------------------------------------_
1377 TliIS PROCEDURE WILL SEND A SOFTWARE RESET TO TliE KEYBOARD.
1378 SCAH CODE 'AA' SHOULD BE RETURNED TO THE CPU.
1379 ; ------------------------- -----------------------------------------------
E643 1380 KBD_RESET PROC NEAR
E643 BoDe 1381 MOV AL.OCH ; SET KBD CLK LINE LOW
E645 E661 1382 OUT PORT_B.AL I WRITE 8255 PORT B
E647 895629 1383 MOV CX.I0582 ; HOLD KBD CLK LOW FOR 20 MS
E64. 1384
E64. E2FE 1385 LOOP S8 ; LOOP FOR 20 MS
E64C eoce 1386 MOV Al,OCCH ; SET CLK, ENABLE LINES HIGH
EME E661 1387 OUT PORT_B,AL
£650 1388 SP_TEST: I ENTRY FOR MANUFACTURING TEST 2
£650 B04C 1389 HOV Al,4CH ; SET KBO eLK HIGH, ENABLE lOW
E652 E661 1390 OUT PORT_B,AL
£654 BOFD 1391 MOV Al.OFDH ; ENABLE KEYBOARD INTERRUPTS
E656 E621 1392 OUT INTA01 •.U ; WRITE 8259 IMR
E658 FB 1393 sn ; ENABLE SYSTEM INTERRUPTS
E659 6400 1394 HOV AH,O ; RESET INTERRUPT INDICATOR
E658 28C9 1395 SUB CX.cx • SETUP INTERRUPT TIMEOUT CNT
£650 1396 69:
E650 F6C4FF 1397 TEST AH, OFFH ; DID A KEYBOARD IHTR OCCUR?
E660 7502 1398 JNZ GI0 ; YES - READ SCAN COOE RETURNED
E662 E2F9 1399 LOOP G9 ; NO - LOOP TILL TIMEOUT
E664 1400 GI0:
£664 E460 1401 IN Al.POIH_A ; READ KEYBOARD SCAN CODE
£666 8AD8 1402 MDV Bl,Al I SAVE SCAN CODE JUST READ
E668 Boce 1403 MOV AL.OCCH ; CLEAR KEYBOARD
E66A E661 1404 OUT PORT_B.AL
EbbC C3 1405 RET ; RETURN'TO CALLER
1406 KBD_RESET ENDP
1407
1408 ; --------------------------------------------------- ----- ----------------
1409 BLINK LED PROCEDURE FOR MFG BURN-IN AND RUN-IN TESTS
1410 IF LEO IS ON. TURN IT OFF. IF OFF, TURN ON.
1411 ; ------------------------------------------------------------------------
£66D 1412 PROC NEAR
E660 FB 1413 sn
E66E 50 1414 PUSH AX ; SAVE AX REG CONTENTS
E66F £461 1415 IN AL,PORT_B ; READ CURRENT VAL OF PORT B
E67l 8AEO 1416 MOV AH,AL
E673 F6DO 1417 NOT Al I FLIP ALL BITS
E675 2440 1418 AND AL,01000000B I ISOLATE CONTROL BIT
E677 80E4BF 1419 AND AH,101111118 ; MASK OUT OF ORIGINAL VAL
E67A OAC4 1420 OR AL,AH ; OR NEW CONTROL BIT IN
E67e E661 1421 OUT
£67E B020 1422 MOV AL,EOI
E6&0 E620 1423 OUT INTAOO.AL
E682 58 1424 POP AX ; RESTORE AX REG
E683 CF 1425 IRET
1426 BLINK_INT EHOP
1427
1428 ; ----- CHECKSUH AND CALL INlT CODE IN OPTIONAL ROMS
1429
E684 1430 PROC NEAR
E684 884000 1431 AX.DATA ; SET ES=DATA
E687 8EtO 1432 ES,AX
A-20 System BIOS

LaC OBJ LINE SOURCE
E6e, 2AE4 ,433 SUB AH,AH I ZERO OUT AH

E688 81.4702 1434 HOV AL.[eX+2] I GET LENGTH INDICATOR
EbaE BI09 1435 HOV CL.D9H I tlULTlPLY BY 512
E690 03EO 1436 SHL AX,CL
E6n 86C8 1437 HOV eX.AX J SET COUNT
E694 51 1438 PUSH CX
E695 BI04 1439 HOV CL.4
E697 03E8 1440 SHR AX,CL
E699 0300 1441 ADO OX,AX I SET POINTER TO NEXT HODUlE
E69B 59 1442 pop CX
1443
E69C E8B005 1444 CALL ROS_CHECKSUH_CNT I DO CHECKSUH
E69F 7405 1445 JZ ROM_CHECK_l
E6Al E86501 1446 CALL ROM_ERR , PRINT ERROR INFO
E6A4 E8l3 1447 JMP SHORT ROM_CHECK_END
E6A6 1448 ROH_CHECK_l:
E6A6 52 1449 PUSH OX I SAVE POINTER
E6A7 26C70600010300 1450 HOV ES; IO_ROM_INIT. 0003H , LOAD OFFSET
E6Af 268CIE0201 1451 MOV ES: IO_ROM_SEG,DS LOAD SEGMENT
E6B3 26FFIEODOl 1452 CALL DWORD PTR ES: IO_ROM_INIT ; CALL INIT RTM.
E6B8 SA 1453 POP OX
E689 1454 ROH_CHECK.....END :
E689 (3 1455 RET
1456 ROM_CHECK 'HOP
1457
,---------------------------------------------- -- --------
1458 ;
1459 THIS SUBROUTINE WILL PRINT A MESSAGE ON THE DISPLAY
1460
1461 I ENTRY REQUIREMENTS:
1462 SI = OFFSET I ADDRESS I OF MESSAGE BUFFER
1463 ex = MESSAGE BYTE COUNT
1464 MAXIHI.JH MESSAGE LENGTH IS 36 CHARACTERS
1465 ; --------------------------------------------------------
EbBA 1466 P_MSG ""OC NEAR
EbBA E88118 1467 CALL O~S
EbBD 803E120001 1466 CMP MFG_TST,1 , HFG TEST HOOE?

E6t2 7505 1469 JH' 012 , NO - DISPLAY ERROR HSG
E6e4 B601 1470 HOV OH,I I YES - SETUP TO BEEP SPEAKER
E6C6 E906FF 1471 JMP ERR_BEEP , YES - BEEP SPEAKER
E6C9 1472 G12: ; WRITE_MSG:
E6(9 2E8,6,04 1473 HOV Al,CS:(SI1 , PUT CHAR IN AL
Ebce 46 1474 INC SI POINT TO NEXT CHAR
EbeD 50 1475 PUSH AX ,
I
SAVE PRINT CHAR
EbeE E865FF 1476 CAll PRT_HEX I CALL VIDEO_IO
POP AX
E60l 58
E602 3eOA
1477
1478 CHP AL,IO ,
I RECOVER PRINT CHAR
WAS IT LINE FEED
E604 75F3 1479 JH' 012 I N()'KEEP PRINTING STRING
f606 C3 1460 RET
1461 P_HSG 'HOP
1482
E607 20524F4D 1463 nA DB ROM',I3.10
E6DB 00
E6Dt 01.
1484
EbOD 1485 D_EOI ""OC NEAR
f60D 50 1466 PUSH AX
EbDE B020 1487 HOV AL.20H
E6EO E620 1466 20H,Al
f6E2 58 1469 POP AX
f6E3 CF 1490 IRET
1491 D_EOI 'HOP
1492
1493 ; --- INT 19 -----------------------------------------------------
1494 ; BOOT STRAP LOADER
1495 IF A 5 1/4" DISKETTE DRIVE IS AVAILABLE ON THE SYSTEM,
1496 TRACK O. SECTOR 1 IS READ INTO THE BOOT LOCATION
1497 (SEGMENT O. OFFSET 7C00) AND CONTROL IS TRANSFERRED
1496 THERE.
1499
1500 IF THERE IS NO DISKETTE DRIVE. OR IF THERE IS A
1501 HARDWARE ERROR CONTROL IS TRANSFERRED TO TIfE RESIDENT
1502 BASIC ENTRY POINT.
1503
1504 ; IPL AS~PTIONS:
1505 6255 PORT 60H BIT 0 =1 IF IPL FROM DISKETTE

1506 J ------------------ - - - - ------- -- -- --- - - - ----------- -- ------------
1507 ASSUHE CS:CODE.DS:ABSO
System BIOS A-21

LaC OBJ LINE SOURCE
1508
1509 1----- IPL WAS SUCCESSFUL
1510
E6E4 1511 H4:
E6E4 EAOO7COOOO 1512: JMP BOOT_LOCH
E6f2 1513 ORG OE6F2H
E6F2: 1514 BOOT_STRAP PROt NEAR
E6F2 FB 1515 STI I ENABLE INTERRUPTS
E6F3 ZBca 1516 SUB AX,AX
E6F5 SEDS 1517 MOV DS,AX
1518
1519 ; ----- RESET DISKETTE PARAMETER TABLE VECTOR
1520
E6F7 C7067800C7EF 1521 MOV
E6FD 8COE7AOO 1522 MOV WORD PTR DISK_POINTER+2,CS
E701 AllOO4 152:3 MOV AX,DATA_WORD(OFFSET EQUIPJLAGl ; GET THE EQUIPMENT SWITCHES
E704 ASOI 1524 TEST AL,l ; ISOLATE IPL SENSE SWITCH
E706 741E 1525 JZ H3 ; GO TO CASSETTE BASIC ENTRY POlm
1526
152:7 ;----- MUST LOAD SYSTEM FROM DISKETTE -- CX HAS RETRY COUNT
1528
E708 690400 152:9 NOV CX,4 ; SET RETRY COUNT
E70B 1530 HI: ; IPL_SYSTEN
E70B 51 1531 PUSH ex ; SAVE RETRY COUNT
E70C 9400 1532 MOV AH,O ; RESET THE DISKETTE SYSTEM
nOE con 1533 INT 13H ; DISKETTE_IO
E7lD 720F 1534 Je H2 ; IF ERROR, TRY AGAIN
E712 BaOlO2 1535 NOV AX,20IH ; READ IN THE SINGLE SECTOO
E7lS 2B02 1536 SUB OX,DX
E717 8ECZ 1537 MOV ES,DX
E7l9 BBOO7e 1538 MOV BX,OFFSET BOOT_LOCN
E7le 690100 1539 MOV CX,! ; SECTOR l, TRACK 0
E71F con 1540 INT 13H ; DISKETTE_IO
E721 59 1541 H2: POP ex ; RECOVER RETRY COUNT
E722 73CO 1542 JNe H. I CF SET BY UNSUCCESSFUL READ
E724 E2E5 1543 LOOP HI I DO IT FOR RETRY TINES
1544
1545 ;----- UNABLE TO IPL FROM THE DISKETTE
1546
En6 1547 H3: I CASSETTE_JUHP:
E726 COl8 1548 INT 18H ; USE INTERRUPT VECTOR TO GET TO BASIC
1549
1550
1551 ;-----INT 14-------------------------------------------------------------
1552 ; RS232_IO
1553 nilS ROUTINE PROVIDES BYTE STREAM I/O TO THE COMMUNICATIONS
1554 PORT ACCORDING TO THE PARAMETERS:
1555 I AH )=0 INITIALIZE THE COMMUNICATIONS PORT
1556 (All HAS PARAMETERS FOR INITIALIZATION
1557
1558
1559 ----- BAllO RATE -- -PARITY-- STOPBIT --WORD LENGTH--
1560 DOD - 110 XO - NONE o - 1 10 - 7 BITS
1561 001 - 150 01 - 000 1 - 2 11 - 8 BITS
1562 010 - 300 11 - EVEN
1563 011 - 600
1564 100 - 1200
1565 101 - 2400
1566 110 - 4800
1567 111 - 9600
1568
1569 ON RETURN, CONDITIONS SET AS IN CALL TO C0t1t10 STATUS (AH=3)
1570 (AHI=l SEND THE CHARACTER IN {All OVER THE COMMO LINE
1571 {All REGISTER IS PRESERVED
1572 ON EXIT, BIT 7 OF AH IS SET IF THE ROUTINE WAS UNABLE
1573 TO TRANSMIT THE BYTE OF DATA OVER THE LINE.
1574 IF BIT 7 OF AH IS NOT SET, THE REMAINDER OF AH
1575 IS SET AS IN A STATUS REQUEST, REFLECTING THE
1576 CURRENT STATUS OF THE LINE.
1577 {AH)=2 RECEIVE A CHARACTER IN {All FROM COMMa LINE BEFORE
1578 RETURNING TO CALLER
1579 ON EXIT, AH HAS THE CURRENT LINE STATUS, AS SET BY THE
1580 THE STATUS ROUTINE, EXCEPT THAT THE ONLY BITS
1581 LEFT ON ARE THE ERROR BITS (7,4,3,2,1)
1582 IF AH HAS BIT 7 ON (TIME oun THE REMAINING
1583 BITS ARE NOT PREDICTABLE.
1584 THUS, AM IS NON ZERO ONLY .... EN AN ERROR
A-22 System BIOS

LaC OBJ LINE SOURCE
1585 OCC~RED.
1586 IAH)=3 RETURN THE COtlt1Q PORT STATUS IN (AX)
1587 AH CONTAINS THE LINE STATUS
1588 BIT 7 = TIME OUT
1589 BIT 6 = TRANS SHIFT REGISTER EMPTY
1590 BIT S = TRAN HOLDING REGISTER EMPTY
1591 BIT 4 = BREAK DETECT
1592 BIT 3 = FRAMING ERROR
1593 BIT 2 = PARITY ERROR
1594 BIT 1 = OVERRUN ERROR
1595 BIT 0 = DATA READY
1596 AL CONTAINS THE MOOE" STATUS
1597 BIT 7 = RECEIVED LINE SIGNAL DETECT
1598 BIT 6 = RING INDICATOR
1599 BIT 5 = DATA SET READY
1600 BIT 4 = CLEAR TO SEND
1601 BIT 3 = DELTA RECEIVE LINE SIGNAL DETECT
1602 BIT .2 = TRAILING EDGE RING DETECTOR
1603 BIT 1 = DELTA DATA SET READY
1604 BIT 0 = DELTA CLEAR TO SEND
1605
1606 (OX) = PARAMETER INDICATING WHICH RS232 CARD (0,1 AllOWED)
1607 I
1608 I DATA AREA RS232_BASE CONTAINS THE BASE ADDRESS OF THE 8250 ON THE
1609 CARD LOCATION 400H CONTAINS UP TO It RS232 ADDRESSES POSSIBLE
1610 DATA AREA LABEL RS2:32_TIH_OUT (BYTE) CONTAINS OUTER LOOP COUNT
1611 VALUE FOR TIMEOUT (DEFAULT=lJ
1612 ; OUTPUT
1613 AX MODIFIED ACCORDING TO PARI15 OF CALL
1614 ALL OTHERS UNCHANGED
1615 ; - - --- - -- - - -- --- - - - -- --------- - - ---- -------------------------------------
1616 ASSUHE CS:CODE,DS:DATA
£729 1617 ORO OE729H
£729 1616 Al LABEL WORD 1 TABLE OF INIT YAWE
E729 1704 1619 DW 1047 J 110 BAUD
E72B 0003 1620 DW 7.8 J 150
£720 6001 1621 DW 384 I 300
E72:F CODO 1622 DW I" 1 600
£731 6000 1623 DW 9. ; 1200
E733 3000 1624 DW 48 I 2.400
£735 1800 1625 DW 2. ; 4800
£737 Deoo 1626 DW 12 1 9600
1627
£739 1626 RS232_1O PROC FAR
1629
1630 J----- VECTOR TO APPROPRIATE ROUTINE
1631
E739 FB 1632 srI I INTERRUPTS BACK ON
E73" IE 1633 PUSH DS ; SAYE SEGMENT
E738 52 1634 PUSH DX
E73C 56 1635 PUSH SI
El3D 57 1636 PUSH DI
£73£ 51 1637 PUSH CX
E73F 53 1636 PUSH BX
E740 8BF2 1639 MOY SI,DX I R5232 YALUE TO 51
E742 8BFA. 1640 MDY DI,DX
£744 DIE6 1641 SHL SI,I I WORD OFFSET
E7lt6 E8FS17 1642 CALL DDS
E749 6814 1643 ttOV DX,RS232_BA5E[SI J J GET BASE ADDRESS
£74B 0802 1644 DR DX,DX I TEST FOR 0 BASE ADDRESS
£740 7413 1645 JZ A3 I RETURN
E74F DAE4 1646 DR AH,AH J TEST FOR IAH)=O
E751 7416 1647 JZ A4 1 COHMUN INIT
£753 FEte 1648 DEC AH J TEST FOR (AH}=1
£755 7445 1649 JZ AS ; SEJ.Il AL
E757 FEee 1650 DEC AH I TEST FOR ("H)=2
E759 746. 1651 JZ Al2 i RECEIVE INTO At
£758 1652 A.2:
£758 FEee 1653 DEC AH ; TEST FOR IAM)=3
E750 7503 1654 JHZ A'
E7SF £98300 1655 JMP Al8 J COt1t'lINlCATION STATUS
£762 1656 .1.3: ; RETURN FROM RS232
E762 58 1657 pop BX
£763 S9 1658 pop CX
E764 SF 1659 pop DI
E765 5£ 1660 pop SI
£766 5A 1661 pop DX
System BIOS A-23

LaC OBJ LINE SOURCE
E767 IF 1662 pop os

E768 CF 1663 IRET I RETURN TO CAllER, NO ACTION
1664
1665 1----- INITIALIZE THE Cot1l1UHICATIONS PORT
1666
E769 1667 A4:
E769 8AEO 1668 MaY AH.AL ; SAVE INIT PARMS IN AH
E766 83C203 1669 AOO OX.3 I POINT TO 8250 CONTROL REGISTER
£76E B080 1670 MaY AL,SOH
E770 EE 1671 OUT OX.Al ; SET DLAB=l
1612
1673 ; ----- DETERMINE BAUD RATE DIVISOR
1674
E771 8A04 1675 MOY Cl,AH ; GET PARMS TO 0 L
E773 6104 1676 MaY Cl.4
E775 D2e2 1677 ROL Dl,CL
E777 61£20EOO 1678 ANO OX,OfH ; ISOLATE THEM
E77B eF29E7 1679 MOV 01.0FFSET Al ; BASE OF TABLE
E77E 03FA 1680 ADD OI.OX ; PUT INTO INDEX REGISTER
E760 8814 1681 MOV DX,RS232_BASE[SIJ ; POINT TO HIGH ORDER OF DIVISOR
E782 4, 1682 INC OX
E783 2E8A4501 1683 MOV AL,CS:IOIltl ; GET HIGH ORDER OF DIVISOR
E787 EE 1684 OUT OX,AL ; SET MS OF DIV TO 0
E786 4A 1665 DEC OX
E789 2E8A05 1686 MOV AL.CS: [01 J I GET LOW ORDER OF DIVISOR
E78C EE 1687 OUT DX.AL j SET lOW OF DIVISOR
E780 83C,03 1688 ADD OX.3
E790 8AC4 1689 MOV AL,AH ; GET PARMS BACK
E792 241F 1690 ANO AL,OIFH i STRIP OFF THE BAUD BITS
E794 EE 1691 OUT DX,AL ; LINE CONTROL TO 8 BITS
E795 4A 169, OEC OX
E796 4A 1693 DEC OX
E797 BODO 16 . . MOV AL,O
E799 EE 1695 OUT DX.AL I INTERRUPT ENABLES ALL OFF
E79A EB49 1696 JMP SHORT A18 I COM_STATUS
1697
1698 ;----- SEND CHARACTER IN (AU OVER COMMO LINE
1699
E70C 1700 AS:
E79C 50 1701 PUSH AX ; SAVE CHAR TO SEND
E790 83C,04 1702 ADD DX,4 ; MOOEM CONTROL REGISTER
E7AO B003 1703 MOV AL,3 ; DTR AND RTS
E7A, EE 1704 OUT OX,AL ; DATA TERMINAL READY, REQUEST TO SEND
E7A3 4, 1705 INC OX ; MOOEM STATUS REGISTER
E7A4 4, 1706 INC OX
E7AS B730 1707 MOY 6H.30H i DATA SET READY & CLEAR TO SEND
E7A7 E84800 1708 CALL WAIT_FOR_STATUS ; ARE Balli TRUE
E7AA 7408 1709 JE A9 ; YES. READY TO TRANSMIT CHAR
E7Ae 1710 A7:
E7AC 59 1711 pcp ex
E7AO 8AC1 171, MOV AL.CL ; RElOAD DATA BYTE
E7AF 1713 A8:
E7AF 80Ct80 1714 OR AH,80H I INDICATE TIME OUT
E7B, EBAE 1715 JMP Al ; RETURN
E7B4 1716 A9: ; CLEAR_To_sum
E7B4 4A 1717 DEC OX ; LINE STATUS REGISTER
E7B5 1718 AI0: ; IoIAIT_SEND
E7BSB7Z0 1719 MOV BH.20H i IS TRANSMITTER READY
E787 E83800 1120 tALL WAIT_FaR_STATUS ; TEST FOR TRANSMITTER READY
E7BA 75FO 1121 JNZ A7 I RETURN WITH TIME OUT SET
E7BC 1122 All: ; OUT_CHAR
E7ec 83EA05 1123 SUB OX,S I DATA PORT
E78F 59 1124 POP ex ; RECOVER IN CX TEMPORARILY
E7CO 8AC1 1125 MOV .U,tL I MOVE CHAR TO AL FOR OUT. STATUS IN AH
ne, EE 1126 OUT DX.AL ; OUTPUT CHARACTER
E7C3 EB9D 1127 JMP A3 ; RETURN
1128
1129 i ----- RECEIVE CHARACTER FROM COMMO LINE
1730
E7C5 1731 AI,:
E7CS 83C,04 1732 ADO DX.4 I MODEM CONTROL REGISTER
E7C8 B001 1733 MOV AL.I ; DATA TERHINAL READY
E7CA EE 1734 OllT DX.AL
E7ca 4, 1735 INC ox ; MODEM STATUS REGISTER
ncc 42: 1736 INC ox
nco 1737 A13: ; WAIT_OSR
E7CD B7Z0 1738 MOY BH.2:0H I DATA SET READY
A-24 System BIOS

LOC OBJ LINE SOURCE
E7CF E82000 1739 CALL WAITJOR_STATUS I TEST FOR DSR

E702 750B 1740 JNZ A. I RETURN WITH ERROR
E704 1741 ,4.15: I WAIT_DSR_END
E704 4" 1742 DEC OX I LINE STATUS REGISTER
E705 1743 A16: I WAIT_RECV
E70S B701 1744 HeV BH,l I RECEIVE BUFFER FULL
E707 E81800 1745 CALL WAIT]OR_STATUS ; TEST FOR REC. SUFF. FULL
E70A 7503 1746 JNZ AS 1 SET TIME OUT ERROR
E70e 1747 A17: , GET_CHAR
E70C 80E41E 1748 AND AH,OOOl1110S I TEST FOR ERR CONDITIONS ON RECY CHAR
E70F 8614 1749 MOV OX, RS232_SASE[ SI 1 1 DATA PORT
E7El EC 1750 IN AL,oX ; GET CHARACTER FROM LINE
E7E2 E970FF 1751 JMP A3 I RETURN
1752
1753 j----- COMMO PORT STATUS ROUTINE
1754
E7ES 1755 A18:
E7ES 8B14 1756 HeV DX;RS232_BASE{ SI J
E7E7 83C205 1757 ADD OX,S ; CONTROL PORT
E7EA EC 1758 IN AL,OX ; GET LINE CONTROL STATUS
E7EB 8AEO 1759 MOV AH,AL ; PUT IN AH FOR RETURN
E7ED 42 1760 INC OX j POINT TO MODEM STATUS REGISTER
E7EE EC 1761 IN AL,OX I GET MOOEM CONTROL STATUS
E7EF E970FF 1762 JMP A3 ; RETURN
1763 I - -- - - - - - - - - - ----------- -- - - - ------------
1764 ; WAIT FOR STATUS ROUTINE
1765
1766 ; ENTRY:
1767 SH=STATUS SInS) TO LOOK FOR,
1768 OX=AOoR. OF STATUS REG
1769 i EXIT:
1770 ZERO FLAG ON = STATUS FOUND
1771 ZERO FLAG OFF = TIMEOUT.
1772 AH=LAST STATUS READ
1773 j ----------------------------------------
E7F2 1774 WAITJOR_STATUS PROC NEAR

E7F2 BASD7t 1775 MOV BL.RS232_TlM_OUTI 01 1 ; LOAD OUTER LOOP ClJl.lIT
E7F5 1776 WFSO:
E7F5 26C9 1777 SUB ex.ex
E7F7 1778 WFS1:
E7F7 EC 1779 IN AL,OX I GET STATUS
E7F8 8AEO 1780 MOV AH,AL MOVE TO AH
E7FA 22C7 1781 AND AL,SH ISOLATE BITS TO TEST
E7FC 3AC7 1782 CMP AL.BH ; EXACTLY = TO MASK
E7FE 7408 1783 JE WFS_END I RETURN WITH ZERO F LAG ON
E800 E2F5 1784 LOOP WFSI ; TRY AGAIN
E802 FEeB 1785 DEC BL
E804 75EF 1786 JNZ WFSO
E806 OAFF 1787 0. SH.SH I SET ZERO F LAG OFF
E808 1788 WFS_END:
E808 C3 1789 RET
1790 WAITJOR_STATUS ENDP
1791 RS232_IO ENQP
1792
1793 ;-------------------------------------------------------------------------
1794 PRINT ADDRESS AND ERROR MESSAGE FOR ROM CHECKSUM ERRORS
1795 j-------------------------------------------------------------------------
E809 1796 ROM_ERR PROC NEAR
£809 52 1797 PUSH OX I SAVE POINTER
ESOA 50 1798 PUSH AX
E80B aCDA 1799 HeV OX,OS I GET ADDRESS POINTER
E800 81FAOOC8 1800 CMP OX,OC800H
E811 7E13 1801 JLE ROM_ERR_SEEP SPECIAL ERROR INDICATION
E813 8AC6 1802 HeV AL,DH
E8l5 E800FE 1803 CALL XPC_BYTE DISPLAY ADDRESS
E818 BAC2 1804 HeV AL,OL
EalA EBOSH 1805 CALL XPC_8YTE
UlD BED7E6 1806 t10V 5I.OFFSET F3A ; DISPLAY ERROR HSG
E820 E897FE 1807 CALL P_MSG
E823 1808 ROM_ERR_END :
E823 58 1809 pop AX
e824 5A 1810 POP OX
E825 C3 1811 RET
E826 1812 ROM_ERR_BEEP:
E826 BA0201 1813 MOV OX,0102H I BEEP 1 LONG, 2 SHORT
E829 E8A3FO 1814 CALL ERR_BEEP
Eazc EBFS 1815 JMP SHORT ROM_ERR_HI)
System BIOS A-25

LaC OBJ LINE SOURCE
1616
1817
1818 ; ---- INT 16 -------.-------------------------.--------------------------
1619 1 KEYBOARD lID
1820 THESE ROUTINES PROVIDE KEYBOARD SUPPORT
1821 INPIlT
1822 (AH ):0 READ THE NEXT ASCII CHARACTER STRUCK FROM THE KEYBOARD
1823 RETURN THE RESULT IN (All, SCAN CODE IN (AH)
1824 (AH )=1 SET THE Z flAG TO INDICATE IF AN ASCII CHARACTER IS
1625 AVAILABLE TO BE READ.
1826 (ZFl=l -- NO CODE AVAILABLE
1827 (ZF )=0 -- CODE IS AVAILABLE
182:8 IF IF = O. THE NEXT CHARACTER IN THE BUFFER TO BE READ
1829 IS IN AX. AND THE ENTRY REMAINS IN THE BUFFER
1830 (AH)"2 RETURN THE CURRENT SHIFT STATUS IN AL REGISTER
1831 THE BIT SETTINGS FOR THIS CODE ARE INDICATED IN THE
1832 THE EQUATES FOR KB_FLAG
1833 ; OUTPUT
1834 AS NOTED ABOVE , ONLY AX AND FLAGS CHANGED
1835 All REGISTERS PRESERVED
1636 ;------------------------------------------------------------------------
1837 ASSUME CS:CODE ,DS:DATA
E82E 1636 ORG OE82EH
E82E 1839 KEYBOARD_IO PROC FAR
E82E FB 1640 STI ; INTERRUPTS BACK ON
E82F IE 1841 PUSH OS ; SAVE CURRENT OS
£830 53 1842 PUSH BX ; SAVE BX TEMPORARILY
E831 E80AI7 1843 CALL DOS
E834 OAE4 1844 DR AH,AH ; AH=O
E836 740A 1845 JZ Kl ; ASCII_READ
E838 FEte 1846 DEC AH ; AH=l
E83A 741E
Ea3C FEte
1847
1848
JZ
DEC
'2AH ; AH=Z
E83E 7428 1849 JZ K3 ; SHIFT_STATUS
E840 EBZC 1850 JMP SHORT INTIO_END ; EXIT
1651
1852: ; ----- READ THE KEY TO FIGURE OUT WHAT TO DO
1853
£842 1854 KI: ; ASCII READ
E842 FB 1855 STI ; INTERRUPTS BACK ON DURING LOOP
E8 .. 3 90 1856 NOP ; AllOW AN INTERRUPT TO OCCUR
E844 FA 1857 CLI ; INTERRUPTS BACK OFF
E845 BBIElAOO 1858 MOV ex,BUFFER_HEAD ; GET POINTER TO HEAD OF BUFFER
E849 381EICOO 1859 CMP ex.BUFFER_TAIL ; TEST END OF BUFFER
E840 74F3 1860 JZ Kl ; LOOP UNTIL SOMETHING IN BUFFER
E84F 6B07 1861 MOV AX,[BXl ; GET SCAN CODE ANO ASCII CODE
E651 E81000 1862 CALL K4 ; MOVE POINTER TO NEXT POSITION
E854 891ElAOO 1863 110v BUFFER_HEAD,BX ; STORE VALUE IN VARIABLE
E858 EBl4 1864 JMP SHORT INTIO_END ; RETURN
1865
1866 ;----- ASCII STATUS
1867
E85A 1868 K2:
E85A FA 1869 CLI I INTERRUPTS OFF
EMe 881EIAOO 1870 MOV ex,BUFFER_HEAD ; GET HEAD POINTER
E85F 3BIEICOO 1871 CMP eX,BUFFER_TAIL I IF EQUAL {Z=ll THEN NOTHING THERE
E863 8B07 1872 MOV AX,[BX]
E865 FB 1673 STI , INTERRUPTS BACK ON
E866 56 1874 POP BX ; RECOVER REGISTER
E867 IF 1875 POP OS ; RECOVER SEGMENT
E868 CA02:00 1876 RET 2 ; THROW AWAY FLAGS
1877
1878 1----- SHIFT STATUS
1879
E86B 1880 K3:
E86B "01700 1881 MOV AL,KBJLAG ; GET THE SHIFT STATUS FLAGS
E86E 1882 INTIO_END:
E86E 58 1883 pop BX ; RECOVER REGISTER
EMF IF 1884 POP OS I RECOVER REGISTERS
E870 CF 1885 IRET ; RETURN TO CALLER
1886 KEYBOARD_IO EHOP
1887
1888 ; ----- INCREMENT A BUFFER POINTER
1889
E871 1890 K4 PROC NEAR
E871 43 1891 INC BX ; MOVE TO NEXT WORD IN LIST
E812 43 1892 INC BX
A-26 System BIOS

LaC OBJ LINE SOURCE
E871 381E8200 1893 eMP BX,8UFFER_END I AT END OF BUFFER?

E677 7504 1894 JNE K5 I NO. CONTINUE
E679 681E8000 1695 MOV BX,BUFFER_ST.6.RT I YES. RESET TO BUFFER BEGINNING
E87D 1696 K5:
E670 C3 1897 RET
1896 K4 ENDP
1899
1900 ;----- TABLE OF SHIFT KEYS AND MASK VALUES
1901
Ea7E 1902 K6 LABEL BYTE
Ea7E 52 1903 DB INSJEY ; INSERT KEY
Ee7F 3A 1904 DB CAPS]EY .Nt/r·CKEY ,SCROll_KEY ,ALTJEY ,tTl_KEY
E880 45
E881 46
E682 38
E883 ID
E864 2A 1905 DB
E885 36
0008 1906 K6L EOU $-K6
1907
1908 1----- SHIFT MASK TABLE
1909
E886 1910 .7 LABEL BYTE
E886 80 1911 DB INS_SHIFT I INSERT MODE SHIFT
E887 40 1912 DB
E888 20
E889 10
E88A 08
E88B 04
EBBC 02 1913 DB
E88D 01
191't
1915 1----- SCAN CODE TABLES
1916
EME 18 1917 K8 DB 27,-1,0,-1,-1,-1,30. -1
EBaF FF
E890 00
E891 FF
E892 FF
E893 FF
E894 IE
E895 FF
E896 FF 1918 08 -1,-1,-1.31,-1.127.-1.17
E897 FF
E898 FF
E899 IF
E89.4 FF
EMS 7F
E89C FF
E890 11
E89E 17 1919 08
E89F 05
E8AO 12
E8Al 14
E8A2 19
E8A3 15
E8A4 09
EBAS OF
E8A6 10 1920 08 16.27,29.10,-1,1.19
E8A7 18
E8A8 10
E8A9 OA
EBAA FF
EBAS 01
EBAC 13
E8AO 04 1921 DB 4.6,7,6,10,11,12:.-1.-1
E8AE 06
EeAF 07
E8BO 08
E8Bl OA
E8B2 DB
E883 DC
EBS4 FF
ESBS FF
E6B6 FF 1922 DB -1.-1.28.26 ,2ft,3, 2:2,2
EBB7 FF
E688 Ie
System BIOS A-27

LaC OBJ LINE SOURCE
EBB9 lA
ESBA 18
ESBB 03
ESBt 16
ESBD 02
ESBE DE 1923 DB 14,13,-1,-1,-1,-1,-1.-1
E6BF 00
ESCO FF
ESCI FF
EBC2 FF
EaCl FF
E8C4 FF
Eacs FF
EaC6 20 1924 DB • ,-I
ESt7 FF
1925 ;----- tTL TABLE SCAN
,Be. 1926
'9 LABEL BYTE
Esce 5E 1927 DB 1;14,95,96,97,98,99,100.101
ESC9 SF
ESCA 60
Esce 61
Esce 62
EeCD 63
EBCE 64
E8CF 65
E8DO 66 1928 DB 102,103,-1,-1,119,-1,132.-1
E8Dl 67
E8D2 FF
E8D3 FF
E604 77
E805 FF
E806 84
E6D7 FF
f6D8 73 1929 DB 115.-1,116,-1,117 ,-1,116.-1
E8D9 FF
ESDA 74
f6DB FF
ESDC 75
EBDD FF
E8DE 76
-.
E6DF FF
E8EO FF 1930 DB
1931 ;----- lC TABLE
E8El
E8El IB
1932
193]
••• lABEL BYTE
DB DISH. I 1234567890-=' ,06H,09H
E6E2 31323334353637
3639302030
ESEE 06
EaEF 09
EBFO 71776572747975 1934 DB 'qwel"tyuiop[ J I ,DOH .-1.' asdfghjkll ' ,027H
696F70SBSD
E6Ft 00
E6FD FF
E8FE 61736466676864
bBbe3B
E90B 27
E909 60 1935 DB 60H,-1 ,5CH. 'zxcvbnnh .1' • ~1, '*' ,-1, '
E90.A FF
E90B 5C
E90C 7A7B6376626E6D
2C2:E2F
E916 FF
E917 2A
E918 FF
E919 20
E91A FF .9..
1937 1----- UC TABLE
DB
-.
E91B 193B .11 LABEL BYTe
E91B IB 1939 DB 27, • !~I$' ,37, 05EH,' &*t 1_+' ,OBH.O
E91C 21402324
E920 25
E921 5E
E922 262A28295F2B
E92B OB
E929 00
E92A 51574552545955
494F507B7D
.... DB 'QWERTYUIOPO' .ODH,-I, • ASDFGHJKU'"
A-28 System BIOS

LOC OBJ LINE SOURCE
£936 00
E937 FF
E938 4153444647484.
484C3A22
E943 7E 1941 DB 07EH.-I, I IZXCVBNM<>?' ,-1.0.-1.' •• -1
E944 FF
E945 7C5A584356424£
4D3C3E3F
E950 FF
E951 00
E952 FF
E953 20
E95<+ FF
1942 ;----- UC TABLE SCAN
E955 1943 K 12 LABEl BYTE
E955 54 1944 DB 84,85,86,87.88,89,90
E956 S5
E957 56
E958 57
E959 58
E95A 59
E958 SA
E<;ISC 58 1945 DB 91,92.93
E950 5C
E95E 50
1946 ;----- AlT TABLE SCAN
E95F 1947 K13 LABEL BYTE
E95F 68 1948 DB 104,105,106,107,108
E960 69
E961 6.1.
£962 68
E963 be
E964 60 1949 DB 109,110,111,112,113
E965 bE
E966 6F
E967 70
E968 71
1950 ;----- t-ruM STATE TABLE
E969 1951 Kl' LABEL BYTE
E969 37363920343536 1952 DB '789-456+1230. '
2B313233302E
1953 ; ----- BASE CASE TABLE
E976 1954 K15 LABEL BYTE
E976 47 1955 DB 71,72,73,-1,75,-1,77
£977 48
E978 49
E979 FF
E97A 4B
Ens FF
E97C 40
E97D fF 1956 DB -1,79,80,81,82,83
EnE 4F
E97F 50
E980 51
E981 52
E982 53
1957
1958 ; ----- KEYBOARD INTERRUPT ROUTINE
1959
E987 1960 ORG OE987H
E987 1961 KB_INT PROC FAR
£987 FB 1962 sn ; ALLOW FURTHER INTERRUPTS
E988 50 1963 PUSH AX
E989 53 1964 PUSH BX
E98A 51 1965 PUSH ex
E988 52 1966 PUSH ox
E<;I8C 56 1967 PUSH SI
E98D 57 1966 PUSH OI
E98E IE 1969 PUSH OS
E98F 06 1970 PUSH ES
E990 Fe 1971 ClO ~ FORWARD DIRECTION
E991 EaAA15 1972 CALL DOS
E994 E460 1973 IN AL,KB_DATA ; READ IN THE CHARACTER
£996 50 1974 PUSH AX ; SAVE IT
E997 E461 1975 IN AL,KB_CTL ; GET THE CONTROL PORT
E999 8AEO 1976 MOV AH,AL ; SAVE VALUE
E99B OC80 1977 OR AL,80H I RESET BIT FOR KEYBOARD
System BIOS A-29

LOC OSJ LINE SOURCE
E990 E661 1976 OUT KB_CTl,AL

E99F 66EO 1979 XCHG AH,AL I GET BACK ORIGINAL CONTROL
E9Al E661 1980 OUT KB_CTL,AL ; KB HAS BEEN RESET
f9A3 58 1981 POP AX ; RECOVER SCAN CODE
E9A4 8AED 1982 HOV AH tAL I SAVE SCAN CODE IN AH ALSO
1983
1984 ; ----- TEST FOR OVERRUN SCAN CODE FROM KEYBOARD
1985
E9A6 3tFF 1986 CMP Al.OFFH ; IS THIS AN DVE'RRUN CHAR
E9A8 7503 1987 JNZ KI6 I NO, TEST FOR SHIFT KEY
f9AA E97A02 1988 JMP K62 ; BUFFERJULl_BEEP
1989
1990 ;----- TEST FOR SHIFT KEYS
1991
f9AO 19n K16: ; TEST_SHIFT
f9AO 247F 1993 AND Al.07FH ; TURN OFF THE BREAK BIT
E9Af DE 1994 PUSH CS
E9BO 07 1995 POP ES ; ESTABLISH ADDRESS OF SHIFT TABLE
E9Bl Bf7EE8 1996 HOV DI.OFFSET K6 I SHIFT KEY TABLE
E984 890800 1997 MOV CX,K6l LENGTH
E9B7 F2 1998 REPNE StASB 1 LOOK THROUGH THE TABLE FOR A MATtH
E9B8 AE
E989 8AC4 1999 MOV Al,AH ; RECOVER SCAN CODE
E9BS 7403 2000 JE KI7 I JUHP I F MATCH FOUND
f9BD E96500 2001 JMP K25 ; IF NO MATCH, THEN SHIFT NOT FOUND
2002
2003 ;----- SHIFT KEY FOUND
2004
E9CO 81EF7FE8 2005 Kl7: SUB DI,OFFSET K6+1 ; ADJUST PTR TO SCAN CODE MTCH
E9C4 2E6AA586E8 2006 MOV AH,CS:K7!oIl ; GET MASK INTO AH
E9C9 ABBD 2007 TEST AL,80H ; TEST FOR BREAK KEY
E9CB 7551 2008 JNZ K23 ; BREAK_SHIFT_FOUND
2009
2010 ;----- SHIFT MAKE FOUND, DETERMINE SET OR TOGGLE
2011
E9CD BOFCIO 2012 CMP
E900 7307 2013 JAE KIa ; IF SCROLL SHIFT OR ABOVE. TOGGLE KEY
2014
2015 ;----- PLAIN SHIFT KEY, SET SHIFT ON
2016
E902 08261700 2017 O. ; TURN ON SHIFT BIT
E906 E98000 2018 JMP ; INTERRUPT_RETURN
2019
2020 1----- TOGGLED SHIFT KEY, TEST FOR 1ST MAKE OR NOT
2021
'909 2022 K18: ; SHIFT-TOGGLE
E909 F606170004 2023 TEST KBJLAG. CTl_SHIFT ; CHECK CTl SHIFT STATE
E9DE 7565 2024 JNZ K25 ; JUMP IF CTl STATE
E9EO 3C52 2025 I CHECK FOR INSERT KEY
E9E2 7522 2026 JNZ K22 ; JUMP IF NOT INSERT KEY
E9E4 F60617Q008 2027 TEST KBJLAG. All_SHIFT ; CHECK FOR ALTERNATE SHIFT
E9E9 755A 2028 JNZ K25 ; JUMP IF ALTERNATE SHIFT
E9EB F60b170020 2029 K19: TEST KBJLAG. NUN_STATE ; CHECK FOR BASE STATE
E9FO 7500 2030 JNZ K21 ; JUMP IF NUH LOCK IS ON
E9F2 F606170003 2031 TEST KBJLAG, LEFT_SHIFT+ RIGHT_SHIFT
E9F7 7400 2032 JZ K22 ; JUMP IF BASE STATE
2033
E9F? 2034 K20: ; NUMERIC ZERO. NOT INSERT KEY
E9F9 863052 2035 MOV AX. 5230H ; PUT OUT AN ASCII ZERO
E9Ft E90601 2036 JMP K57 ; BUFFERJILl
E9FF 2037 K21 : ; HIGHT BE NUMERIC
E9FF F606170DOJ 2038 TEST
fAD4 74F3 2039 JZ K20 ; JUMP NUMERIC, NOT INSERT
2040
EA06 2041 K22: ; SHIFT TOGGLE KEY HIT; PROCESS IT
EA06 84261800 2042 ; IS KEY ALREADY DEPRESSED
fADA 7540 2043 JNZ K26 ; JUMP I f KEY ALREADY DEPRESSED
fADe 08261800 2044 O. KB_FlAG_l.AH ; INDICATE THAT THE KEY IS DEPRESSED
EAlO 30261700 2045 XO. KB_FlAG.AH ; TOGGLE THE SHIFT STATE
EA14 3C52 2046 CMP AL,IHS_KEY ; TEST FOR 1ST HAKE OF INSERT KEY
EA16 7541 2047 JNE K26 ; JUHP IF NOT INSERT KEY
EA16 880052 2048 MOV AX , INSJEY*256 ; SET SCAN CODE INTO AH. 0 INTO AL
EAIB E98701 2049 JMP K57 J PUT INTO OUTPUT BUFfER
2050
2051 ; ----- BREAK SHIFT FOUND
2052
fAIE 2053 K23: ; BREAK-SHIFT-FOUND
A-30 System BIOS

LaC OBJ LINE SOURCE
fAIE SOFClO 2054 eMP AH,SCROll_SHIFT IS THIS A TOGGLE KEY

EA21 731A 2:055 JAE K2' YES. HANDLE BREAK TOGGLE
EA23 F6D4 2056 NOT AH I INVERT MASK
EA25 20261700 2057 AND KB_FlAG.AH ; TURN OFF SHIfT BIT
EA29 3eB8 2058 eMP Al,AlT_KEY+80H IS THIS ALTERNATE SHIFT RelEASE
EAlB 752C ,059 JHE K26 ; INTERRUPT_RETURN
2060
2061 .----- ALTERNATE SHIFT KEY RELEASED. GET THE VALUE INTO BUFFER
2062
fAZD A01900 Z063 MOV AL.ALI_INPUT
EA30 B400 2064 MOV AH,D ; SCAN CODE OF 0
EA32 88261900 2065 MOV ALT_INPUT,AH ; ZERO OUT THE FIELD
EA36 3COO 2066 eMP Al,O WAS THE INPUT=O
£A38 741F Z067 JE K26 ; INTERRUPT_RETURN
EA3A E9AI01 2068 JMP K58 ; IT WASH' T. SO PUT IN BUFFER
EA30 2069 K24: ; BREAK-TOGGLE
EA30 F604 2070 NOT AH INVERT MASK
EA3F 20261800 2071 AND KB_FLAG_l.AH INDICATE NO LONGER DEPRESSED
£A43 EB14 2:072 JMP SHORT K26 INTERRUPT_RETURN
2073
2074 .----- TEST FOR HOLD STATE
2075
EMS 2076 K25: ; tiD-SHIFT-FOUND
EA45 3C80 2077 eMP AL.80H ; TEST FOR BREAK KEY
EA47 7310 2078 JAE K26 NOTHING FOR BREAK CHARS FROM HERE ON
EA49 F606180008 2079 TEST KBJLAG_I.HOLO_STATE ARE WE IN HOLD STATE
EME 7417 2080 JZ K28 BRANCH AROUND TEST IF HOT
EA50 3C45 2081 eMP AL.NUt1_KEY
EA52 7405 2082 JE K26 CAN I T END HOLD ON NUH....LOCK
EA54 a0261800F7 2083 ANO KB_FLAG_l.NOT HOLD_STATE ; TURN OFF THE HOLD STATE BIT
EA59 2084 K26: INTERRUPT-RETURN
EA59 FA 2085 eLI I TURN OFF INTERRUPTS
EA5A B020 2086 MOV AL.Eor ENO OF INTERRUPT COMNAND
EA5C E620 2087 OUT 020H,AL ; SEND COMMAND TO INT CONTROL PORT
EASE 2088 K27: ; INTERRUPT -R ETURN-NO- EOI
EASE 07 2089 POP ES
EASF IF 2090 POP DS
EA60 SF 2091 POP 01
EA61 5E 2092 POP S1
EM2 SA 2093 POP OX
EM3 59 2094 POP ex
EA64 5B 2095 POP 8X
EMS 58 2096 PDP AX RESTORE STATE
EA66 CF 2097 IRET RETURN. INTERRUPTS BACK ON
2098 WITH FLAG CHANGE
2099
2100 ;----- HOT IN HOLD STATE. TEST fOR SPECIAL CHARS
2101
EA67 2102 K28: ; NO-HOLD-STATE
EM7 F606170008 2103 TEST KBJLAG.ALT_SHIFT I ARE WE IN ALTERNATE SHIFT
EA6C 7503 2104 JNZ K29 l JUMP IF ALTERNATE SHIFT
EME E99100 2105 JMP K38 ; JUMP IF NOT ALTERNATE
2106
2107 1----- TEST FOR RESET KEY SEQUENCE (CTl ALT DEL>
2108
EA71 2109 K29: l TEST-RESET
EA7l F606170004 2110 TEST KBJLAG.CTl_SHIFT ; ARE (olE IN CONTROL SHIFT ALSO
EA76 7433 2111 JZ K31 ; NO_RESET
EA78 3C53 2112 eMP AL.DELJEY 1 SHIFT STATE IS THERE. TEST KEY
EA7A 752F 2113 JNE K31 ; NO_RESET
2114
2115 1----- CTL-ALT-DEL HAS BEEN FOUND, DO I/O CLEANUP
2116
EA7C C70672003412 2117 MOV RESET_FLAG. 1234H ; SET FLAG FOR RESET FUNCTION
EA82: EA5BEOOOFO 2118 JMP RESET l JUMP TO POWER ON DIAGNOSTICS
2119
2120 ;----- ALT-INPUT-TABLE
EA87 2121 K30 LABEL BYTE
EA87 52 2122 08 82.79,80.81.75.76.77
EA88 4F
EA89 50
EA8A 51
EA8S 4B
EA8C 4C
EA80 40
EA8E 47 2123 08 71.72.73 I 10 NUMBERS ON KEYPAD
EA8F 48
System BIOS A-31

LOC OBJ LINE SOURCE
EA90 49
2124 ;----- SUPER-SHIFT-TABLE
fA9l 10 2125 DB 16.l7,18.19,20.21.22,23 ; A-Z TYPEWRITER CHARS
fA92 11
EA93 12
EA94 13
EA95 14
EA96 15
EA97 16
EA98 17
E.6.99 18 2126 DB 24,25,30,31,32.33.34.35
EA9A 19
EA9B IE
EA9C IF
EA9D 20
EA9E 21
EA9F ZZ:
EAAO 23
EAAl 24 2127 DB 36,37,38,44,45,46,47,48
fAA2: 25
fAA] 26
EAA4 2C
EAA5 20
EAM 2E
EAA7 2F
EAA8 30
EAA9 31 2128 DB 49.50
EAAA 32
2129
2130 ;----- IN ALTERNATE SHIFT. RESET NOT FOUND
2131
EAA8 2132 K31: ; NO-RESET
EAAS 3C39 2133 CHP Al,S7 ; TEST FOR SPACE KEY
EAAD 7505 2134 JHE K32 ; NOT THERE
EAAF B020 2135 HDV AL, ' ; SET SPACE CHAR
EASl E92101 2136 JHP K57 ; BUFFERJILL
2137
2138 ; ----- LOOK FOR KEY PAD ENTRY
2139
EAB4 2140 K32: ; ALT-KEY-PAD
EAB4 8F87EA 2141 HDV OI,OFFSET K30 ; All-INPUT-TABLE
fAS7 890AOO 2142 HOV CX,10 I LOOK FOR ENTRY USING KEYPAD
fABA F2 2143 REPNE SCASB ; LOOK FOR MATCH
EABS AE
EABC 7512 2144 JHE KJ3 ; NO_AlTJEYPAD
EABE SlEF88EA 2145 SUB DI,OFFSET K30+1 ; 01 NOW HAS ENTRY VALUE
EAt:;: A01900 2146 HOV AL,ALT_INPUT ; GET THE CURRENT BYTE
EAtS 840A 2147 MOV AH.IO ; MULTIPLY BY 10
EAt7 F6E4 2148 MUL AH
EAC9 03C7 2149 ADD AX.DI ; ADO IN THE LATEST ENTRY
EAce A21900 2150 HDV ALT_INPUT,Al ; STORE IT AWAY
fACE E689 2151
2152
JMP "b ; THROW AWAY THAT KEYSTROKE
2153 ;----- LOOK FOR SUPERSHIFT ENTRY

2154
fAOO 2155 K33: I NO-ALT-KEYPAO
fAOO C606190000 2156 ; ZERO ANY PREVIOUS ENTRY INTO INPUT
fADS B9lAOO 2157 MOV CX.26 ; 01. ES ALREADY POINTING
fA08 F2 2158 REPNE SCASB ; LOOK FOR MATCH IN ALPHABET
EA09 AE
fADA 7505 2159 JHE 'l4 I NOT FOUND, FUNCTION KEY OR OTHER
fAOC 8000 2160 HOV AL,O ; ASCII CODE OF ZERO
fADE E9F400 Z161 JMP K57 ; PUT IT IN THE BUFFER
2162
2163 1----- LOOK FOR TOP ROW OF ALTERNATE SHIFT
2164
fAEl 2165 K34: ; ALT-TOP-ROW
EAfI 3C02 2166 CMP AL.Z ; KEY WITH 'I' ON IT
EAn noe 2167 JB K35 ; NOT ONE OF INTERESTING KEYS
EAES 3COE 2168 CHP AL.14 ; IS IT IN THE REGION
EAE7 7308 2169 JAE K35 I AlT-FUNCTION
EAE9 80C476 2170 ADD AH,I18 ; CONVERT PSUEDO SCAN COOE TO RANGE
EAft BODO 2171 HOV AL,O ; INDICATE AS SUCH
EAEE E9E400 2172 JMP K57 ; BUFFERJILL
2173
2174 ;----- TRANSLATE ALTERNATE SHIFT PSEUDO SCAN CODES
2175
A-32 System BIOS

LOC OBJ LINE SOURCE
EAn 2176 K35: ; ALI-FUNCTION

EAFl 3e36 2177 eMP AL.59 I TEST FOR IN TABLE
EAF3 7303 2178 JAE ",7 ; AL T -CONTINUE
EAF5 2179 K36: ; CLOSE-RETURN
EAF5 E961FF 2180 JMP K2. ; IGNORE THE KEY
EAFa 2181 K37: ; Al T -CONTINUE
EAFa 3(47 2182 eMP Al.7l ; IN KEYPAD REGION
EAFA 73F9 2183 JAE K3. ; IF SO. IGNORE
EAFC BB5FE9 2:184 MOV BX,OFFSET K13 ; ALI SHIFT PSEUDO SCAN TABLE
EAFF E'HBOI 2185 JMP i<.:....5 I TRANSLATE THAT
2186
2187 ;----- NOT IN Al"'!:::~NATE SHIFT
2186
fB02 2189 K38: I NOT-All-SHIFT
EBOC F60617DOO4 2190 TEST KBJLAG.CTL_SHIFT ; ARE WE IN CONTROL SHIFT
EB07 7458 2191 JZ K44 ; NOT -eTL-SHIFT
2192
2193 ; ----- CONTROL SHIFT, TEST SPECIAL CHARACTERS
2194 ; ----- TEST FOR BREAK AND PAUSE KEYS
2195
E809 3C46 2196 eMP Al,SCROLL]EY ; TEST FOR BREAK
fBOB 7518 2197 JHE K39 ; NO-BREAK
EBOD 861E8000 2198 MOV BX I BUFFER_START ; RESET BUFFER TO EMPTY
EBll 891ElAOO 2199 MOV BUFFER_HEAD,BX
EB15 89lEICOO 2200 MOV BUFFER_TAIL.BX
EB19 C606710080 2201 MOV BIOS_BREAK,80H ; TURN ON BIOS_BREAK BIT
EB1E C[HB 2202 INT IBH ; BREAK INTERRUPT VECTOR
EB20 2BCO 2203 SUB AX,AX ; PUT OUT DUMMY CHARACTER
EB22 E9BOOO 2204 JMP K57 ; BUFFERJIll
E825 2205 K39: ; NO-BREAK
EB25 3C45 2206 eMP Al.NUH_KEY ; LOOK FOR PAUSE KEY
EB27 7521 2207 JHE K41 ; NO-PAUSE
EB29 800El80008 2208 OR KBJlAG_l.HOlD_STATE ; TURN ON THE HOLD FLAG
EB2E B020 2209 MOV Al.EOI ; END OF INTERRUPT TO CONTROL PORT
EB30 E620 2210 OUT 020H.Al ; ALLOW FVRTHER KEYSTROKE INTS
2211
2212 ;----- DURING PAUSE INTERVAL. TURN CRT BACK ON
2213
EB32 803E490007 2214 eMP CRT_MODE ,7 ; IS THIS BLACK AND WHITE CARD
E837 7407 2215 JE K40 ; YES. NOTHING TO DO
EB39 BA0803 2216 MOV OX.0308H ; PORT FOR COLOR CARD
EB3C A06500 2217 MOV ALICRT_MODE_SEl ; GET THE VALUE OF THE CURRENT MODE
EB3F EE 2218 OUT DX.AL SET THE CRT MODE. SO THAT CRT IS ON
EB40 2219 K40: PAUSE-LOOP
EB40 F6061BOOOB
EB45 75F9
2220
2221
TEST
JHZ
KBJLAG_l,HOLD_STATE
K40 , LOOP UNTIL FLAG TURNED OFF
EB47 E914FF 2222 JMP K27 , INT ERRUPT_R ETURN_ NO_ EOI
EB4A 2223 K41 : ; NO-PAUSE
2224
2225 ;----- TEST SPECIAL CASE KEY 55
2226
EMA 3C37 2227 eMP AL.55
EB4C 7506 222B JHE K42 I NOT-KEY-55
EB4E B80012: 2229 MOV AX.l14*256 I START/STOP PRINTING SWITCH
EBSI E98100 2230 JMP K57 ; BUFFERJIlL
2231
2232 1----- SET UP TO TRANSLATE CONTROL SHIFT
2233
EB54 2234 K42: ; NOT-KEY-55
EB54 BB8EE8 2235 MOV BX,OFFSET K8 I SET UP TO TJ;!AHSLATE tTL
EBS7 3C3B 2236 eMP AL,59 ; IS IT IN TABLE
2237 I CTL-TABLE-TRANSLATE
EB59 12:76 2238 JB K5. I YES. GO TRANSLATE CHAR
EBSB 2239 K43: ; CTL-TABLE-TRANSLATE
EBSB BBC8E8 2240 MOV BX,oFFSET K9 I CTL TABLE SCAN
EB5E E9BCOO 2241 JMP K63 I TRANSLATE_SCAN
2242
2243 ; ----- NOT IN CONTROL SHIFT
2244
EB61 2245 K44: I NOT-CTL-SHIFT
EB61 3C47 2246 eMP ,U.71 I TEST FOR KEYPAD REGION
EB63 732:C 2247 JAE K4B ; HANDLE KEYPAD REGION
EB65 Fb06170003 2248 TEST KBJ LAG , LEFT_SHIFT+RIGHT_SHIFT
EB6A 745A 2249 JZ K54 ; TEST FOR SHIFT STATE
2250
2251 1----- UPPER CASE. HANDLE SPECIAL CASES
2252
System BIOS A-33

LOCOBJ LINE SOURCE
EB6C 3eOF 2253 CHP Al.lS I BACK TAB KEY

fB6E 7505 2254 JHE .OS ; NOT-SACK-TAB
E870 88000F 2255 HOV AX.lS*Z56 ; SET PSEUDO SCAN CODE
fB73 E660 2256 JHP SHORT K57 ; BUFFER_FILL
E875 2257 K45: ; NOT-SACK-TAB
E875 3e37 2258 CHP Al.s5 ; PIHHT SCREEN KEY
EB77 7509 2259 JHE .0. ; NOT-PRINT-SCREEN
2260
2261 ;----- ISSUE INTERRUPT TO INDICATE PRINT SCREEN FUNCTION
2262
E879 B020 2263 HOV AL.EO! I END OF CURRENT INTERRUPT
EB7B E620 2264 OUT 020H ,AL ; SO FURTHER THINGS CAN HAPPEN
EB7C COOS 2265 IHT SH ; ISSUE PRINT SCREEN INTERRUPT
EB7F E90CFE
EB82
2266
2267 K46:
JHP
." I GO BACK WITHOUT EOI OCCURRING
; NOT-PRINT-SCREEN
EBB2 3e38 2268 CHP AL.59 ; FUNCTION KEYS
E584 7206 2269 JB '07 ; NOT-UPPER-FUNCTION
EBa6 8855E9 2270 HOV eX.OFFSET K12 ; UPPER CASE PSEUDO SCAN CODES
EB89 E99100 2271 JHP K63 ; TRANSLATE_SCAN
EBSC 2272 K47: ; NOT -UPPER-FUNCTION
EB8C BBIBE9 2273 HOV BX.OFFSET Kll ; POINT TO UPPER CASE TABLE
EBaF f840 2274 JHP SHORT K56 ; OK. TRANSLATE THE CHAR
2275
2276 ;----- KEYPAD KEYS. MUST TEST HUM LOCK FOR DETERMINATION
2277
E891 2278 K48: ; KEYPAD-REGION
fB9l F60617002Q 2279 TEST KBJLAG.NUM_STATE ; ARE WE IN NUM_LOCK
EB96 7520 22M JHZ .52 ; TEST FOR SURE
fB98 F606170003 2281 TEST KBJLAG.LEFT_SHIFT+RIGHT_SHIFT ; ARE WE IN SHIFT STATE
EB90 7520 2282 JHZ '53 ; IF SHIFTED. REAllY NUM STATE
2263
2284 1----- BASE CASE FOR KEYPAD
2285
EB9F 2286 K49: ; BASE-CASE
EB9F 3C4A 2267 CHP AL.74 ; SPECIAL CASE FOR A COUPLE OF KEYS
fBAI 740B 2268 JE .SO ; MINUS
EBA3 3C4E 2289 CHP AL.76
EBA5 740C 2290 JE '51
EBA7 2C47 2291 SUB AL.7l ; CONVERT ORIGIN
EBA9 B876E9 2292 HOV BX.OFFSET K15 ; BASE CASE TABLE
EBAC fB7l 2293 JHP SHORT K64 ; CONVERT TO PSEUDO SCAN
EBAE 2294 K50:
EBAE B8ZD4A 2295 HOV AX.74*256+'-' ; MINUS
EBBI EB22 2296 JHP SHORT K57 ; BUFFER_FILL
EBB3 2297 K51:
EBB3 B62B4E 2296 HOV AX.78*256+'+' ; PLUS
EBB6 EBID 2299 JHP SHORT K57 ; BUFFERJIlL
2300
2301 ;----- MIGHT BE NUN LOCK. TEST SHIFT STATUS
2302
EBB6 2303 K52: ; ALMOST-NUN-STATE
EBBB F606170003 2304 TEST KBJLAG.LEFT_SHIFT+RIGHT_SHIFT
EBBD 75EO 2305 JHZ .09 ; SHIFTED TEMP OUT OF NUM STATE
EBBF 2306 K53: ; REALLYJIUN_STATE
EBBF 2C46 2307 SUB AL.70 ; CONVERT ORIGIN
EBCI BB69E9 2308 MOV BX,OFFSET K14 ; NUM STATE TABLE
EBC4 EBOB 2309 JMP SHORT K56 ; TRANSLATE_CHAR
2310
2311 ; ----- PLAIN OLD LOWER CASE
2312
EBC6 2313 K54: I NOT-SHIFT
EBC6 3C3B 2314 CHP AL,59 ; TEST FOR FUNCTION KEYS
EBCB 7204 2315 JB .55 ; NOT-LOWER-FUNCTION
EBCA BOOO 2316 HOV Al.O ; SCAN CODE IN AH ALREADY
EBCC EB07 2317 JHP SHORT K57 ; BUFFER_FILL
EBCE 2318 K55: ; NOT-LOWER-FUNCTION
EBCE BBEIE6 2319 HOV BX.OFFSET KID ; LC TABLE
2320
2321 ; ----- TRANSLATE THE CHARACTER
2322
EB01 2323 K56: ; TRANSLATE-CHAR
EBOI FEC6 2324 DEC AL I CONVERT ORIGIN
EBD3 ZED7 2325 XLAT CS:K11 ; CONVERT THE SCAN CODE TO ASCII
2326
2327 1----- PUT CHARACTER INTO BUFFER
2326
E80S 2329 K57: I BUFFER-FILL
A-34 System BIOS

LOC OBJ LINE SOURCE
EBDS 3eFF 2330 eMP .H.-l ; IS THIS AN IGNORE CHAR

EB07 741F 2331 JE 059 ; YES. DO NOTHING WITH IT
E609 BOFCFF 2:332 eMP AH.-l ; LOOK FOR -1 PSEUDO SCAN
EBDC 74lA 2333 JE 059 J NEAFCINTERRUPT_RETURN
2334
2335 1----- HANDLE THE CAPS LOCK PROBLE"
2336
EBDE 2.337 K58: I BUfFER-FIlL-HaTEST
EBDE F606170040 2338 TEST KB]LAG,CAPS_STATE I ARE WE IN CAPS LOCK STATE
EBn 742:0 2339 JZ 061 I SKIP IF NOT
2340
2341 1----- IN CAPS lOCK STATE
2342
EBES f606170003 2343 TEST KBJLAG.lEFT_SHIFT+RIGHT_SHIFT I TEST FOR SHIFT STATE
EBEA 740F 2344 JZ 060 I IF NOT SHIFT I CONVERT LOWER TO UPPER
2345
234& ; ----- COHVERT ANY UPPER CASE TO LOWER CASE
2347
EBEC 3C41 2346 eMP AL, 'A' ; FIND OUT IF ALPHABETIC
EBEE 7215 2349 Je 061 ; NOT_tAPS_STATE
EBFO 3C5A 2350 eMP AL.'Z'
EBF2 7711 2351 JA 061 ; NOT_CAPS_STATE
EBF4 0420 2352 ADD AL. 'a'-'A' I CONVERT TO LOWER CASE
EBF6 EeOD 2353 JMP SHORT K61 ; NOT_CAPS_STATE
EBFa 2:354 K59: ; NEAR-INTERIWPT-RETURN
EBfa E95EFE 2355 JMP 026 I INTERRUPT_RETURN
2356
2:357 ;----- CONVERT ANY LOWER CASE TO UPPER CASE
2358
EBFB 2359 K60: j LOWER-TO-UPPER
EBFB 3C61 2:360 eMP AL, '.,.' i FIND OUT IF ALPHABETIC
EBFD 7206 2361 JB 061 ; NOT_CAPS_STATE
EBFF 3C7A 2362 eMP AL, 'z'
ECOI 7702: 2363 JA 061 ; NOT_CAPS_STATE
EC03 2C20 2364 SUB AL. '.,.'-'A' ; CONVERT TO UPPER CASE
EC05 2365 K61: ; NOT -CAPS-STATE
EC05 8BIEICOO 2366 MOV BX ,BUFFER_TAIL I GET THE END POINTER TO TIlE BUFFER
EC09 SBn 2367 MOV SI,BX ; SAVE TIlE VALUE
ECOB E863FC 2368 CALL 04 ; ADVANCE tHE TAIL
ECOE 3BIElAOO 2369 eMP BX,BUFFER_HEAD ; HAS THE BUFFER WRAPPED AROUND
EC12 7413 2370 JE 062 ; BUFFERJULL_BEEP
EC14 8904 2371 MOV [SIl,AX j STORE THE VALUE
EC16 891EICOO 2372: MOV BUFFER_TAIL,BX ; MOVE THE POINTER UP
ECIA E93CFE 2373 JMP 026 ; INTERRUPT_RETURN
2:374
~375 j----- TRANSLATE SCAN FOR PSEUDO SCAN CODES
2376
ECIO 2377 K63: I TRANSLATE-SCAN
ECID 2C3B 2378 SUB AL.59 j CONVERT ORIGIN TO FUNCTION KEYS
ECIF 2379 K64: ; TRANSLATE-SCAN-ORGO
ECIF 2ED7 2:380 XLAT CS:K9 ; CTL TABLE SCAN
EC2l SAEO 2381 MOV AH,AL j PUT VALUE INTO AH
EC23 BODO 2362 MOV AL,O I ZERO ASCII CODE
EC25 EBAE 2383 JMP 057 ; PUT IT INTO THE BUFFER
2384
2385 KB_INT ENDP
2386
2:387 j----- BUFFER IS FULL, SOUND TIlE BEEPER
2388
EC27 2389 K62: ; BUFFER-FULL-BEEP
EC27 B020 2390 MOV AL,EOI j END OF INTERRUPT COMMAHD
EC29 E620 2391 OUT 20H ,AL I SEtID COMMAND TO INT CONTROL PORT
EC2:B BB8000 2392 MOV BX,oaOH ; NUMBER OF CYCLES FOR 1/12 SECOND TONE
EC2E E461 2393 IN AL.KB_CTL ; GET CONTROL INFORMATION
EC30 50 2394 PUSH AX I SAVE
EC31 2.395 K65: ; BEEP-CYCLE
EC31 24FC 2396 AND Al,OFCH ; TURN OFF TIMER GATE Atil SPEAKER DATA
ECB E661 2:397 OUT KB_CTl,AL ; OUTPUT TO CONTROL
EC35 B94BOO 2398 MOV CX.48H ; HALF CYCLE TIME FOR TONE
Ee38 2399 K66:
EC38 E2:FE 2400 lOOP 066 ; SPEAKER OFF
EC3A OC02 2401 OR Al,2 ; TURN ON SPEAKER BIT
EC3C E661 2402 OUT KB_CTl,Al ; OUTPUT TO CONTROL
EC3E B94BOO 2403 MOV CX,48H I SET UP COUNT
EC41 2404 K67:
EC41 E2FE 2405 LODP 067 ; ANOTHER HALF CYCLE
EC43 46 2:406 DEC ex I TOTU TIME COUNT
System BIOS A-35

LOC OBJ LINE SOURCE
EC44 75E8 2407 JNZ K65 ; DO ANOTHER CYCLE

Et46 58 2408 pop AX I RECOVER CONTROL
Et47 E661 2409 OUT KB_CTL,AL J OUTPUT THE CONTROL
EC49 E91ZFE 2410 JNP .27
2411
2412 ROS CHECKSUH SUBROUTINE
2413 ; ----------------------------------------
EC4C 2414 ReS_CHECKSUM PROt NEAR ; NEXT_ROS_MODUlE
EC4C 890020 2415 NOV eX,BIn i NUMBER OF BYTES TO ADO
EC4F 2416 ROS_CHECKsur"CCNT: ; ENTRY FOR OPTIONAL ROS TEST
EC4F 32CO 2417 XOR AL.Al
EC51 2418 e26:
EC51 0207 2419 AOO Al,DS:(BX]
EC53 43 2420 INC BX I POINT TO NEXT BYTE
EC54 EZFB 2421 LOOP C26 I ADO All BYTES IN RDS MODULE
EC56 DAca 2422 OR AL,AL I SUM = O?
EC58 C3 2423 RET
2424 ROS_CHECKSUM 'NOP
2425
2426 j-- INT 13 --------------------------------------------------------------
2427 ; DISKETTE 110
2428 nus INTERFACE PROVIDES ACCESS TO THE 5 1/4" DISKETTE DRIVES
2429 INPUT
2430 (AH )=0 RESET DISKETTE SYSTEM
2431 HARD RESET TO NEC, PREPARE COMMAND, RECAL REQUIRED
2432 ON ALL DRIVES
2433 (AH)=l READ THE STATUS OF THE SYSTEM INTO (AU
2434 DISKETTE_STATUS FROM LAST OPERATION IS USED
2435
2436 ; REGISTERS FOR READIWRITE/VERIfY/FORMAT
2437 (OU - DRIVE HUMBER (0-3 ALLOWED, VALUE CHECKED)
2438 (DH) - HEAD NUMBER (0-1 ALLOWED, NOT VALUE CHECKEO)
2439 (CH) - TRACK NUMBER (0-39, NOT VALUE CHECKED)
2440 (CLl - SECTOR NU~IBER (1-8. NOT VALUE CHECKED.
2441 HOT USED FOR FORMAll
2442 (ALI - NUMBER OF SECTORS ( MAX = 8, NOT VALUE CHECKED. NOT USED;
2443 FOR FORMATI
2444 (ES:BX) - ADDRESS OF BUFFER ( HOT REQUIRED FOR VERIFY)
2445
2446 (AH 1=2 READ THE DESIRED SECTORS INTO MEMORY
2447 {AH )=3 WRITE THE DESIRED SECTORS FROM MEMORY
2448 (AH )=4 VERIFY THE DESIRED SECTORS
2449 (AH )=5 FORMAT THE DESIRED TRACK
2450 FOR THE FORMAT OPERATION. THE BUFFER POINTER (ES,BXI
2451 MUST POINT TO THE COLLECTION OF DESIRED ADDRESS FIELDS
2452 FOR THE TRACK. EACH FI'HD IS COMPOSED OF 4 BYTES,
2453 (C,H,R,NI, WHERE C = TRACK NUMBER. H=HEAD HUMBER,
2454 R = SECTOR HUMBER. N= NUMBER OF BYTES PER SECTOR
2455 100=128, 01=256, 02=512, 03=10241. 'THERE MUST BE ONE
2456 ENTRY FOR EVERY SECTOR ON THE TRACK. THIS INFORMATION
2457 IS USED TO FINO THE REQUESTED SECTOR DURING READ/wRITE
2458 ACCESS.
2:459
2460 ; DATA VARIABLE -- DISK_POINTER
2461 DOUBLE WORD POINTER TO THE CURRENT SET OF DISKETTE PARAMETERS
2462 I OUTPIJT
2463 AH = STATUS OF OPERATION
2:464 STATUS BITS ARE DEFINED IN THE EQUATES FOR
2465 DISKETTE_STATUS VARIABLE IN THE DATA SEGMENT OF THIS
2466 MODULE.
2467 CY = 0 SUCCESSFUL OPERATION (AH=O ON RETURNI
2468 CY = 1 FAILED OPERATION (AH HAS ERROR REASON)
2469 FOR READ/WRITEIVERIFY
2470 DS,BX,DX,CH,Cl PRESERVED
2471 AL = NUMBER OF SECTORS ACTUALLY READ
2472 ***** AL MAY NOT BE CORRECT IF TIME OUT ERROR OCCURS
2473 NOTE: IF AN ERROR IS REPORTED BY THE DISKETTE CODE. THE
2474 APPROPRIATE ACTION IS TO RESET THE DISKETTE. THEN RETRY:
2475 THE OPERATION. ON READ ACCESSES. NO MOTOR START DELAY
2476 IS TAKEN, SO THAT THREE RETRIES ARE REQUIRED ON READS
2477 TO ENSURE THAT THE PROBLEM IS NOT DUE TO MOTOR
2478 START-UP.
2479 1------------------------------------------------------------------------
2480 ASSUME CS:CODE,DS:DATA,ES:DATA
E(59 2481 ORG OEC59H
EC59 2482 OISKETTE_IO PROC FAR
EC59 FB 2483 STI ; INTERRUPTS BACK ON
A-36 System BIOS

LaC OBJ LINE SOURCE
ECSA 53 2484 PUSH ex I SAVE ADDRESS

EC5B 51 2485 PUSH ex
ECSC IE 2486 PUSH os I SAVE SEGMENT REGISTER VALUE
Eeso 56 2487 PUSH Sl I SAVE All REGISTERS DURING OPERATION
ECSf 57 2488 PUSH 01
ECSF 55 2469 PUSH 8P
Et60 52 2490 PUSH ox
EC6l 8BEt 2491 NOV BP,SP I SET UP POINTER TO HEAD PAR"
EC63 f8D812 2492 CALL DDS
EC66 f8lCOO 2493 CALL Jl I CALL THE REST TO ENSURE OS RESTORED
fC69 880400 2494 HOV BX,4 I GET THE MOTOR WAIT PARAMETER
ECbC EaFOOI 2495 CALL GET_PARM
fe6 F 88264000 2496 NOV MOTDR_COUNT.AH I SET THE TIMER COUNT FOR THE MOTOR
fen 811.264100 2497 MOV AH.DISKETTE_STATUS I GET STATUS OF OPERATION
fe77 80FCOl 2498 CMP AH.l ; SET THE CARRY FLAG TO INDICATE
Ee7A F5 2499 CMC ; SUCCESS OR FAILtmE
Ee7B SA 2500 POP OX ; RESTORE ALL REGISTERS
EC7t 50 2501 POP BP
EC7D SF 2502 POP 01
Ee7E Sf 2503 POP 51
Ee7F IF 2504 POP os
EcaD 59 2505 POP cx
EC81 58 2506 POP ex I RECOVER ADDRESS
EC82 CA020D 2507 RET 2 ; THROW AWAY SAVED FLAGS
2508 ENIlP
2509
EC85 2510 Jl PROC NEAR
EC85 SAFO 2511 HOV DH,Al I SAVE I SECTORS IN DH
EC87 8026)F007F 2512 AND MOTOR_STATUS,07FH I INDICATE A READ OPERATION
ECat OAE4 2513 OR AH,AH ; AH=O
ECBE 7427 2514 JZ DISK_RESET
Ee90 FEte 2515 DEC AH ; AH=l
fen. 7473 2516 JZ DISK_STATUS
EC94 C606410000 2517 MOV DISKETTE_STATUS,O ; RESET THE STATUS INDICATOR
Ee99 BOFA04 2518 CMP DL.4 I TEST FOR DRIVE IN 0-3 RANGE
Ee9C 7313 2519 JAE J3 ; ERROR IF ABOVE
EC9E FEte 2520 DEC AH ; AH=2
ECAO 7469 2521 JZ
ECA2 FEee 2522 DEC ; AH=3
EeM 7503 2523 JHZ J2 I TEST_DISK_VERF
ECAb E99500 2524 JMP
EtA9 2525 J2: ; TEST_DISK_VERF
EtA9 fEee 2526 DEC AH ; AH=4
ECAB 7467 2527 JZ OIS~VERF
ECAD FEte 2528 DEC AH I AH=5

ECAF 7467 2529 JZ DISKJORMAT
ECBl 2530 J3:
ECBl C606410001 2531 HOV QISKETTE_STATUS,BAD_CMQ; ERROR CODE. NO SECTORS TRANSFERRED
ECB6 C3 2532: RET ; UNDEFINED OPERATION
2533 Jl ENOP
2534
2535 ;----- RESET THE DISKETTE SYSTEM
2536
ECB7 2537 DISK_RESET PROC NEAR
ECB7 BAf203 2538 MOV DX,03F2H ; ADAPTER CONTROL PORT
EeBA FA 2539 CLI ; NO INTERRUPTS
ECBB A03FOD 2540 HOV AL,MOTOR_STATUS ; WHICH MOTOR IS ON
ECBE 8104 2541 MOV CL,4 ; SH 1FT COUNT
Eceo 02EO 2542 SAL AL,Cl ; MOVE MOTOR VALUE TO HIGH NYBBlE
ECC2 11.620 2543 TEST AL, 20H ; SE LECT CORRESPONDING DRIVE
ECt4 7S0C 2544 JNZ J5 J JlR1P IF MOTOR ONE IS ON
ECC6 A840 2545 TEST AL. 40H
Ecca 7506 2546 JNZ J4 I JUf1P IF MOTOR TWO IS ON
ECCA 11.880 2547 TEST AL. aOH
Ecce 7406 2548 JZ J6 ; JUMP IF MOTOR ZERO IS ON
ECCE FEeD 2549 INC AL
Eeoo 2550 J4:
EeDO FEtO 2551 INC AL
fC02 2552 J5:
fC02 FEtO 2553 INC AL
ECD4 2554 J6:
ECD4 OC06 2555 OR AL,a I TURN ON INTERRUPT ENABLE
fCob EE 2556 OUT OX,AL I RESET THE ADAPTER
ECD7 C6063EOOOO 2557 MOV SEEK_STArus,O ; SET RECAL REQUIRED ON ALL DRIVES
Eeoc C606410000 2558 MOV DISKETTE_STATUS. 0 ; SET OK STATUS fOR DISKETTE
ftEI OC04 2559 OR AL,4 ; TURN OFf RESET
feB EE 2560 oor DX,.t,L ; TURN OFF THE RESET
System BIOS A-37

LOC OBJ LINE SOURCE
ECE4 FB 2561 STI ; REENABlE THE INTERRUPTS

feES E82A02 2562 CAll CHK_STAT_2 I DO SENSE INTERRUPT STATUS
2563 ; FOLLOWING RESET
EtEs ,0,04200 2564 MOV I IGNORE ERROR RETURN AND 00 OWN TEST
EtEB 3etO 2565 eMP AL,OCOH ; TEST FOR DRIVE READY TRANSITION
ECEO 7406 2566 JZ J7 ; EVERYTHING OK
ECEF 800E410020 2567 OR DISKETTE_STATUS,8AD_NEC I SET ERROR CODE
ECF4 C3 2568 RET
2569
2570 ;----- SEND SPECIFY COMMAND TO NEt
2571
ECF5 2572 J7: ; DRIVE_READY
ECFS 8403 2573 MOV AH,03H ; SPECIFY COMMAND
feF7 E84701 2574 CALL NEC_OUTPUT ; OUTPUT THE CONMAND
EeFA B80100 2575 MOV BX,I ; FIRST BYTE PARM IN BLOCK
ECFa E86eDl 2576 CALL GET_PARM ; TO THE NEC CONTROLLER
EDOO 6B0300 2577 MOV 6X.3 ; SECOND BYTE PARM IN BLOCK
E003 E86601 2578 CALL GET]ARM ; TO THE NEC CONTROLLER
ED06 2579 J8: ; RESET_RET
Eo06 C3 2580 RET ; RETURN TO CALLER
2581 DISK_RESET ENOP
2582
2583 ; ----- DISKETTE STATUS ROUTINE
2584
ED07 2585 PROC NEAR
ED07 ,0,04100 2586 MOV A L, DISKETTE_STATUS
mOA C3 2587 RET
2588 ENOP
2589
2590 ; ----- DISKETTE READ
2591
EDOB 2592 DISK_READ PROt NEAR
EO DB B046 2593 MOV Al,046H I READ COMMAND FOR DMA
EOOD 2594 J9: ; DISK_READ_CONT
EO 00 E8B801 2595 CALL DNA_SETUP j SET UP THE DMA
EOIO 84E6 2596 MOV AH,OE6H ; SET UP PO CONNANO FOR NEC CONTROLLER
E012 E836 2597 JMP SHORT IUCOPN I GO 00 THE OPERATION
2598 DISK_READ ENDP
2599
2600 j----- DISKETTE VERIFY
2601
E014 2602 DISK_VERF PROC NEAR
E014 8042 2603 MOV AL,042H I VERIFY COMMAND FOR oMA
ED16 EBFS 2604 JMP J9 ; DO AS IF DISK READ
2605 DISK_VERF ENOP
2606
2607 ;----- DISKETTE FORMAT
2608
ED18 2609 DISK_FORNAT PROt NEAR
ED18 a00E3F0080 2610 OR MOTOR_STATUS,80H I INDICATE WRITE OPERATION
EOlD 804,0, 2611 MOV Al,04AH ; WILL WRITE TO THE DISKETTE
[OIF E8A601 2612 CALL DHA_SETUP ; SET UP THE DMA
f022 8440 2613 MOV AH.04DH ; ESTABLISH THE FORMAT COMMAND
EO.24 EB24 2614 JMP SHORT RlrCOPN ; 00 THE OPERATION
f026 2615 JiO: I CONTINUATION OF RICOPN FOR FHT
f026 BB0700 2616 MOV BX.7 ; GET THE

E029 E84001 2617 CAll GET_PARM ; BYTES/SECTOR VALUE TO NEC
E02e 880900 2618 MOV BX.9 ; GET THE
ED2F £63,0,01 2619 CALL GET_PARM ; SECTORS/TRACK VALUE TO NEC
E032 aBOFCD 2620 MOV BX,15 ; GET THE
E035 £83401 2621 CALL GET_PARM j GAP LENGTH VALUE TO NEC
E038 B81100 2622 MOV BX.17 ; GET THE FILLER BYTE
E038 E9A800 2623 JMP J16 ; TO THE CONTROLLER
2624 DISK_FORMAT ENDP
2625
2626 1----- DISKETTE WRITE ROUTINE
2627
E03£ 2628 PROC NEAR
ED3E 800E3FOQ80 2629 j INDICATE WRITE OPERATION
E043 804,0, 2630 MOV AL.04AH ; DMA WRITE COMMAND
E045 E88001 2631 CAll DMA_SETUP
E048 84C5 2632 HOV AH,OCSH ; NEC COMMAND TO WRITE TO DISKETTE
2633 DISK_WRITE EHOP
2634
2635 j----- ALLOW WRITE ROUTINE TO FALL nITO RlrCOPN
2636
2637 j ----------------------------------------------------------------
A-38 System BIOS

LOC OBJ LINE SOURCE
2638 ; RW_OPN
2639 THIS ROUTINE PERFORMS THE READIWRITE/vERIFY OPERATION
2640 ; ----------------------------------------------------------------
ED4A 2641 RW_OPN PROC NEAR
ED4A 7308 2642 JNe J11 ; TEST FOR DHA ERROR
ED4C C606410009 2643 MOV DISKETTE_STATUS,DHA_BOUNOARY ; SET ERROR
E051 BODO 2644 NOV AL,O ; NO SECTORS TRANSfERRED
E053 C3 2645 RET I RETURN TO MAIN ROUTINE
E054 2646 Jll:
E054 50 2647 PUSH AX I SAVE TIlE COHMAND
2648
2649 ; ----- TURN ON THE MOTOR ANO SELECT TIlE DRIVE
2650
f055 51 2651 PUSH CX ; SAVE THE TIS PARHS
E056 8ACA 2652 MOV Cl,Ol ; GET DRIVE NUMBER AS SHIFT COUNT
EOSS BOOI 2653 MOV Al,l MASK fOR DETERMINING HOTOR BIT
ED SA 02EO 2654 SAL AL,CL SHIFT THE MASK BIT
E05C FA 2655 eLI I NO INTERRUPTS WHILE DETERMINING
2656 HOTOR STATUS
EDSO C6064000FF 2657 MOV MOTOR_COUNT ,OFFH ; SET LARGE COUNT DURING OPERATION
E062 84063FOO 2658 TEST Al,MOTOR_STATUS TEST THAT MOTOR FOR OPERATlNG
E06b 7531 2659 JNZ J14 If RUNNING, SKIP THE WAIT
E068 80263fOOFO 2660 AND MOTOR_STATUS,OFOH TURN OFF All MOTOR BITS
f06D 08063FOO 2661 OR MOTOR_STATUS,Al I TURN ON THE CURRENT MOTOR
E071 FB 2662 STI INTERRUPTS BACK ON
E072 BOlO 2663 NOV Al,lOH ; MASK BIT
E074 o2EO 2664 SAL AL,Cl ; DEVElOP BIT MASK FOR MOTOR ENABLE
f076 DAC2 2665 OR AL,DL ; GET DRIVE SELECT BITS IN
E078 ceDe 2666 OR AL,OCH ; NO RESET, ENABLE DMA/INT
f07A 52 2667 PUSH OX ; SAVE REG
E07B BAF203 2666 MOV OX,03F2H ; CONTROL PORT ADDRESS
f07E EE 2669 OUT OX,Al
ED7F SA 2670 POP OX I RECOVER REGISTERS
2671
2672 ;----- WAIT FOR MOTOR IF WRITE OPERATION
2673
E080 F6063F0080 2674 TEST MOTOR_STATUS,60H IS THIS A WRITE
E085 7412 2675 JZ J14 ; NO, CONTINUE WITHOUT WAIT
ED87 861400 2676 MOV BX,20 ; GET THE MOTOR WAIT
EDBA EBOFOD 2677 CAll GET_PARM ; PARAMETER
E08D OAE4 2678 OR AH,AH I TEST FOR NO WAIT
EoaF 2679 J12: I TEST_WAIT_TINE
ED8F 7408 2680 JZ J14 ; EXIT WITH TIME EXPIRED
ED91 28C9 2681 SUB ex,cx ; SET UP 1/8 SECOND LOOP TINE
E093 2682 J13:
E093 E2FE 2683 lOOP J13 ; WAIT FOR THE REQUIRED TlME
ED95 FEee 2684 DEC AH ; DECREMENT TINE VALUE
E097 fBF6 2665 JMP J12 ; ARE WE DONE YET
E099 2666 J14: I MOTOR_RUNNING
E099 FB 2667 STI ; INTERRUPTS BACK ON FOR BYPASS WAIT
ED9A 59 2666 POP ex
2689
2690 ;----- 00 THE SEEK OPERATION
2691
ED9B fBOFOO 2692 CAll SEEK ; HOVE TO CORRECT TRACK
E09E 58 2693 POP AX ; RECOVER COMMAND
ED9F SAFe 2694 MOV BH,AH ; SAVE COMMAND IN BH
EOAI B600 2695 MOV OH,O ; SET NO SECTORS READ IN CASE OF ERROR
fOAl 7248 2696 JC J17 ; I f ERROR, THEN EXIT AFTER MOTOR OFF
EDAS BEFOED90 2697 MOV SI,OfFSET J17 ; DUMMY RETURN ON STACK FOR NEC_OUTPUT
EDA9 56 2698 PUSH SI SO THAT IT WIll RETURN TO MOTOR OFF
2699 ; LOCATION
2700
2701 ;----- SEND OUT THE PARAMETERS TO THE CONTROLLER
2702
EDAA E89400 2703 CALL NEC_OUTPUT ; OUTPUT THE OPERATION COMMAND
EOAD SA660l 2704 MOV AH,EBP+IJ ; GET THE CURRENT HEAD NUMBER
EDBO 00E4 2705 SAL AH.l I MOVE IT TO BIT 2
EDBl 00E4 2706 SAl AH,l
EDB4 80E404 2707 AND AH,4 ; ISOLATE THAT BIT
EOB7 OAfl 2708 OR AH,DL ; OR IN THE DRIVE HUMBER
EDB9 E88500 2709 CAll NEC_OUTPUT
2710
2711 ;----- TEST FOR FORMAT COMMAND
2712
fDBC 80FF4D 2713 eMP BH ,04DH ; IS THIS A FORMAT OPERATION
fOSF 7503 2714 JNE J15 ; NO. CONTINUE WITH R/W/V
System BIOS A-39

LaC OBJ LINE SOURCE
EDtl E962FF 2715 JHP J10 I I f SO. HANDLE SPECIAL

EDe4 2716 J15:
EDC4 8AES 2717 my I CYLINDER NlII1BER
EDt6 E87800 2718 CALL NEe_OUTPUT
EDC9 8A6601 2719 tIDy AH,IBP+l] I HEAD Nl.Jt'EER fROM STACK
EDCC E87200 2720 CALL NEC_OUTPUT
EDeF 8AEJ 2721 HOV AH.CL I SECTOR HI.l1BER
EDDI f86DOO 2722 CALL NEC_OUTPUT
EDD4 880700 2723 HOY BX.7 I BYTES/SECTOR PARH fROI1 BLOCK
EOD? E89200 2724 CALL GET_PARH ; TO THE NEC
EDDA 880900 272.5 MOV BX.9 I EDT PARM fROI1 BLOCK
fOOD E88COO 2726 CALL GET_PARH ; TO THE NEC
EDEO BBOBOO 2727 MOV BX.ll I GAP LENGTH PARM fROH BLOCK
EDE] E88600 2728 CALL GET_PARH ; TO THE NEC
EDE6 BeaDOD 2729 tIOV Bx.n J DTL PARM fRotI BLOCK
EDE9 2730 JI6; I RioCOPNJINISH
fDE9 E88000 2731 I TO THE NEC
EDEC 5£ 2732 POP SI ; CAN NOW DISCARD THAT DUtItIY
2733 ; RETURN ADDRESS
2734
2735 1----- LET THE OPERATION HAPPEN
'7>6
EOED f84301 2737 I WAlT fOR THE INTERRUPT
EDFO 2138 J17: I MOTOR_Off
fOFO 7245 2739 JC J21 ; LOOK fOR ERROR
EDF! E87401 2740 CALL RESULTS ; GET THE NEC STATUS
EDFS 723F 2741 JC J20 ; LOOK fOR ERROR
2742
2743 1----- CHECK THE RESULTS RETURNED BY THE CONTROLLER
2744
EDF7 FC 2745 CLO I SET THE CORRECT DIRECTION
fDFS 8E4200 2746 MDY SI.OFFSET NEC_STATUS ; POINT TO STATUS FIElD
EDF8 At 2747 Loos NEC_STATUS I GET 5TO
EOFt 24tO 2748 AND AL.OCOH I TEST FOR ~HAL TERMINATION
EDFE 7438 2749 JZ J22 I OPN_OK
EEOD 3e40 2750 tMP AL.040H ; TEST FOR ABNORMAL TERMINATION
EE02 7529 2751 JNZ J!8 ; NOT ABNORMAL, BAD NEt
2752
2753 1----- ABNORt1AL TERMINATION. FItIJ OUT WHY
2754
EE04 At 2755 Loos NEt_STATUS i GET STl
fEDS ODED 2756 SAL AL.l ; TEST FOR EDT FDUm
fED7 8404 2757 IIOY
£E09 7224 2758 JC J19 I RWJAlL
EEDB ODED 2759 SAL AL.I
fEOD ODED 2760 SAL AL.I I TEST FOR CRC ERROR
fEDF 8410 2761 HOY AH.BAD_CRC
EEl! 7ZIC 2762 JC J19 I RWJAIl
EE13 ODED 2763 SAL AL.! ; TEST FOR DMA OVERRUN
EElS 6408 2764 HOY AH,8AD_OtIA
EE17 7216 2765 JC J19 I RWJAlL
E£19 ODED 2766 SAL AL ••
EEIB ODED 2767 SAL AL.! ; TEST FOR RECORD NOT fOlNJ
EEID 840lt 2768 HOY AH, RECORD_NOTJND
EEIF 720E 2769 JC J19 ; RWJAlL
fEZ! ODED 2770 SAL .U.l
fEU 8403 277! HOY AH,WRITE_PROTECT ; TEST FOR WRITE_PROTECT
Ef25 72:08 2772 JC J19 ; RN_FAIL
fE27 ODED 2773 SAL AL,I I TEST HISSING ADDRESS HARK
EE29 8402- 2774 my AH.BAO_ADDR_HARK
EE2B 7202 2775 JC J19 ; RWJAIl
2776
2777 ;----- NEC tlJST HAVE fAILED
2778
EE2D 2779 J18:
EE2D 8420 2780
fE2F 2781 J19; 1 RN-FAIL
EEZF 08264100 2782 OR DISKETTE_STATUS,AH
EE33 f87801 '2783 CALL NUteTRANS ; HOW MANY WERE REALLY TRANSFERRED
EE36 2784 J20: I RN_ERR
EE36 C3 2785 RET ; RETURN TO CALLER
EE37 2786 J21: I RN_ERR_RES
EE37 E82fOl 2787 CALL RESULTS I FLUSH THE RESULTS BUFFER
EE3" C3 2788 RET
2789
2790 ,----- OPERATION WAS SUCCESSFUL
2791
A-40 System BIOS

LOC OBJ LINE SOURCE
EE3B 2792 J22:

EE3B E87001 2793 CALL NUM_TRANS I HOW MANY GOT MOVED
EE3E 32E4 2794 XOR AH,AH I NO ERRORS
EE40 C3 2795 RET
2797 ; ------------------------------------------------------------------------
2798 ; NEC_OUTPUT
2799 THIS ROUTINE SENDS A BYTE TO THE NEC CONTROLLER AFTER TESTING
2800 FOR CORRECT DIRECTION AND CONTROLLER READY THIS ROUTINE WILL
2801 TIME OUT IF THE BYTE IS NOT ACCEPTED WITHIN A REASONABLE
2802 AMOUNT Of TIME, SETTING THE DISKETTE STATUS ON COMPLETION.
2803 INPUT
2804 (AH) BYTE TO BE OUTPUT
2805 ; OUTPUT
2806 CY =0 SUCCESS
2807 CY = 1 FAILURE -- DISKETTE STATUS UPDATED
2808 IF A FAILURE HAS OCCURRED, THE RETt.lRN IS MADE ONE LEVEl :
2809 HIGHER THAN THE CALLER OF NEC_OUTPUT.
2810 THIS REMOVES THE REQUIREMENT OF TESTING AFTER EVERY
2811 CALL OF NEC_OUTPUT.
2812 (All DESTROYED
2813 J------------------------------------------------------------------------
EE41 2814 NEC_OUTPUT PROC NEAR
EE41 52: 2815 PUSH OX ; SAVE REGISTERS
EE42 51 2816 PUSH ex
EE43 BAF403 2817 MOY DX,03F4H ; STATUS PORT
EE46 33C9 2818 XOR CX,CX ; COUNT FOR TIME OUT
EE48 2819 J23:
EE48 EC 2820 IN AL,DX ; GET STATUS
EE49 A840 2821 TEST AL,040H ; TEST DIRECTION BIT
EE4B 740C 2822 JZ J25 ; DIRECTION OK
EE4D E2F9 2823 LOOP J23
EE4F 2824 J24: ; TIME_ERROR
EE4F 800E410080 2825 OR DISKETTE_STATUS, TIME_OUT
EE54 59 2826 POP ex
EE55 5A 2827 POP OX I SET ERROR CODE AND RESTORE REGS
EE56 58 2828 POP AX I DISCARD THE RETURN ADDRESS
EE57 F9 2829 STe ; INDICATE ERROR TO CALLER
EE58 C3 2830 RET
EE59 2831 J25:
EE59 33C9 2832 XOR ex,cx ; RESET THE COUNT
EE5B 2833 J26:
EE5B EC 2834 IN AL,OX I GET THE STATUS
EE5C AB80 2835 TEST AL,oaOH ; IS IT READY
EE5E 7504 2836 JNZ J27 ; YES. GO OUTPUT
EE60 E2F9 2837 LOOP J26 I COUNT DOWN AND TRY AGAIN
EE62 EBEB 2838 JMP J24 ; ERROR CONDITION
EE64 2839 J27: I OUTPUT
EE64 8AC4 2840 MOY AL,AH ; GET BYTE TO OUTPUT
EE66 B2F5 2841 MOY DL,OF5H ; DATA PORT (3F5)
EE68 EE 2842 OUT OX,AL ; OUTPUT THE BYTE
EE69 59 2843 POP ex I RECOVER REGISTERS
EE6A SA 2844 POP OX
EE6B C3 2845 RET ; CY = 0 FROM TEST INSTRUCTION
2846 NEC_OUTPUT ENDP
2847 j------------------------------------------------------------------------
2848 I GET _PARM
2849 THIS ROUTINE FETCHES THE INDEXED POINTER FROM THE DISK_BASE
2850 BLOCK POINTED AT BY THE DATA VARIABLE DISK]OINTER. A BYTE FROM:
2851 THAT TABLE 15 THEN MOVED INTO AH. THE INDEX Of THAT BYTE BEING
2852 THE PARM IN BX
2853 ; ENTRY --
2854 BX = INDEX OF BYTE TO BE FETCHED * 2:
2855 IF THE LOW BIT OF BX IS ON, THE BYTE IS IMMEDIATELY OUTPUT
2856 TO THE NEC CONTROLLER
2857 I EXIT --
2858 AH = THAT BYTE FROM BLOCK
2859 i ------------------------------------------------------------------------
EE6C 2860 GET_PARM PRDC NEAR
EE6C IE 2861 PUSH as ; SAVE SEGMENT
EE60 2BCO 2862 SUB AX , J,Y.. ; ZERO TO AX
EE6F 8ED8 2863 HOY OS,AX
2864 ASSUME oS:ABSO
EE7l C5367800 2865 lOS SI,DISK_POINTER POINT TO BLOCK
EE75 DlEB 2866 SHR BX,I DIVIDE BX BY 2. AND SET FUG
2867 FOR EXIT
EE77 8A20 2868 MOY AH,rSI+BX] GET THE WORD
System BIOS A-41

LOC OBJ LINE SOURCE
EE79 iF 2869 POP OS I RESTORE SEGMENT

2870 ASSUME DS:OATA
EE7A nt5 2871 JC NEt_OUTPUT ; IF FLAG SET. OUTPUT TO CONTROLLER
EE7t C3 2872 I RETURN TO CALLER
2873 ENDP
2874 ; ------------------------------------------------------------------------
2875 ; SEEK
2876 THIS ROUTINE WILL MOVE THE HEAD ON THE NAMED DRIVE TO THE
2877 NAMED TRACK. IF THE DRIVE HAS NOT BEEN ACCESSED SINCE THE
2878 DRIVE RESET COHMAND WAS ISSUED, THE DRIVE WILL BE RECALIBRATED.
2879 , INPUT
2880 IOU = DRIVE TO SEEK ON
2881 (CH) = TRACK TO SEEK TO
2882 ; OUTPUT
2883 CY = 0 SUCCESS
2884 CY =1 FAILURE -- DISKETIE_STATUS SET ACCORDINGLY
2885 (AX) DESTROYED
2886 ;------------------------------------------------------------------------
EE70 2887 SEEK PROC NEAR
Ef70 B001 2888 MOY AL,1 ; ESTABLISH MASK FOR RECAL TEST
EE7F 51 2889 PUSH ex ; SAVE INPUT VALUES
EESO SACA 2890 MOY CL,DL I GET DRIVE VALUE INTO CL
EEe2 Olto 2691 ROL AL,CL ; SHIFT IT BY THE DRIVE VALUE
EE84 59 2692 POP ex ; RECOVER TRACK VALUE
fE85 84063EOO 2893 TEST AL,SEEK_STATUS I TEST FOR RECAL REQUIRED
EE89 7513 2694 JNZ JZ. I NO_RECAl
EEBB 08063EOO 2895 OR SEEK_STATUS,.A.L ; TURN ON THE NO RECA L BIT IN FLAG
EESF 8407 2896 MaY AH,07H ; RECAlIBRATE COHMAND
EE91 EBADFF 2697 CALL NEC_OUTPUT
EE94 8AE2- 2898 MOY AH,Dl
EE96 E8ASFF 2899 CALL NEC_OUTPUT ; OUTPUT THE DRIVE NUMBER
EE99 E87600 2900 CAll CHK_STAT_2 ; GET THE IHTERUPT AND SEHSE INT STATUS
EE9C 7229 2901 Je J3Z ; SEEK_ERROR
2902
2903 ;----- DRIVE IS IN SYNCH WITH CONTROLLElh SEEK TO TRACK
2904
EE9E 290S J2S:
EE9E B40F 2906 MaY AH,OFH ; SEEK COMMAND TO NEC
EEAD E89EFF 2907 CALL NEC_OUTPUT
EEA! 6AE2 2908 MOY AH,DL I DRIVE NUMBER
EEAS E899FF 2909 CALL NEC_OUTPUT
EEAa 8AE5 2910 MOY AH,CH ; TRACK HUMBER
EEAA E894Ff 2911 CALL NEC_OUTPUT
EEAD E86200 2912 CALL CHK_STAT_2 ; GET ENDING INTERRUPT AND
2913 ; SENSE STATUS
2914
2915 ;----- WAIT FOR HEAD SETTLE
2916
EESO 9C 2917 PUSHF ; SAVE STATUS FLAGS
fEB 1 BB1200 2918 MOY eX,ls ; GET HEAO SETILE PARAMETER
EEB4 E8B5FF 2919 CALL GET_PARN
HB7 51 2920 PUSH ex i SAVE REGISTER
HBB 2921 J29: I HEA.D_SETIlE
HBB B92602 2922 MOY CX,S50 ; 1 MS LOOP
fEBB OAE4 2923 OR AH.AH I TEST FOR TINE EXPIRED
fEBO 7406 2924 JZ J31
EEBF 2925 J30;
EEBF E2FE 292:6 lOOP J30 ; DELAY FOR 1 MS
EECI FEte 2927 OEe AH i DECREMENT THE COUNT
EEt3 EBF3 2928 JMP JZ9 ; 00 IT SOME MORE
EEtS 2929 J31 :
EEtS 59 2930 POP ex ; RECOVER STATE
EEC6 90 2931 POPF
EEt7 2932 J32: ; SEEK_ERROR
EEt7 C3 2933 RET ; RETURN TO CALLER
2934 SEEK ENDP
2935 ; ------------------------------------------------------------------------
2936 ; DNA_SETUP
2937 THIS ROUTINE SETS UP THE DNA FOR READ!WRITE/vERIFY OPERATIONS.
2938 ; INPUT
2939 (AU = MODE BYTE FOR THE DNA
2940 (ES:8X) - ADDRESS TO READ!WRITE THE DATA
2941 ; OUTPUT
2942 (AX) DESTROYED
2:943
EEce 2944 DMA_SETUP PROC NEAR
EEte 51 2945 PUSH ex I SAVE THE REGISTER
A-42 System BIOS

LOC OBJ LINE SOURCE
EEC9 FA 2946 ell , NO MORE INTERF<!UPTS

EECA E60C 2947 OUT DMA+12,Al J SET THE FIRST/LAST F/F
EEce 50 2948 PUSH AX
EEeD 58 2949 POP AX
EEeE E608 2950 OUT DMA+ll,Al I OUTPUT THE HOOE BYTE
EEDO Bceo 2951 NOV AX,ES I GET THE ES VALUE
EEOZ 8104 2952 HOV CL,4 ; SHIFT COUNT
EED4 03tO 2953 ROL AX,Cl ; ROTATE LEFT
EED6 SAf8 2954 HOV CH,Al I GET HIGHEST NYBLE OF ES TO eH
EEOS 24FO 2955 AND Al,OFOH I ZERO THE LOW NYBBlE FROM SEGMENT
EEDA 03e3 2956 ADD AX,BX I TEST FOR CARRY FROM ADDITION
EEOC 7302 2957 JNC J33
eEOE FEes 2958 INC CH ; CARRY MEANS HIGH 4 BITS MUST BE INC
EEEO 2959 J33:
EEED 50 2960 PUSH AX I SAVE START ADQRESS
fEEl E604 2961 OUT OMA+4.AL ; OUTPUT LOW ADDRESS
EEEl 8AC4 2962 MOV Al,AH
fEES E604 2963 OUT OMA+4.AL I OUTPUT HIGH ADDRESS
EEn 8AC5 2964 NOV Al,CH ; GET HIGH 4 BITS
EEE9 2.40F 2965 AND AL,OFH
EEEB E681 2966 OUT 081H,Al ; OUTPUT THE HIGH 4 BITS TO
2967 ; THE PAGE REGISTER
2968
2969 ;----- DETERMINE COUNT
2970
EEED 8AE6 2971 HOV AH,DH I HUHBER OF SECTORS
EfEF 2ACO 2972 SUB AL.AL I TIMES 256 INTO AX
EEFl 01E6 2973 SHR AX.l J SECTORS * 128 INTO AX
EEF3 50 2974 PUSH AX
EEF4 880600 2975 NOV BX.6 I 6ET THE BYTES/SECTOR PAR"
EEF7 E872FF 2976 CALL GET_PARM
EEFA BAce 2977 MOV CL.AH ; USE AS SHIFT COUNT 10=128. 1=256 ETC)
EEFC 58 2978 POP AX
EEFD 03EO 2979 SHL AX,CL ; MULTIPLY BY CORRECT AMOUNT
EEFF 48 2980 DEC AX ; -1 FOR DNA VALUE
EFOO 50 2981 PUSH AX ; SAVE COUNT VALUE
EFOI E605 2982 OUT DMA+5.AL ; LOW BYTE OF COUNT
EF03 8AC4 2983 HOV AL.AH
EFOS E605 2984 OUT DMA+5,AL I HIGH BYTE OF COUNT
EF07 FB 2985 STI ; INTERRUPTS BACK ON
EFOS S9 2986 POP ex ; RECOVER COUNT VALUE
EF09 58 2987 POP AX ; RECOVER ADDRESS VALUE
EFOA 03el 2988 ADD AX,CX ; ADD. TEST FOR 64K OVERFLOW
fFOC 59 2989 POP ex ; RECOVI;R REGISTER
EFOD 800Z 2990 HOV AL.2 ; HODE FOR 8237
EFOF E60A 2991 OUT DMA+I0.AL ; INITIALIZE THE DISKEnE CHANNEL
EFll C3 2992 RET ; RETURN TO CALLER.
2993 I CF l SET BY ABOVE IF ERROR
2994 ENDP
2995 ; - ---- - --- - - - - - - --------------------------- --- --- - - - ---- - -- - - - - - - ----- - --
2996 ; CHK_STAT_2
2997 THIS ROUTINE HANDLES THE INTERRUPT RECEIVED AFTER A
2998 RECALIBRATE. SEEK. OR RESET TO THE ADAPTER.
2999 THE INTERRUPT IS WAITED FOR. THE INTERRUPT STATUS SENSED.
3000 AND THE RESULT RETURNED TO THE CAllER.
3001 ; INPUT
3002 NONE
3003 ; OUTPUT
3004 CY = 0 SUCCESS
3005 CY = 1 FAILURE -- ERROR IS IN DISKETIE_STAnlS
3006 (AX) DESTROYED
30 0 7 ; - -- -- ---- - - --- - --- - - --- ------------------- -- - - --- -- -- - -- - -------- -- - - - --
EFl2 3008 CHK_STAT_2 PROC NEAR
EF12 E81EOO 3009 CALL WAIT_INT ; WAIT FOR THE INTERRUPT
EFtS 7214 3010 JC J34 ; IF ERROR. RETURN IT
EF17 Moa 3011 HOV AH .08H ; SENSE INTERRUPT STA.TIJS COMMAND
EF 19 E825FF 3012 CALL NEC_OUTPUT
EFIC E84AOO 3013 CALL RESULTS i READ IN THE RESULTS
EFlF nOA 3014 JC J34 ; CHK2_RETURN
EFZI A04200 3015 HOV AL,NEC_STATUS ; GET THE FIRST STATIJS BYTE
EF2:4 2460 3016 AND AL.060H ; ISOLATE THE BITS
Ef2:6 3C60 3017 CNP AL.060H ; TEST FOR CORRECT VALUE
EF28 740Z 3018 JZ J35 I IF ERROR. GO NARK IT
EFGA Fa 3019 ele ; GOOD RETURN
EF2S 3020 J34:
EF2B C3 3021 RET ; RETURN TO CALLER
EF2:C 3022 J35: I CHK2_ERROR
System BIOS A-43

LOC OBJ LINE SOURCE
EF2C 800E410040 3023 OR

En1 F9 3024 STC ; ERROR RETURN COOE
EF32 C3 302:5 RET
3026 tHK_STAT_2 ENDP
3027 ; ---------------------------------------------------- __ ---- _____________ _
3028 ; WAIT INT
3029 THIS ROUTINE WAITS FOR A~ INTERRUPT TO OCCUR. A TIME OUT
3030 ROUTINE TAKES PLACE DURING THE WAIT. SO THAT AN ERROR MAY BE
3031 RETURNED IF THE DRIVE IS NOT READY.
3032 INPUT
3033 NONE
3034 ; OUTPUT
3035 tV =0 SUCCESS
3036 ty = 1 FAILURE -- DISKETTE_STATUS IS SET ACCOROINGLY
3037 (AX J DESTROYED
3038
En3 3039 WAIT_HIT PROC NEAR
EF33 Fe 3040 ST! ; TURN ON INTERRUPTS. JUST IN CASE
EF34 53 3041 PUSH BX
EF35 51 3042: PUSH CX ; SAVE REGISTERS
EF36 6302: 3043 MOV BL.2 ; CLEAR THE COUNTERS
EF38 33C9 3044 XOR CX.CX ; FOR 2 SECOND WAIT
EF3A 3045 J36:
EnA F6063E0080 3046 TEST SEEK_STATUS.INTJlAG ; TEST FOR INTERRUPT OCCURRING
EF3F 750C 3047 JHZ J37
EF41 ElF7 3048 LOOP J36 I COUNT DOWN WHILE WAITING
EF43 FEte 3049 DEC Bl ; SECOND LEVEL COUNTER
EF45 75F3 3050 JHZ J36
EF47 800E410080 '3051 OR DISKETTE_STATUS ,TIME_OUT ; NOTHING HAPPENEO
EF4C F9 3052 STC ; ERROR RETURN
EF4D 3053 J37:
EF4D ge 3054 PUSHF ; SAVE CURRENT CARRY
EF4E 80263E007F 3055 AND SEEK_STATUS. NOT INTJLAG ; TURN OFF INTERRUPT FLAG
EF53 90 3056 POPF ; RECOVER CARRY
EF54 59 3057 POP CX
EF55 5B 3058 POP BX ; RECOVER REGISTERS
EF56 C3 3059 RET ; GOOD RETURN COOE COMES
3060 ; FROM TEST INST
3061 ENDP
3062 j--------------------------------------------------------
3064 THIS ROUTINE HANDLES THE DISKETTE INTERRUPT
3065 ; INPUT
3066 NONE
3067 ; OUTPUT
3068 THE INTERRUPT FLAG IS SET IS SEEK_STATUS
3069 1-----------------------------------------,---------------
EF57 3070 ORG OEF57H
EF57 3071 DISK_INT PROt FAR
EF57 F8 3072 ST! ; RE ENABLE INTERRUPTS
EF58 IE 3073 PUSH os
EF59 50 3074 PUSH AX
EF5A E8EI0F 3075 CALL DDS
EF5D 800E3E0080 3076 OR SEEK_STATUS ,INTJLAG
EF62 B020 3077 MOV AL,20H ; END OF INTERRUPT MARKER
EF64 E620 3078 OUT 20H.AL ; INTERRUPT CONTROL PORT
H66 58 3079 POP AX
EF67 IF 3080 POP OS ; RECOVER SYSTEM
EF68 CF 3081 IRET • RETURN FROM INTERRUPT
3082 DISK_INT EtOlP
3083 1------------------------------------------------------------------------
3084 ; RESULTS
3085 THIS ROUTINE WILL READ ANYTHING THAT THE NEt COt-iROLLER HAS
3086 TO SAY FOLLOWING AN INTERRUPT.
3087 INPUT
3088 HONE
3089 ; OUTPUT
3090 CY = 0 SUCCESSFUL TRANSFER
3091 CY = 1 FAILURE -- TIME OUT IN WAITING FOR STATUS
3092 NEC_STATUS AREA HAS STATUS BYTE LOADED INTO IT
3093 (AH ) DESTROYED
3094 ; ------------------------------------------------------------------------
EF69 3095 RESULTS PROC NEAR
EF69 FC 3096 ClD
EF6A BF4Z00 3097 HOV OI,OFFSET NEC_STATUS ; POINTER TO DATA AREA
EF6D 51 3098 PUSH CX I SAVE COUNTER
EF6E 52 3099 PUSH OX
A-44 System BIOS

LOC OBJ LINE SOURCE
Ef6F 53 3100 PUSH BX

EnO B307 3101 MOV BL.7 ~ MAX STATUS BYTES
3102:
3103 ,----- WAIT FOR REQUEST FOR HASTER
3104
EF7Z 3105 J38: ; INPUT_lOOP
EF72 33C9 3106 XOR eX,ex ; COUNTER
EF74 BAF403 3107 MOV DX,03F4H , STATUS PORT
EF77 3108 J39: , WAIT FOR MASTER
EF77 EC 3109 IN Al,DX ; GET STATUS
EF7e A880 3110 TEST Al,OsOH J HASTER READY
EF7A 750C 3111 JHZ J40A ; TEST_DIR
EF7e E2:F9 3112 LOOP J39 ; WAIT_MASTER
EF7E 800E410080 3113 OR DISKETTE_STATUS, TINE_OUT
EFa3 3114 J40: ; RESULTS_ERROR
Ha] F9 3115 STC ; SET ERROR RETURN
EFS4 58 3116 POP BX
EF85 SA 3117 POP OX
EF8b 59 3118 POP CX
EFa7 C3 3119 RET
3120
3121 ;----- TEST THE DIRECTION BIT
3122
EF88 3123 J40A:
EF88 EC 3124 IN AL,DX ; GET STATUS REG AGAIN
EF89 A840 3125 TEST AL,040H I TEST DIRECTION BIT
EFBB 7507 3126 JHZ J42 ; OK TO READ STATUS
EFSD 3127 J41: ; NECJAIL
EFaD 800E410020 3128 OR DISKETTE_STATUS, BAD_NEC
EF92 EBEF 3129 JMP J40 ; RESULTS_ERROR
3130
3131 ;----- READ IN THE STATUS
3132
EF94 3133 J42: ; INPUT_STAT
EF94 42 3134 IHC OX ; POINT AT DATA PORT
EF95 EC 3135 IN AL,OX ; GET THE DATA
£F96 8805 3136 MOV [OIl,AL ; STORE THE BYTE
EF98 47 3137 INC OI I INCREMENT THE POINTER
EF99 890AOO 3138 MOV CX,IO ; LOOP TO KIll TIME FOR NEC
EF9C E2FE 3139 J43: LOOP J43
EF9E 4A 3140 DEC OX ; POINT AT STATUS PORT
EF9F EC 3141 IN AL,OX ; GET STATUS
EFAO A810 3142 TEST Al,010H ; TEST FOR NEC STILL BUSY
EFA2 7406 3143 JZ J44 ; RESULTS DONE
EFA4 FEeB 3144 DEC BL i OECREMENT THE STATUS COUNTER
EFA6 75CA 3145 JHZ J3' ; GO BACK FOR MORE
EFA8 E8E3 3146 JMP J41 ; CHIP HAS FAILED
3147
3146 ;----- RESULT OPERATION IS DONE
3149
EFAA 3150 J44:
EFAA 5B 3151 POP BX
EFAB SA 3152 POP OX
EFAC 59 3153 POP CX ; RECOVER REGISTERS
EFAD C3 3154 RET ; GOOD RETlmN CODE FROM TEST INST
3155 j -------- -- - - - - - - ----- ---- - - ---------- ---- -- ---- - - - ------- -- - - - --
3156 ; NUN_TRANS
3157 THIS ROUTINE CALCULATES THE NUt1BER OF SECTORS THAT
3156 WERE ACTUALLY TRANSFERRED TO/FROM THE DISKETTE
3159 INPUT
3160 (CH) = CYlINDER OF OPERATION
3161 (Cll = START SECTOR OF OPERATION
3162 ; OUTPUT
3163 (AL) = NUMBER ACTUAU Y TRANSFERRED
3164 NO OTHER REGISTERS MODIFIED
3165 ; ----------------------------------------------------------------
EFAE 3166 HUM_TRANS PROC NEAR
£FAE A04500 3167 MOV Al,NEC_STATUS+3 ; GET CYlINDER ENDED UP ON
EFBI 3ACS 3168 CMP AL,CH ; SAME AS WE STARTED
EFB3 A04700 3169 HOV Al,NEC_STATUS+5 ; GET ENDING SECTOR
EFB6 740A 3170 JZ J45 I IF ON SAME cn, THEN NO ADJUST
EFB8 BB0800 3171 MOV BX,8
H8B E8AEFE 3172 CAll GET_PARH ; GET EDT VALUE
EFBE 8AC4 3173 MOV AL,AH I INTO AL
EFCO FECO 3174 INC AL I USE EOT+l FOR CALCULATION
EFe2 3175 J4S:
£Fez 2;.el 3176 SUB Al,Cl I SUBTRAt;T START FROM Et«J
System BIOS A·45

LOC OBJ LINE SOURCE
EFC4 C3 3177 RET

3178 NUN_TRANS ENOP
3179 RESULTS ENOP
3180 ;----------------------------------------------- ________________________ _
3181 ; DISK_BASE
3182 THIS IS THE SET OF PARAMETERS REQUIRED FOR DISKETTE OPERA.TION.
3183 ll-IEY ARE POINTED AT BY THE DATA VARIABLE DISK_POINTER. TO
3184 MODIFY THE PARAMETERS. BUILD ANOTHER PARAMETER BLOCK AND POINT
3185 DISK_POINTER TO IT.
3186 ;----------------------------------------------------------- ____________ _
EFt7 3187 ORG OEFC7H
EFt7 3188 LABEL BYTE
EFt7 CF 3189 11001111B I SRT=C, HD UNLOAD=OF - 1ST SPECIFY BYTE
EFCe 02: 3190 DB 2 ; HD LOAD=I. MODE=DHA _ ;>NIl SPFC':TFY RYTF
EFC9 25 3191 DB MOTOR_WAIT ; WAIT AFTER OPH TIL MOTOR OFF
EFeA 02 3192 DB ; 512 BYTES/SECTOR
EFCB 08 3193 DB ; EDT ( LAST SECTOR ON TRACK I
EFCC ZA 3194 DB 02AH ; GAP LENGTH
EFce FF 3195 DB OFFH ; Dll
EFeE 50 3196 DB OSOH ; GAP LENGTH FOR FORMAT
EfCf F6 3197 DB OF6H ; FILL BYTE FOR FORMAT
EFDO 19 3198 DB 25 ; HEAD SETTLE TIME (MILLISECONDS)
EFOI 04 3199 DB 4 ; MOTOR START TIME (1/8 SECONDS)
3200
3201 ;--- 1HT 17 -------------------------------------------------------------
3202 ; PRINTER_IO
3203 nilS ROUTINE PROVIOES COI1I1lJNICATION WITH THE PRINTER
3204 INPUT
3205 (AH1=O PRINT THE CHARACTER IN (All
3206 ON RETURN, AH=1 IF CHARACTER COULD NOT BE PRINTED
3207 (TINE OUT I. OTHER BITS SET AS ON NORMAL STATUS CALL
3208 (AHI=l INITIALIZE THE PRINTER PORT
3209 RETURNS WITH IAH) SET WITH PRINTER STATUS
3210 (AHI=2 READ THE PRINTER STATUS INTO I AH I
3211 7 6 4 2-1 0
3212 I I I I I_TIME OUT :
3213 I I I 1_ UNUSED
3214 I I 1 = I/O ERROR
3215 I 1 = SELECTED
3216 1 = OUT OF PAPER
3217 1 = ACKNOWLEDGE
3218 1 = NOT BUSY
3219
3220 (OXI = PRINTER TO BE USED (0,1.21 CORRESPONDING TO ACTUAL
3221 VALUES IN PRINTER_BASE AREA
3222
3223 ; DATA AREA PRINTER_BASE CONTAINS THE BASE ADDRESS OF THE PRINTER
3224 ; CAROlS) AVAILABLE (LOCATED AT BEGINNING OF DATA SEGMENT.
3225 ; 408H ABSOLUTE. 3 WORDS)
3226
3227 1 DATA AREA PRINT_TIN_OUT (BYTE) MAY BE CHANGED TO CAUSE DIFFERENT
3228 ; TIME-OUT WAITS. DEFAUlT=20
322'i1
3230 ; REGISTERS AH IS MODIFIED
3231 ALL OTHERS UNCHANGED
3232 ;------------------------------------------------------------------------
3233 ASSUME CS:COOE ,DS:DATA
EFOZ 3234 ORG OEFD2H
EFOZ 3235 PRINTER_IO PROC FAR
EFOZ fB 3236 STI INTERRUPTS BACK ON
EFD3 IE 3237 PUSH OS SAVE SEGMENT
EFD4 52 3238 PUSH OX
EFOS 56 3239 PUSH SI
HOb 51 3240 PUSH ex
EF07 53 3241 PUSH BX
EFDB E8630F 3242 CALL DDS
HOB BBF:?: 3243 MOV SI,OX ; GET PRINTER PARM
EFDD 8A5e78 3244 MOV BL,PRINT TIM Ol1T[SIJ ; LOAD TIME -OUT PARM
fFEO 01E6 3245 SHL 51,1 I WORD OFFSET INTO TABLE
EFEZ 685408 3246 MOV ox, PRINTER_BASEl 51 J ; GET BASE ADDRESS FOR PRINTER CARD
EFES OB02 3247 OR OX,OX ; TEST OX FOR ZERO,

3248 ; INDICATING NO PRINTER
EFE7 740C 3249 JZ Bl ; RETURN
EFE9 OAE4 3250 OR AH,AH ; TEST FOR (AHI=O
fFEB 740E 3251 JZ B2 ; PRINT_Al
EfED fEte 3252 DEC AH ; TEST FOR (AH)=1
EFEf 743f 3253 JZ 88
A-46 System BIOS

LOC OBJ LINE SOURCE
EFF 1 FECC 3254 DEC AH I TEST FOR (AH) =2

EFF3 7428 3255 JZ OS ; PRINTER STATUS
EFF5 3256 Bl: ; RETURN
EFFS 58 3257 pop OX
EFF6 59 3258 POP ex
EFF7 SE 3259 POP SI ; RECOVER REGISTERS
EFFS SA 3260 POP ox J RECOVER REGISTERS
EFF9 IF 3261 POP os
EFFA Cf 3262 IRET
3263
3264 ; ------ PRINT THE CHARACTER IN (AU
32:65
EHS 32:66 82::
EFFB 50 32:67 PUSH AX ; SAVE VALUE TO PRINT
EFFe EE 3268 OUT OX,AL I OUTPUT CHAR TO PORT
EFFO 42 32:69 IHC OX I POINT TO STATUS PORT
EFFE 32:70 83:
EFFE ZBC9 3271 SUB eX,ex
FOOO 3272:
FOOD EC 3273 IN AL,OX ; GET STATUS
FOOl BAED 32:74 MOV AH.AL ; STATUS TO AH ALSO
F003 ABBD 3275 TEST AL.SOH ; IS THE PRINTER CURRENTLY BUSY
F005 750E 3276 JNZ 84 ; OULSTROBE
F007 E2F7 32:77 LOOP 83_1 ; TRY AGAIN
F009 FEeB 3278 DEC BL ; DROP LOOP COUNT
F006 75Fl 3279 JNZ B3 ; GO TILL TIMEOUT ENDS
FOOD 80CCOI 3280 OR AHol i SET ERROR FLAG
FOlD 80E4F9 32:81 AND AH,OF9H i TURN OF F THE OTHER BITS
F013 EBB 32:82: JMP SHORT 87 ; RETURN WITH ERROR FLAG SET
F015 32:83 84: ; OUT_STROBE
F015 BODO 32:84 MOV AL,OOH ; SET THE STROBE HIGH
FOl742 32:85 tHC ox ; STROBE IS BIT 0 OF PORT C OF 8255
F018 EE 32:86 OUT OX,AL
F019 BOOC 32:87 MOV AL,OCH ; SET THE STROBE LOW
FO 18 EE 3288 OUT OX,AL
FDIC 58 3289 POP AX ; RECOVER THE OUTPUT CHAR
3290
3291 j------ PRINTER STATUS
32:92
FOlD 3293 85:
FO 10 50 3294 PUSH AX I SAVE AL REG
FOIE 32:95 B6:
FOIE 865408 3296 NOV DX.PRINTER_BASE[ 51 J
F021 42 32:97 INC OX
F022 EC 32:98 IH AL,OX ; GET PRINTER STATUS
F023 BAEO 3299 NOV AH.AL
F025 60E4F8 3300 AHD AH.OF8H ; TURN OFF UNUSED BITS
F028 3301 87: i STATUS_SET
F026 SA 3302: POP OX ; RECOVER AL REG
F029 BAC2 3303 MOV AL,DL ; GET CHARACTER INTO AL
F02B 80F448 3304 XOR AH.48H i FLIP A COUPLE OF BITS
F02E EBes 3305 JMP 01 ; RETURN FROM ROUTINE
3306
3307 ; ------ INITIALIZE THE PRINTER PORT
3308
F030 3309 B8:
F030 50 3310 PUSH AX I SAVE AL
F031 42 3311 INC OX ; POINT TO OUTPUT PORT
F032 42 3312 INC OX
F033 B008 3313 MOV AL,8 ; SET INIT LINE lOW
F035 EE 3314 OUT OX.AL
F036 B8E803 3315 NOV AX.IOOO
F039 3316 B9: ; INIT_lOOP
F039 48 3317 DEC AX ; LOOP FOR RESET TO TAKE
Fa3A 75FO 3318 JHZ 09
F03e BOOC 3319 MOV AL.OCH ; NO INTERRUPTS. NON AUTO LF.
3320 ; HIIT HIGH
F03E EE 3321 OUT OX.AL
F03F EBOD 3322 O.
3323 ENDP
3324
F041 62El 3325 C2 OW C24 J RETURN ADDRESS FOR DUMMY STACK
3326
3327 ;--- INT 10 -------------------------------------------------------------
3328 ; VIDEO_IO
3329 THESE ROUTINES PROVIDE THE CRT INTERFACE
3330 THE FOLLOWING FUNCTIONS ARE PROVIDED:
System BIOS A-47

LOC OBJ LINE SOURCE
3331 IAHI=O SET MODE (All CONTAINS MODE VALUE

3332 (AU=O 40X2:5 Bioi (POWER ON DEFAULT)
3333 (AU=l 40X25 COLOR
3334 (Al )=2: BOX2:5 Bioi
3335 {Al )=3 eOX25 COLOR
3336 GRAPHICS MODES
3337 (AL )=4 320XlOO COLOR
3338 {All:::5 32:0X200 Bioi
3339 (All=6 640XlOO Bioi
3340 CRT MODE=7 BOX25 BLW CARD I USED INTERNAL TO VIDEO ONL Yl
3341 *** NOTE Bioi MODES OPERATE SAME AS COLOR MODES. BUT
3342 COLOR BURST IS NOT ENABLED
3343 (AH)=l SET CURSOR TYPE
3344 (CH 1:;: BITS 4-0 = START LINE FOR CURSOR
3345 ** HARDWARE WILL ALWAYS CAUSE BLIN
3346 ** SETTING BIT 5 OR 6 WILL CAUSE ERRATIC
3347 BLINKING OR NO CURSOR AT ALL
3348 (CLl = BITS 4-0 = END LINE FOR CURSOR
3349 (AH ) =2 SET CURSOR POSITION
3350 (DH,DLl = ROW,COLUMN (0,0) IS UPPER LEFT
3351 (BH I = PAGE NUMBER (MUST BE 0 FOR GRAPHICS HODES)
3352: (-'H)=3 READ CURSOR POSITION
3353 (BHI = PAGE NltIBER (MUST BE 0 FOR GRAPHICS NODES)
3354 ON EXIT (oH,DLl = ROW,COLUMN OF CURRENT CURSOR
3355 (CH,CLl = CURSOR MODE CURRENTLY SET
3356 (AH )=4 READ LIGHT PEN POSlnON
3357 ON EXIT:
3358 (AH I = 0 -- LIGHT PEN SWITCH NOT DOWN/NOT TRIGGERED
3359 (AH I = 1 -- VALID LIGHT PEN VALUE IN REGISTERS
3360 (DH.DLl = ROW , COLUMN OF CHARACTER LP POSN
3361 (CHI = RASTER LINE (0-199)
3362 (BX) = PIXEl COLUMN (0-319,6391
3363 IAHJ=5 SelECT ACTIVE DISPLAY PAGE (VALID ONLY FOR ALPHA MODESI
3364 {ALl=NEW PAGE VAL (0-7 FOR MODES OU, 0-3 FOR MODES 2&31:
3365 (AHI=6 SCROLL ACTIVE PAGE UP
3366 (All = NUNBER OF LINES, INPUT LINES BLANKED AT BOTTOM
3367 OF WINDOW
3368 AL = 0 MEANS BLANK ENTIRE WINDOW
3369 (CH,Cll = ROW,COLUNN OF UPPER LEFT CORNER OF SCROLL
3370 (OH,Dll = ROW,COLUMN OF LOWER RIGHT CORNER OF SCROLL
3371 (BH I = ATTRIBUTE TO BE USED ON BLANK LINE
3372 {AH 1=7 SCROLL ACTIVE PAGE DOWN
3373 tAll = NUMBER OF LINES, INPUT LINES BLANKED AT TOP
3374 OF WINDOW
3375 AL = 0 MEANS BLANK ENTIRE WINDOW
3376 {CH.CLl = ROW.COLUMN OF UPPER LEFT CORNER OF SCROLL
3377 {DH.OLl = ROW.COLUNN OF LOWER RIGHT CORNER OF SCROLL
3378 (BHI = ATTRIBUTE TO BE USED ON BLANK LINE
3379
3380 CHARACTER HANDLING ROUTINES
3381
3382 (AH I = 8 READ ATTRIBUTE/CHARACTER AT CURRENT CURSOR POSITION
3383 (BHI = DISPLAY PAGE fVALID FOR ALPHA HODES ONLYI
3384 ON EXIT:
3385 (All = CHAR READ
3386 (AHI = ATTRIBUTE OF CHARACTER READ (ALPHA HODES ONLYI
3387 (AH) = 9 WRITE ATTRIBUTE/CHARACTER AT CURRENT CURSOR POSITION
3388 (BHI = DISPLAY PAGE (VALID FOR ALPHA MODES ONLY)
3389 (CX) = COUNT OF CHARACTERS TO WRITE
3390 (AL I = CHAR TO WRITE
3391 (BU = ATTRIBUTE OF CHARACTER (ALPHA )/COLOR OF CHAR
3392 (GRAPHICS I
3393 SEE NOTE ON WRITE DOT FOR BIT 7 OF BL = 1.
3394 (AH) = 10 WRITE CHARACTER ONLY AT CURRENT CURSOR POSITION
3395 CBHI = DISPLAY PAGE (VALlO FOR ALPHA MODES ONLY)
3396 (CX I = COUNT OF CHARACTERS TO WRITE
3397 I AL J = CHAR TO WRITE
3398 FOR READ/WRITE CHARACTER INTERFACE WHILE IN GRAPHICS MODE. llIE
3399 CHARACTERS ARE FORMED FROM A CHARACTER GENERATOR IMAGE
3400 MAINTAINED IN THE SYSTEM ROM. ONLY THE 1ST 12:8 CHARS
3401 ARE CONTAINED THERE. TO REAO/wRITE THE SECOND 128
3402 CHARS. THE USER MUST INITIALIZE THE POINTER AT
3403 INTERRUPT 1FH (LOCATION 0007CH) TO POINT TO THE lK BYTE
3404 TABLE CONTAINING THE COOE POINTS FOR THE SECOND
3405 12:8 CHARS (128-255l.
3406 FOR WRITE CHARACTER INTERFACE IN GRAPHICS MODE, THE REPLICATION :
3407 FACTOR CONTAINED IN (CXI ON ENTRY WILL PRODUCE VALID
A-48 System BIOS

LOC OBJ LINE SOURCE
3408 RESULTS ONLY FOR CHARACTERS CONTAINED ON THE SAME ROW.

3409 CONTINUATION TO SUCCEEDING LINES WILL NOT PRODUCE
3410 CORRECtlY.
3411
3412 GRAPHICS INTERFACE
3413 (AH) = 11 SET COLOR PALETTE
3414 IBH) = PALETTE COLOR 10 BEING SET (0-127)
3415 (BLI = COLOR VALUE TO BE USED WITH THAT COLOR 10
3416 NOTE: FOR THE CURRENT COLOR CARD, THIS ENTRY POINT
3417 HAS MEANING ONLY FOR 320X200 GRAPHICS.
3418 COLOR ID =0 SElECTS THE BACKGROUND COLOR (O-ISI:
3419 COLOR ID =1 SELECTS THE PALETTE TO BE USED:
3420 o = GREEN( 1 JlRED( 2 IIYELLOW(31
3421 1 = CYAN! I I/MAGEHTA(2)IWHITE(31
3422 IN 40X2S OR 80X25 ALPHA MODES. THE VALUE SET
3423 FOR PALETTE COLOR 0 INDICATES THE
3424 BORDER COLOR TO BE USED (VALUES 0-31,
3425 WHERE 16-31 SELECT THE HIGH INTENSITY
3426 BACKGROUND SET.
3427 (AH) = 12 WRITE DOT
3428 (OX 1 = ROW NUMBER
3429 (CX I = COLUMN NUMBER
3430 (All = COLOR VALUE
3431 IF BIT 7 OF AL = 1, THEN THE COLOR VALUE IS
3432 EXCLUSIVE OR '0 WITH THE CURRENT CONTENTS OF
3433 THE DOT
3434 fAH) = 13 REAO DOT
3435 (OX) = ROW NUMBER
3436 (CX) = COLUMN HUMBER
3437 (AL) RETURNS THE DOT REAO
3438
3439 ; ASCII TELETYPE ROUTINE FOR OUTPUT
3440
3441 (AH) = 14 WRITE TELETYPE TO ACTIVE PAGE
3442 (Al} = CHAR TO WRITE
3443 (Bll = FOREGROUND COLOR IN GRAPHICS MODE
3444 NOTE -- SCREEN WIDTH IS CONTROLLED BY PREVIOUS MODE SET :
3445
3446 (AH) = 15 CURRENT VIDEO STATE
3447 RETURNS THE CURRENT VIDEO STATE
3448 (All = MODE CURRENTlY SET ( SEE AH=O FOR EXPLANATION)
3449 (AHI = NUMBER OF CHARACTER COLUMNS ON SCREEN
3450 (BHI = CURRENT ACTIVE DISPLAY PAGE
3451
3452 CS.SS,OS,ES,BX,CX.DX PRESERVED DURING CALL
3453 ALL OTHERS DESTROYED
3454 ;------------------------------------------------------------------------
3455 ASSUME CS :CODE ,OS:DATA. ES:VIDEO_RAM
F045 3456 ORG OF045H
F045 3457 Ml LABEL WORD I TABLE OF ROUTINES WITHIN VIDEO 110
F045 FCFO 3458 OW OFFSET SET_MODE
F047 tOFl 3459 OW OFFSET SET_CTYPE
F049 EEF 1 3460 OW OFFSET SET_CPOS
F04B 39F2 3461 DW OFFSET READ_CURSOR
F04D 9CF7 3462 DW OFFSET REAO_LPEN
F04F 17F2 3463 OW OFFSET ACT_DISP_PAGE
FOS1 9HZ 3464 DW OFFSET SCROLL_UP
F053 38F3 3465 ow OFFSET SCROLL_DOWN
FOSS 74F3 3466 DW OFFSET READ_AC_CURRENT
F057 B9F3 3467 ow OffSET WRITE_At_CURRENT
F059 Een 3468 ow OFFSET WRITE_C_CURREHT
FOSB 4EF2 3469 DW OFFSET SET_COLOR
F05D 2FF4 3470 ow OFFSET WRITE_DOT
F05F lEF4 3471 DW OffSET READ_~OT
FObl laF7 3472 ow OFFSET WRITE_TTY

f063 NFl 3473 DW OFFSET VIDEO_STATE
0020 3474 MIL EQU $-Ml
3475
FObS 3476 ORG OF065H
FObS 3477 VIDEO_IO PROC NEAR
FObS FB 3478 STI ; INTERRUPTS BACK ON
f066 Fe 3479 ClO ; SET DIRECTION FORWARD
F067 06 3480 PUSH ES
F06e IE 3481 PUSH OS j SAVE SEGMENT REGISTERS
F069 52 3482 PUSH ox
FObA 51 3483 PUSH ex
FObB 53 3484 PUSH BX
System BIOS A-49

LOC OBJ LINE SOURCE
F06t 56 3485 PUSH SI

F06D 57 3486 PUSH DI
F06E 50 3487 PUSH AX ; SAVE AX VALUE
f06F 8'&'C4 3488 HDV AL.AH ; GET INTO LOW BYTE
F071 32:E4 3489 XDR AH,AH ; ZERO TO HIGH BYTE
F073 DIED 3490 SAL AX.l ; *2 FOR TABLE LOOKUP
F075 SBFO 3491 HOV 51.AX ; PUT INTO 51 FOR BRANCH
F077 30Z000 3492 CHP AX,Mll ; TEST FOR WITHIN RANGE
F07A 7204 3493 JB HZ ; BRANCH AROUND BRANCH
F07t 58 3494 POP AX ; THROW AWAY THE PARAMETER
F07D E94501 3495 JHP VIDEO_RETURN ; DO NOTHING IF NOT IN RANGE
Foeo 3496 HZ:
Foao EBBBDE 3497 CALL DDS
F083 880068 3498 HOV AX,OB800H ; SEGMENT FOR COLOR CARD
F086 883EI000 3499 HOV OI,EQUIPJlAG ; GET EQUIPMENT SETTING
FOBA 81E73000 3500 AHD OI,30H I ISOLATE CRT SWITCHES
F08E 83FF30 3501 CMP Dl,30H ; IS SETTING FOR Bioi CARD?
F091 7502 3502 JHE H3
F093 B48D 3503 HOV AH,OBOH ; SEGMENT FOR BW CARD
F095 3504 H3:
F09S 8Eeo 3505 MeV ES,AX I SET UP TO POINT AT VIDEO RAM AREAS
F097 58 3506 POP AX I RECOVER VALUE
F098 8A264900 3507 HOV AH,CRT_HODE ; GET CURRENT MODE INTO AH
F09C 2EFFA445FO 3508 JHP WORD PTR CS: [SI+OFFSET MIl
3509 VIOEO_lO ENOP
3510 ;--------------------------------------------------------
3511 I SET_MODE
3512 THIS ROUTINE INITIALIZES THE ATTACHMENT TO
3513 THE SELECTED MODE. THE SCREEN IS BLANKED.
3514 INPUT
3515 (ALI = MODE SELECTED (RANGE 0-91
3516 i OUTPUT
3517 NOHE
3518 1--------------------------------------------------------
3519
3520 .----- TABLES FOR USE IN SETTING OF MODE
3521
FOA4 3522 ORG OFOA4H
FDA4 3523 VIDEO_PARMS LABEL BYTE
3524 ;----- INlT_TABlE
FOA4 38 3525 DB 38H ,28H .ZCH .0AH.lFH ,6,19H • SET UP FOR 40XZS
FDA5 28
FOA6 20
FOA7 OA
FOA8 IF
FOA9 06
FOAA 19
FOAB Ie 3526 DB lCH.2,7,6.7
FOAC 02
FOAD 07
FOAE 06
FOAF 07
Foeo 00 3527 DB 0,0,0,0
FOBI 00
FOB2 00
FOB3 00
0010 3528 "4 EQU $-VIDEO_PARHS
3529
FOB4 71 3530 DB 7lH.50H ,5AH ,OAH, IFH ,6, 19H ; SET UP FOR 80X2S
FOBS 50
FOS6 SA
FOB7 OA
FOB8 IF
FOB9 06
FOBA 19
FOBB lC 3531 DB lCH,2,7.6.7
FOBC 02
FOBD 07
FOBE 06
FOBF 07
FOCO 00 3532 DB 0.0.0,0
FOCI 00
FOC2 00
FOC3 00
3533
FOC4 38 3534 DB 38H, 28H,2DH. OAH. 7FH,6.64H ; SET UP FOR GRAPHICS
FOC5 28
A-50 System BIOS

LOC OBJ LINE SOURCE
FOCb 20
FOC7 DA.
Face 7F
FOC9 06
FOCA 64
Face 70 3535 DB 70H,2.1,6,7
Foce 02
FOCO 01
FOCE 06
foeF 07
FOOD 00 3536 DB 0,0,0,0
FOOl 00
F002 00
FOOl 00
3537
FOD4 61 3538 DB 61H,50H.52H .OFH.19H.6, 19H J SET UP fOR 80X25 B&W CARD
fODS SO
FOD6 52
FOD7 OF
FOD8 19
FOD9 06
FOCA 19
FODS 19 3539 DB 19H.2 .DOH .OSH ,OCH
FOOt 02:
FOOD 00
FODE 08
FOOF DC
FOED 00 3540 DB 0.0,0,0
FOE I 00
FOE2 00
FOE3 00
3541
FOE4 3542 M5 LABEL WORD ; TABLE Of REGEN LENGTHS
rOf4 0008 3543 OW 2048 ; 40X2:5
FOe6 0010 3544 ow 4096 ; 80X25
FOE8 0040 3545 ow 16384 j GRAPHICS
FOEA 0040 3546 ow 16364
3547
3548 ; ----- COLUMNS
3549
FOEC 3550 M6 LABEL BYTE
FOEt 28 3551 DB 40 .40 ,80.80 ,40,40.80.60
FOED 28
FOEE 50
FOEF 50
FOFO 28
FOF 1 28
FOF2 50
fOF3 SO
3552
3553 ;----- C_REG_TAB
3554
FOF4 3555 H7 LABEL BYTE I TABLE OF HOOf SETS
FOF4 2C 3556 DB 2~.2~.20H.2~.UH.2EH.IEH.2~
FOF5 28
FOF6 20
FOF7 29
FOF8 2A
FOF9 2£
FOFA lE
FOFB 29
3557
FOFC 3558 SET_HOOE PROC NEAR
FOFC 13A0403 3559 tfOV OX.0304H ; ADDRESS OF COLOR CARD
FOFF 8300 3560 HOV BL.O ; HODE SET FOR COLOR CARD
FlOl 63FF30 3561 CH" DI.30H ; IS BW CARD INSTALLED
FI04 7506 3562 JHE HB ; OK WITIf COLOR
Fl06 B007 3563 tfOV AL.7 ; INDICATE BW CARD HODE
FI08 B2B4 3564 HOV DL.OB4H I ADDRESS OF BW CARD (3B4)
FIOA FEC3 3565 INC Bl I HaDE SET FOR BW CARD
FlOC 3566 M8:
FlOC 6AEO 3567 HOV AH.Al ; SAVE MODE IN AH
FlOE A24900 3568 HOV CRT_MOOE.AL I SAVE IN GLOBAL VARIABLE
FIll 69166300 3569 HOV ADDR_6845.DX ; SAVE ADDRESS OF BASE
F1l5 IE 3570 PUSH OS j SAVE POINTER TO DATA SEGMENT
F1l6 50 3571 ruSH AX I SAVE HODE
FIl7 52 3572 ruSH OX I SAVE tJUTPUT PORT VALUE
System BIOS A-51

LOC OBJ LINE SOURCE
F1l8 83C204 3573 ADD OX.4 ; POINT TO CONTROL REGISTER

FUB 6AC3 3574 HOV AL,al ; GET MODE SET FOR CARD
FllD EE 3575 OUT Ox.AL I RESET VIDEO
FIlE 5A 3576 POP OX ; BACK TO BASE REGISTER
FllF 26CO 3577 SUB AX,AX ; -SET UP FOR ABSO SEGMENT
FllI 8E08 3578 HOV OS.AX I ESTABLISH VECTOR TABLE ADDRESSING
3579 ASSUME OS: ABSO
Fl23 C5IE7400 3580 LOS BX.PARM_PTR ; GET POINTER TO VIDEO PARMS
FIl7 58 3581 POP AX ; RECOVER PARMS
3582 ASSUME OS:CODE
Flza 891000 3583 HOV CX,M4 I LENGTH OF EACH ROW OF TABLE
F12B BOFCOl 3584 tHP AH,2 ) DETERMINE WHICH ONE TO USE
FIlE 1210 3585 Jt H. ; MODE IS 0 OR 1
Fl3a 0309 3586 ADD ex.cx j MOVE TO NEXT ROW OF INIT TABLE
FI3l aOFt04 3587 tHP AH.4
FI3S 7209 3588 Jt H. I MODE IS 2 OR 3
FI37 0309 3589 ADD ex.cx i MOVE TO GRAPHICS ROW OF INIT_TABLE
F139 eOFC07 3590 tHP AH.7
F 13C 7202 3591 Jt H. ; MODE IS 4.5. OR 6
F13E 0309 3592 ADD BX,CX j MOVE TO Bioi CARD ROW OF INIT_TABLE
3593
3594 j----- BX POINTS TO CORRECT ROW OF INITIALIZATION TABLE
3595
F140 3596 M9:
Fl40 50 3597 PUSH AX j SAVE MODE IN AH
F141 32E4 3598 XOR AH ,AH j AH WILL SERVE AS REGISTER
3599 i HUMeER DURING LOOP
3600
3601 j----- LOOP THROUGH TABLE. OUTPUTTIING REG ADDRESS. THEN VALUE FROM TABLE
3602
Fl43 3603 MID: I INIT LOOP
F143 8At4 3604 HOV AL.AH i GET 6845 REGISTER NUMBER
F145 EE 3605 OUT DX,AL
F14& 42 3606 INC OX i POINT TO OAT A PORT
Fl47 FEt4 3607 INC AH I NEXT REGISTER VALUE
F149 BA07 3608 MOV AL,IBXl ; GET TABLE VALUE
F14B EE 3609 OUT DX.AL ; OUT TO CHIP
F14C 43 3610 INC ex ; '-lEXT IN TA.BLF.
F14D 4A 3611 DEC ox j BACK TO POINTER REGISTER
F14E E2F3 3612 LOOP MIO ; 00 THE WHOLE TABLE
FISO 58 3613 POP AX ; GET MODE BACK
FIst IF 3614 POP OS ; RECOVER SEGMENT VALUE
3615 ASSUME DS:DATA
3616
3617 j ----- FILL REGEN AREA WITH BLANK
3618
F152 33FF 3619 XDR 01,01 j SET UP POINTER FOR REGEN
FIS4 893E4EOO 3620 HOV CRT_START,DI ; START ADDRESS SAVED IN GLOBAL
F158 C606620000 3621 HOV ACTIVE_PAGE ,0 I SET PAGE VALUE
f 150 690020 3622 MOV CX,SIn j NUMBER OF WORDS IN COLOR CARD
Fl6C aoFt04 3623 tHP AH,4 j TEST FOR GRAPHICS
FIB 720B 3624 Jt Hl2 ; NO_GRAPHICS_INIT
Fl6S eOFC07 3625 tHP AH,7 j TEST FOR BW CARD
Fl6e 7404 3626 JE H11 I BW_CARD_INIT
Fl6A 33CO 3627 XOR AX,AX j FILL FOR GRAPHICS MODE
Fl6C EB05 3628 JHP SHORT M13 j CLEAR_BUFFER
Fl6E 3629 Mll: ; BW_CARD_INIT
Fl6E 8508 3630 HOV CH,OSH ; BUFFER SIZE ON BW CARD
FI7a 3631 MI2: ; NO_GRAPHICS_INIT
F170 682007 3632 HDV AX,' '+7*256 I FILL CHAR FOR ALPHA
FI73 3633 M13: ; CLEAR_BUFFER
FI73 F3 3634 .EP STOSW j FILL THE REGEN BUFFER WITH BLANKS
F174 AS
3635
3636 i----- ENABLE VIDEO AND CORRECT PORT SETIING
3637
FI7S C70660000706 3638 HOV I SET CURRENT CURSOR MODE
FI7S A04900 3639 HOV ; GET THE MODE
Fi7E 32E4 3640 XD. AH,AH I INTO AX REGISTER
FleD BBFO 3641 HOV SI,AX ; TABLE POINTER. INOEXED BY MOOE
FI82 66166300 3642 HOV OX.AOOR_6845 I PREPARE TO OUTPUT TO
3643 ; VIDEO ENABLE PORT
Fl8b 83C204 3644 ADD OX,4
Fl89 2E8A84F4FO 3645 HOV AL,CS:[SI+OFFSET M7]
FISE EE 3646 OUT DX,AL ; SET VIDEO ENABLE PORT
FieF A26500 3647 HOV CRT_MODE_SET,AL ; SAVE THAT VALUE
36'8
A-52 System BIOS

LOC OBJ LINE SOURCE
3649 1----- DETERMINE NUMBER OF COlutlNS, BOTH FOR ENTIRE DISPLAY

3650 1----- AND THE NllHBER TO BE USED FOR TTY INTERFACE
3651
F 192 2E8A84ECFO 3652 MaV Al,CS:[SI + OFFSET M6J
F197 32:E4 3653 XOR AH,AH
Fl99 A,34.6.00 3654 HOV CRT_eOls,AX I NUHBER OF COLUMNS IN TliIS SCREEN
3655
3656 1----- SET CURSOR POSITIONS
3657
F19C 81£60EOO 3658 AND 5I.OEH I WORD OFFSET INTO CLEAR LENGTH TABLE
FlAO 2ESB8CE4FO 3659 HOV CX.CS:ISI + OFFSET MS] , LENGTH TO CLEAR
FIAS 890E4COO 3660 HOV CRT_LEN.CX j SAVE LENGTH OF CRT -- NOT USED FOR BW
FlA9 890800 3661 HOV CX.8 I CLEAR ALL CURSOR POSITIONS
FlAt BF5000 3662 HOV DI.OFFSET CURSOR_POSN
FlAF IE 3663 PUSH OS I ESTABLISH SEGMENT
fleD 07 3664 POP ES ADDRESSING
F IB1 33CO 3665 XOR AX,AX
FIB3 F3 3666 REP STOSW j FILL WITH ZEROES
FIB4 AB
3667
3668 1----- SET UP OVERSCAN REGISTER
3669
FIBS 42 3670 INC OX j SET OVERSCAN PORT TO A DEFAULT
FIBb B030 3671 HOV AL.30H j VALUE OF 30H FOR ALL MOOES
3672: j EXCEPT 640X200
flB8 803E490006 3673 CHP CRT_MOOE.6 ; SEE IF THE MODE IS 640X200 BW
FIBD 7502 3674 JNZ HI" IF IT ISNT 640X200. THEN GOTO REGULAR
FIBF B03F 3675 HOV AL.3FH ; IF IT IS 640X200. THEN PUT IN 3FH
FlCl 3676 M14:
FIel EE 3677 OUT DX.Al j OUTPUT THE CORRECT VALUE TO 309 PORT
F It2 A26600 3678 HOV CRT_PALETTE,AL ; SAVE THE VALUE FOR FUTURE USE
3679
3680 j----- NORMAL RETURN FROM ALL VIDEO RETURNS
3681
FltS 3682 VIDEO_RETURN:
FICS SF 3683 POP DI
FlC6 SE 3684 POP SI
FIC7 58 3685 POP BX
FICS 3686 HIS: I VIOEO_RETURN_C
Flce 59 3687 POP CX
FlC9 SA 3688 POP OX
FICA IF 3689 POP OS
Flce 07 3690 POP ES j RECOVER SEGMENTS
Flee CF 3691 IRET ; ALL DONE
3692 SET_MOOE ENDP
3693 ; ----------------------------------------------------------------
3694 j SET_CTYPE
3695 THIS ROUTINE SETS THE CURSOR VALUE

3696 j INPUT
3697 j (CXI HAS CURSOR VALUE CH-START LINE. CL-STOP LINE
3698 ; OUTPUT
3699 NONE
3700 j----------------------------------------------..-----------------
FlCD 3701 SET_CTYPE PROC NEAR
FlCD 640.6. 3702 HOV AH.IO I 6845 REGISTER FOR CURSOR SET
FIeF 890E6000 3703 HOV CURSOR_HODE.CX ; SAVE IN OATA AREA
FI03 E80200 3704 CALL HI6 I OUTPUT CX REG
FID6 EBED 3705 JMP VIDEO_RETURN
3706
3707 j----- THIS ROUTINE OUTPUTS THE CX REGISTER TO THE 6645 REGS NAMED IN AH
3708
Floe 3709 N16:
Floe 88166300 3710 HOY DX.ADOR_6645 I ADDRESS REGISTER
flOC 8AC4 3711 HOV AL.AH j GET VALUE
FIDE EE 3712 OUT DX.At j REGISTER SET
FlOF 42 3713 INC OX j DATA REGISTER
FlED 8AC5 3714 HOV AL.CH ; DATA
FIE2 EE 3715 OUT OX.AL
Fln 4A 3716 DEC OX
FIE4 8At4 3717 HOV .At.AH
FIE6 FEtD 3716 INC AL I POINT TO OTHER DATA REGISTER
FlEe EE 3719 OUT OX.AL j SET FOR SECOND REGISTER
FIE9 42 3720 INC OX
FlEA 8AC1 3721 HOV AL.CL ; SECOND DATA VALUE
FlEt EE 3722 OUT OX.AL
FlED C3 3723 RET I ALL DONE
3724 SET_CTYPE ENDP
System BIOS A-53

LOC OBJ LINE SOURCE
3725 1------------------------------------------------
3726 ; SET_CPOS
3727 THIS ROUTINE SETS THE CURRENT CURSOR
3728 POSITION TO THE NEW X-V VALUES PASSED
3729 ; INPUT
3730 OX - ROW,COLUt1N OF NEW CURSOR
3731 BH - DISPLAY PAGE OF CURSOR
3732 ; OUTPUT
3733 CURSOR IS SET AT 6845 IF DISPLAY PAGE
3734 IS CURRENT DISPLAY
3735 ; --------------- ---------------------------------
FlEE 3736 SET_CPOS PROC NEAR
FlEE 8ACF 3737 MOV CL.BH
FIFO 32EO 3738 XOR CH,CH ; ESTABLISH LOOP COUNT
FIFe! DIEI 3739 SAL CX.l ; WORD OffSET
FIF4 88Fl 3740 MOV SI,CX , USE IHDEX REGISTER
FIF6 895450 3741 MOV [SI+OFFSET CURSOR_POSN1,DX i SAVE THE POINTER
FIF9 383E6200 3742 CMP ACTIVE_PAGE .BH
FIFO 7505 3743 JHZ M17 , SET_CPOS_RETURN
FIFf 8BC2 3744 MOV AX,DX ; GET ROW/COLUMN TO AX
flOl E80200 3745 CALL M18 ; CURSOR_SET
F204 3746 MI7: I SET _CPOS_RETURN
Fl04 EBBF 3747 JMP VIDEO_RETURN
3748 SET_CPOS ENOP
3749
3750 ,----- SET CURSOR POSITION. AX HAS ROW/COLUHN FOR CURSOR
3751
fZOb 3752 M18 PROC NEAR
FlOb E87COO 3753 CAll POSITION ; DETERMINE LOCATION IN REGEN BUFFER
Fl09 88C8 3754 MOV CX,AX
flOB 030E4EOO 3755 ADO CX,CRT_START ; ADD IN THE START ADDR FOR THIS PAGE
F20F DIF9 3756 SAR CX,l ; DIVIDE BY 2 FOR CHAR ONLY COUNT
Flll 840E 3757 MOV AH,14 ; REGISTER NUMBER FOR CURSOR
FZ13 EBC2FF 3758 CALL M16 ; OUTPUT THE VALUE TO THE 6845
F216 C3 3759 RET
3760 MI8 ENOP
3761 ; ---------- ------------------------------------------------------
3762 ; ACT_DISP_PAGE
3763 THIS ROUTINE SETS THE ACTIVE DISPLAY PAGE, ALLOWING THE
3764 FULL USE OF THE RAM SET ASIDE FOR THE VIDEO ATTACHMENT
3765 INPUT
3766 AL HAS THE NEW ACTIVE DISPLAY PAGE
3767 ; OUTPUT
3768 THE 6845 IS RESET TO DISPLAY THAT PAGE
376 <;I ; -------------- --- --------------------- --------------------------
fl17 3770 ACT_DISP_PAGE ?ROC NEAR
fl17 A26200 3771 MOV ACTIVE_PAGE.AL I SAVE ACTIVE PAGE VALUE
fZu' 880E4COO 37TZ. MOV CX,CRT_LEN ; GET SAVED LENGTH OF REGEN BUFFER
F21E 98 3773 CBW ; CONVERT AL TO WORD
F21F 50 3774 PUSH AX ; S.a.VE PAGE V.a.LUE
f220 f7Et 3775 HUL ex 1 DISPLAY PAGE TIMES REGEN LENGTH
F2ll A34EOO 3776 MOV CRT_START .AX ; SAVE START ADDRESS FOR
3777 ; LATER REQUIREMENTS
F225 88C8 3778 MOV CX.AX ; START ADDRESS TO CX
F227 DIF9 3779 SAR CX,1 i DIVIDE BY 2 FOR 6845 HANDLING
F229 B40C 3780 MOV AH.12 ; 6845 REGISTER FOR START ADDRESS
F22B EBAAFF 3781 CALL MI6
FZ2E 58 3782 POP ax ; RECOVER PAGE VALUE
F22F DID 3783 SAL BX.I ; *2 FOR WORD OFFSET
fZ31 884750 3784 MOV AX,[BX + OFFSET CURSOR_POSH] j GET CURSOR FOR THIS PAGE
F234 E8CFFF 3785 CAll HI8 ; SET THE CURSOR POSITION
F237 EBec 3786 JMP SHORT VIDEO_RETURN
3788 ;----------------------------------------------------------------
3789 ; READ_CURSOR
3790 THIS ROUTINE READS THE CURRENT CURSOR VALUE FROM THE
3791 6845. FORMATS IT. AND SENDS IT BACK TO THE CALLER
3792 INPUT
3793 BH - PAGE OF CURSOR
3794 I OUTPUT
3795 ox - ROW, COLUHN OF THE CURRENT CURSOR POSITION
3796 CX - CURRENT CURSOR MODE
3797 ; ----------------------------------------------------------------
fZ39 3798 READ_CURSOR PROC NEAR
F239 8AOF 3799 MOV BL,BH
FZ38 32FF 3800 XOR BH,BH
FZ3D DIE3 3801 SAL BX.l j WORD OFFSET
A-54 System BIOS

LaC OBJ LINE SOURCE
F2:3F 885750 3802: MDV OX,(BX-tOFFSET CURSOR_POSNI

F242 8BOE6000 3803 MOV eX,CURSOR_MODE
F2:46 SF 3804 pop 01
F247 SE 3805 POP SI
F2:48 58 3806 POP BX
FZ49 58 3807 POP AX I DISCARD SAVED ex AND ox
F24A 58 3808 POP AX
F2:4B If 3809 POP OS
F2:4C 07 3810 POP ES
F2:40 CF 3811 rRET
3812 READ_CURSOR ENDP
3813 ;----------------------------------------------------------- ____________ _
3814 ; SET COLOR
3815 THIS ROUTINE WIll ESTABLISH THE BACKGROUND COLOR. THE OVERSCAN
3816 COLOR. AND THE FOREGROUND COLOR SET fOR MEDIUM RESOLUTION
3817 GRAPHICS
3818 INPUT
3819 (BH ) HAS COLOR ID
3820 IF BH=O, THE BACKGROUND COLOR VALUE IS SET
3821 FROM THE LOW BITS OF BL (0-31 )
3822 IF BH=I, THE PALETTE SELECTION IS MADE
3823 BASED ON THE LOW BIT OF BL:
3824 O=GREEN. RED. YELLOW FOR COLORS 1.2.3
3625 l=BLUE. CYAN. MAGENTA FOR COLORS 1.2:.3
3826 (BLl HAS THE COLOR VALUE TO BE USED
3827 ; OUTPUT
3828 THE COLOR SelECTION IS UPDATED
3829 i ------------------------------------------------------------------------
F24E 3630 SET_COLOR PROC NEAR
F2:4E 88166300 3831 MOV DX.ADDR_o84S j 1/0 PORT FOR PALETTE
F2:52 83e205 3832 ADD OX.S ; OVERSCAN PORT
F255 A066DO 3833 MOV AL.CRT_PALETTE ; GET THE CURRENT PALETTE VALUE
F258 DAFF 3834 OR BH.BH ; IS THIS COLOR 01
F2:5A 750E 3835 JHZ M20 i OUTPUT COLOR I
3836
3637 j----- HANDLE COLOR 0 BY SETTING THE BACKGROUND COLOR
3838
F25C 24EO 3839 AND AL,OEOH ; TURN OFF LOW 5 BITS OF CURRENT
F25E 80E31F 3840 AND BL.OIFH ; TURN OfF HIGH 3 BITS OF INPUT VALUE
Fl61 OAt3 3841 OR AL.BL ; PUT VALUE INTO REGISTER
Fl6] 3842 M19: ; OUTPUT THE PALETTE
Fl63 EE 3643 OUT aX.AL i OUTPUT COLOR SELECTION TO 309 PORT
F264 Alb6DO 3844 MOV CRT_PALETTE.AL ; SAVE THE COLOR VALUE
Flo? E95BFF 3845 JMP VIDEO_RETtmN
3846
3647 1----- HANDLE COLOR 1 BY SELECTING THE PALETTE TO BE USED
3848
F26A 3649 M20:
Fl6A 24DF 3850 AND AL,ODFH ; TURN OFF PALETTE SELECT BIT
F20C DOEB 3851 SHR BLo! ; TEST THE LOW ORDER BIT OF Bl
FloE 73F3 3852 JNC M19 ; ALREADY DONE
F270 OC20 3853 OR AL,20H ; TURN ON PA LEnE SelECT BIT
F272 EBEF 3654 JMP M19 iGOOOIT
3855 SET_COLOR ENOP
3856 ; ---- - -- - - - - ---- - - -- - ------- - - - ------ ----- -- - - - --
3857 ; VIDEO STATE
3858 RETURNS THE CURRENT VIDEO STATE IN AX
3859 AH = NUMBER OF COLUMNS ON THE SCREEN
3860 AL = CURRENT VIDEO MODE
3861 BH = CURRENT ACTIVE PAGE
3862 1------------------------------------------------
F274 3863 VIDEO_STATE PROC NEAR
F2:74 8A264AOO 3864 MOV AH,BYTE PTR CRT_COLS ; GET NUMBER OF COLUMNS
F2:78 A04900 3865 MOV AL,CRT_MODE ; CURRENT MODE
F27B 8A3E62:DO 3866 MOV BH, ACTIVE_PAGE ; GET CURRENT ACTIVE PAGE
F27F SF 3867 POP 01 1 RECOVER REGISTERS
F2:80 5E 3868 POP SI
F28l 59 3869 POP CX j DISCARD SAVED BX
Fla2 E943FF 3870 JMP M15 ; RETURN TO CALLER
3871 VIDEO_STATE ENDP
3872 j--------------------------------------------------------
3873 ; POSITION
3874 THIS SERVICE ROUTINE CALCULATES THE REGEN
3875 BUFFER ADDRESS OF A CHARACTER IN THE ALPHA MODE
3876 ; INPUT
3877 AX = ROW, COLUMN POSITION
3878 ; OUTPUT
System BIOS A-55

LaC OBJ LINE SOURCE
3879 AX = OFFSET OF CHAR POSITION IN REGEN BUFFER

3880 I - - - - - -- - ---- - -- - ---- - - - - --- - - --- ---------- --- - - ------- --
F285 3881 POSITION PROC NEAR
F285 53 3882 PUSH BX ; SAVE REGISTER
Flab 8B06 3883 MOV BX,AX
FlBB 8AC4 3884 MOV AL,AH ; ROWS TO AL
FlBA F6264AOO 3885 MUL BYTE PTR CRT_COLS ; DETERMINE BYTES TO ROW
FleE 32FF 3886 XOR BH,BH
f290 03e3 3887 ADO AX,BX ; ADO IN COLUMN VALUE
F29Z DIED 3888 SAL AX,1 ;* 2 FOR ATTRIBUTE BYTES
F294 58 3889 POP BX
F295 (3 3890 RET
3891 POSITION ENDP
3892 1--------------------------------------------------------
3893 ; SCROLL UP
3694 THIS ROUTINE MOVES A BLOCK OF CHARACTERS UP
3895 ON THE SCREEN
3896 INPUT
3897 (AH I = CURRENT CRT MODE
3898 (All = NUMBER OF ROWS TO SCROLL
3899 (CX I = ROW/COLUMN OF UPPER LEFT CORNER
3900 (OX) = ROW/COLUMN OF LOWER RIGHT CORNER
3901 (BHI = ATTRIBUTE TO BE USED ON BLANKED LINE
3902 (OS) = DATA SEGMENT
:903 (ES I = REGEN BUFFER SEGMENT
3904 ; OUTPUT
3905 NONE -- THE REGEN BUFFER IS MODIFIED
3906 ;--------------------------------------------------------
3907 ASSUME CS:CODE,DS:OATA,ES:DATA
,.96 3908 SCROLL_UP PROC NEAR
F296 8A08 3909 MOV BL,AL ; SAVE LINE COUNT IN BL
F298 SOFt04 3910 CMP AH.4 ; TEST FOR GRAPHICS MODE
F29B 7208 3911 JC Nl ; HANDLE SEPARATELY
F290 aOFCOl 3912 CMP AH.7 ; TEST FOR BW CARD
FlAD 7403 3913 JE Nl
Fl"2 E9FOOl 3914 JMP GRAPHICS_UP
FZAS 3915 Nl: ; UP_CONTINUE
F2AS 53 3916 PUSH BX ; SAVE FILL ATTRIBUTE IN BH
FlA6 8BCl 3917 MOV AX,CX ; UPPER LEFT POSITION
FlAB £83700 3918 CALL SCROll_POSITION ; DO SETUP FOR SCROLL
FlAB 7431 3919 JZ N7 I BLANKJIELD
F2AD 03FO 3920 ADD SI.AX ; FROM ADDRESS
F2AF 8AE6 3921 MOV AH,DH I ; ROWS IN BLOCK
FlBl ZAn 3922 SUB AH.BL ; ; ROWS TO BE MOVED
F2B3 3923 N2: ; ROW_LOOP
F2B3 E872:00 3924 CALL NI0 I MOVE ONE ROW
FlBb OlF5 3925 ADD SI.BP
FlBa 03FD 3926 ADO OI,SP ; POINT TO NEXT LINE IN BLOCK
FlBA FEee 3927 DEC AH ; COUNT OF LINES TO MOVE
FlBt 75F5 3928 JNZ N2 j ROW_LOOP
FlBE 3929 N3:
FlBE 58 3930 POP AX I RECOVER ATTRIBUTE IN AH
F2BF B020 3931 MOV AL. ; FILL WITH BLANKS
FlCI 3932 ; CLEAR_LOOP
Flel E86000 3933 CALL NIl ; CLEAR THE ROW
Fle4 03FO 3934 ADD OI,SP ; POINT TO NEXT LINE
Flt6 FEte 3935 DEC BL j COUNTER OF LINES TO SCROLL
Flca 75F7 3936 JNZ N4 ; CLEAR_LOOP
F2eA 3937 j SCROLL_END
FleA EB7l0e 3938 CALL DDS
FleD 803E490007 3939 CMP CRT_MODE. 7 ; IS THIS THE BLACK AND WHITE CARD
fl02 7407 3940 JE N6 ; IF SO. SKIP THE MODE RESET
Fl04 A06500 3941 MOV AL,CRT_MODE_SET ; GET THE VALUE OF THE MODE SET
Fl07 BA0803 3942 MOV DX.03D8H I ALWAYS SET COLOR CARD PORT
FlOA EE 3943 OUT DX,AL
FlOB 3944 N6:
F2DB E9E7FE 3945 JMP
HOE 3946 N7: ; BLANKJIELD
F2DE 8ADE 3947 MOV BL,OH ; GET ROW COUNT
FlED EBoC 3948 JMP N3 ; GO CLEAR THAT AREA
3949 SCROLL_UP ENIlP
3950
3951 ;----- HANDLE COMMON SCROLL SET UP HERE
3952
FlEZ 3953 SCROLL_POSITION PROC NEAR
F2EZ 803E490002 3954 CMP CRT_MODE.2 I TEST FOR SPECIAL CASE HERE
F2E7 7218 3955 JB N9 ; HAVE TO HANDLE 80X25 SEPARATELY
A-56 System BIOS

LOC OBJ LINE SOURCE
FZE9 B03E490003 3956 CHP CRT_HOOE,3

F2EE 7711 3957 JA N.
3958
3959 1----- SOX25 COLOR CARD SCROLL
3960
FHO 52 3961 PUSH OX
FZFl BADA03 3962 HOV DX,30AH ; GUARANTEED TO BE COLOR CARD HERE
F2F4 50 3963 PUSH AX
F2F5 3964 H6: ; WAH_DISP_ENABLE
F2F5 EC 3965 IH AL,OX I GET PORT
f2F6 A808 3966 TEST AL,e I WAIT FOR VERTICAL RETRACE
F2F8 74FB 3967 JZ H8 ; WAIT_DISP_ENABLE
fZfA B025 3966 HOV AL,25H
F2FC B208 3969 NOV Dl,008H ; DX=3D8
F2FE EE 3970 OUT OX.AL ; TURN OFF VIDEO
F2FF 58 3971 POP AX ; DURING VERTICAL RETRACE
F300 SA 3972: POP OX
F30l 3973 H9:
F30l E881FF 3974 CALL POSITION ; CONVERT TO REGEN POINTER
F304 03064EOO 3975 ADO AX ,CRT_START I OFFSET OF ACTIVE PAGE
FlOB 8BF8 3976 HOV DI,AX ; TO ADDRESS FOR SCROLL
FlOA BBfO 3977 HOV SI.AX I FROM ADDRESS FOR SCROLL
F30C 2B01 3978 DX,CX ; OX = #ROWS, ;-COLS IN BLOCK
F30E FEC6 3979 INC OH
F310 FEC2 3980 INC Ol ) INCREHENT FOR 0 ORIGIN
nl2 32ED 3981 XOR CH,CH ; SET HIGH BYTE OF cOUNT TO ZERO
F314 8B2E4AOO 3982 HOV BP,CRT_COLS ; GET NUMBER Of COLUMNS IN DISPLAY
F318 03ED 3983 ADO BP,BP ; TIMES 2 FOR ATTRIBUTE BYTE
F31A 8AC3 3984 HOV AL,BL ; GET LINE COUNT
F31C F6264AOO 3985 HUl BYTE PTR CRT_COLS ; DETERMmE OFFSET TO FROM ADDRESS
F320 03CO 3986 ADO AX,AX ; *2 FOR ATTRIBUTE BYTE
n22 06 3967 PUSH ES , ESTABLISH ADDRESSING TO REGEN BUFFER
F323 IF 3988 POP OS I FOR BOTH POINTERS
F324 80FBOO 3989 CMP BL,O ; 0 SCROLL MEANS BLANK FIELD
F327 C3 3990 RET ; RETURN WITH FLAGS SET
3991 SCROll_POSITION ENOP
3992
3993 ;----- MOVE_ROW
3994
F328 3995 Hl0 PROC NEAR
F328 8ACA 3996 MOV CL,DL ; GET. OF COLS TO MOVE
F32A 56 3997 PUSH 51
n2B 57 3998 PUSH 01 ; SAVE START ADDRESS
F32C F3 3999 REP HOVSW ; MOVE mAT LINE ON SCREEN
F32D A5
F32E 5F 4000 POP 01
F32F SE 4001 POP 51 ; RECOVER ADDRESSES
F330 C3 4002 RET
4003 Hl0 ENDP
4004
4005 j----- CLEAR_ROW
4006
F331 4007 H11 PROC NEAR
F331 8ACA 4008 HOV CL,DL I GET. COLlR1NS TO CLEAR
F333 57 4009 PUSH 01
F334 F3 4010 REP STOSW ; STORE THE FILL CHARACTER
F335 A6
F336 SF 4011 POP 01
F337 C3 4012 RET
4013 H11 ENDP
4014 ;--------------------------------------------------------
4015 ; SCROll_DOWN
4016 THIS ROUTINE MOVES mE CHARACTERS WITHIN A
4017 DEFINED BLOCK DOWN ON THE SCREEN, FILLING THE
4018 TOP LINES WITH A DEFINED CHARACTER
4019 ; INPUT
4020 (AH) = CURRENT CRT HOOE
4021 (AU = NUMBER OF LINES TO SCROLL
4022 (CX) = UPPER LEFT CORNER OF REGION
4023 (OX) = LOWER RIGHT CORNER OF REGION
4024 (BH) = FILL CHARACTER
4026 (ES I = REGEN SEGMENT
4027 ; OUTPUT
4026 NONE -- SCREEN IS SCROllED
4029 ;--------------------------------------------------------
F338 4030 SCROLl....DOWH PPDC NEAR
System BIOS A-57

LOC OBJ LINE SOURCE
F338 FD 4031 STO I DIRECTION FOR SCROLL DMI

F339 BAD8 4032 tIOV SL.AL JUNE CiX..NT TO Bt
F338 eOFCOlt 4033 CMP AH,4 I TEST FOR GRAPHICS
F33£ 72:08 4014- JC HI.
F340 BOFC07 4035 CMP AH,7 I TEST FOR BW CARD
F34~ 7403 4036 JE HI.
F345 £9A601 4037 JMP GRAPHICS_DCJIoI4
F348 4038 NI2:: I CONTINUE OQIIII
F348 53 4039 PUSH BX I SAVE ATTRIBUTE IN BIt
F349 BBC2 4040 HOV AX,OX ~ LOWER RIGHT CORNER
f348 £894Ff 4041 CAll SCROLL"..POSITION ; GET REGEN LOCATION
F34£ 7420 4042: JZ HI.
F350 28FO 4043 SUB 51 ,A)( J 51 IS FROf1 ADDRESS
F352 8.£6 4044 I10V AH,DH ; GET TOTAL I ROWS
F354 2AE3 4045 SUB AH.BL I cOUNT TO HOVE IN SCROLL
F35b 4046 N13:
F356 ESCFfF 4041 CALL HID I I10VE ONE ROW
F359 2BFS 4048 SUB SI,BP
F358 2BFD 4049 SUB DI,BP
F350 FEee 4050 DEC AH
f35F 75F5 4051 JHZ H13
'361 4052 H14:
F3&1 58 4053 PDP AX I RECOYER ATTRIBUTE IN AH
F362 B020 4054 HOV AL,'
'364 4055 H15:
F364 fBCAFF 4056 CALL H11 I CLEAR ONE ROW
F367 2BFD 4057 SUB DI.BP I GO TO NEXT ROW
F369 FECB 4058 DEC BL
F36B 75F7 4059 JHZ HIS
F36D E95AFF 4060 JMP HS I SCROl'--.END
F370 4061 N16:
F370 8ADE 4062 MDV BL.DH
F372 EBED 4063 JMP Hl'
4064 SCROlL..DOWN ENDP
4065
4066
;-------------------------------------..------------------
, READ_AC_CURRENT
4067 THIS ROUTINE READS THE ATTRIBUTE AN) CHARACTER ,
4068 AT THE CURRENT CURSOR POSITIoN Am REruRNS THEM :
4069 I TO THE CALLER
4070 ,INPUT
4071 (AH J = CURRENT CRT MODE
4072 (BH) = DISPLAY PAGE ( ALPHA MODES ONLY »
4073 IDS) = DATA SEGMENT
4074 I ES) = REGEN SEGMENT
4075 ;OUTPUT
4076 (AU = CHAR READ
4077 I AH I = ATTRIBUTE READ
4078 ;--------------------------------------------------------
4079 A~SI.R1E CS:CODE .DS: DATA, ES :OATA
F374 4080 READ_AC_CURRENT PROC NEAR
F374 80FC04 4081 CMP AH,4 , IS THIS GRAPHICS
F377 7208 4082 JC PI
F379 80FC07 4083 CMP AH,7 ; IS THIS BW CARD
F37C 7403 4084 JE PI
F37E E9A802 4085 JMP GRAPHICS_READ
'381 4086 PI: 1 READ_AC_CONTIt«lE
F381 E8UOO 4087 CALL FINO_POSITION
F364 SBF3 4088 MDV SI.BX 1 ESTABLISH ADDRESSiNG IN SI
4089
4090 1----- WAIT FOR HORIZONTAL RETRACE
4091
F386 88166300 4092 miv DX.ADDR_6845 J GET BASE ADDRESS
F38A 83C206 4093 ADD DX.6 i POINT AT STATUS PORT
F38D 06 4094 PUSH ES
F38E IF 4095 POP OS I GET SEGMENT FOR QUIIZK ACCESS
F38F 4096 P2: 1 WAIT FOR RETRACE LOW
F38F EC 4097 IH AL,DX l GET STATUS
F390 A801 4098 TEST AL.1 o IS HCAl RETRACE LOW
F392 75FB 4099 JHZ P' o WAIT UNTIL IT IS
F394 FA 4100 CLI ; NO MORE INTERRUPTS
F395 4101 P3: j WAIT FOR RETRACE HIGH
F395 EC 410. IN AL.OX 1 GET STATUS
F396 A801 4103 TEST AL.1 j IS IT HIGH
F398 74FB 4104 JZ P3 1 WAIT ~TIL IT IS
F39A AD 4105 LODSW I GET THE CHAR/ATTR
F39B E927FE 4106 JMP VIDEO_RETURN
4107 READ_At_CURRENT EN)P
A-58 System BIOS

LOC OBJ LINE SOURCE
4108
F39E 4109 FIND_POSITION PROC NEAR
F39E SACf 4110 "OV CL,BH J DISPLAY PAGE TO ex
F3AO 32EO 4111 XOR CH,CH
F3A2 8BF 1 4112 MOV SI,CX I MOVE TO SI FOR INDEX
F3A4 01E6 4113 SAL 51.1 I ,. 2 FOR WORD OFFSET
F3A6 884450 4114 MOV AX,(SI+ OFFSET ClmSOR_POSNI ; GET ROW/COLUMN OF ntAT PAGE
F3A9 3308 4115 XOR aX.BX ; SET START ADDRESS TO ZERO
nAB E306 4116 JCXZ P5 ; NO_PAGE
F3AO 4117 P4; ; PAGE_LOOP
F3AO 031E4COO 4118 ADD I LENGTH OF BUFFER
FlBI E,FA 4119 LOOP
F3B3 4120 1'5: I NO_PAGE
F3B3 E8CFFE 4121 CALL POSITION ; DETERMINE LOCATION IN REGEN
nB6 0308 4122 ADD BX,AX ; ADD TO START OF REGEN
F368 C3 412:3 RET
412:4 FIND_POSITION ENOl'
4125 ; ------------------------------------------------
412:6 ; WRITE_AC_CURRENT
412:7 THIS ROUTINE WRITES THE ATTRIBUTE
4128 AND CHARACTER AT THE CURRENT CURSOR
412:9 POSITION
4130 INPUT
4131 (AH 1 :: CURRENT CRT MODE
4132 (BH) :: DISPLAY PAGE
4133 {CXI :: COUNT OF CHARACTERS TO WRITE
4134 (All :: CHAR TO WRITE
4135 (Bll :: ATTRIBUTE OF CHAR TO WRITE
4136 (DSI :: DATA SEGMENT
4137 (ESI :: REGEN SEGMENT
4138 ; OUTPUT
4139 NONE
4140 j------------------------------------------------
F3B9 4141 WRITE_At_CURRENT PROt NEAR
F3B9 80FC04 4142: CMP A,H,4 I IS THIS GRAPHICS
F3et 7208 4143 JC P6
F3BE 80FC07 4144 CMP AH,7 ; IS THIS BW CARD
F3Cl 7403 4145 JE P6
F3C3 £96201 4146 JMP GRAPHICS_WRITE
nC6 4147 P6: I I,~IHTE_AC_CONTINUE
F3C6 8AE3 4148 MeV AH,BL I GET ATTRIBUTE TO AH

F3ee 50 4149 PUSH AX I SAVE ON STACK
F3C9 51 4150 PUSH CX ; SAVE WRITE COUNT
F3eA ESPIFF 4151 CALL FHID_POSITION
nco SBFe 4152: MeV DI,BX j ADDRESS TO 01 REGISTER
F3CF 59 4153 POP CX ; WRITE COUNT
F300 58 4154 POP BX ; CHARACTER IN BX REG
nOl 4155 P7: I WRITE_LOOP
4156
4157 ;----- WAIT FOR HORIZONTAL RETRACE
4158
F30l 88166300 4159 MOV DX.ADDR_6845 ; GET BASE ADDRESS
F30S 83C206 4160 ADD DX.6 ; POINT AT STATUS PORT
F30B 4161 PB:
F30e EC 4162 IN Al.OX ; GET STATUS
F3D9 1.801 4163 TEST Al.1 ; IS IT LOW
F30B 7SFB 4164 JHZ P. I WAIT UNTI L IT IS
F30C FA 4165 ClI I NO MORE INTERRUPTS
nOE 4166 P9:
nOE EC 4167 IN AL,DX ; GET STATUS
F30F 1.801 4168 TEST AL,l I IS IT HIGH
nEl 74FB 4169 JZ P9 ; WAIT UNTIL IT IS
F3E3 8BC3 4170 MOV AX,BX I RECOVER THE CHAR/ATTR
F3ES AB 4171 STOSW ; PUT THE CHAR/ATTR
F3E6 FB 4172 STI ; INTERRUPTS BACK ON
F3E7 E2E8 4173 LOOP P7 I AS MANY TIMES AS REQUESTED
F3E9 E9D9fD 4174 JMP VIDEO_RETURN
4175 WRITE_AC_CURRENT ENDP
4176 ; ------------------------------------------------
4177 I WRITE_C_CURRENT
4178 THIS ROUTINE WRITES THE CHARACTER AT
4179 THE CURRENT CURSOR POSITION. ATTRIBUTE
4iso UNCHANGED
4181 ; INPUT
4182 (AH I :: CURRENT CRT MODE
4183 (BHl :: DISPLAY PAGE
4184 (CXl :: COUNT OF CHARACTERS TO ~ITE
System BIOS A-59

LOC OBJ LINE SOURCE
4185 I All = CHAR TO WRITE

4187 I E51 = REGEN SEGMENT
4188 ; OUTPUT
4189 NONE
4190 ; -- ---- -- - -- - --- - -- ----- ---- - - ------------- -- --.-
F3Ee 4191 WRITE_C_CURRENT PROC NEAR
F3Ee 60FC04 4192 CMP AH,4 I IS THIS GRAPHICS
F3Ef 7208 4193 JC Pl.
F3Fl 8~FC07 4194 CMP AH,7 I IS THIS BN CARD
F3F4 7403 4195 JE PlO
F3F6 £97FOI 4196 JMP GRAPHICS_WRITE
F3F9 4197 P10:
F3F9 SO 4198 pUSH AX I SAVE ON STACK
f3FA 51 4199 PUSH CX I SAVE WRITE COUNT
F3FB EBAOfF 4200 CALL FIND_POSITION
F3F£ aSFB 4201 MOV OI,BX I ADDRESS TO 01
F400 59 4202 POP CX I WRITE COUNT
F401 58 4203 POP BX I BL HAS CHAR TO WRITE
F402 4204 Pll: I WRITE_LOOP
4205
4206 ; ----- WAIT FOR HORIZONTAL RETRACE
4207
F402 88166300 4208 MOV OX , ADOR_6845 ; GET BASE ADDRESS
f406 83C206 4209 ADD DX,6 i POINT AT STATUS PORT
F'409 4210 P12:
f'l.09 EC 4211 IN AL,DX I GET STATtJS
F40A A801 42:12 TEST AL,l ; IS IT LOW
F40C 75F8 4213 JNZ P .. I WAIT UNTIL IT IS
F40£ FA 421'. CLI i NO MORE INTERRUPTS
F40F 4215: Pl3:
F40F EC 4216 IN AL,DX ; GET STATUS
F410 A801 4217 TEST Al,l ; IS IT HIGH
F412 74F8 4218 JZ P13 I WAIT UNTIL IT IS
F414 8AC3 4219 MOV Al,Bl I RECOVER CHAR
F416 AA 422:0 STOSB ; PUT THE CHAR/ATTR
F417 FB 422:1 STI I INTERRUPTS BACK ON
F416 47 4222 INC OI J BlR1P POINTER PAST ATIRIBUTE
F419 E2£7 4223 LOOP Pll ; .1.5 MANY TIMES AS REQUESTED
F418 E9A7FD 4224 JMP VIDEO_RETURN
4225 WRITE_C_CllRRENT ENDP
4226 ; ----------------------------------------------------------------
422:7 ; READ DOT -- WRITE DOT
4228 THESE ROUTINES WILL WRITE A DOT, OR READ THE DOT AT
4229 TliE INDICATED LOCATION
4230 I ENTRY --
4231 OX = ROW (0-199) (THE ACTUAL VALUE DEPENDS ON THE MODE)
4232 CX = COLUMN ( 0-639) ( THE VALUES ARE NOT RANGE CHECKED )
4233 AL = DOT VALUE TO WRITE (1,2 OR 4 BITS DEPENDING ON MODE,
4234 REQ'D FOR WRITE DOT ONLY, RIGHT JUSTIFIED)
4235 BIT 7 OF AL=l INDICATES XOR THE VALUE INTO THE LOCATION :
4236 OS = DATA SEGMENT
4237 ES = REGEN SEGMENT
4238
4239 ; EXIT
4240 AL = DOT VALUE READ, RIGHT JUSTIFIED, READ ONLY
4241 ,----- --- -- --------------------------- ----- ------ -- - -------------
4242 ASSUME CS:COOE,DS:DATA,ES:DATA
F41£ 4243 READ_DOT PRoe NEAR
F41E £83100 4244 CALL R3 ; DETERMINE BYTE POSITION OF DOT
F"+21 268A04 4245 MOV AL,ES:[SII I GET THE BYTE
F424 22C4 4246 Am Al,AH I MASK OFF THE OTHER BITS IN THE BYTE
F426 OlEO 4247 SHL AL,Cl I lEFT JUSTIFY THE VALUE
F428 BACE 4248 HOV CL,DH I GET NUMBER OF BITS IN RESULT
f42A 02eo 4249 ROL Al,Cl I RIGHT JUSTIFY THE RESULT
F42C E9%FD 4250 JMP VIDEO_RETt.RN I RETURN FROH VIDEO 10
4251 ENDP
4252
F42F 4253 WRITE_DOT PROC NEAR
F42F 50 42:54 PUSIt AX I SAVE ~OT VALUE
F430 50 4255 PUSH AX J TWICE
F431 EBIEDD 4256 CALL R3 I DETERMINE BYTE POSITION OF THE DOT
F434 02£8 4257 SHR AL,CL I SHIFT TO SET UP THE BITS FOR OUTPUT
F436 22C4 4256 AND Al,AH I STRIP OFF THE OTHER BITS
F438 268AOC 4259 HOY Cl,ES:[SIJ ; GET THE CURRENT BYTE
F438 58 4260 POP BX ; RECOVER XOR FLAG
F43C F6C380 4261 TEST BL,80H ; IS IT ON
A-60 System BIOS

LOC OBJ LINE SOURCE
F43F 7500 4262 JHZ 02 ; YES. XOR THE DOT

F441 F6D4 4263 NOT AH , SET THE MASK TO REMOVE THE
F443 22ce 4264 ANO el.AH I INDICATED BITS
F445 OAel 4265 OR AL.CL ; OR IN THE NEW VALUE OF THOSE BITS
F447 4266 Rl: 1 F !NISH_OOT
F447 268804 4267 MOV Es:[srl,AL , RESTORE THE BYTE IN MEMORY
F44A 58 4266 POP AX
f44B E977FD 4269 JMP YIDEO_RETURN ; RETURN FROt1 VIDEO ID
F44E 4270 R2:: I XOR_DOT
F44E 32Cl
F450 EBFS
4271
4272
XOO
JMP .,
Al.Cl EXCLUSIVE OR THE DOTS
I FINISH UP THE WRITING
4273 WRITE_DOT ENOP
4274 ; ------------------------------------------ --------------
4275 ; THIS SUBROUTINE DETERMINES THE REGEN BYTE LOCATION
4276 ; OF THE INDICATED ROW COLUMN VALUE IN GRAPHICS MODE.
4277 ENTRY --
4278 OX = ROW VALUE (0-199)
4279 CX = COLUMN VALUE (0-639)
4260 EXIT --
4281 SI = OFFSET INTO REGEN BUFFER FOR BYTE OF INTEREST
4282 AH = MASK TO STRIP OFF THE BITS OF INTEREST
4263 Cl = BITS TO SHIFT TO RIGHT JUSTIFY THE MASK IN AH
4284 DH =# BITS IN RESULT
4285 ; --------------------------------------------------------
F452 4286 03 PROC NEAR
F452 53 4287 PUSH BX ; SAVE BX DURING OPERATION
F453 SO 4286 PUSH AX ; WILL SAVE AL DURING OPERATION
4289
4290 ; ----- DETERMINE 1ST BYTE IN IOICATEO ROW BY NULTIPL YING ROW VALUE BY 40
4291 1----- ( lOW BIT OF ROW DETERMINES EVEN/ODD, 80 BYTES/ROW
4292
F454 B028 4293 MaV AL,40
F456 52 4294 PUSH OX i SAVE ROW VALUE
F457 BOE2FE 4295 ANO OL,OFEH I STRIP OFF ODD/EVEN BIT
F45A f6E2 4296 MUL DL ; AX HAS ADDRESS OF 1ST BYTE
4297 , OF INDICATED ROW
F45C 5A 4298 POP OX ; RECOVER IT
F450 F6ClOI 4299 TEST DL.t ; TEST FOR EVEN/ODD
F460 7403
F462 050020
4300
4301
J2
ADO
'4
AX,2000H
I JlJMp IF EVEN ROW
I OFFSET TO LOCATION OF 000 ROWS
F465 4302 R4: I EVEN_ROW
F465 SBFO 4303 MOV SI,AX ; MOVE POINTER TO SI
F467 58 4304 POP AX j RECOVER AL VALUE
F468 8BOl 4305 MOV OX,CX 1 COLUMN VALUE TO OX
4306
4307 j----- DETERMINE GRAPHICS MOOE CURRENTLY IN EFFECT
4308
4309 i ----------------------------------------------------------------
4310 ; SET UP THE REGISTERS ACCORDING TO THE MODE
4311 CH = MASK FOR LOW OF COLUMN ADDRESS ( 7/3 FOR HIGHIHED RES)
4312 CL = # OF ADDRESS BITS IN COLUMN VALUE ( 312 FOR HIM)
4313 BL = MASK TO SELECT BITS FROM POINTED BYTE (80H/COH FOR HIM)
4314 BH = NUHBER OF VALID BITS IN POINTED BYTE ( 112 FOR H/M)
4315 1----------------------------------------------------------------
4316
F46A BBC002 4317 MOV BX.2COH
F460 690203 4318 MOV CX,302H ; SET PARMS FOR MED RES
F470 603E490006 4319 CMP CRT_MODE.6
F475 7206 4320 JC .S i HANDLE IF MED ARES
F477 BB8001 4321 MOV BX,180H
F47A 690307 4322 MaV CX,703H 1 SET PARMS FOR HIGH RES
4323
4324 j----- DETERMINE BIT OFFSET IN BYTE FROM COLUMN MASK
4325
F47D 4326 R5:
F47D 2lEA 4327 ANO CH.oL i AODRESS OF PEL WIntIN BYTE TO CH
4328
4329 1----- DETERMINE BYTE OFFSET FOR THIS LOCATION IN COLUMN
4330
F47F D3EA 4331 SH. OX,CL i SHIFT BY CORRECT AMOUNT
F481 03F2 433Z AOO SI,DX J INCREMENT THE POINTER
F483 BAF7 4333 MaV DH,BH j GET THE # OF BITS IN RESULT TO DH
4334
4335 ;----- tlULTIPLY BH (VALID BITS IN BYTEI BY CH (BIT OFFSET)
4336
F485 2AC9 4337 SUB CL.CL ; ZERO INTO STORAGE LOCATION
F487 4338 R6:
System BIOS A-61

LOC OBJ LINE SOURCE
F487 00C6 4339 ROR U.I I lEFT JUSTIFY THE VALUE

4340 I IN AL (FOR WRITE)
F489 02tO 4341 ADO CL,CH ; ADD IN THE BIT OFFSET VALUE
F48B HeF 4342: DEC BH ; LOOP CONTROL
F48D 75F8 4343 JHZ R' J ON EXIT. CL HAS SHIFT COUNT
4344 I TO RESTORE BITS
F48F 8AE3 4345 MOV AH,BL ; GET MASK TO AH
F491 D2EC 4346 SHR AH,Cl ; MOVE THE MASK TO CORRECT LOCATION
F493 58 4347 POP BX I RECOVER REG
F494 C3 4348 RET ; RETURN WITH EVERYTHING SET UP
4349 R3 ENDP
4350 ; ----------------------------------------------------------------
4351 j SCROLL UP
4352 THIS ROUTINE SCROLLS UP THE INFORMATION ON THE CRT
4353 ; ENTRY
4354 CH.eL = UPPER LEFT CORNER OF REGION TO SCROLL
4355 OH.DL = LOWER RIGHT CORNER OF REGION TO SCROLL
4356 BOTH OF THE ABOVE ARE IN CHARACTER POSITIONS
4357 BH = FILL VALUE FOR BLANKED LINES
4358 AL = # LINES TO SCROLL I AL=O MEANS BLANK THE ENTIRE
4359 FIElD)
4362 EXIT
4363 NOTHING. THE SCREEN IS SCROLLED
4364 ; ------- - ------------------ ------------------- -------------------
F495 4365 GRAPHICS_UP PROC NEAR
F495 8ADe 4366 MOV BL,AL ; SAVE LINE COUNT IN BL
F497 BSCI 4367 MOV AX.CX ; GET UPPER LEFT POSITION INTO AX REG
4368
4369 j----- USE CHARACTER SUBROUTINE FOR POSITIONING
4370 ; ----- ADDRESS RETURNED IS MULTIPLIED BY 2 FROM CORRECT VALUE
4371
F499 E86902 4372
F49C B8fe 4373 MOV DI.AX ; SAVE RESULT AS DESTINATION ADDRESS
4374
4375 j----- DETERMINE SIZE OF WINDOW
4376
F49E 2BOI 4377 SUB DX,CX
F4AO 81t20101 4378 ADO DX,IOIH ; AOJUST VALUES
F4A4 00E6 4379 SAL OH,I ; MULTIPLY 11 ROWS BY 4
4380 SINCE 8 VERT DOTS/CHAR
F4A6 00E6 4381 SAL OH,1 j AND EVEN/ODD ROWS
4382
4383 ;----- DETERMINE CRT MODE
4384
F4A8 803E490006 4385 eMP ; TEST FOR MEDIUM RES
f4AD 7304 4386 JHe ; FIND_SOURCE
4387
4388 ; ----- MEDIUM RES UP
4389
F4AF 00E2 4390 SAL Old ; 11 COllJMNS * 2. SINCE 2 BYTES/CHAR
F4Bl 01E7 4391 SAL 01 tl ; OFFSET *2 SINCE 2 BYTES/CHAR
4392
4393 j----- DETERMINE THE SO\.JRCE ADDRESS IN THE BUFFER
4394
F4B3 4395 R7: ; FINO_SOI../RCE
F4B3 06 4396 PUSH ES I GET SEGMENTS BOTH POINTING TO REGEN
F4B4 IF 4397 POP OS
F4B5 2:AEO 4398 SUB CH.CH ; ZERO TO HIGH OF COUNT REG
F4B7 DOE3 4399 SAL Bl.l j MULTIPLY NUMBER OF LINES BY 4
F4B9 DOE3 4400 SAL BL.l
F4BB 742:0 4401 JZ R11 ; IF ZERO. THEN BLANK ENTIRE FIELD
F4BD BAC) 4402 MOV Al.Bl ; GET NUMBER OF LINES IN AL
F4BF 8450 4403 MOV AH.80 ; 80 BYTESIROW
F4Cl F6E4 4404 MUL AH I DETERMINE OFFSET TO SOURCE
F4C3 BBF7 4405 MOV SI,DI I SET UP SOURCE
F4C5 03FO 4406 ADO SI.AX , AOD IN OFFSET TO IT
F4C7 8AE6 4407 MOV AH.DH ; NUMBER OF ROWS IN FIELD
F4C9 ZAn 4408 SUB AH.BL ; DETERMINE NUMBER TO HOVE
4409
4410 1----- lOOP THROUGH. MOVING ONE ROW AT A TIME. BOTH EVEN AND ODD FIELDS
4411
F4CB 4412 R8:
F4CB E88000 4413 CALL IH 7 ; MOVE ONE ROW
F4CE 81EEBOIF 4414 SUB SI. 2000H-80 I MOVE TO NEXT ROW
F402: 81EFBOIF 4415 SUB DI.2000H-80
A-62 System BIOS

LOC OBJ LINE SOURCE
F4D6 FEee 4416 DEC .H j NUteER OF ROWS TO HOVE

F408 75Fl 4417 JNZ R. ; CONTINUE TILL ALL MOVED
4416
4419 J----- FILL IN TlfE VACATED LINE(S)
4420
F4DA 4421 R9: • CLEAR_ENTRY
F4DA BAC7 4422 HOV Al.BH ; ATTRIBUTE TO FIll WIlli
F40C 4423 RIO:
F4DC E88800 4424 CALL RIB ; CLEAR TlIAT ROW
F40F 8lEFBOIF 4425 SUB DI.20DCH-BO ; POINT TO NEXT LINE
F4E3 FEte 4426 DEC BL ; NUMBER OF LINES TO FILL
F4E5 7SF5 4427 JHZ RIO ; CLEAR_LOOP
F4E7 E908Ft 4428 JMP VIDEO_RETURN ; EVERYTHING DONE
F4EA 4429 Rll: ; BLANKJIELD
F4EA 8ADE 4430 HOV Bl.OH i SET BLANK COlNT TO
4431 ; EVERYTHING IN fIELD
F4EC EBEe 4432 R. ; CLEAR TliE fIELD
4433 EHOP
4434 ; - - - - - - - - ------- - - ----- -- - ---------------- -- - - - -- -- -- ---- - - - - - ---
4435 ; SCROLL DOWN
4436 THIS ROUTINE SCROLLS 0010I-I TliE INfORMATION ON THE CRT
4437 ENTRY
4438 CH,CL '" UPPER lEFT CORNER OF REGION TO SCROll
4439 DH.Dl = LOWER RIGHT CORNER OF REGION TO SCROLL
4440 BOTH OF THE ABOVE ARE IN CHARACTER POSITIONS
4441 BH = FILL VALUE FOR BLANKED LINES
4442 AL = • LINES TO SCROLL (AL=O MEANS BlANK THE ENTIRE
4443 FIELD I
4446 ; EXIT
4447 NOTHING. THE SCREEN IS SCROLLED
4448 ; ----------------------------------------------------------------
F4EE 4449 GRAPHICS_DOWN PROC NEAR
f4EE FO 4450 STD ; SET DIRECTION
F4EF BADe 4451 MOV BL.AL ; SAVE LINE COUNT IN BL
F4F 1 8Be2 4452 HOV AX.DX ; GET LOWER RIGHT POSITION INTO AX REG
4453
4454 ; ----- USE CHARACTER SUBROUTINE FOR POSITIONING
4455 ;----- ADDRESS RETURNED IS MULTIPLIED BY 2 FROH CORRECT VALUE
4456
F4F3 E80F02 4457
F4F6 8BFe 4458 HOV OI.AX I SAVE RESULT AS DESTINATION ADDRESS
4459
4460 ; ----- DETERMINE SIZE OF WINDOW
4461
F4F8 2:BOl 4462 SUB OX.CX
r4FA 81C20101 4463 ADD DX,10lH ; ADJUST VALUES
f4FE 00E6 4464 SAL DH.I ; MULTIPLY. ROWS BY 4
4465 SINCE 8 VERT DOTS/CHAR
F500 00E6 4466 SAL DH.1 ; AND EVEN/ODD ROWS
4467
4468 ;----- DETERMINE CRT HOOE
4469
F502 803E490006 4470 CHP ; TEST FOR HEDIlI1 RES
F507 7305 4471 JNC ; FItI)_~CE_O~
4472
4473 ;----- MEDIUM RES DOWN
4474
F509 00E2 4475 SAL OLd ; • COLlJ'flS * 2. SINCE
4476 ; 2 BYTES/CHAR (OFFSET OK I
F50B DIE7 4477 SAL 01.1 ; OFFSET *2 SINCE 2 BYTES/CHAR
F50D 47 4478 INC 01 ; POINT TO LAST BYTE
4479
4480 ; ----- DETERMINE THE SOURCE ADDRESS IN THE BUFFER
4481
F50E 4482 R12: ; FIND_SOURCE_D~
f50E 06 4483 PUSH ES ; BOTH SEGHENTS TO REGEN

FSOF IF 4484 POP OS
F510 UEO 4485 SUB CH.CH ; ZERO TO HIGH OF COUNT REG
F512 81C7FOOO 4486 ADD 01.240 ; POINT TO LAST ROW OF PIXE LS
F516 Don 4487 SAL BLol ; ttULTIPlY NUMBER OF LINES BY 4
F518 Don 4488 SAL BL.I
f5lA 742:E 4489 JZ R,. i IF ZERO. TliEN BUNK ENTIRE FIELD
F5lC 8AC3 4490 HOV AL.Bt i GET NUt1BER OF LINES IN AL
F51E 8450 4491 HOV AN.80 ; 80 BYTES/ROW
F52:0 F6E4 4492 "'L AN J DETERMINE OFFSET TO SOURCE
System BIOS A-63

LOC OBJ LINE SOURCE
FS22 SBF7 4493 MOV SI,OI I SET UP SOURCE

F524 2BFO 4494 SUB SI,AX I SUBTRACT THE OFFSET
F526 8AE6 4495 MOV AH,DH I NUNBER OF ROWS IN FIELD
F528 2AE3 4496 SUB AH.Bl I DETERMINE NUMBER TO MOVE
4497
4498 ;----- lOOP THROUGH, HOVING ONE ROW AT A TIME, BOTH EVEN AND 000 FIELDS
4499
F52A 4500 R13: J ROW_lOOP_DOWN
F52A E82100 4501 CAll "7 ; MOVE ONE ROW
F52D 81EE5020 450Z SUB 51.2000H+80 I MOVE TO NEXT ROW
F531 SlEF5020 4503 SUB DI,2000H-teO
F535 FEee 4504 DEC AH ; HUMBER OF ROWS TO HOVE
F537 75Fl 4505
4506
JHZ
." I CONTINUE TILL ALL HOVED
4507 j----- FILL IN THE VACATED LINEIS)

4508
F539 4509 R14: I CLEAR_ENTRY_DOWN
F539 8AC7 4510 MOV Al,BH ; ATTRIBUTE TO FILL WITH
F53B 4511 R15: ; CLEAR_lOOP_DOWN
F53B £82900 4512 CALL "8 ; CLEAR A ROW
FS3E 81EF5020 4513 SUB DI.2000H+80 ; POINT TO NEXT LIHE
FS42 FECB 4514 DEC BL ; NUNBER OF LINES TO FILL
F544 75FS 4515 JHZ R'S I CLEAR_lOOP_DOWN
F546 FC 4516 CLD ; RESET THE DIRECTION FLAG
F547 E918FC 4517 JHP VIDEO_REn.JI:;!N ; EVERYTHING DONE
F54A 4518 R16: ; BlANKJIELO_DOWN
F54A SADE 4519 MOV BL.DH ; SET BLANK COUNT TO
4520 ; EVERYTHING IN FIElD
F54C EBES 4521 JHP R'4 I CLEAR THE FIELD
452:2: GRAPHICS_DOWN ENDP
452:3
4524 1----- ROUTINE TO MOVE ONE ROW OF INFORNATION
4525
F54E 4526 R'7 PRDC NEAR
F54E 8AC,., 4527 MOV CL.Ol ; NUMBER OF BYTES IN THE ROW
F550 56 4528 PUSH 51
F551 57 4529 PUSH 01 ; SAVE POINTERS
F552 F3 4530 REP MOVSB ; NOVE THE EVEN FIElD
F553 A4
FS54 SF 4531 POP 01
F555 5E 4532 PDP 51
F556 81C600Z0 4533 ADD SI.ZOOOH
F55,., 81C70020 4534 ADD OI.ZOOOH I POINT TO THE ODD FIELD
F55E 5b 4535 PUSH 51
F55F 57 453b PUSH 01 ; SAVE THE POINTERS
F560 8ACA 4537 HOV CL.OL ; COUNT BACK
F562 F3 4538 REP Novse ; MOVE THE ODD FIELD
F5b3 A4
F564 SF 4539 PDP 01
F565 5E 4540 POP 51 ; POINTERS BACK
F5b6 C3 4541 RET ; RETURN TO CAlLER
4542 .17 ENDP
4543
4544 ; ----- CLEAR A SINGLE ROW
4545
F567 4546 "8 ""DC NEAR
F567 8ACA 4547 HDV Cl.OL I NUMBER OF BYTES IN FIELD
F569 57 4548 PUSH 01 ; SAVE POINTER
F56,., F3 4549 REP STOSB ; STORE THE NEW VALUE
F56B AA
F56C SF 4550 POP 01 ; POINTER BACK
F56D 81C70020 4551 ADD oI.2000H ; POINT TO ODD fIELD
f571 57 4552 PUSH 01
f57Z 8ACA 4553 HOV CL.OL
f574 F3 4554 REP STOSS FILL THE ODD fIlELo
F575 AA
F576 SF 4555 POP 01
F577 C3 4556 RET I REn.JI:;!N TO CAlLER
4557 "8 ENDP
4558 ;----------------------------------------------------------------
4559 ; GRAPHICS WRITE
4560 THIS ROUTINE WRITES THE ASCII CHARACTER TO THE
4561 CURRENT POSITION ON THE SCREEN.
4562 ; ENTRY
4563 At = CHARACTER TO WRITE
4564 BL = COLOR ATTRIBUTE TO BE USED FOR fOREGROUND COLOR
4565 IF BIT 7 IS SET. THE CHAR IS XOR '0 INTO THE REGEN
A-64 System BIOS

LaC OBJ LINE SOURCE
4566 BUFFER (0 IS USED FOR THE BACKGROlrnD COLOR I

4567 ex = NUMBER OF CHARS TO WRITE
4570 ; EXIT
4571 NOTHING IS RETURNED
4572
4573 ; GRAPHICS READ
4574 THIS ROUTINE READS THE ASCII CHARACTER AT THE CURRENT
4575 CURSOR POSITION ON THE SCREEN BY MATCHING THE DOTS ON
4576 THE SCREEN TO THE CHARACTER GENERATOR CODE POINTS
4577 ; ENTRY
4578 NONE ( 0 IS ASSUMED AS THE BACKGROUND COLOR
4579 ; EXIT
4580 AL = CHARACTER READ AT THAT POSITION (0 RETURNED IF
4581 NONE FOUND)
4582
4583 FOR BOTH ROUTINES, THE IMAGES USED TO FORM CHARS ARE
4584 I CONTAINED IN ROM FOR THE 1ST 128 CHARS. TO ACCESS CHARS
4585 I IN THE SECOND HALF, THE USER MUST INITIALIZE THE VECTOR AT
4586 INTERRUPT IFH (LOCATION 0007CH J TO POINT TO THE USER
4587 SUPPLIED TABLE OF GRAPHIC IMAGES (8XS BOXES).
4588 FAILURE TO DO SO WILL CAUSE IN STRANGE RESULTS
4589
4590 ASSUME CS:COOE,OS:DATA.ES:oATA
F578 4591 GRAPHICS_WRITE PROC NEAR
F57S 6400 4592 MOV AH ,0 ; ZERO TO HIGH OF CODE POINT
F57A 50 4593 PUSH AX I SAVE CODE POINT VALUE
4594
4595 1----- DETERMINE POSITION IN REGEN BUFFER TO PUT CODE POINTS
4596
F57B E88401 4597 CALL S26 I FIND LOCATION IN REGEN BUFFER
F57E S8F8 4598 NOV oI.AX ; REGEN POINTER IN or
4599
4600 ;----- DETERMINE REGION TO GET CODE POINTS FROM
4601
F580 58 4602 pop AX ; RECOVER CODE POINT
F581 3eso 4603 OMP AL.SOH I IS IT IN SECOND HAlF
F583 7306 4604 JAE SI ; YES
4605
4606 1----- IMAGE IS IN FIRST HALF. CONTAINED IN ROM
4607
f585 BE6EF ... 4608 HOV 5I.DFA6EH
F588 OE 4609 PUSH CS ; SAVE SEGMENT ON STACK
f589 EBOF 4610 JMP SHORT 52:
4611
4612 ;----- IMAGE IS IN SECOND HALF, IN USER RAM
4613
F588 4614 51: ; EXTEND_CHAR
F58B 2.C80 4615 SUB AL,SDH ; ZERO ORIGIN FOR SECOND HALF
F580 1 E 4616 PUSH DS ; SAVE DATA POINTER
F58E 2BF6 4617 SUB SI,SI
F590 BEOE 4618 MOV oS,SI ; ESTABLISH VECTOR ADDRESSING
4619 ASSUME oS:AB50
F592 C5367eoo 4620 lDS SI,EXT_PTR ; GET THE OFFSET OF THE TABLE
FS96 eCDA 4621 MOV OX,OS ; GET THE SEGMENT OF THE TABLE
4622 ASSUME DS:oATA
F598 IF 4623 POP DS I RECOVER DATA SEGMENT
F599 52 4624 PUSH DX ; SAVE TABLE SEGMENT ON STACK
4625
4626 ;----- DETERMINE GRAPHICS HOOE IN OPERATION
4627
F59A 4628 S2: I DETERMINE_MODE
f59A DIED 4629 SAL AX,! ; MULTIPLY CODE POIHT
FS9C DIED 4630 SAL AX,! ; VALUE BY 8
F59E 0 lEO 4631 SAL AX,l
F5AO 03FO 4632 ADD SI,AX I 51 HAS OFFSET OF DESIRED CODES
FSA2 e03E490006 4633 OMP CRT_MODE ,6
FSA7 IF 4634 POP DS j RECOVER TABLE POINTER SEGMENT
F5AS 7Z2C 4635 JO S7 ; TEST fOR MEDIUM RESOLUTION MODE
4636
4637 ;----- HIGH RESOLUTION MODE
4638
FSAA 4639 53: ; HIGH_CHAR
fSAA 57 4640 PUSH 01 ; SAVE REGEN POINTER
F5AB 56
FSAC 8604 ....
4641 PUSH
HOV
51
oH,4
; SAVE CODE POItITER
I NUMBER OF TIMES THROUGH LOOP
System BIOS A-65

LOC OBJ LINE SOURCE
F5AE 4643 54.

F5AE AC
F5AF F6C380
"44
lt6lt5
LOOse
TEST BL,SDH
I GET BYTE FROH CODE POINTS
I SHOULD WE USE THE FUNCTION
F582 7516 4646 JHZ 56 I TO PUT CHAR IN
F584 AA 4647 STOSB I STORE IN REGEN BUfFER
f585 At 4648 LOOSS
F586 4649 55'
FSB6 268885FFlF 4650 HOY ES:[DI+2DDOH-IJ,AL ; STORE IN SECCHJ HAlF
FSBB 83C74F . .51 ADD bI , 79 I MOVE TO NEXT ROW IN REGEN
F5BE FEtE 4652 DEC OH I DONE WITH LOOP
FSCO 75Et 4653 JNZ 54
FSC2 5£ 4654 PDP 51
f5C3 SF 4655 pop OI I RECOVER REGEN POINTER
FSC4 47 4656 INC Ot ; POINT TO NEXT CHAR POSITION
F5C5 E2£3 4657 LOOP 53 ~ MORE CHARS TO WRITE
F5C7 E9FBFB 4658 JHP

FSCA 4659 56;
fStA 263205 4660 XOR Al,ES:[DIJ I EXClUSIVj: OR WITH CURRENT
F5CD AA 4661 STOS8 ; STORE THE CODE POINT
FSCE At 4662- loosB ; AGAIN FOR DO~ FIELD
FSCF 263285FFIF 4663 XOR Al,ES: 101+2000H-11
F5D4 fBED 4664 JHP 55 J BACK TO HAINSTREAH
4665
4666 ;----- ttEDIlJ1 RESOLUTION WRITE
F~6
F506 8AD3
....
4667
4669
57:
HOY CL.St I SAVE HIGH COLOR BIT
F5De DIE7 4670 SAL 01,1 j OFFSET*2 SINCE 2 BYTEs/CHAR
F5DA £8Dl00 4671 CAll 519 ; EXPAND BL TO FULL WORD OF COLOR
FSDD 4672 58: I MED_CHAR
FSDD 57 4673 PUSH DI ; SAVE REGEN POINTER
FSDE 56 4674 PUSH 51 ; SAVE THE CODE POINTER
F5Df 8604 4675 i10V OH.4 ; NUMBER OF LOOPS
F5El 4676 59:
F5El At 4677 Loose I GET CODE POINT
FSE! E8DEOa 4678 CALL 521 J DOUBLE UP ALL THE BITS
F5£5 23C3 4679 AND AX,BX ; CONvERT THEM TO FOREGRotHJ
4680 ; COLOR ( 0 BACK )
F5£7 F6C280 4681 TEST Dt,eOH ; IS THIS XOR FUNCTION
F5E'" 7407 4682 ; NO. STORE IT IN AS IT IS
....
JZ 510
F5EC 263225 4683 XOR AH.~S:[DI1 ; DO FUNCTION WITH HALF
FSEF 26324501 XOR AL,ES:[DI+ll ; AND WITH OTHER HALF
F5F3 4685 SID:
FSn 268825 4686 ttOV ES:[OIJ.AH J STORE FIRST BYTE
F5F6 26864501 4687 t10V ES:[OI+1J ••U ; STORE SECOND BYTE
FSf" At 4688 LODse I GET CODE POINT
F5fS E8C500 4689 CAll 521
F5FE 2.le3 4690 AND AX,8X J CONVERT TO COLOR
F600 F6C280 4691 TEST Dl,80H I AGAIN, IS THIS XOR FUNCTION
F603 740A 4692 JZ 511 ; NO. JUST STORE TME VALUES
F605 2632 ...5002:0 4693 XOR AH,ES:[OI+2:000H1 J FUNCTION WITH FIRST HALF
F60 ... 2632850120 4694 XOR AL,ES:[OI+2001HJ J At«) WITH SECOND HALF
F60F 4695 Sl1:
F60F 2688AS0020 4696 HOY ES: (OI+2000Hl,AH
F614 2688650120 4697 HOV ES:loI+2000H+ll,Al J STORE IN SECOND PORTION OF BUFFER
F619 83C750 4698 ADD 01,80 ; POINT TO NEXT LOCATION
F61C FEtE 4699 DEC DH
F61E 7SCI 4700 JNz S9 ; KEEP GOING
F620 5£ 4701 pop SI J RECOVER CODE PONTER
F621 SF 4702 pop 01 ; RECOVER REGEN POINTER
F622 47 4703 INC DI J POINT TO NEXT CHAR POSITION
F623 47 4704 INc DI
F624 £287 4705 LOOP S8 ; MORE TO tRITE
F626 E99CFB 4706 JHP
4707 GRAPHICS_~iTE ENDP
4706 j----':"'-------------------
4709 I GRAPHICS READ
4710 J .. -----------------------
F629 4711 GRAPHICS_READ PROt NEAR
F629 £80600 4712 CALL S26 I CONVERTED TO OFFSET IN REGEN
F62C 88FO 4713 I10V SI,AX I SAVE IN SI
F62.£ 83Eeoe 4714 SUB SP,8 ; AlLOCATE SPACE to SAVE THE
4715 I READ CODE POINT
F631 8BEt 4716 MOV BP,SP J POINTER TO SAVE AREA
4717
4718 1----- DETERMINE GRAPHICS HODES
4719
A-66 System BIOS

LaC OBJ LINE SOURCE
F631 &03E490006 4720 CHP

F638 06 4721 PUSH ES
F639 IF 4722 POP OS I POINT TO REGEN SEGMENT
F63A nu 4723 JC 513 J MEOIUtt RESOLUTION
4724
4725 J----- HIGH RESOLUTION READ
4726
4727 1----- GET VALUES FROM REGEN BUFFER AND CONVERT TO CODE POINT
4728
F63C 8604 4729 MOV OH,4 ; NUttBER OF PASSES
F63E 4730 512:
F63E 6,6,04 4731 MOV AL.ISI J I GET FIRST BYTE
F640 884600 4732 HOV [BP),AL ; SAVE IN STORAGE AREA
F643 45 4133 INC BP I NEXT LOCATION
F644 6A840020 4734 HOV Al,[SI+2000Hl I GET LOWER REGION BYTE
F648 884600 4735 MOV (BP),AL ; ADJUST AND STORE
F64B 4S 4736 INC BP
F64C 63C650 4737 ADO 51.80 J POINTER INTO REGEN
F64F FEtE 4738 DEC DH ; LOOP CONTROL
F651 75E6 4739 JNZ 512 ; DO IT SOME MORE
f653 E81790 4740 JMP 515 I GO MATCH THE SAVED CODE POINTS
4741
4742 ;----- MEDIUH RESOLUTION READ
4743
F656 4744 513:
F656 01E6 4745 SAL 51,1 I OFFSET*2 SINCE 2 BYTES/CHAR
F658 5604 4746 MOV OH,4 ; NUMBER OF PASSES
F65A 4747 514:
F65A E88800 4748 CALL 523 I GET PAIR BYTES FROM REGEN
4749 i INTO SINGLE SAVE
F650 81t60020 4750 ADD 51, 2000H ; GO TO LOWER REGION
F661 E88100 4751 CALL 523 ; GET THIS PAIR INTO SAVE
F664 81EEBOlf 4752 SUB 51, 2000H-80 ; ADJUST POINTER BACK INTO UPPER
f668 FECE 4753 DEC OH
F66A 75EE 4754 JNZ 514 ; KEEP GOING UNTIL ALL 8 DONE
4755
4756 ;----- SAVE AREA HAS CHARACTER IN IT. HATCH IT
4757
FMC 4758 515: ; FIND_CHAR
F66C BF6EFA90 4759 MOV DI.OFFSET CRT_CHAR_GEN J ESTABLISH ADDRESSING
f670 DE 4760 PUSH CS
F671 07 4761 POP ES I CODE POINTS IN CS
F672 83E008 4762 SUB BP,8 ; ADJUST POINTER TO BEGINNING
4763 OF SAVE AREA
f675 BBFS 4764 MOV SI,BP
F677 Fe 4765 CLO ENSURE DIRECTION
F678 BODO 4766 MOV Al,O I CURRENT CODE POINT BEING MATCHED
F67A 4767 SI6:
F67A 16 4768 PUSH 55 ; ESTABLISH ADDRESSING TO STACK
f67B IF 47&9 POP DS ; F,OR THE STRING COMPARE
F67C BA8000 4770 MaV OX,128 ; NUMBER TO TEST AGAINST
F67F 4771 517:
F67F 56 4772 PUsH 51 I SAVE SAVE AREA POINTER
F680 57 4773 PUSH DI ; SAVE CODE POINTER
F661 890800 4774 MOV CX,8 I NUMBER OF BYTES TO HATCH
F684 F3 4775 REPE CMPSB I COMPARE THE 8 BYTES
F685 A6
F68b SF 4776 POP 01 I RECOVER THE POINTERS
f687 SE 4777 POP 51
F686 741E 4778 JZ 518 ; IF ZERO FLAG SET, THEN MATCH OCCURRED
F66A FEtD 4779 INC AL I NO MATCH, MOVE ON TO NEXT
fMC 63C706 4780 ADO DI,8 ; NEXT CODE POINT
F68F 4A 4781 DEC ox I LOOP CONTROL
F690 75EO 4782 JHZ 517 ; DO ALL OF THEM
4783
4784 ;----- CHAR NOT MATCHED, MIGHT BE IN USER SUPPLIED SECOND HALF
4785
F692 3COO 4786 CMP Al,O ; Al <> 0 IF ONLY IS" HALF SCANNED
F694 7412 4787 J' 518 I IF = 0, THEN ALL HAS BEEN SCANNED
F696 2BCO 4788 SUB AX,AX
F696 6E06 4789 HOV OS,AX ; ESTABLISH ADDRESSING TO VECTOR
4790 ASSutlE as: ABSO
F69A C43E7COO 4791 LES DI,EXT_Pl'R ; GET POINTER
F69E 8ceo 4792 HOV AX,ES , SEE IF THE POINTER REAllY EXISTS
f6AO OBC7 4793 OR AX,OI ; IF ALL 0, THEN DOESN'T EXIST
F6A2 7404 4794 JZ 518 ; NO SENSE LOOKING
F6A4 B080 4795 MOV Al,128 I ORIGIN FOR SECotI) HALF
System BIOS A-67

LOC OBJ LINE SOURCE
FbA6 EBOZ 4796 JMP 51. J GO BACK AND TRY FOR IT

4797 ASSUME DS:DATA
4798
4799 ;----- CHARACTER IS FOUND ( Al=D IF NOT FOUND I
4600
F6A8 4801 S18:
F6A8 83C408 4802 ADO SP.8 ; READJUST THE STACK. THROW AWAY SAVE
F6AB E917FB 4803 JMP VIDEO_RETURN ; ALL DONE
4804 GRAPHICS_READ ENDP
4805 ; --------------------------------------------------------
4806 EXPAND_MED_COLOR
4807 THIS ROUTINE EXPANDS THE LOW 2: BITS IN Bl TO
4808 FILL THE ENTIRE BX REGISTER
4809 ENTRY
4810 BL = COLOR TO BE USED ( LOW 2 BITS )
4811 ; EXIT
4812 BX = COLOR TO BE USED ( 8 REPLICATIONS OF THE
4813 2 COLOR BITS J
4814 i --------------------------------------------------------
FbAE 4815 519 PROC NEAR
F6AE 60E303 4816 AND BL.3 i ISOLATE THE COLOR BITS
F6BI 8AC3 4817 MOV AL,BL ; COPY TO AL
F6B3 51 ex ; SAVE REGISTER
F6B4 690300 4819 MOV CX.3 ; HUMBER OF TIMES TO DO THIS
f6B7 4820 S20:
F6B7 ODED 4821 SAL AL,1
F6B9 ODED 4822 SAL AL,1 ; LEFT SHIFT BY 2
F6BB OA08 4823 OR BL.AL ; ANOTHER COLOR VERSION INTO BL
FbBD E2F8 4824 LOOP 520 ; FILL ALL OF BL
F6BF SAFB 4825 HOV BH.BL j FILL UPPER PORTION
F6CI 59 4826 POP ex ; REGISTER BACK
FoC2 C3 RET j ALL DONE
4828 S19 ENDP
4829 j --------------- -------------------------- --- ------------
4830 EXPAND_BYTE
4831 THIS ROUTINE TAKES THE BYTE IN AL AND DOUBLES
4832 ALL OF THE BITS, TURNING THE 8 BITS INTO
4833 16 BITS. THE RESULT IS LEFT IN AX
4634 j--------------------------------------------------------
F6e} 4835 521 PROC NEAR
F6e3 52 4836 PUSH ox I SAVE REGISTERS
F6C4 51 4837 PUSH ex
F6es 53 4638 PUSH BX
F6C6 lBOZ 4839 SUB OX,OX ; RESULT REGISTER
Foes 690100 4840 MOV CX,1 j MASK REGISTER
F6eB 4841
F6te SBD8 4842 MOV BX,AX i BASE INTO TEMP
F6CD 2309 4843 AND BX,CX ; USE MASK TO EXTRACT A BIT
F6CF OB03 4844 OR oX,ex ; PUT IHTD RESULT REGISTER
F601 DIED 4845 5HL AX,!
F603 olEl 4846 SHL CX,1 ; SHIFT BASE ANa MASK BY 1
F6DS 8808 4847 MOV BX,AX ; BASE TO TEMP
F607 2309 4848 AND BX,CX ; EXTRACT THE SAME BIT
F609 0603 4849 OR OX,BX i PUT INTO RESULT
f6DS olEl 4850 5HL CX,l ; SHIFT ONLY MASK NOW,
4851 I MOVING TO NEXT BASE
FoOD 73Et 4652 JNe 522 ; USE MASK BIT COMING OVT TO TERMINATE
F6DF 8BC2 4853 MOV AX,OX ; RESULT TO PARM REGISTER
f6El 58 4854 POP BX
F6E2 59 4855 POP ex ; RECOVER REGISTERS
f6B SA 4856 POP ox
F6E4 C3 4857 RET I ALL DONE
4858 S21 ENDP
4859 ; --------------------------------------------------------
4860 j MED_READ_BYTE
4861 THIS ROUTINE WILL TAKE 2 BYTES FROM THE REGEN
4862 BUFFER, COMPARE AGAINST THE CURRENT FOREGROUND
4863 COLOR, AND PLACE THE CORRESPONDING ON/OFF SIT
4864 PATTERN INTO THE CURRENT POSITION IN THE SAVE
4865 ; AREA
4866 j ENTRY
4867 51,05 = POINTER TO REGEN AREA OF INTEREST
4868 ex = EXPANDED FOREGROUND COLOR
4869 SP = POINTER TO SAVE AREA
4870 j EXIT
4871 SP IS INCREMENT AFTER SAVE
4872 i - --- - - - - - --- -- --- -- - -- ----- -- - - - - - -- ----- ---- --- ----- ---
A-68 System BIOS

LaC OBJ LINE SOURCE
F6ES 4873 S23 PROC NEAR

F6ES 6A24 4874 MOV AH,[SIJ GET FIRST BYTE
F6E7 8A4401 4875 MOV AL,ISI+lJ GET SECOND BYTE
F6EA 8900CO 4876 MaV eX,oeOOOH 2: BIT MASK TO TEST THE ENTRIES
F6ED 8200 4877 MOV altO ; RESULT REGISTER
F6EF 4878 524:
F6EF 65CI 4879 TEST AX,ex l IS THIS SECTION BACKGROI..NJ?
F6FI Fa 4880 CLC ; C LEAR CARRY IN HOPES THAT IT IS
F6F2 7401 4881 JZ 52. ; IF ZERO, IT IS BACKGROUND
F6F4 F9 488Z STC I WASN'T, SO SET CARRY
F6FS 0002 4883 525: RCL QL,l ; HOVE THAT BIT INTO THE RESULT
F6F? 01E9 4884 SHR eX,I
FbF9 DlE9 4885 SHR eX.I ; HOVE THE HASK TO THE RIGHT BY 2: BITS
F6FB 73F2 4886 JNt S24 ; DO IT AGAIN IF MASK DIDN'T FALL OUT
F6FD 885600 4887 MOV [BP1,DL ; STORE RESULT IN SAVE AREA
noD 45 4888 INC BP ; ADJUST POINTER
nOl C3 4889 RET ; ALL DONE
4890 S23 ENOP
4891 I - --- - - - - - - - - - - - - - ----------------- -------- - - - ---
4892 ; V4_POSITION
4893 THIS ROUTINE TAKES THE CURSOR POSITION
4894 CONTAINED IN THE MEMORY LOCATION. AND
4895 CONVERTS IT INTO AN OFFSET INTO THE
4896 REGEN BUFFER, ASSIMING ONE BYTE/cHAR.
4897 FOR MEDIUM RESOLUTION GRAPHICS,
4898 THE NUMBER MUST BE DOUBLED.
4899 ENTRY
4900 NO REGISTERS, MEMORY LOCATION
4901 CURSOR_POSH IS USED
490Z ; EXIT
4903 AX CONTAINS OFFSET INTO REGEN BUFFER
4904 ; ---------------------------- ___________________ _
F702 4905 526 PROC NEAR
F702 10.15000 4906 MOV AX,CURSOR_POSN ; GET CURRENT CURSOR
F105 4907 GRAPH_POSH LABEL NEAR
F705 53 4908 PUSH BX , SAVE REGISTER
F10b 8808 4909 MOV BX,AX ; SAVE A COPY OF ClRRENT C~SOR
F70S 8AC4 4910 MOV AL.AH ; GET ROWS TO AL
F70A f6264AOO 4911 MUL BYTE PTR CIH_COLS ; MULTIPLY BY BYTES/COLIJI'fl
F70E DIED 4912 SHL AX 01 ; MULTIPLY * 4 SINCE 4 ROWS/BYTE
F710 DIED 4913 SHL AX,!
F712 2AFF 4914 SUB BH,BH ; ISOLATE COLlJtt>.I VALUE
F714 03C3 4915 AOO AX,BX ; DETERMINE OFFSET
F716 58 4916 POP BX , RECOVER POINTER
F717 C3 4917 RET ; ALL DONE
4918 526 ENDP
491 9 ; - - - - ---- -- ------- - - - - - - - - - -- --- - ----------------------------------------
4921 THIS INTERFACE PROVIDES A TELETYPE LIKE INTERFACE TO T1iE VIDEO

492Z CARD. WE INPUT CHARACTER IS WRITTEN TO WE CURRENT CURSOR
4923 POSITION. AND THE CURSOR IS MOVED TO THE NEXT POSITION. I f THE
4924 CURSOR LEAVES THE LAST COLUMN OF THE FIELD, THE COLUHN IS SET
4925 TO ZERO, AND THE ROW VALUE IS INCREMENTED. IF THE ROW VALUE
4926 LEAVES THE FIELD, THE CURSOR IS PLACED ON THE LAST ROW. FIRST
4927 COLUMN, AND THE ENTIRE SCREEN IS SCROLLED UP ONE LINE. t&iEN
4928 THE SCREEN IS SCROLLED UP. THE ATTRIBUTE FOR FILLING THE NEWLY
4929 BLANKED LINE IS READ FROM THE CURSOR POSITION ON THE PREVIOUS
4930 LINE BEFORE THE SCROLL, IN CHARACTER MODE. IN GRAPHICS ttODE.
4931 THE 0 COLOR IS USED.
4932 ; ENTRY
4933 (AH) ; CURRENT CRT MOOE
4934 {All = CHARACTER TO BE WRITTEN
4935 NOTE THAT BACK SPACE, CAR RET, BElL AJ.IJ LINE FEED ARE HANllED
4936 AS COHMAHDS RATHER THAN AS DISPLAYABLE GRAPHICS
4937 (Bll = FOREGROUND COLOR FOR CHAR WRITE IF CURRENTLY IN A
4938 GRAPHICS MODE
4939 ; EXIT
4940 ALL REGISTERS SAVED
4941 I - -- ---------- --- - - - - - - - - - - - ---------- - ----------------------------------
4942 ASSUME CS:CODE,DS:DATA
F7la 4943 WRITE_TIV PROC NEAR
F718 50 4944 PUSH AX ; SAVE REGISTERS
F719 50 4945 PUSH AX , SAVE CHAR TO WRITE
F7U 8403 4946 MOV AH,3
F71C 8A3E6200 4947 I10V SH.ACTIVE_PAGE ; GET THE CURRENT ACTIVE PAGE
F720 COlO 4948 INT lOH , READ THE CURRENT CURSOR POSITION
F72:2 58 4'" pop AX ; RECOVER OtAR
System BIOS A-69

LOC OBJ LINE SOURCE
4950
4951 ; ----- OX NOW HAS THE CURRENT CURSOR POSITION
4952-
F723 3e08 4953 CHP AL.a I IS IT A BACKSPACE
F7ZS 7452 4954 JE U8 ; BACK_SPACE
F727 3COO 4955 CHP AL,OOH I IS IT CARRIAGE RETURN
F729 7457 4956 JE U' ; CAR_RET
F72B 3eOA 4957 CMP AL,OAH I IS IT A LINE FEED
F720 7457 4958 JE UIO I LINE3EED
F12F 3C07 4959 CHP Al,07H I IS IT A BELL
F731 745A 4960 JE U11 ; BELL
4961
4962- ;----- WRITE THE CHAR TO THE SCREEN
4963
4964
F733 640.60 4965 NOV AH,10 ; WRITE CHAR ONLY
F735 B90100 4966 MOV eX.l ; ONLY ONE CHAR
F738 COlO 4967 INT 10M ; WRITE THE CHAR
4968
4969 1----- POSITION THE CURSOR FOR NEXT CHAR
4970
F73A FEel 4971 INC DC
F73C 3AI64.6oOO 4972 CMP Dl.BYTE PTR CRT_COLS ; TEST FOR COLUMN OVERFLOW
F740 7533 4973 JNZ U7 ; SET_CURSOR
F742 8200 4974 MOV OL.O ; COLUMN FOR CURSOR
F744 SOFEl6 4975 CMP OH,24
F747 752.60 4976 JNZ U. J SET_CURSOR_INC
4977
4978 ; ----- SCROLL REQUIRED
4979
F749 4980 U1:
F749 B402 4981 MOV AH ,2
F74B COlO 4982 INT 10M j SET THE CURSOR
4983
4984 j----- DETERMINE VALUE TO FILL WITH DURING SCROLL
4985
F74D A04900 498b NOV AL,CRT_MODE I GET THE CURRENT MODE
F7s0 3C04 4987 CMP AL,4
F752 7206 4988 JC U2 j READ-CURSOR
F754 3C07 4989 CMP AL.7
F7s6 B700 4990 MOV BH,O j FILL WITH BACKGROUND
F758 7506 4991 JNE U3 ; SCROll-UP
F75A 4992 U2: ; READ-CURSOR
F75A B408 4993 MOV AH.8
F75C COlO 4994 INT 10M j READ CHAR/ATTR .l.T C~RENT CURSOR
F75E 8AFe 4995 MOV BH,AH I STORE IN BH
F7bO 4996 U3: ; SCROLL-UP
F760 B80106 4997 HOV AX,60lH j SCROLL ONE LINE
F763 2BC9 4998 SUB eX,ex ; UPPER LEFT CORNER
F7bS B618 4999 MOV DH,24 LOWER RIGHT ROW
F767 8A164AOO 5000 MOV DL,BYTE PTR CRT_COLS ; LOWER RIGHT COLUMN
F768 FEeA 5001 DEC DC
F76D 5002 U4: j VIDEO-CALL-RETURN
F7bD COlO 5003 1NT 10M j SCROLL UP THE SCREEN
F7bF 5004 us: j TTY-RETURN
F76F 58 5005 POP AX j RESTORE THE CHARACTER
F770 E952FA 5006 JMP VIDEO_RETURN j RETURN TO CALLER
F773 5007 U6: I SET-CURSOR-INC
F773 FEC6 5008 INC OM j NEXT ROW
F775 5009 U7: ; SET -CURSOR
F775 B402 5010 NOV AH,2
F777 EBF4 SOIl JMP U4 j ESTABLISH THE NEW CURSOR
5012
5013 j ----- BACK SPACE FOUND
5014
F779 5015 U8:
F779 80FAOO 5016 CMP DL,O I ALREADY AT END OF LINE
F77C 74F7 5017 JE U7 I SET_CURSOR
F77E FECA 5018 DEC DC I NO -- JUST HOVE IT BACK
F780 EBF3 5019 JMP U7 I SET_CURSOR
5020
5021 j----- CARRIAGE RETURN FOUND
5022
F782 5023 U9:
F782 B200 5024 "OV DL,O ; MOVE TO FIRST COLUMN
F784 EBEF 5025 JMP U7 ; SET_CURSOR
5026
A-70 System BIOS

LOC OBJ LINE SOURCE
5027 ;----- LINE FEED FOUND

5028
F78b 5029 Uto:
F78b BOFElS 5030 CMP DH.24 I BOTTOM Of SCREEN
F789 75£8 5031 JNE U6 , YES. SCROLL THE SCREEN
F7aB EBBC 5032 JMP Ul ; NO. JUST SET THE CLJi;!SOR
5033
5034 ; ----- Bell FOUNtl
5035
F7eD 5036 Ull:
F78D 8302 5037 MOV BL.G I SET UP COlMT FOR 8EEP
F78f £871EE 5038 CALL BEEP ; SOUND THE POD BELL
F792 EBOB 5039 JMP US ; TTY_RETURN
5040
5041 ; ------- -------- -------------------------------------------------
5042 LIGHT PEN
5043 THIS ROUTINE TESTS THE LIGHT PEN SWITCH AND THE LIGHT
5044 PEN TRIGGER. IF BOTH ARE SET, THE LOCATION OF THE LIGHT:
5045 PEN IS DETERMINED. OTHERWISE. A RETURN WITH NO
5046 INFORMATION IS MADE.
5047 ; ON EXIT
5048 (AH I = 0 IF NO LIGHT PEN INFORMATION IS AVAILABLE
5049 BX.CX.DX ARE DESTROYED
5050 (AH) = 1 IF LIGHT PEN IS AVAILABLE
5051 (DH,oLl = ROW,COLUMN OF CURRENT LIGHT PEN
5052 POSITION
5053 (CH) = RASTER POSITION
5054 (BX) = BEST GUESS AT PIXEL HORIZONTAL POSITION:
5055 1----------------------------------------------------------------
5056 ASSUME CS:COOE.DS:OATA
5057 j----- SUBTRACT_TABLE
F794 5058 VI LABEL BYTE
f794 03 5059 DB
F795 03
f796 05
F797 05
F798 03
F799 03
F79A 03
F79B 04
F79C 5060 PROC NEAR
5061
5062 ;----- WAIT FOR LIGHT PEN TO BE DEPRESSED
5063
F79C 8400 5064 NOV AH,D I SET NO LIGHT PEN RETURN CODE
F79E 88166300 5065 I10V OX.ADOR_6845 ; GET BASE ADDRESS OF 6845
F7A2 83C206 5066 ADD DX.6 ; POINT TO STATUS REGISTER
F7A5 EC 5067 IN AL.DX ; GET STATUS REGISTER
F7Ab A804 5068 TEST AL.4 ; TEST LIGHT PEN SWITCH
F7A8 757£ 5069 JHZ V6 ; NOT SET. RETURN
5070
5071 ;----- NOW TEST FOR LIGHT PEN TRIGGER
5072
F7AA A802 5073 TEST AL,2 ; TEST LIGHT PEN TRIGGER
F7AC 7503 5074 JNZ V7A ; RETURN WITHOUT RESETTING TRIGGER
F7AE £98100 5075 JMP V7
5076
5077 ;----- TIHGGER HAS BEEN SET I READ THE VALUE IN
5078
'lBl 5079 V7A:
F7Bl 8410 5080 MDV AH.16 ; LI~HT PEN REGISTERS ON 6845
5081
5082 ; ----- INPUT REGS POINTED TO BY AH. AND CONVERT TO ROW COLUMN IN OX
5083
F7B3 88166300 5084 MDV ox .ADDR_6645 ; ADDRESS REGISTER FOR 6845
F7B7 6AC4 5085 MDV AL,AH ; REGISTER TO READ
f7B9 EE 5086 OUT DX.AL ) SET IT UP
F7eA 42 5087 INC ox I DATA REGISTER
f7BB EC 5088 IN AL.DX ; GET THE VALUE
F7Be 8A£8 5089 MOV CH.AL ; SAVE IN CX
F7BE 4A 5090 DEC ox ; ADDRESS REGISTER
F7BF FEC4 5091 INC AH
net 8AC4 5092 MOV AL.AH I SECOND DATA REGISTER
F7C3 EE 5093 OUT DX.AL
F7C4 42 5094 INC ox I POINT TO DATA REGISTER
F7C5 EC 5095 IN AL.DX I GET SECOND DATA VALUE
F7C6 8A£5 S096 I10V AH.CH I AX HAS INPUT VALUE
System BIOS A-71

LOC OBJ LINE SOURCE
5097
5098 ;----- AX HAS THE VALUE READ IN FROM THE 6845
5099
nCB 8AIE4900 5100 MaV Bl.CRT_HOoE
F7CC 2AFF 5101 SUB BH,BH I MODE VALUE TO ex
F7eE ZE8A9F94F7 5102 MaV BL.CS:Vl[BX] I DETERNINE AMOUNT TO SUBTRACT
F703 2&3 5103 SUB AX,BX ; TAKE IT AWAY
F70S 861E4EOO 5104 MOV ex. CRT_START
F7D9 DlEB 5105 SH' BX,l
F1DB 2BC3 5106 SUB Ax,ex
F1DO 7902 5107 JNS V, ; IF POSITIVE, DETERMINE MODE
F70F 2BCO 5108 SUB AX,AX I <0 PLAYS AS 0
5109
5110 j----- DETERMINE NODE OF OPERATION
5111
F7El 5112 V2: I DETERMINE_HODE
F7El 8103 5113 MOV CL,3 ; SET *8 SHIFT COUNT
F7E3 803E490004 5114 CMP CRT_MODE ,4 ; DETERMINE IF GRAPHICS OR ALPHA
F7EB 722A 5115 JB V4 I ALPHA_PEN
F7EA 803E490007 5116 CMP CRT_MODE.7
F7EF 7423 5117 JE V4 i ALPHA_PEN
5118
5119 ; ----- GRAPHICS MODE
5120
F7Fl 8228 5121 MOV DL.40 ; OIVISOR FOR GRAPHICS
F7F3 F6FZ 5122 OIV OL ; DETERMINE ROW( AL) AND COLlJMN( AH)
5123 ; AL RANGE 0-99, AH RANGE 0-39
5124
5125 ; ----- DETERMINE GRAPHIC ROW POSITION
5126
F7F5 8AE8 5127 MaV CH,AL ; SAVE ROW VALUE IN CH
F7F7 02EO 5128 ADD CH,CH ; *2 FOR EVEN/ODD FIELD
F7F9 8ADC 5129 MOV BL,AH ; COLUMN VALUE TO BX
F7FB 2AFF 5130 SUB BH,BH ; NULTIPL Y BY 8 FOR MEDIUM RES
F7FD 803E490006 5131 CMP CRT_MODE,6 ; DETERMINE MEDIUM OR HIGH RES
F802 7504 5132 JHE V, I NOT_HIGH_RES
F804 BI04 5133 MaV CL,4 ; SHIFT VALUE FOR HIGH RES
FM6 DOE4 5134 SAL AH.l 1 COLUMN VALUE TIMES 2 FOR HIGH RES
Faoa 5135 V3: I NOT_HIGH_RES
F80S D3E3 5136 SHL BX,CL ; MULTIPLY *16 FOR HIGH RES
5137
5138 1----- DETERMINE ALPHA CHAR POSITION
5139
F80A 8A04 5140 HOV DL,AH ; COLUt1H VALUE FOR RETURN
FSOC 8AFO 5141 MaV DH,AL ; ROW VALUE
F80E DOEE 5142 SH, DH,l ; OIVIDE BY 4
F810 DOEE 5143 SHR DH,l FOR VALUE IN 0-24 RANGE
F812 EBI2 5144 JMP SHORT V5 LIGHT _PEN_RETURN_SET
5145
5146 1----- ALPHA MODE ON LIGHT PEN
5147
F814 5148 V4: I ALPHA_PEN
F814 F6364AOO 5149 OIV BYTE PTR CRT_COLS ; DETERMINE ROW,COLUMN VALUE
F818 8AFO 5150 MOV DH,AL ; ROWS TO DH
F81A 8AD4 5151 MOV OL,AH I COLS TO DL
FalC 02EO 5152 SAL AL,CL ; MUL TIPL Y ROWS * a
F8tE 8AE8 5153 MOV CH,AL 1 GET RASTER VALUE TO RETURN REG
F8Z0 8ADC 5154 MOV BL,AH I COLUMN VALUE
F822 32FF 5155 XO, BH,BH TO ex
F824 D3E3 S156 SAL BX,CL
F626 5157 VS: LIGHT_PEN_RETURN_SET
F8l6 B401 5158 HOV All. 1 INDICATE EVERTHING SET
Fa28 5159 V6: , LIGHT_PEN_RETURN
Fa28 52 5160 PUSH OX ; SAVE RETURN VALUE (IN CASE)
F829 88166300 5161 MOV DX,ADDR_6a45 ; GET BASE ADDRESS
F82D a3C207 5162 ADD OX.7 ; POINT TO RESET PARM
F830 EE 5163 OUT DX,AL ; ADDRESS. NOT DATA, IS IMPORTANT
f831 SA 5164 POP OX ; RECOVER VALUE
F832 5165 V7: ; RETURN_NO_RESET
Fa32 SF 5166 PDP 01
F833 5E 5167 POP SI
Fa34 IF 5168 POP OS I DISCARD SAVED 8X,ex,Ox
F835 IF 5169 POP OS
FS36 IF 5170 POP OS
5171
F837 IF 5172 PDP OS
F838 07 5173 POP ES
A-72 System BIOS

LOC OBJ LINE SOURCE
F!39 Cf 5174 IRET

5175 READ_lPEN EHOP
5176
5177 ;--- INT 12 -------------------------------------------------------------
5176 ; MENORY_SIZE_DET
5179 THIS ROUTINE DETERMINES THE AMOUNT OF t'lEHORY IN THE SYSTEM
5180 AS REPRESENTED BY THE SIolITCHES ON TlfE PLANAR. NOTE THAT THE
5181 SYSTEM HAY NOT BE ABLE TO USE lID MEMORY UNLESS THERE IS A FULL:
5182 COMPLEMENT OF 64K BYTES ON THE PLANAR.
5183 ; INPUT
5184 NO REGISTERS
5185 THE HEMORY_SIZE VARIABLE IS SET DURING POWER ON DIAGNOSTICS
5186 ACCORDING TO THE FOLLOWING HARDWARE ASSUMPTIONS:
51a7 PORT 60 BITS 3.2 = 00 - 16K BASE RAM
51as 01 - 32K BASE RAM
5189 10 - 4BK BASE RAM
5190 11 - 64K BASE RAM
5191 PORT 62 BITS 3-0 INDICATE AMOUNT OF I/O RAM IN 32K INCREMENTS
5192 E.G •• 0000 - NO RAM IN 110 CHANNEL
5193 0010 - 64K RAM IN I/O CHANNEL. ETC.
5194 ; OUTPUT
5195 (AX) :: NUMBER OF CONTIGUOUS IK BLOCKS OF HEMORY
5196 ; ------------------------------------------------------------------------
5197 ASSUME CS:COOE ,OS:OATA
F841 5196 ORG OF841H
F841 5199 HEHORY_SIZE_OET PROC FAR
F841 FB 5200 STI ; INTERRUPTS BACK ON
F84Z IE 5201 PUSH OS ; SAVE SEGMENT
F843 EBF806 5202 CALL DDS
F846 AI1300 5203 MOV AX ,MEMORY_SIZE ; GET VALUE
f849 IF 5204 POP OS i RECOVER SEGMENT
F84A CF 5205 IRET ; RETlmN TO CALLER
5207
5206 ;--- INT 11 -----------------------------------------------------
5209 ; EQUIPMENT DETERMINATION
5210 THIS ROUTINE ATTEMPTS TO DETERHINE WHAT OPTIONAL
5211 DEVICES ARE ATTACHED TO THE SYSTEM.
5212 ; INPUT
5213 NO REGISTERS
5214 THE EQUIPJLAG VARIABLE IS SET DURING THE POWER ON
5215 DIAGNOSTICS USING THE FOLLOWING HARDWARE ASStR1PTIONS:
5216 PORT 60 = LOW ORDER BYTE OF EQUPMENT
5217 PORT 3fA = INTERRUPT 10 REGISTER OF 8250
5218 BITS 7-3 ARE ALWAYS 0
5219 PORT 378 = OUTPUT PORT Of PRINTER -- 8255 PORT THAT
52:20 CAN BE READ AS WELL AS WRITTEN
5221 ; OUTPUT
5222 (AX) IS SET, BIT SIGNIFICANT. TO INDICATE ATTACHED I/O
5223 BIT 15.14 ::: NUMBER OF PRINTERS ATTACHED
5224 BIT 13 HOT USED
5225 BIT 12 = GAME I/O ATTACHED
5226 BIT 11.10.9 ::: t-U1BER OF RS232 CARDS ATTACHED
5227 BIT 8 UNUSED
5228 BIT 7.6 = NUMBER OF DISKETTE DRIVES
5229 00=1. 01=2. 10=3. 11=4 ONLY IF BIT 0 = 1
5230 BIT 5.4 = INITIAL VIDEO HOOE
5231 00 - UNUSED
5232 01 - 40X25 BW USING COLOR CARD
5233 10 - 80X25 BW USING COLOR CARD
5234 11 - 60X25 BW USING BW CARD
5235 BIT 3.2 = PLANAR RAM SIZE (OO=16K,01=32K,10=48K.ll=6410
5236 BIT 1 NOT USED
5237 BIT 0 :: IPl FROM DISKETTE -- THIS BIT It«IICATES THAT
5238 THERE ARE DISKETTE DRIVES ON THE SYSTEH
5239
5240 NO OTHER REGISTERS AFFECTED
5241 ;----------------------------------------------------------------
5242 ASSUME CS :CODE .DS:OATA
f840 5243 ORG Of840H
F840 5244 EQUIPMENT PROC FAR
F84D FB 5245 ST! ; INTERRUPTS BACK ON
F84E IE 5246 PUSH DS ; SAVE SEGMENT RESISTER
F84F E8Ee06 5247 CALL DDS
F852 AllOOO 5248 MOV AX,EQUIP _FLAG ; GET THE CURRENT SETTINGS
F655 IF 5249 POP DS ; RECOVER SEGMENT
F856 CF 5250 IRET ; RETURN TO CALLER
System BIOS A-73

LOC OBJ LINE SOURCE
5251 EQUIPMENT EtIlP

52:52
52:53 ;--- INT 15 ------------------------------------------- _________ _
5254 ; CASSETIE 110
52:55 (AH) =0 TURN CASSETTE HOTOR ON
5256 (AH) =1 TURN CASSETTE MOTOR OFF
52:57 (AH I = 2: READ 1 OR MORE 256 BYTE BLOCKS FRON CASSETTE
5256 (ES,BXI = POINTER TO DATA. BUFFER
5259 (ex I = CO\.JHT OF BYTES TO READ
5260 ; ON EXIT
5261 I ES,BX) = POINTER TO LAST BYTE READ + 1
5262 (OXI = COUNT OF BYTES ACTUALLY READ
5263 (tY) =0 IF NO ERROR OCCURRED
5264 =1 IF ERROR OCCURRED
5265 I AH 1 :;: ERROR RETURN IF I CV) = 1
5266 = 01 IF CRC ERROR WAS DETECTED
5267 = 02 IF DATA TRANSITIONS ARE LOST
5268 = 04 IF NO DATA WAS FOUND
5269 I AH 1 = 3 WRITE 1 OR MORE 256 BYTE BLOCKS TO CASSETTE
5270 IES,BXI = POINTER TO DATA BUFFER
5271 (CX) = COUNT OF BYTES TO WRITE
5272 ; ON EXIT
5273 I EX,BXI = POINTER TO LAST BYTE WRITTEN + 1
5274 (eX) = 0
5275 (AH) = ANY OTHER THAN ABOVE VALUES CAUSES ICY 1= 1
5276 AND (AH 1= 80 TO BE RETURNED I INVALID COMMAND).
5277 ;----------------------------------------------------------------
5278 ASSUME as : DATA. ES: NOTHING. SS: NOTHING ,CS: CODE
f859 5279 ORG OF859H
F859 5280 CASSETTE_IO PROC FAR
F859 FB 5281 STI ; INTERRUPTS BACK ON
FaSA IE 5282 PUSH OS ; ESTABLISH ADDRESSING TO DATA
F858 £6E006 5283 CALL DDS
FaSE 802671007F 5284 AND BIOS_BREAK. 7FH ; MAKE SURE BREAK FLAG IS OFF
F863 E80400 5285 CALL loll ; C~SSETTE_IO_CONT
F866 IF 5286 POP OS

F667 CA02:00 5287 RET ; INTERRUPT RETURN
5288 CASSETTE_IO ENDP
,eo. 5289 loll PROC NEAR
5290 ; - -- - - - - - --- - - -- - --------------- -- --- ----- - - -- -- - -- ---- --
5291 PURPOSE:
5292 TO CALL APPROPRIATE IWUTINE DEPENDING ON REG AH
5293
5294 AH ROUTINE
5295 ; --------------------------------------------------------
5296 HOTOR ON
5297 HOTOR OFF
5298 READ CASSETTE BLOCK
5299 WRITE CASSETTE BLOCK
Fe6 .. OAElt
5300
5301 OR AH.AH ,
; - - - - ------ - -- -- - -------- -- - - - -- - - - ---- ------- -- - --------
TURN ON MOTOR?
FMC 7413 5302 MOTOR_ON , YES. DO IT
F86E FEte 5303
JZ
DEC AH , TURN OFF MOTOR?
Fa70 7418 5304 JZ MOTOR_OFF , YES. DO IT
,
F672 FEte
F874 74l.A.
5305
5306
DEC
JZ
AH
READ_BLOCK , READ CASSETTE BLOCK?
YES. 00 IT
Fe76 FEte 5307 DEC AH , WRITE CASSETTE BLOCK?
F878 7503 5308 JNZ W2 , NOT_OEF~NEO
Fe7A. E92401 5309 JMP WRITE_BLOCK , YES. DO IT

F87D 5310 1012: , COMMAND NOT DEFINED
Fa7D 8480 5311 MOV AH. paOH , ERROR. UNDEFINED OPERATION
F87F f9 5312 STC I ERROR FLAG
fa8D C3 5313 RET
5314 WI ENDP
,sal 5315 PROC NEAR
5316 ; ---- ------------------------------------
5317 ; PlIRPOSE:
5316 TO TURN ON CASSETTE MOTOR
5319 ; ----------------------------------------
F8BI E461 5320 IN AL.PORT_B ; READ CASSETTE OlTTPUT
F88l 24F7 5321 AND AL,NOT oaH ; CLEAR BIT TO TURN ON MOTOR
F885 5322 1013:
FaBS E661 5323 OUT PORT_B.AL ; WRITE IT OUT
Fa87 2AE4 5324 SUB AH.AH ; CLEAR AH
F889 C3 5325 RET
5326 MOTOR_ON EHllP
F8a" 5327 MOTOR_OFF PROC NEAR
A-74 System BIOS

LaC OBJ LINE SOURCE
53,8 i - - - -. - .------ - -- -.---------- - - -- --------

5329 I PURPOSE:
5330 TO TURN CASSETTE MOTOR OFF
5331 1----------------------------.-----------
F88A E461 5332 IN AL,PORT.B ; READ CASSETTE OUTPUT
FesC oeoe 5333 OR Al,08H ; SET BIT TO TURN OFF
F88E ESFS 5334 JMP W3 ; ~ITE IT. CLEAR ERROR. RETURN
5335 MOTOR_OFF ENOP
F890 5336 READ_BLOCK PROC NEAR
5337 I - - - - - -- -- - -. - - - - - - --.-.----- - ------ ------ ----.-- -- -- ------ -- - - --
5338 PURPOSE:
5339 TO READ 1 OR MORE 256 BYTE BLOCKS FROM CASSETTE
5340
5341 I ON ENTRY:
5342 ES IS SEGMENT FOR MEMORY BUFFER (fOR COMPACT CODE I
5343 ex POINTS TO START OF MEMORY BUFFER
5344 ex CONTAINS MJt1BER OF BYTES TO READ
5345 J ON EXIT:
5346 ex POINTS 1 BYTE PAST LAST BYTE PUT IN MEM
5347 ex CONTAINS DECREMENTED BYTE COUNT
5348 OX CONTAINS HUHBER OF BYTES ACTUALLY READ
5349
5350 CARRY FLAG IS CLEAR IF NO ERROR DETECTED
5351 CARRY flAG IS SET IF CRC ERROR DETECTED
5352 ; --_._--------------------------.--._----------------------------
F890 53 5353 PUSH BX ; SAVE BX
F891 51 5354 PUSH CX ; SAVE CX
F892: 56 5355 PUSH 51 I 5AVE 51
Fe93 BE0700 5356 MOV 51. 7 ; SET UP RETRY COUNT FOR LEADER
Fe96 E8BFOI 5357 CALL BEGIN_OP I BEGIN BY STARTING MOTOR
F899 5351;1 W4: ; SEARCH FOR LEADER
F899 E462 5359 IN AL.PORT_C ; GET INTIAL VALUE
F89B 2:410 5360 AND AL.OlOH ; MASK OFF EXTRANEOUS BITS
F890 A26BOO 5361 MOV LAST_VAL.AL I SAVE IN LOC LAST_VAL
FSAO BA7A3F 5362 Mav DX.16250 ; • OF TRANSITIONS TO LOOK FOR
FaA3 5363 W5: ; WAIT_FOR_EDGE
F8A3 F6067100S0 5364 TEST BIOS_BREAK. 80H ; CHECK FOR BREAK KEY
FaAS 7503 5365 JHZ W.A ; JUT1P IF NO BREAK KEY
5366 I JUT1P IF BREAK KEY HIT
FaAA 5367 W6:
F8AA 4A 5368 aEC DX
F8AB 7503 5369 JNZ W7 ; JUT1P IF BEGINNING OF LEADER
FSAD 5370 W6A:
F8AD E98400 5371 JMP W17 ; JUT1P IF NO LEADER FOl.H)
F880 5372 W7:
F6BO E8C600 5373 CALL READ_HALF_BIT ; IGNORE FIRST EDGE
F8B3 nEE 5374 JCXZ ws I JUMP IF NO EDGE DETECTED
FBB5 BA7803 5375 MOV DX.0378H ; CHECK FOR HALF BITS
FSBS B90002: 5376 MeV CX.200H ; MUST HAVE AT LEAST THIS ttANY ONE SIZE
5377 ; PULSES BEFORE CHCKNG FOR SYNC BIT (0)
F8BB E42:1 5378 IN AL, 021H I INTERRUPT MASK REGISTER
F8BD OCOI 5379 OR AL.l ; DISABLE TIMER INTERRUPTS
F8BF E621 5380 OUT 02:IH. AL
FaCI 5381 W6: ; SEARCH-LOR
F8CI F606710080 5382: TEST BIOS_BREAK. SOH I CHECK FOR BREAK KEY
F5C6 756C 5383 JNZ W17 ; JUT1P IF BREAK KEY HIT
F8C8 51 5364 PUSH CX ; SAVE REG CX
F5C9 E8ADOO 5385 CALL READ_HALF _BIT ; GET PULSE W~DTH
F8CC OBC9 53136 OR CX, CX ; CHECK FOR TRANSITION
FaCE 59 5387 pop CX ; RESTORE ONE BIT COUNTER
F8CF 74C8 5388 JZ W4 I JUMP IF NO TRANSITION
FeDI 3BD3 5389 CMP OX,BX I CHECK PULSE WIDTH
F8D3 n04 5390 JCXZ W9 I IF CX=O THEN WE CAN LOOK
5391 I FOR SYNC BIT (0)
FaD5 73CZ 5392 JNC W4 I JUMP IF ZERO BIT (NOT GOOO LEADER)
F8D7 f2E8 5393 LOOP W8 ; DEC CX AND READ ANOTHER HALF ONE BIT
F809 5394 W9: ; FIND-SYNC
FaD9 nE6 5395 JC W8 I JUMP IF ONE BIT (STILL LEADER)
5396
5397 ;----- A SYHCH BIT HAS BEEN FOUND. READ SYN CHARACTER:
5398
F8DB £89BOO 5399 CALL READ_HALF _BIT ; SKIP OTHER HALF OF SYNC BIT 10 J
FeDE E86AOO 5400 CALL READ_BYTE ; READ SYN BYTE
F8EI 3C16 5401 CMP AL, 16H ; SYNCHRONIZA lION CHARACTE~
FeE3 7549 5402: JNE WI. ; JUMP IF BAD LEADER FOUND.

5403
5404 ;----. GOOD CRe so READ DATA BLOCK(S)
System BIOS A-75

LOC OBJ LINE SOURCE
5405
FeES SE 5406 POP 51 I RESTORE REGS
FaE6 59 5407 pOP ex
FaE7 58 5408 POP BX
5409 1----------------------------------------------------------------
5410 ; READ 1 OR MORE 256 BYTE BLOCKS FROM CASSETTE
5411
5412 I ON ENTRY:
5413 ES IS SEGMENT FOR MEMORY BUFFER (FOR COMPACT CODE)
5414 ex POINTS TO START OF MEMORY BUFFER
5415 CX CONTAINS NUMBER OF BYTES TO READ
5416 I ON EXIT:
5417 BX POINTS 1 BYTE PAST LAST BYTE PUT IN MEM
5418 CX CONTAINS DECREMENTED BYTE COUNT
5419 OX CONTAINS NUMBER OF BYTES ACTUALLY READ
5420 1----------------------------------------------------------------
feE8 51 5421 PUSH CX ; SAVE BYTE cout·n
F8E9 5422 IoUO: ; COME HERE BEFORE EACH
5423 I 256 BYTE BLOCK IS READ
F8E9 C7Q66900FFFF 5424 MOV CRC_REG,OFFFFH I INIT CRC REG
FeEF BMOOI 5425 MOV DX,256 ; SET OX TO DATA BLOCK SIZE
FeF2 5426 1411: I RO_BLK
FeF2 F606710080 5427 TEST BIOS_BREAK. 80H ; CHECK FOR BREAK KEY
FaF7 7523 5428 W13 I JUMP IF BREAK KEY HIT
f8F9 E84FOO 5429 CALL READ_BYTE ; READ BYTE FROM CASSETTE
FaFC 721E 5430 JC 10113 j CY SET INDICATES NO DATA TRANSITIONS
faFE nos 5431 JCXZ 10112 ; IF WE'VE ALREADY REACHED
5432 ; END OF MEMORY BUFFER
5433 ; SKIP REST OF BLOCK
f900 268807 5434 MOV ES:tBX),AL ; STORE DATA BYTE AT BYTE PTR
F903 43 5435 INC BX ; INC BUFFER PTR
F904 49 5436 DEC ex ; DEC BYTE COUNTER
f905 5437 10112: ; LOOP UNTIL DATA BLOCK HAS BEEN
5438 ; READ FROM CASSETTE.
F905 4A 5439 DEC OX ; DEC BLOCK CNT
F906 7FEA 5440 JG 1411 j RD_BLK
f908 E84000 5441 CALL READ_BYTE I NOW READ TWO CRC BYTES
F90B E83000 5442 CALL READ_BYTE
F90E 2AE4 5443 SUB AH.AH ; CLEAR AH
f910 813E69000FID 5444 CMP CRC_REG, !.DOFH I IS THE CRC CORRECT
F916 7506 5445 JNE 10114 ; IF NOT EQUAL CRe IS BAD
Fna nOb 5446 JCXZ 1415 I IF BYTE COUNT IS ZERO
5447 I THEN WE HAVE READ ENOUGH
5448 ; SO WE WIL L EXIT
F9U, EBCD 5449 JMP
f91C 5450 1413: "" ; STILL HaRE. SO READ ANOTHER BLOCK
; HISSING-DATA
5451 ; NO DATA TRANSITIONS SO
f91C 8401 5452 MOV AH,OlH ; SET AH=02 TO INDICATE
5453 I DATA TIMEOUT
F91E 5454 1414: ; BAO-CRe
f91E FEC4 5455 INC AH ; EXIT EARLY ON ERROR
5456 ; SET AH=Ol TO INDICATE CRe ERROR
Fno 5457 10115: ; RO-BLK-EX
Fno SA 5458 POP ox ; CAl'.CULATE COUNT OF
F921 2BOI 5459 SUB OX.CX ; DATA BYTES Acru.6.lLY READ
5460 ; RETURN COUNT IN REG OX
F923 50 5461 PUSH AX ; SAVE AX (RET CODE)
F924 F6C490 5462 TEST AH. 90H j CHECK FOR ERRORS
F927 7513 5463 JNZ 10118 ; JUMP IF ERROR DETECTED
F929 ESlFOD 5464 CALL READ_BYTE j READ TRAILER
Fnc ESCE 5465 JHP SHORT 10118 ; SKIP TO TURN OFF MOTOR
F92E 5466 1416: j BAD-LEADER
F92E 4E 5467 DEC 51 ; CHECK RETRIES
F92F 7403 5468 JZ W17 ; JUMP IF TOO MANY RETRIES
F931 E965FF 5469 JMP W4 ; JUMP IF HOT TOO MANY RETRIES
F934 5470 Wl7: j NO VALID DATA FOUND
5471
5472 ;----- NO DATA FROM CASSETTE ERROR, I.E. TIMEOUT
5473
f934 SE 5474 pop SI I RESTORE REGS
F935 59 5475 POP CX I RESTORE REGS
F936 58 5476 POP BX
f937 ZBDl 5477 SUB OX.OX I ZERO HUMBER OF BYTES READ
F939 8404 5478 MOV AH.04H ; TIME OUT ERROR {NO LEADER l
f938 50 5479 PUSH AX
F93C 5480 IU8: I HOT-OFF
A-76 System BIOS

LOC OSJ LINE SOURCE
F93C E421 5481 IH Al. 021H ; RE_ENABLE lNTERRUPTS

F93E 24FE 5482 AND Al. OfFH- 1
F940 E&21 5463 OUT 021H. AL
F942 E845FF 5484 CALL MOTOR_OFf I TURN OF F MOTOR
F945 56 5485 POP AX I RESTORE RETURN CODE
F946 60FCOl 5486 eMP AH,OlH I SET CARRY IF ERROR (AH>Q)
F949 F5 5487 eMC
f94A C3 5488 RET ; FINISHED
5489 READ_BLOCK ENDP
5490 i ----------------------------------------
5491 ; PURPOSE:
5492 TO READ A BYTE FROM CASSETTE
5493 ; ON EXIT
5494 REG AL CONTAINS READ DATA BYTE
5495 i ----------------------------------------
F94B 5'1-96 READ_BYTE PROC NEAR
F94B S3 5497 PUSH BX ; SAVE REGS BX.CX
f94C 51 5'1-98 PUSH ex
F940 BI08 5499 MOY CL,8H i SET BIT COUNTER FOR 8 BITS
F94F 5500 10119: ; BYTE-ASH
f94F 51 5501 PUSH ex ; SAVE CX
5502 ; ---------- ----------------------
5503 ; READ DATA BIT FROH CASSETTE
550'1-
f950 E82600 5505 CALL READ_HALF _BIT ; READ ONE PULSE
F953 E3l0 5506 JCXZ W21 ; IF CX=O THEN TIMEOUT
5507 ; BECAUSE OF NO DATA TRANSITIONS
F955 S3 5508 PUSH BX ; SAVE 1ST HALF BIT'S
5509 ; PULSE WIDTH I IN BX)
F956 E82000 5510 CAll READ_HALF _BIT ; READ COMPLEMENTARY PULSE
F959 58 5511 POP AX ; COMPUTE DATA BIT
F95A nI9 5512 JCXZ W21 ; IF CX=O THEN TIMEOUT DUE TO
5513 ; NO DATA TRANSITIONS
F95C 0308 5514 ADD BX,AX I PERIOD
f95E 81FBF006 5515 eMP BX. 06FOH ; CHECK FOR ZERO BIT
F962 F5 5516 eMC ; CARRY IS SET IF ONE BIT
F963 <;IF 5517 lAHF ; SAVE CARRY IN AH
f964 59 5518 POP ex ; RESTORE CX
5519 i NOTE:
5520 I MS BIT OF BYTE IS READ FIRST.
5521 REG CH IS SHIFTED lEFT WITH
5522 I CARRY BEING INSERTED INTO LS
5523 BIT OF CH.
5524 i AFTER ALL 8 BITS HAVE BEEN
5525 READ. THE MS BIT OF THE DATA BYTE
5526 WIll BE IN THE MS BIT OF REG CH
F965 0005 5527 ReL CH.I ; ROTATE REG CH LEFT WITH CARRY TO
5528 LS BIT OF REG CH
F967 9E 5529 SAHF ; RESTORE CARRY FOR CRC ROUTINE
F968 E80900 5530 CALL CRC_GEN ; GENERATE CRC FOR BIT
F96B FEet;! 5531 DEC CL ; LOOP TILL ALL 8 BITS OF DATA
5532 ; ASSEMBLED IN REG CH
F96D 75EO 5533 JHZ W19 ; BYTE_ASH
F%F 8ACS 5534 MOY AL.CH ; RETURN DATA BYTE IN REG AL
f971 Fa 5535 eLe
F972 5536 10120: ; RO-BYT-EX
F972 59 5537 POP CX ; RESTORE REGS CX,BX
F973 58 5538 POP OX
F974 C3 5539 RET ; FINISHED
f975 5540 W21: ; NO-DATA
f975 59 5541 POP ex i RESTORE CX
F976 F9 5542 STC ; INDICATE ERROR
F977 EBf9 55'1-3 JMP W20 I NO_BYT_EX
5544 READ_BYTE ENDP
5545 ;------------------------------------------------
5546 ; PURPOSE:
5547 TO COMPUTE TIME TILL NEXT DATA
5548 TRANSITION (EDGE)
5549 i ON ENTRY:
5550 EDGE_CNT CONTAINS LAST EDGE COUNT
5551 ; ON EXIT:
5552 AX CONTAINS OlD LAST EDGE CO\.JHT
5553 ex CONTAINS PULSE WIDTH (HALF BIT)
5554 • -- ----- - ----------- ---- ---- ----- ------ ----------
F979 5555
F979 6%400 5556 MOV CX. 100 ; SET TIME TO WAIT FOR BIT
F97C 8A266800 5557 MOY ; GET PRESENT INPUT VALUE
System BIOS A-77

LOC OBJ LINE SOURCE
F9ao 5556 ; RD-H-BIT

F980 E462 5559 IN ; INPUT DATA BIT
f982: 2410 5560 AND Al,OlOH ; MASK OFF EXTRANEOUS BITS
F984 3AC4 5561 CNP Al,AH I SAME AS BEFORE?
F986 ElFa 5562 LaOPE W22 ; LOOP TILL IT CHANGES
f988 11.26600 5563 MOV LAST_VAl,AL ; UPDATE LAST_VAL WITH NEW VALUE
F98B BOOO 5564 HOV AL,a ; READ TIMER'S COUNTER COMMAND
F980 E643 5565 OUT TIM_CTL,Al ; LATCH COUNTER
F98F 881E6700 5566 NOV eX,EDGE_eNT ; BX GETS LAST EDGE COUNT
F993 E440 5567 IN AL. TIHERO ; GET LS BYTE
F995 8AEO 5568 MOV AH,AL ; SAVE IN AH
F997 E440 5569 IN Al, TINERO ; GET MS BYTE
f999 86e4 5570 XCHG AL,AH ; XCHG AL,AH
F99B 2608 5571 SUB eX,AX ; SET BX EQUAL TO HALF BIT PERIOD
f99D A36700 5572 HOV EDGE_CNT ,AX ; UPDATE EDGE COUNT;
F9AO C3 5573 RET
5574 READ_HALF _BIT ENDP
5575 ; ----------------------------------------------------------------
5576 PURPOSE
5577 WRITE 1 OR MORE 256 BYTE BLOCKS TO CASSETTE.
5578 THE DATA IS PADDED TO FILL OUT THE LAST 256 BYTE BLOCK.
5579 ; ON ENTRY:
5580 BX POINTS TO MEMORY BUFFER ADDRESS
5581 CX CONTAINS NUMBER OF BYTES TO WRITE
5582 • ON EXIT:
5583 ex POINTS 1 BYTE PAST LAST BYTE WRITTEN TO CASSETTE
5584 CX IS ZERO
5585
f9Al 5586 PROC NEAR
F9Al 53 5587 PUSH BX
f9A2 51 5588 PUSH CX
F9A3 E461 5589 IN AL,PORT_B ; DISABLE SPEAKER
F9A5 24FD 5590 AND AL,NOT 02H
F9A7 DeDI 5591 OR AL, OlH ; ENABLE TIMER
F9A9 E661 5592 OUT PORT_B,AL
f9AB BOB6 5593 HOV AL,OB6H ; SET UP TIMER -- MODE 3 SQUARE WAVE
F9AO E643 5594 OUT TIM_CTL,AL
F9AF EaMOO 5595 CALL BEGIN_a? ; START MOTOR AND DELAY
f9B2 68A004 5596 MOV AX,l184 ; SET NORMAL BIT SIZE
F9B5 E88500 5597 CALL 10131 ; SET_TIMER
F9B8 690008 5598 MOV CX, 0800H ; SET CX FOR lEADER BYTE COUNT
f9BB 5599 10123: ; WRITE LEADER
F9BB F9 5600 STe ; WRITE ONE BITS
F9BC E86800 5601 CALL WRITE_BIT
F9BF E2FA 5602 lOOP 10123 ; LOOP 'TIL lEADER IS WRITTEN
F9Cl fa 5603 eLe ; WRITE SYNC BIT (0)
F9C2 E86200 5604 CAll WRITE_BIT
F9C5 59 5605 POP ex ; RESTORE REGS CX ,BX
f9Cb 56 5606 POP BX
F9C7 B016 5607 HOV AL, 16H ; WRITE SYN CHARACTER
f9C9 E84400 5608
5609 ; --------- ---------------------------- ------------ ---------- -----
5610 ; PURPOSE
5611 WRITE 1 OR MORE 256 BYTE BLOCKS TO CASSETTE
5612 I ON ENTRY:
5613 BX POINTS TO MEMORY BUFFER ADDRESS
5614 CONTAINS NUMBER OF BYTES TO WRITE
5615 ; ON EXIT:
5616 BX POINTS 1 BYTE PAST lAST BYTE WRITTEN TO CASSETTE
5617 CX IS ZERO
5618 ; ------- ----------- ------------ ------------ ---------- ------- -----
f9CC 5619 WR_BLOCK:
F9CC C70669DOFFFF 5620 HOV CRC_REG,OFFFFH ; INIT CRC
f9D2 BAOOOI 5621 HOV DX,256 ; FOR 256 BYTES
F9D5 5622 10124: ; WR-BLK
F9D5 268M7 5623 MOV AL,ES:[BX] ; READ BYTE FROM HEM
F9Q8 E83500 5624 CAll WRITE_BYTE ; WRITE IT TO CASSETTE
F90B noz 5625 JCXZ 10125 ; UNLESS CX=O, ADVANCE PTRS & DEC COUNT
F9DD 43 5626 INC BX ; INC BUFFER POINTER
f9DE 49 5627 DEC CX ; DEC BYTE COUNTER
f9Df 5628 10125: ; SKIP-AOV
F90F 4A 5629 DEC ox ; DEC BLOCK CNT
F9EO 7FF5 5630 JG "24 ; lOOP TIll 256 BYTE BLOCK
5631 ; IS WRITTEN TO TAPE
5632 ; - ---------------------------------------------------------------
5633 ; WRITE CRe
5634 WRITE l'S COMPLEMENT OF CRC REG TO CASSETTE
A-78 System BIOS

LOC OBJ LINE SOURCE
5635 WHICH IS CHECKED FOR CORRECTNESS WHEN THE BLOCK IS READ :

5636 ; REG AX IS MODIFIED
5637 1------------------------------------------------------_________ _
f9E2 A16900 5638 MOV AX,CRC_REG I WRITE THE ONE'S COMPLEMENT OF THE
5639 ; TWO BYTE CRC TO TAPE
F9E5 F700 5640 NOT AX ; FOR I' 5 COMPLEMENT
f9E7 50 5641 PUSH AX ; SAVE IT
f9E6 86EO 5642 XCHG AH,AL ; WRITE MS BYTE FIRST
F9EA E82300 5643 CALL WRITE_BYTE I WRITE IT
F9ED 58 5644 POP AX ; GET IT BACK
F9EE E8lFOO 5645 CALL WRITE_BYTE I NOW WRITE LS BYTE
F9F 1 OBC9 5646 OR ex,cx ; IS BYTE COUNT EXHAUSTED?
F9F3 7507 5647 JNZ WR_BLoeK ; JUMP IF NOT DONE YET
f9F5 51 5648 PUSH ex ; SAVE REG CX
F9F6 Bnooo 5649 HOV ex, 32 ; WRITE OUT TRAILER BITS
F9F9 5650 10126: ; TRAI L - LOOP
F9F9 F9 5651 STC
f9FA E82AOO 5652 CAll WRITE_BIT
F9FD EZFA 5653 LOOP 10126 ; WRITE UNTIL TRAILER WRITTEN
F9Ff 59 5654 POP CX ; RESTORE REG CX
FAOO BOBO 5655 HOV AL, OBOH ; TURN TIHER2 OFF
FADZ E643 5656 OUT
FA04680100 5657 MOV AX, 1
FAD7 E83300 5658 CAll 10131 SET_TIMER
FADA EB70FE 5659 CALL MOTOR_OFF I TURN MOTOR OFF
FAOD 28CO 5660 SUB AX,AX NO ERRORS REPORTED ON WRITE OP
FAOF C3 5661 RET FINISHED
5662 ENOP
5663 ; --------------------------------
5664 ; WRITE A BYTE TO CASSETTE.
5665 ; BYTE TO WRITE IS IN REG AL.
5666
FAID 5667 PROC NEAR
FAID 51 5668 PUSH CX I SAVE REGS CX,AX
FAll 50 5669 PUSH AX
FAl2 8AE8 5670 MOV CH,AL ; AL=BYTE TO WRITE.
5671 (MS BIT WRITTEN FIRSTi
FAl4 B106 5672 HOV CL,8 ; FOR 8 DATA BITS IN BYTE.
5673 NOTE: TWO EDGES PER BIT
fAl6 5674 W27: I DISASSEMBLE THE DATA BIT
FA16 0005 5675 RCl CH,I I ROTATE HS BIT INTO CARRY
FAIS 9C 5676 PUSHF ; SAVE FLAGS.
5677 NOTE: DATA BIT IS IN CARRY
FA19 E80BOO 5678 ; WRITE DATA BIT
F Ale 90 5679 POPf ; RESTORE CARRY FOR CRC CALC
FAID E82400 5680 CAll CRC_GEN ; COMPUTE CRC ON DATA BIT
FAZO FEC9 5681 DEC Cl I LOOP TIll All 8 BITS DONE
FAZZ 75F2 5682 JNZ 10127 ; JUHP IF NOT DONE YET
FA24 58 5683 POP AX ; RESTORE REGS AX,ex
FA25 59 5684 POP CX
FA26 C3 5685 RET ; WE ARE FINISHED
5686 ENOP
5687 ; ----------------------------------------- ---------------
5688 PURPOSE:
5689 TO WRITE A DATA BIT TO CASSETTE
5690 CARRY FLAG CONTAINS DATA BIT
5691 I.E. IF SET DATA BIT IS A ONE
5692 IF CLEAR DATA BIT IS A ZERO
5693
5694 NOTE: TWO EDGES ARE WRITTEN PER BIT
5695 ONE BIT HAS 500 USEC BETWEEN EDGES
5696 FOR A 1000 USEC PERIOD (1 MIlLISEC)
5697
5698 ZERO BIT HAS 250 USEC BETWEEN EDGES
5699 FOR A 500 USEC PERIOD (.5 MIllISEC)
5700 ; CARRY flAG IS DATA BIT
5701 ; --------- ______________________________________________ _
FAZ7 5702 PROC NEAR

5703 1 ASSUME IT'S A 'I'
FAZ7 B8AO04 5704 HOV AX,1l84 I SET AX TO NOMINAL ONE SIZE
FAZA 1203
fAze 685002
5705
5706
JC
MOV
",.
AX,592
; JUMP IF ONE BIT
; NO, SET TO NOMINAL ZERO SIZE
fA2F 5707 W28! ; WRITE-BIT-AX
FAZf 50 5708 PUSH AX ; WRITE BIT WITH PERIOD EQ TO VALUE AX
FA30 5709 10129:
FA30 E462 5710 IN Al,PORT_C INPUT TIHER_ 0 OUTPUT
FA32 2420 5711 AND Al,020H
System BIOS A-79

LaC OBJ LINE SOURCE
FA34 74FA 5712 JZ W29 ; LOOP TIll HIGH

FA36 5713 1<130:
FA36 £462 5714 IH Al.PORT_C I NOW 1oI"'!T TILL TIMER' 5 OUTPUT IS LOW
FA38 242:0 5715 AHO AL.020H
FA3A 7SFA 5716 JHZ W30
5717 ; RELOAD TIMER WITH PERIOO
5718 I FOR NEXT DATA BIT
FA3C 58 5719 POP AX ; RESTORE PERIOD COUNT
FA30 5720 10131: j SET TIMER
fA3D E642 5721 OUT 042H. AL i SET LOW BYTE OF TIMER 2
FA3F 8AC4 5722 MOV AL. AH
FA41 E642 5723 OUT 042H, AL ; SET HIGH BYTE OF TIMER ~
FA43 C3 5724 RET

5725 WRITE_BIT EHOP
5726 j -------- ----------------------------------------
57<:7 UPDATE CRC REGISTER WITH NEXT DATA BIT
5728 CRC IS USED TO DETECT READ ERRORS
5729 ASSUMES DATA BIT IS IN CARRY
5730
5731 REG AX IS MODIFIED
5732 flAGS ARE MODIFIED
5733 1------------------------------------------------
FA44 5734 CRC_GEN PROC NEAR
FA44 U6900 5735 MOV AX ,CRC_REG
5736 ; THE FOLLOWING INSTUCTIONS
5737 ; WILL SET THE OVERFLOW FLAG
5738 ; IF CARRY AND MS BIT OF CRC
5739 ; ARE UNEQUAL
FAit7 DIDS 5740 R'R AX,!
FA49 DIDO 5741 Rn AX,l
FA4S Fa 574~ ele ; CLEAR CARRY
FA4C 7104 5743 JNO W3Z ; SKIP IF NO OVERFLOW
5744 ; IF DATA BIT XORED WITH
5745 ; CRe REG BIT 15 IS ONE
FA4E 351008 5746 XOR AX,GaIOH i THEN XOR CRC REG WITH 08GIH
FAS1 F9 5747 STe ; SET CARRY
FA52 5748 W32:
FA52 DIDO 5749 Rel AX,I ; ROTATE CARRY (DATA BIll
5750 ; INTO CRC REG
FA54 ...36900 5751 MOV CRC_REG,AX ; UPDATE CRC_REG
FA57 C3 5752 RET j FINISHED
5753 CRC_GEN EHOP
5754
fAsa 5755 BEGIN_OP PROC HEAR I START TAPE ANO DElAY
FAsa E826FE 5756 CALL MOTOR_ON ; TURN ON MOTOR
FAS8 8342 5757 MOV BL,42H jDElAY FOR TAPE DRIVE
5758 iTO GET UP TO SPEED (112 SEC)
fASD 5759 10133:
FASO 890007 5760 MOV CX,700H ; INNER LOOP= APPROX. 10 HIlLISEC
FAbO E2FE 5761 10134: lOOP W,.
FA62 FEte 5762 DEC Bl
FA64 7SF7 5763 JHZ W33
FA66 C3 5764 RET
5765 BEGIN_OP ENDP
5766
fA67 20323031 5767 El DB ' 201',13,10
fA68 00
FA6C OA
5768
5769 j-----------------------------------------------------------------------
5770 CHARACTER GENERATOR GRAPHICS FOR 320X200 AND 640X200 GRAPHICS
5771 j-----------------------------------------------------------------------
FA6E 5772 ORG OFA6EH
FA6E 5773 CRT_CHAR_GEH LABEL BYTE
fA6E 0000000000000000 5774 DB OOOH.OOOH.GOOH,OOOH,OOOH,OOOH,OOOH,OOOH I o_00
FA76 7E81A581BD99817E 5775 DB 07EH,081H,OA5H,081H,OBDH,099H,081H,07EH ; 0_01
FA7E 7EFFOBFFC3E7FF7E 5776 DB 07EH,OFFH,OOBH,OFFH,OC3H,OE7H.OFFH.07EH ; 0_02
FA86 6CFEFEFE7C361000 5771 DB 06CH,OFEH,OFEH,OFEH,07CH.038H.OIOH.OOOH ; 0_03
fASE l0387CFE7C381000 5778 DB OlOH.036H.07CH.OFEH,07CH,036H,OI0H.OOOH I o_04
FA96 387C38FEFE7C387C 5779 DB 036H.07CH.036H,OFEH,OFEH,07CH,036H.07CH I o_05
FA9E lOl0387CFE7C387C 5780 DB OlOH.OIOH,036H.07CH,OFEH,07CH.036H,07CH I o_06
fAA6 0000183C3C180000 5781 DB OOOH,OOOH,018H,03CH,03CH.018H,OOOH,OOOH ; 0_o7
FAAE FFFFE7C3C3E7FFFF 5782 DB OFFH.OFFH,OE7H.OC3H.OC3H,OE7H.OFFH.OFFH ; 0_08
FAB6 003C664242663COO 5783 DB 000H,03CH,066H,04ZH,04ZH,066H,03CH.OOOH ; 0_09
fASE FFC399BDBD99C3FF 5784 DB OFFH.OC3H,099H,OBDH,OBDH,099H,OC3H,OFFH j O_OA
FAC6 OF070F7DCCCCCC78 5785 DB OOFH,007H.OOFH.07DH.OCCH.OCCH.OCCH.078H I 0_08
fACE 3(.b666663C187E1a 5786 DB 03CH.066H.066H,066H.03CH,018H,07£H,OI8H I D_OC
A-80 System BIOS

LOC OBJ LINE SOURCE
FADb 3F333F303070FOEO 5787 DB 03FH,033H.03FH.030H.030H,070H.OFOH.OEOH I O_OD

FADE 7F637f636367E6CO 5788 DB 07FH.Ob3H,07FH.063H,063H.067H,OE6H.OCOH ; D_OE
FAE6 995A3CE7E73C5A99 5789 DB 099H.05AH.03CH.OE7H.0E7H.03CH.05AH.099H ; O_OF
FAEE 80EOF8FEF8E08000 5790 DB 080H.OEOH,OF8H.OFEH.OF8H.OEOH.080H,OOOH ; 0_10
FAF6 020E3EFEJEOE0200 5791 DB 002H.00EH,03EH.OFEH,03EH,OOEH,002H,OOOH ; 0_11
FAFE 183C7E18187E3C18 5792 DB 018H,03CH,07EH,018H,OlBH,07EH,03CH,018H ; 0_12
FBD6 6666666666006600 5793 DB 066H.066H.066H.066H,066H,OOOH,066H.OOOH ; 0_13
FeDE 7FDBDB7BIBIBIBOO 5794 DB 07FH.ODBH.ODBH.07BH,OlBH.OIBH.OIBH.OOOH ; 0_14
FBlb 3E63386C6C38CC78 5795 DB 03EH,063H,038H,ObCH,06CH,038H,OCCH,078H ; 0_15
fBtE 000000007E7E7EDO 5796 DB 000H,OOOH,OOOH.OOOH,07EH.07EH,07EH,OOOH ; 0_16
FB26 183C7E187E3C18Ff 5797 DB 018H,03CH,07EH.018;i.07EH,03cH,OI8H,OFFH ; 0_17
FB2E 183C7E1818181800 5798 DB 018H.03CH,07EH.OIBH,018H.018H.OIBH.OOOH ; O_IB
FB36 181818187E3C1800 5799 DB 018H.018H.018H,018H,07EH,03CH,018H,OOOH ; 0_19
FB3E 00180CFEOC180000 5800 DB 000H.018H.00CH.OFEH.00CH.018H,OOOH,OOOH ; O_lA
FB46 003060FE6030000D 5801 DB OOOH,030H.060H,OFEH,060H.030H,ODOH.OOOH J O_IB
FB4E QOOOCQCOCOFEOOOO 5802 DB OOOH.OOOH,OCOH.OCOH,OCOH,OFEH,OOOH,OOOH I D_IC
fB56 Q02466FF66Z40000 5803 DB 000H.024H.066H.OFFH.06bH,02:4H,OOOH,OOOH ; 0_10
FBSE 00183C7EFFFFOOOQ 5804 DB 000H.018H,03CH,07EH,OFFH.OFFH.OOOH.000H ; O_IE
FB66 QOFFFF7E3ClBOOOO 5805 DB OOOH.OFFH.OFFH.07EH.03CH,OI8H,000H,OOOH ; D_IF
FB6E 0000000000000000 5806 DB OOOH,OOOH.OOOH,OOOH.OOOH.OOOH,OOOH,OOOH ; SP 0_20
FB76 3078783030003000 5807 DB 030H,078H.07BH.030H,030H.OOOH,030H.OOOH ; ! 0_2:1
fB7E 6C6C6COOOOOOOOOO 5808 DB 06CH.06CH,06CH.000H.OOOH.000H,OOOH.OOOH ; " 0_22:
FB86 6C6CfE6CFE6C6COD 5809 DB 06CH,06CH.OFEH,06CH.OFEH,06CH.06CH.OOOH I 10_23
F88E 307CC0780CF83000 5810 DB 030H,07CH.OCOH.078H.00CH.OF8H,030H.000H ; $; 0_2:4
FB96 OOC6CC183066C600 5811 DB OOOH,OC6H,OCCH,018H.030H,066H,OC6H.OOOH ; PER CENT D_2:5
FB9E 386C38760CCC7600 5812 DB 038H.06tH,038H.076H.00CH,OCCH.076H.000H ; & 0_2:6
FBA6 6060COOOOOOOOOOO 5813 DB 060H,060H.OCOH.000H.OOOH,OOOH,OOOH,000H • 0_27
FBAE 1830606060301800 5814 DB 018H,030H,060H,060H,060H,030H.018H,OOOH ; ( 0_28
FBB6 6030181818306000 5815 DB Q60H.030H,018H.018H.018H.030H,060H,OOOH I J 0_29
FBBE 00663CFF3C660000 5816 DB OOOH,066H,03CH,OFFH,03CH.066H.OOOH,OOOH ; * 0_2A
FBe6 003030FC30300000 5817 DB OOOH ,030H, 030H, OFCH .030H,030H, OOOH, OOOH ; + 0_2B
FBCE 0000000000303060 5818 DB OOOH. OOOH. OOOH ,OOOH ,OOOH. 030H. 030H. 060H ; , D_2C
FBD6 OOOOOOFCOOOOOOOO 5819 DB OOOH,OOOH,OOOH,OFCH,OOOH.OOOH,OOOH,OOOH ; - 0_20
FBDE 0000000000303000 5820 DB OOOH ,OOOH. OOOH ,OOOH ,OOOH ,030H. 030H, OOOH ; • 0_2E
FBE6 060C1830bOC08000 5821 DB 006H.00CH.018H.030H.060H.OCOH,080H.OOOH I /O_2:F
FBEE 7CC6CEDEF6E67COO 5822 DB 07CH.OC6H,OCEH,00EH,OFbH,OE6H,07CH.OOOH ; 0 D_30
FBF6 307030303030FCOO 5823 DB 030H,070H,030H,030H,030H,030H,OFCH,OOOH ; 1 0_31
FBFE 78CCOC3860CCFCOO 5824 DB 078H.OCCH,OOCH.038H.060H,OCCH,OFCH,OOOH ; 2: 0_32:
FC06 78CCOC380CCC7800 5825 DB 078H,OCCH.OOCH,038H,OOCH,OCCH,078H,000H ; 3 0_33
FCOE lC3C6CCCFEOClEOO 5826 DB OlCH.03CH.06CH,OCCH,OFEH,OOCH.OIEH,OOOH ; 4 D_34
FCIb FCCOF80COCCC7800 5827 DB OFCH,OCOH,OF8H.00CH.00CH.OCCH.07BH,OOOH ; 5 0_35
FCtE 38MCOF8CCCC7800 5828 DB 038H.060H.OCOH.OF8H.OCCH,OCCH,078H,OOOH ; 6 0_36
FC26 FCCCOC1830303000 5829 DB OFCH,OCCH.00CH,OIBH,030H.030H.030H.OOOH ; 70_37
FC2E 78CCCC78CCCC7800 5830 DB 078H.OCCH.OCCH,078H.OCCH.OCCH.078H,OOOH ; 8 0_38
FC3b 78CCCC7COC187000 5831 DB 078H,OCCH,OCCH,07CH.00CH.018H,070H,OOOH ; 9 0_39
fC3E 0030300000303000 5832 DB 000H,030H,030H,OOOH.OOOH,030H.030H.OOOH ; : 0_3A
FC46 0030300000303060 5833 DB 000H.030H.030H.OOOH.OOOH,030H,030H,060H ; I 0_3B
FC4E 183060C060301800 5834 DB 018H,030H,060H,OCOH,OMH,030H.OIBH,OOOH ; < 0_3C
FC5b OOOOFCOOOOFCOOOO 5835 DB OOOH, OOOH. OFCH .OOOH .OOOH ,OFCH,OOOH ,OOOH ; = 0_30
FC5E 6030180C18306000 5836 DB 060H.030H.018H.OOCH,018H.030H,060H,OOOH ; > 0_3E
FC66 78CCOC1830003000 5837 DB 078H.OCCH.00CH,018H.030H,OOOH,030H,OOOH ; ? 0_3F
FCbE 7CC6DEDEOEC07800 5838 DB 07CH.OC6H,ODEH,ODEH.ODEH,OCOH.078H.000H ; ill 0_40
Ft76 3078CCtCFCCCCtOO 5839 DB 030H,078H,OCCH,OCCH.OFCH.OCCH.OCCH,OOOH ; A 0_41
FC7E FC66667C6666FCOO 5840 DB OFCH.066H,066H,07CH,06bH,Ob6H.OFCH,OOOH ; B D_42
FC86 3C66COCOC0663COO 5841 DB 03CH.066H,OCOH.OCOH,OCOH.066H.03CH.000H I C 0_43
FceE F86C66b6666CF800 5842 DB OF8H.06CH.066H.066H.066H.06CH.Of8H,ODOH ; D 0_44
FC9b FE6268786862FEOO 5843 DB OFEH.062H.068H,078H,068H,062:H,OFEH,OOOH I E 0_45
FC9E FE6268786860FOOO 5844 DB OFEH,062H.068H,078H,06BH.ObOH.OFOH.OOOH ; F 0_46
fCA6 3C66COCOCE663EOO 5845 DB 03CH.066H.OCOH.OCOH.OCEH,066H,03EH,OOOH ; G D_47
fCAE CCCCCCFCCCCCCCOO 5846 DB OCCH.OCCH.OCCH.OFCH.OCCH,OCCH,OCCH,OOOH ; H 0_48
FCB6 7830303030307800 5847 DB 078H.030H,030H,030H,030H,030H,078H.OOOH ; 10_49
fCBE t EOCOCOCCCCC7800 5848 DB OlEH,OOCH,OOCH.OOCH.OCCH,OCCtl,078H.000H ; J 0_4.
FCC6 E6666C786C66E600 5849 DB OE6H,066H,06CH,07BH.ObCH.066H.OE6H.OOOH ; K 0_46
FCCE F060606062b6FEOO 5850 DB OFOH.060H,060H.060H,06ZH,066H,OFEH,OOOH ; L D_4C
FC06 c6EEfEFED6C6CbOO 5851 DB OC6H,OEEH,OFEH,OFEH,006H.OC6H.OC6H.ODOH I M 0_40
FCDE C6E6F6DECECbC600 5852 DB OC6H,OE6H,OFbH.00EH.OCEH,OC6H,OC6H.OOOH ; N 0_4E
FCE6 386CC6C6C66C3800 5a53 DB 038H,06CH,OC6H,OC6H.OC6H,06CH,038H,OOOH ; OO_4F
FCEE fC66667C6060FOOO 5854 DB OFCH,066H,06bH,07CH,060H.060H.OFOH.000H ; P D_50
FCF6 78CCCCCCOC781COO 5855 DB 078H,OCCH,OCCH,OtCH,ODCH.078H,OlCH.OOOH J Q 0_51
FCFE FC66667C6C66E600 5856 DB OFCH,066H,066H,07CH,06CH.066H.OE6H,OOCH r R 0_52
FD06 78CCE0701CCC7800 5857 DB 078H.OCCH,OEOH.070H.OICH,OCCH,078H,OOOH ; SO_53
FDOE FCB4303030307800 5858 DB OFCH,OB4H,030H,030H,030H,030H,07BH.OOOH ; T D_54
FD16 cccccccccctCFCOO 5859 DB OCCH.OCCH.OCCH,OCCH.OCCH,OCCH,OFCH.OOOH ; U 0_55
FOI E CCCCCCCCCC783000 5860 DB OCCH.OCCH,OtCH,OCCH,OCCH.078H,030H.OOOH ; V 0_56
FD2b C6C6C606FEEECbOO 5861 DB OC6H.OC6H,OC6H,006H.OFEH,OEEH,OC6H,OOOH ; W D_57
F02E C6C66C38386CC600 5862 DB OC6H,OC6H,06CH,03BH,03BH.ObCH.OC6H,OOOH ; X 0_5B
F036 CCCCCC7830307800 5663 DB OCCH.OCCH,OCCH,078H,030H,Q1.0H,078H,OOOH 1 Y D_sq
System BIOS A-81

LOC OBJ LINE SOURCE
FD3E FECb8C1832bbFEOO 5864 DB OFEH.OC6H.08tH.018H,Ol2H,066H,OFEH.000H • Z 0_5A

FD46 7860606060607800 5865 DB 078H.060H.060H.P60H.060H.060H.078H.OOOH ; [ 0_5B
FD4E C06030180C060200 5866 DB OCOH,060H,030H,016H,OOCH,006H,002H,oOOH • BACKSLASH O_SC
FD56 7818181818187800 5867 DB 07BH,OI8H,018H.018H.018H,OlBH,078H.OOOH ; ] o_50
FD5E 10386CC600000000 5868 DB 010H,038H,06CH,OC6H,OOOH.000H.OOOH,OOOH I CIRt\.n1FI-EX 0_5E
F066 OOOOOOOOOOQOOOfF 5869 DB OOOH, OOOH, OOOH ,OOOH .OOOH ,OOOH. OOOH .OFFH I _ 0_5F
FD6E 3030180000000000 5870 DB OlOH,030H,018H,OOCH,OOOH,000H.OOOH.OOOH ; , D_60
F076 0000780C7CCC7600 5871 DB OOOH.OOOH.078H,OOCH,07CH,OCCH,076H.000H ; LOWER CASE A o_61
F07E E060607C66660COO 5872 DB OEOH.060H.060H.07CH.066H,066H.ODCH,OOOH ; L.C. B D_62
FDe6 000078CCCOCC7800 5873 DB OOOH.000H.078H,OCCH,OCOH,OCCH,078H.000H ; L.t. C o_63
FU8E lCOCOC7CCCCC760Q 5874 DB 01tH,oOCH.00CH,07CH,OCtH,OCCH.076H.OOOH ; L.C. D 0_64
FD96 000078CCFCC07800 5875 DB OOOH.000H.078H.OCCH,OFCH.OCOH,078H.000H j L.C. E o_65
FDI:ilE 386C60F06060FOOO 5876 DB 038H.06CH,060H.OFOH.060H,060H.OFOH.000H ; L.C. F D_66
FUM 000076CCCC7COCF6 5877 DB OOOH.OOOH.076H,OttH,OCCH,07CH,OOCH.OF8H J L.C. G o_67
FDAE E0606C766666E600 5878 DB OEOH,060H,06CH.076H.066H.066H.OE6H.OOOH ; L.C. H 0_68
FDB6 3000703030307800 5879 DB 030H,OOOH,070H,030H,030H,030H,078H,OOOH ; L.C. I o_69
FUBE OCOOOCOCOCCCCC78 5880 DB OOCH,OOOH,OOCH,OOCH,OOtH,OCCH,OCCH,078H L.C. J 0_6A
Foe6 E060666C786CE600 5881 DB OEOH.060H.066H,06CH.078H,06CH,OE6H,OOOH I l.C. K 0_6B
FDCE 7030303030307800 5882 DB 070H,030H,030H,030H.030H.030H,078H,OOOH L.t. l D_6C
FOD6 OOOOCCFEFED6CbOO 5883 DB OOOH,OOOH,OCCH,OFEH,OFEH,OD6H,OC6H,OOOH L.C. M o_60
FDDE OOOOF8CCCCCCCCOO 5884 DB 000H,OOOH,OF8H,OCCH.OCCH.OCCH,OCCH,OOOH L.C. N 0_6E
FDE6 000078CCCCCC7800 5885 DB 000H.000H,078H,OCCH.OCCH,OCCH,078H,OOOH • L.C. a O_~F
FDEE 00000C66667C60FO 5886 DB 000H,OOOH,ODCH.066H,066H,07CH,060H,OFOH I L.C. P o_70
FDFb 000076CCCC7COCIE 5887 DB 000H,OOOH,076H,OCCH,OCCH,07CH.OOCH,OlEH L.C. Q 0_71
FOFE OOOOOC766660FOOO 5888 DB 000H,OOOH,ODCH.076H.066H,060H.OFOH,OOOH L.C. R 0_72
FEat:. 00007CC0780CF800 5889 DB 000H.000H.07CH,OCOH,078H,OOCH.OF8H,OOOH ; L.C. S 0_73
HOE 10307C3030341800 5890 DB OIOH,030H,07CH,030H,030H,034H,018H,000H ; L.C. T o_74
FE 16 OOOOCCCCCCCC7600 5891 DB 000H,OOOH,OCCH,OCCH,OCCH.OCCH,076H,OOOH • L.C. U o_75
FEIE 0000CCCCCC783000 5892 DB 000H,OOOH,OCCH,OCCH,OCCH,078H,030H,OOOH ; L.C. V 0_76
FE26 OOOOC6D6FEFE6COO 5893 DB 000H.OOOH,OC6H,006H,OFEH,OFEH,06CH,OOOH L.C. W 0_77
FEZE OOOOC66C386CC600 5894 DB OOOH,OOOH,OC6H,06CH,03SH,06CH.OC6H,OOOH L.C. X ° 78
FE36 0000CCCCCC7COCF8 5895 DB 000H,OOOH,OCCH,OCCH,OCCH,07CH,OOCH,OF8H L.C. Y 0_79
FEJE 0000FC983064FCOO 5896 DB 000H.OOOH,OFCH,098H.030H,064H,OFCH,OOOH L.C. Z 0_7A
FE46 lC3030E030301COO 5897 DB 0ICH,030H,0'30H,OEOH,030H,030H,OICH,000H {0_7B
FE4E 1818180018181800 5898 DB 018H,OI8H,018H,OOOH,OI8H,018H,018H,OOOH I D_7C
FE56 E030301C3030EOOO 5899 DB OEOH.030H,030H,OlCH,030H,030H,OEOH,OOOH } 0_70
FE5E 76DCOOOOOOOOOOOO 5900 DB 076H,OOCH,OOOH.OOOH,OOOH,OOOH,OOOH,OOOH ; TILDE D_7E
FE66 0010386CC6C6FEOO 5901 DB 000H,010H,038H,06CH,OC6H,OC6H,OFEH,OOOH I DELTA D_7F
5902
5903 ; --- INT lA ---------------------------------------------
5904 ; TIME_OF _DAY
5905 ; THIS ROUTINE AllOWS THE CLOCK TO BE SET/READ
5906
5907 ; INPUT
5908 (AH) = 0 REAO THE ClJ);!RENT ClOCK SETTING
5909 RETlJ);!NS CX = HIGH PORTION OF COUNT
5910 OX = LOW PORTION OF COUNT
5911 AL = 0 IF TIMER HAS NOT PASSED
5912 24 HOURS SINCE LAST READ
5913 <>0 IF ON ANOTHER OAY
5914 (AHI =1 SET THE ClJ);!RENT CLOCK
5915 CX = HIGH PORTION OF COUNT
5916 OX = lOW PORTION OF COUNT
5917 ; NOTE: COUNTS OCCUR AT THE RATE OF
5918 1193180/65536 COUNTS/SEC
5919 (OR ABOUT 18.2 PER SEcmm -- SEE EQUATES BELOl.oII
5920 ; ---------- _____________________________________________ _
5921 ASSUME CS :CODE ,DS:OATA

FE6E 5922 ORG OFE6EH
FE6E 592:3 TIME_OF _DAY PROt FAR
FE6E FB 592:4 ST! ; INTERRUPTS BACK ON
FE6F IE 5925 PUSH OS ; SAVE SEGMENT
FE70 E8CBOO 5926 CALL DDS
FE73 OAE4 5927 DR AH,AH ; AH=O
FE75 7407 5928 JZ T2 ; REAO_TIME
FE77 FECC 5929 DEC ; AH=l
A"
FE79 7416 5930 JZ T3 ; SET_TIME
FE7S 5931 TI: ; TOO_RETURN
FE7B FB 5932 ST! ; INTERRUPTS BACK ON
FE7C IF 5933 POP OS ; RECOVER SEGMENT
FE70 CF 5934 IRET ; RETURN TO CALLER
FE7E 5935 T2: ; READ_TIME
FE7E FA 5936 CLl ; NO TIMER INTERRUPTS WHILE READING
FE7F A07000 5937 MOV AL, TIMER_On
FE82 C606700000 5938 MOV TIMER_OFL.O • GET OVERFLOW. Am RESET THE FLAG
FE87 880E6EOO 5939 MOV CX, TIMER_HIGH
FE8B 88166COO 5940 MOV ox, TIMER_lOW
A-82 System BIOS

LOC OBJ LINE SOURCE
FE8F EBEA 5941 JMP T1 ; TOO_RETURN

FE91 5942 T3: • SET_TIME
FE91 FA 5943 ClI ; NO INTERRUPTS WHILE WRITING
FE92 89166COO 5944 MeV TIMER_LOW.OX
FE96 690E6EOO 5945 MeV TIMER_HIGH.ex ; SeT THE TIME
FE9A C606700000 5946 MOV TIMER_OFLtO J RESET OVERFLOW
FE9F EBDA 5947 JMP T1 ; TOO_RETURN
5948 TIME_OF _DAY ENDP
5949
5950 ; --- -- - - - - --------------- -- -- ----- -------- ----- -- --------
5951 I THIS ROUTINE HANDLES THE TIMER INTERRUPT FROM
5952 CHANNEl 0 OF THE 82:53 TIMER. INPUT FREQUENCY
5953 IS 1.19316 MHZ AND THE DIVISOR IS 65536. RESULTING
5954 IN APPROX. 18.2 INTERRUPTS EVERY SECOND.
5955
5956 ; 11iE INTERRUPT HANDLER MAINTAINS A COUNT OF INTERRUPTS:
5957 I SINCE POWER ON TIME. WHICH MAY BE USED TO ESTABLISH
5958 • TINE OF DAY.
5959 I THE INTERRUPT HANDLER ALSO DECREMENTS THE MOTOR
5960 CONTROL COUNT OF THE DISKETTE, AND WHEN IT EXPIRES,
5961 ; WILL TURN OFF THE DISKETTE MOTOR, AND RESET THE
5962 ; MOTOR RUNNING flAGS.
5963 ; THE INTERRUPT HANDLER WILL ALSO INVOKE A USER ROUTINE
5964 THROUGH INTERRUPT lCH AT EVERY TIME TICK. 11iE USER

5965 ; MUST CODE A ROUTINE AND PLACE THE CORRECT ADDRESS IN :
5966 ; THE VECTOR TABLE.
5967 ; --------------------------------------------------------
FEAS 5966 ORG OFEASH
FEAS 5969 TIMER_INT PROC FAR
FEAS FB 5970 STI INTERRUPTS BACK ON
FEA6 IE 5971 PUSH OS
FEA7 50 5972 PUSH AX
HAB 52 5973 PUSH OX j SAVE MACHINE STATE
FEA9 E89200 5974 CALL DDS
FEAC FF066COO 5975 INC TIMER_lOW ; INCREMENT TIME
FEBO 7504 5976 JHZ T4
FEBl FF066EOO 5977 INC TIMER_HIGH INCREMENT HIGH WORD OF TIME
FEB6 5978 T4:
FEBb 833E6EOOI8 5979 CMP TIMER_HIGH, 0 18H ; TEST FOR COUNT EQUALING 2:4 HOI.JRS
FEBB 7515 5980 JHZ T5 I DISKETTE_CTl
FEBD 813E6C008000 5981 CMP TINER_LOW,OBOH
FEC3 750D 5982 JHZ T5
5983
5984 ;------ TIMER HAS GONE 24 HOURS
5985
FEes 2:6CO 5986 SUB AX,AX
FEe7 A36EOO 5987 MaV TIMER_HIGH ,AX
FEeA A36eoo 5988 MOV TIMER_LOW,AX
FEtD C606700001 5989 MOV TIMER_OFL,l
5990
5991 ; ------ TEST FOR DISKETTE TIME OUT
5992
FED:?: 5993 T5:
FED:?: FEOE4000 5994 DEC MOTOR_COUNT
FE06 7508 5995 JHZ T6 I RETURN IF COUNT NOT OUT
FED8 8D:?:63FOOFO 5996 AND MOTOR_STATUS,OFOH I TURN OFF MOTOR RUNNING BITS
FEOO BCOC 5997 MOV AL,OCH
FEDF BAF2:03 5998 MOV DX.03F2H FOC CTl PORT
FEE2 EE 5999 OUT DX,AL I TURN OFF THE MOTOR
FEE3 6000 T6: I TIMER_RET:
FEE3 C01C 6001 IHT lCH I TRANSFER CONTROL TO A USER ROUTINE
FEES BI)2:0 6002: MOV AL,EOI
FEE7 E620 6003 OLT 020H.AL ; END OF INTERRUPT TO 82:59
FEE9 SA 6004 POP OX
FEEA 58 6005 POP AX
FEEB IF 6006 POP OS ; RESET MACHINE STATE
FEEC CF 6007 IRET ; RETURN FROM INTERRUPT
6008 TIMER_INT ENDP
6009
FEED 31383031 6010 F3B DB '1801',13,10
FEF1 00
FEF2 OA
6011
6012 ; ----------------------------------------------------------------
6013 THESE ARE THE VECTORS WHICH ARE MOVED INTO
6014 THE 8086 INTERRUPT AREA DURING POWER ON.
6015 ONLY THE OFFSETS ARE DISPLAYED HERE. CODE SEGMENT
System BIOS A-83

LOC OBJ LINE SOURCE
6016 WIll BE ADDED FOR All OF THEM. EXCEPT WHERE NOTED

6017 1------·---------------------------------------------------------
6018 ASSUME CS:CODE
FEF3 6019 ORG OFEF3H
FEF3 6020 VECTOR_TABLE LABEL WORD ; VECTOR TABLE FOR HOVE TO INTERRUPTS
FEf3 ASFE 6021 OW OFFSET TIMER_tNT INTERRUPT 6
fEFS 87E9 6022 OW OFFSET KB_nrr I INTERRUPT 9
FEf7 00E6 6023 OW OFfSET D_EOI ; INTERRUPT A
FEF9 00E6 6024 OW OffSET D_EOl ; INTERRUPT B
FEFB DDE6 6025 OW OFFSET D_EOl ; INTERRUPT C
FEFO DOH 6026 OW OFFSET D_EOI i INTERRUPT D
FEFF 57EF 6027 OW OffSET DISK_INT ; INTERRUPT E
FfOI 00E6 6028 OW OFFSET D_EOI ; INTERRUPT F
fFO} 65FD 6029 OW OFFSET VIDEO_IO ; INTERRUPT 10H
FF05 4DF8 6030 OW OFFSET EQUIPMENT INTERRUPT I1H
FF07 41F6 6031 OW OFFSET MEMORY_SIZE_OET INTERRUPT 12H
FF09 59EC 6032: OW OFFSET OISKETTE_IO INTERRUPT 13H
FFOB 39E7 6033 OW OFFSET RS232_IO INTERRUPT 14H
HOD 59F8 6034 OW OffSET CASSETTE_IO INTERRUPT ISH
HOF 2EE8 6035 OW OFFSET KEYBOARD_IO INTERRUPT 16H
FF 11 C2EF 6036 'W OFFSET PRINTER_IO INTERRUPT 17H
6037
FFl3 0000 6038 OW OOOOOH INTERRUPT ISH
6039 OW OF600H MUST BE INSERTED INTO TABLE LATER
6040
FFIS FlE6 6041 OW OFFSET BOOT_STRAP INTERRUPT 19H
FFI76EFE 6042: OW TIME_OF _DAY INTERRUPT IAH -- TIME OF DAY
FF19 53FF 6043 'W ~UMMY_RETURN INTERRUPT ISH -- KEYBOARD BREAK AOOR
FFIB 53FF 6044 OW DUNMY_RETURN INTERRUPT lC -- TIMER BREAK ADDR
FflO A4FO 6045 OW VIDEO_PARMS INTERRUPT 10 -- VIDEO PARAMETERS
FFIF C7EF 6046 OW OFFSET DISK_BASE INTERRUPT IE -- DISK PARMS
FfZl OO~O 6047 OW INTERRUPT IF -- POINTER TO VIDEO EXT
6048
FF23 504152:49545920 6049 02 OB 'PARITY CHECK I ' ,13,10
43484543482031
FF31 00
FF32 0.6.
FF33 20333031 6050 F1 OB , 301',13,10
FF37 00
FF38 OA
FF39 313331 6051 OB '131' ,13,10
FF3C 00
FF3D OA
6052
FF3E 6053 OOS PROC NEAR
FF3E 50 6054 PUSH AX ; SAVE AX
FF3F B84000 6055 MOV AX.DATA
FF42 8E08 6056 MOV OS,AX ; SET DATA SEGMENT
FF44 58 6057 POP AX ; RESTORE AX
FF45 C3 6058 RET
6059 DOS ENOP
6060
6061 1--------------------------------------------------------
6062 TEMPORARY INTERRUPT SERVICE ROUTINE
6063 ; --------------------------------------------------------
FF47 6064 ORG OFf47H
FF47 6065 011 PROt NEAR
fF47 8401 6066 MOV AH,I
FF49 50 6067 PUSH AX , SAVE REG AX CONTENTS
FF4A BOFF 6068 MOV AL,OFfH I MASK ALL INTERRUPTS Off
FF4C E621 6069 OUT INTAOl,AL
FF4E B020 6070 MOV AL,EO!
FFSO E620 6071 OUT INTAOO,AL
FFS2 58 6072 POP AX ; RESTORE REG AX CONTENTS
FFS3 6073 DUMMY_RETURN: ; NEED IRET FOR VECTOR TA.BLE
FFS3 CF 6074 IRET
6075 011 ENDP
6076
6077 ;-- INT 5 ---------------------------------------------------------------
6078 THIS LOGIC WILL BE INVOKED BY INTERRUPT 05H TO PRINT THE
6079 SCREEN. THE CURSOR POSITION AT THE TIME THIS ROUTINE IS INVOKED
6080 WILL BE SAVED AND RESTORED UPON COMPLETION. THE ROUTINE IS
6081 INTENDED TO RUN WITH INTERRUPTS ENABLED. IF A SUBSEQUENT
6082 'PRINT SCREEN' KEY IS DEPRESSED DURING THE TIME THIS ROUTINE
6083 IS PRINTING IT WILL BE IGNORED.
6084 ADDRESS 50:0 CONTAINS THE STATUS OF THE PRINT SCREEN:
6085
A-84 System BIOS

LOC OBJ LINE SOURCE
6086 50:0 =0 EITHER PRINT SCREEN HAS NOT BEEN CALLED

6087 OR UPON RETURN FROM A CALL THIS INDICATES
6088 A SUCCESSFUL OPERATION.
6089 =1 PRINT SCREEN IS IN PROGRESS
6090 =2:55 ERROR ENCOUNTERED DURING PRINTING
6091 ;------------------------------------------------------------------------
60n ASSUME es:eOOE.OS:XXOATA
FF54 6093 ORG OFF54H
FF54 6094 PRINT_SCREEN PRoe FAR
FF54 FB 6095 STI ; MUST RUN WITH INTERRUPTS ENABLED
FFS5 IE 609b PUSH OS ; MUST USE 50:0 FOR DATA AREA STORAGE
FF5b 50 6097 PUSH AX
FFS7 53 6098 PUSH BX
FF58 51 6099 PUSH CX I WILL USE THIS LATER FOR CURSOR LIMITS
FF59 52 6100 PUSH OX ; WILL HOLD Ct..IRRENT Ct..IRSOR POSITION
FF5A 885000 6101 MOV AX .XXDATA I HEX 50
FF5D 8E08 6102: NOV OS.AX
FFSF 803EOOOOOI 6103 CMP STATUS_BYTE. 1 I SEE IF PRINT ALREADY IN PROGRESS
FF64 745F 6104 JZ EXIT I JUMP IF PRINT ALREADY IN PROGRESS
FF6b e006000001 6105 MOV STATUS_BYTE, 1 ; INDICATE PRINT NOW IN PROGRESS
FF6B B40F 6l0b MOV AH.15 ; WILL REQUEST THE CURRENT SCREEN MODE
FF6D COlO 6107 INT 10H [ALl=t1ODE
6108 [AH1=NlIt1BER COLl.It1NS/LINE
6109 tBHJ=VISUAL PAGE
6110 ; ----------------------------------------------------------------
6111 AT THIS POINT WE KNOW THE COLt.n1NS/LINE ARE IN
611l [AX 1 AND THE PAGE IF APPLICABLE IS IN IBH I. THE STACK
6113 HAS DS,A.X.8X,CX.OX PUSHED. [All HAS VIDEO MODE
6114 ; ----------------------------------------------------------------
FF6F BAce 6115 MOV CL.AH ; WILL MAKE USE OF [ex J REGISTER TO
FF71 8519 6116 MOV CH,l5 ; CONTROL ROW & COLUMNS
FF73 E85500 6117 CALL CRlF I CARRIAGE RETURN LINE FEED ROUTINE
FF76 51 6118 PUSH ex ; SAVE SCREEN BOUNDS
FF77 9403 6119 MOV AH , 3 ; WILL NOW READ THE CURSOR.
FF79 COlO 6110 WT 10H I AND PRESERVE THE POSITION
FF7B 59 6111 POP CX ; RECALL SCREEN BOUNDS
FF7C 52 61Zl PUSH OX ; RECALL {BHI=YISUAL PAGE
FF7D 3302 61Z3 XOR OX.OX ; WILL SET CURSOR POSITION TO [o.OJ
6 Il4 ; -------- -- ----- - ---- - - - -- ---- ------ ---- - -- - - - - - -- - - ---------- ---
61Z5 THE LOOP FROM PRIlO TO THE INSTRUCTION PRIOR TO PRIZO
61Z6 IS THE lOOP TO READ EACH CURSOR POSITION FROM THE
6127 SCREEN AND PRINT.
61 Z8 ; ----------------------------------------------------------------
FF7F 6129 PRIlO:
FF7F 6402: 6130 HOV AH,Z I TO INDICATE CURSOR SET REQUEST
FFSt COlO 6131 INT IOH ; NEW CURSOR POSITION ESTABLISHED
FFS3 6408 6132 HOV AH.8 ; TO INDICATE READ CHARACTER
FFSS COlO 6133 INT IOH ; CHARACTER NOW IN [ALI
FFS7 OACO 6134 OR AL.AL I SEE IF VALID CHAR
FF89 7502: 6135 JNZ PRII5 ; JUMP IF YALIO CHAR
FF6B B020 6136 HOV AL, • ; MAKE A BlANK
FF80 6137 FRII5:
FFao 52 6138 PUSH OX ; SAYE CURSOR POSITION
FFeE HO, 6139 XOR DX.OX ; INDICATE PRINTER 1
FF90 32E4 6140 XOR AH.AH I TO INDICATE PRINT CHAR IN [ALI
FF92 C017 6141 INT 17H ; PRINT THE CHARACTER
FF94 SA 6142 POP OX ; RECALL CURSOR POSITION
fF95 F6C42:5 6143 TEST AH. Z5H I TEST FOR PRINTER ERROR
FF9S 7521 6144 JNZ ERRIO ; JUMP IF ERROR DETECTED
FF9A FEtl 6145 INC DL ; ADVANCE TO NEXT COLUMN
FF9C 3ACA 6146 CMP CL,OL ; SEE IF AT END OF LINE
FF9E 75DF 6147 JNZ PRIlO ; IF NOT PROCEED
FFM 3202 6148 XOR DL,DL ; BACK TO COLUMN 0
HAl 8AE2 6149 MaY AH,DL I {AH]=O
FFA4 52: 6150 PUSH OX ; SAVE NEW CURSOR POSITION
FFAS E82300 6151 CALL CRLF ; LINE FEED CARRIAGE RETURN
fFA8 SA 615l POP OX ; RECALL CURSOR POSITION
FFA9 FEC6 6153 INC DH ; ADVANCE TO NEXT LINE
FFAB 3AEE 6154 eHP CH.DH ; FINISHED?
HAD 7500 6155 JNZ PRIlO ; IF NOT CONTINUE
FFAF 6156 PRIZO:
FFAF SA 6157 POP OX ; RECALL CURSOR POSITION
FF80 6402 6158 HOV AH.2 I TO INDICATE CURSOR SET REQUEST
FFS2: COlO 6159 INT IOH I CURSOR POSITION RESTORED
FFB4 C606000000 6160 HOV STATUS_BYTE ,0 INDICATE FINISHED
FFB9 EBM 6161 JHP SHORT EXIT ; EXIT THE ROUTINE
FFBe 6162 ERRI0:
System BIOS A-85

LOC OBJ LINE SOURCE
FFeB SA 6163 POP OX I GET CURSOR POSITION

FFBt 8402 6164 HOV AH,Z I TO REQUEST CURSOR SET
FFBE COlO 6165 INT 10H ; CURSOR POSITION RESTOf;!ED
FFeD 6166 ERRZO:
FFeo C6060000FF 6167 HOV STATUS_BYTE,OffH I INDICATE ERROR
FFC5 6166 EXIT:
FFCS 5.1. 6169 POP OX ; RESTORE ALL THE REGISTERS USED
FFC6 59 6170 POP ex
FFC7 58 6171 PDP BX
FFee 58 61n PDP AX
FFC9 1 F 6173 POP 05
FFCA CF 6174 IRET
6175 PRINT_SCREEN ENlJP
6176
6177 1------ CARRIAGE RETURN, LINE FEED SUBROUTINE
6178
FFCB 6179 CRLF PROt NEAR
FFee 3302 6180 XOR OX,OX I PRINTER 0
FFeD 32E4 6181 XOR AH,AH ; WILL NOW SEND INITIAL IF,CR
6182 ; TO PRINTER
FFCF BOOA 6183 HDV AL,12Q ; LF
FFOI C017 6184 INT 17H ; SEND THE LINE FEED
FFD3 32E4 6185 XOR AH ,AH ; NOW FOR THE CR
FFD5 BODO 6186 HOV AL.t5Q ; CR
FF07 C017 6187 INT 17H ; SENO THE CARRIAGE RETURN
FFD9 C3 6186 RET
6189 CRlF ENDP
6190
FFOA 50415249545920 6191 Dl DB 'PARITY CHECK 2' ,13,10
434845434B2032
FFE8 00
FFE<;I OA
FFEA 363031 61n FJ DB '601',13,10
FFEO 00
FFEE OA
6193
6194 CODE ENlJ5
6195
6196 ; --------------------------------
6197 POWER ON RESET VECTOR
6198 ; ----------- ------------- -- ------
6199 VECTOR SEGMENT AT OFFFFH
6200
6201 ; ----- POWER ON RESET
6202
0000 EA5BEOQOFO 6203 JHP RESET
6204
0005 31302F3Z372F38 6205 DB '10/27/82 ' I RELEASE MARKER
32
6206 VECTOR ENlJ5
6207 END
A-86 System BIOS

LOC OBJ LINE SOURCE
$TITLEf FIXED DISK BIOS fOR IBH DISK CONl'RDlLER I
J-- tHT 13 -----------.------------------------------------------
; FIXED DISK 110 INTERFACE
TillS INTERFACE PROVIDES ACCESS TO 5 1/4" FIXED DISKS

THROUGH THE IBH FIXED DISK CONTROLLER.
10 1- --- - ---------------- ----- - ---- ----- - ------- - -- -- --- ----- -------

11
1Z , ---- - - ------------ -- - ----- ---- - -- - - - -- ------- - - - - --- -- --- --- ----
13 THE BIOS ROUTINES ARE MEANT TO BE ACCESSED THROUGH
14 SOFTWARE INTERRUPTS ONLY. ANY ADDRESSES PRESENT IN
15 THE LISTINGS ARE INCLUDED ONLY FOR COMPLETENESS.
16 HOT FOR REFERENCE. APPLICATIONS WHICH REFERENCE
17 ABSOLUTE ADDRESSES WITHIN THE CODE SEGMENT
18 VIOLATE THE STRUCTURE AND DESIGN OF BIOS.
19 1- -- - - ------------- - - - - -- - - ------- - -- ---------- -- ----------------
2.
.21
22
24
25
; INPUT (AH = HEX VALUE)
(AHI=OO RESET DISK (DL = 80H.81H) / DISKETTE

(AHI=Ol READ TltE STATUS OF THE LAST DISK OPERATION INTO (AU
NOTE: DL < 80H - DISKETTE
26 Dl > BOH - DISK
27 (AIO=02: READ THE DESIRED SECTORS INTO MEMORY
28 IAHI=03 WRITE THE DESIRED SECTORS fROt1 MEMORY
2. UH 1=04 VERIFY THE DESIRED SECTORS
3. IAH)=05 FORMAT THE DESIRED TRACK
31 I AH 1=06 FORMAT THE DESIRED TRACK AND SET BAD SECTOR FLAGS
32 I AH )=07 FORHAT THE DRIVE STARTING AT THE DESIRED TRACK
33 (AH )=08 RETURN THE C~RENT DRIVE PARAMETERS
34
3S I AH )=09 INITIALIZE DRIVE PAIR CHARACTERISTICS
36 INTERRUPT 41 POINTS TO DATA BLOCK
37 I AH )=OA READ LONG
38 (AH)=OB IoRITE LONG
3' NOTE: READ AND WRITE LONG ENCOI1PASS 512 • 4 BYTES ECC
4. (AH )=OC SEEK
41 (AHI=OD ALTERNATE DISK RESET (SEE Dl)
42 (AH )=OE READ SECTOR BUFFER
.43
44
46
47
(AH )=DF WRITE SECTOR BUFFER.
IRECO\"I1ENDED PRACTICE BEFORE FORMATTING)
IAHI=10 TEST DRIVE READY
UH 1=11 RECALIBRATE
(AH 1=12 CONTROLLER RAM DIAGNOSTIC
48 (AH )=13 DRIVE DIAGNOSTIC
4. (AH )=14 CONTROLLER INTERNAL DIAGNOSTIC
5.
51 REGISTERS USED fOR FIXED DISK OPERATIONS
52
53 (DLI DRIVE HUt1BER (BOH-B7H FOR DISK, VALUE CHECKED)
54 (DH) HEAD NUMBER 10-7 AllOWED. NOT VAlUE CHECKED)
55 IC!"!J CYlINDER HUMBER (0-1023. NOT VALUE CHECKEDHSEE ell
56 tcU - SECTOR tM1BER (1-17, HOT VALUE CHECKED)
57
58 NOTE: HIGH 2: BITS OF CYLINDER NUt1BER ARE PLACED
5'6. IN THE HIGH 2 BITS OF THE CL REGISTER

110 BITS TOTAL)
61 (ALI - NU1BER OF SECTORS (MAXlMUt1 POSSIBLE RANGE 1-80H.
62 FOR READ/WRITE LONG 1-79tO
63 (INTERLEAVE VALUE FOR FORHAT 1-1601
64 (ES:BXI - ADDRESS OF BUFFER FOR READS AND WRITES,
65 (NOT REQUIRED FOR VERIFY)
66 J
67 I OUTPUT
65 AH = STATUS OF CURRENT OPERATION
69 STATUS BITS ARE DEfINED IN THE EQUATES BELOW
70 CY = 0 SUCCESSFUL OPERATION (AH=O ON RETURN)
71 CY = 1 FAILED OPERATION (AH HAS ERROR REASON)
72
73 NOTE: ERROR llH INDICATES THAT THE DATA READ HAD A RECOVERABLE
74 ERROR WHICH WAS CORRECTED BY THE ECC AlGORITHH. mE DATA
75 IS PROBABLY GOOD. HOWEVER THE BIOS ROUTINE IHDICATES AN
76 ERROR TO ALLOW THE CONTROLLING PROGRAM A CHANCE TO DECIDE
17 FOR ITSELF. THE ERROR HAY NOT RECUR IF THE OUA IS
Fixed Disk BIOS A-87

LOC OBJ LINE SOURCE
78 REWRITTEN. (ALI CONTAINS THE BlMST LENGTH.

7.
80 IF DRIVE PARAMETERS WERE REQUESTED.
81
82 DL = NUt'BER OF CONSECUTIVE ACKNOWLEDGING DRIVES ATTACHED «0-2)
83 (CONTROLLER CARD ZERO TAlLY ONLY)
8. DH = tlAXltruM USEABLE VALUE FOR HEAD HUt1BER
CH = ttAXltu1 USEABLE VALUE FOR CYLINDER NUt'BER
S.
8S
87
Cl = I1A.XII'M1 USEABLE VALUE FOR SECTOR NlI1BER
AND CYLINDER NIA1BER HIGH BITS
00
8. REGISTERS WILL BE PRESERVED EXCEPT WHEN THEY ARE USED TO RETURN
.,
•0
'i2
IHFORI1ATION •
HOTE; IF AN ERROR IS REPORTED BY THE DISK CODE. THE APPROPRIATE

93 ACTION IS TO RESET THE DISK. THEN RETRY TIlE OPERATION.
.
.. I
95 1------- --------- ------- ----------------- - -- ----- ---- ---- - --- ------- -- ---
DOFF .7 SENSEJAIL EOU OFFH I SENSE OPERATIot~ FAILED
ooee UNDEF _ERR EQU OBBH I tklDEFItIED ERROR OCCURRED

'0
00&0
0040
••
lDO
TIME_OUT
BAD_SEEK
EQU
EQU
OOH
'DH
I ATTACHMENT fAILED TO RESPOf-()
J SEEK OPERATIOH fAILED
0020 101 BAD_CNTLR EQU 2DH J COHlROLLER HAS FAILED
0011 102 DATA_CORRECTED EQU 11H I ECC CORRECTED DATA ERROR
0010 103 BAD_ECC EQU lOH I BAD ECC ON DISK READ
OOOB 10' BAD_TRACK EQU DBH ; BAD TRACK FLAG DETECTED

DMA_BOUNDARY DOH I AHEMPT TO DttA ACROSS 64K BOUtmARY'
0009 lOS Et'"
INIT_FAIl D7H I DRIVE PARAMETER ACTIVITY' fAILED
0007 10' Et'"
0005 107 BAD_RESET EQU OSH I RESET FAILED
0004 100 RECORD_NOTJHD EOU D'H I REQUESTED SECTOR HOT FOl/tI)
GOOl 10. BAD_ADDR_MARK EQU D2H I ADDRESS MARK NOT FOUND

0001 110 BAD_CtI) EOII DlH ; BAD tOt1t1AtlD PASSED TO DISK 110
111
112 J ----------------------------------.-----
113 INTERRUPT Atm S1'ATUS AREAS
114 ,----------------------------------------
11S
11. cumlY' SEGMENT AT 0
0034- 117 DO. ODH*4- I FIXED DISK ItITERRUPT VECTOR
0034 118 HDISK_INT LABEl. DWORD
Qolte OR.
OQ4e "'
120 DRG_VECTOR
13H~
LABEl OWORO
I DISK ItHERRUPT VECTOR
0064 121 DO. 19H*4 ; BOOTSTRAP ItnERRUPT VECTOR

0064 122 BOOT_VEC LABEL DWORD
0078 123 DO. lEH*4 I DISKETTE PARAMETERS
0078 12. DISKETTE_PARM LABEL aWORD
0100 12S DO. 0401i*4 I HEW DISKETTE INTERRUPT VECTOR
0100 1£. DISK_VECTOR LABEL DWORD
0104 127 DO. 041H*4 I FIXED DISK PARAMETER VECTOR
0104 128 HF_TBL_VEt LABel DWORD
7COO 1£. DO. 7COOH I BOOTSTRAP LOADER VECTOR
7COD 13D BOOT_LOCN LABel FAR
131 OUt1HY ENDS
132
133 DATA SEGMENT AT 401i
0042 13' OR. '2H
0042 13S CND_BLOCK LABEL BYTE
0042 (7 11) 13. HD_ERROR DB 7 DUP(?) I OVERLAYS DISKETTE STATUS
DDbt 137 DO. 06CH
DObe 1111 130 TIMER_lOW 0" I TIMER lOW WORD
0072 13' OR. 72H
,.0
0072: 1111
0074 ,., RESET_FLAG
OR.
OW
74H
I 1234H IF KEYBOARD RESET UNDERWAY
0074 11 142 DISK_STATUS DB ; FIXED DISK STATUS BYTE

0075 ?? ,.3 HF _tu'1 DB I tWIT OF FIXED DISK DRIVES
..
0076 11 14. CONTROL_BYTE DB ; ConTROL BYTE DRIVE OPTIONS
"S
0077 11
,,.7 PORT_OFF
DATA ENDS
DB I PORT OFFSET
,.0 CODE SEGMENT

14'
150 J ________ w ------------ ------- ----------- ----- ----- -------
151 I HARDWARE SPECIFIC VALUES

152
153 I - CONTROllER 110 PORT
154 > WHEN READ FROM:
A-88 Fixed Disk BIOS

LOC OBJ LINE SOURCE
155 HF _PORT+D - READ DATA (FRDtt CONTROLLER TO CPU)

156 HF _PORT+l - READ CONTROLLER HARDWARE STATUS
151 I CONTROLLER TO CPU)
158 HF _PORT.! - READ CONFIGlRATIOH SWITCHES
159 HF _PORT+3 - NOT USED
160 > NItEN WRITTEN TO!
161 HF _PORT+O - WRITE DATA (fROt1 CPU TO CONTROLLER)
162 HF _PORHl - CONTROLLER RESET
163 HF _PORT.! - GENERATE CONTROLLER SELECT PULSE
164 HF _PORT+3 - WRITE PATTERN TO DI1A AN) INTERRUPT
165 MASK REGISTER
I ••
167 J - - - --------- - -- - -- ----- -- -- ------ --- - - - .--- -- -- - -- - --- --
I ••
0'32.0 I •• HF _PORT EOU 0320H I DISK PORT
0008 17. RI_BUSY EOU 000010008 I DISK PORT 1 BUSY BIT
0004 171 RI_BUS EOU 000001008 COHMAND/DATA BIT
0002 172 Rl_IOMODE EOU 000000108 HOOE BIT
0001 173 EOU 00000001B REQUEST BIT
174
0047 17' DHA.READ EOU 01000111B I CHAN-IEl 3 1047H)
004S 17. DHA_WRITE EOU 01001011B I CHANNEL 3 I04BHI
0000 177 DHA EOU o I DHA ADDRESS
0062 17. OMA.HIGH EOU 082H I PORT FOR HIGH it BITS OF DttA
17'
0000
0001 ,.,
I •• TST_ROY_CHO
RECAL_CI"I)
EQU OOOOOOOOB I CNTLR READY (DOH)
RECAL 101H)
0003 I., SENSE_CHO
EQU
EQU
00000001B
000000118 SENSE (OlH)
0004 ,.3 fHTDRV_CHD EQU 00000100B DRIVE (04HI
ODDS ,.4 CHK_TRK_CHD EQU 000001018 T CHK 105HI
0006 I •• fNTTRK.CMD EQU 00000110B TRACK (MHI
0007
0006
OOOA
OOOB ,
....
I ••
,.7
,
FMTBAD_CHD
READ_tND
WRITE_CHO
SEEK.CHO
EQU
EQU
EQU
EQU
000001118
000010008
000010108
000010118
BAD
READ
(07H)
(OSHI
WRITE 10AHI
SEEK (OBH I
Dooe I •• INIT_DRV_CND EQU 000011008 IMIT (OCH)
DODD
DOOE '"
I.'
RD_ECC_CND
RD_BUFF _CMD
EQU
EQU
000011018
000011108
BURST I DOH)
BUFFR (OEH)
OOOF ,.3 WR_8UFF _CHD EQU 000011118 BUFFR (OFH)
ODED ,.4 RAM.DIAG_Ctl) EQU 111000008 RAM IEOH)
DOn
OOE4 '"
".
CHK_ORV_CMD
CNTLR_DIAG_CMD
EQU
EQU
111000118
111001008
DRV (ElH)
CMTLR IE4H)
ODES ,.7 RD.LONG_CI1D EQU 111001018 RLONG IE5H)
..
00E6 I •• WR_LONG_CND EQU 111001108 WLONG IE6H)
0020 ,,.,
'" INT_CT~PORT EQU 20" J 8259 CONTROL PORT
0020 EOI EQU 20" ; END OF INTERRUPT CotIMAND
2"
0008 2.3 EOU
0002 2" EOU
2 ••
••• ASSUME CS:CODE

0000
0000 55
"7
2 ••
ORG
DB
OH
055H I GENERIC BIOS HEADER
0001 AA
0002 10
•••
21'
DB
DB
OAAM
loa
211
212 ; - ----- --- --------------- --- -- --------- - - --- - ------- --- -- - - ------
213 I FIXED DISK 110 SETUP
21.
215 - ESTABLISH TRANSfER VECTORS FOR TH!: FIXED DISK
216 I - PERFORM POWER ON DIAGNOSTICS
217 SHOULD AN ERROR OCCUR A "1701" MESSAGE IS DISPLAYED
21.
21 9 1------------- - ---------------.-•• -.--------------- - - -- ------- ---
220
0003 .21 PROC FAR
0003 EBIE .22 SHORT L3
0005 35303030303539 223 '5000059 (CJCOPYRIGHT IBM 1962' J COPYRIGHT NOTICE
2D284329434F50
59524947485420
20494240203139
3832
0023 224 l3:
22. ASSUNE DS:DUHMY
0023 2BCD 22. SUB /Of..,/lY. J ZERO
0025 8E08 227 Hav DS,AX

LOC OBJ LINE SOURCE
0027 FA "8 CLI

0028 A14COO "9 HOV AX,WORD PTR ORG,:..VECTOR I GET DISKETTE VECTOR
0028 AlOOOI 230 HOV WORD PTR OISK_VECTOR,AX I INTO INT 40H
002E A14EOO 231 MOV AX,WORD PTR ORG_VECTOR+2
0031 A30201 2" HOV WORD PTR OISK_ VECTOR+2, AX
0034 C7064C005602 233 HOV WORD I"TR ORG_VECTOR, OFFSET DISK_IO i HOISK HANDLER
OOJA 8CO[(.[00 234 HOV WORD PTR ORG_ VECTOR .. Z ,CS
DOJE B86007 235 HOV AX, OFFSET liD_lilT I HDISK INTERRUPT
0041 A33400 23. MOV WORD PTR HDISK_INT ,AX
0044 8eOnbOQ 237 HOV WORD PTR HDISK_INHZ ,CS
0048 C7066400860 I 238 HOV WORD PTR BOOT_VEC,OFFSET BOOT_STRAP ; BOOTSTRAP
004E 8CO[6600 239 HOV WORD PTR Boor_VEC"Z,CS
0052 C70b0401E703 240 HOV WORD PTR Hr _TBL_VEC,OFFSET FD_TBL I PARAMETER TBL
0058 8eOE0601 201 HOV WORD PTR HF _TBL_VEC .. Z,CS
Dose FB 242 STI
243
244 ASSUI'IE OS:OATA
0050 884000 245 HOV AX.DATA I ESTABLISH SEGMENT
0060 8E08 24. MOV OS.AX
0062 C606740000 247 MOV DISK_StATUS.O ; RESET THE STATUS INOICATOR
0067 C606750000 248 MOV ttF_NUM.O ; ZERO COUNT OF DRIVES
OObC C606430000 249 HOV CND_BLOCK"l.O ; DRIVE ZERO. SET VALUE IN BLOCK
0071 C606770000 250 MOV PORT_OFF.O I ZERO CARD OFFSET
251
0076 892:500 252 ~IOI/ CX,25H I RETRY COUNT
0079 253
0079 E8F200 254 CALL HD_RESET_l I RESET CotlTROLtER
007e 7305 255 JHC L7
DOlE E2F9 25. LOOP L4 i TRY RESET AGAIN
0080 [9aFDO 257 JHP
0083 258 L7:
0083 890100 259 HOV eX,I
0086 8A8000 2.0 HOV DX.80H
2'1
0089 880012 262 HOV AX,I20011 ; CONTROLLER DIAGNOSTICS
OOBe con 2.3 INT Btl
DOSE 7303 264 JNC P7
0090 E9AFOO 265 JHP ERROR_EX
0093 2•• P7:
0093 880014 267 HOV AX.14001i I CotlTROLLER DIAGNOSTICS
0096 con 268 INT 13H
0098 7303 269 Jt~C P9
G09A [9.4.500 270 JHP ERROR_EX
"'10 271 P9:
0090 C7066COOOOOO 272 HOV TIMER_LOW.O I ZERO TIMER
00A3 AI7200 273 MOV AX,RESETJLAG
00A6 303412 274 CHP AX,123411 I KEYBOARO REseT
00A9 7506 275 JIIE P8
00A8 (7066C009.4.01 27. tlOV TIt'iER_LOW.410D I SI<:IP WAlT ON RESET
00B1 277 P8:
OOBI [42:1 278 III AL,021H ; TIMER
DOB3 24fE 279 AlID AL,GFEIl I ENABLE TIt1ER
00B5 [621 280 OUT 021H,AL ; START lIMER
00B7 281
0087 E88400 282 CALL tiO_RESET_I ; RESET CONTROLLER
D08A n07 283 JC PIO
OOBe 680010 284 MOV AX.IOOOH ; READY
COBF con 285 WT 13B
00C1 730B 28. Jtle P2
00C3 287 PIa:
OOC3 A16eDO 288 HOV
OOC6 30BEOI
00C9 72Ee
Dace [87590
289
290
291
J.
CMP
JHP
AX.4460 I ~5 SECONDS
DaCE 292 P2:

OOCE 890100 293 ~IOV CX.I
0001 BMODO 294 HOV OX .80H
295
0004 B80011 29. 110V AX.ll DOH ; RECALIBRATE
0007 con 297 INT 131l
0009 7267 298 JC ERROO_EX
299
OODB B80009 300 HOV AX.OQOOH ; SET DRIVE PARAMETERS
OODE con 301 INT 131i
ODED 7260 302 JC ERROR_EX
303
00E2 B800C8 304 HOV AX.OC80011 I DMA TO BUFF ER

LOC OBJ LINE SOURCE
00E5 8EtO 305 I10V ES,AX I SET SEGtt~NT

00E7 2BDB 30. SUB aX,ex
DOn 88000F 307 I10V AX.OfOOII I WRITE SECTOR BUFFER
OOEt COll 308 INT 13"
OOEE 7252 30' JC ERROR_EX
310
OOfO FE067500 311 INC Hf_HUM ; DRIVE ZERO RESPONDED
312
OOF4 BA1302 313 HOV DX,21lH I EXPANSION BOX
DOH BODO 314 HOV AL,O
OOF9 EE 315 OUT DX.AL I TURN BOX OFF
OOFA 8A2103 31. nov DX.321H ; TEST IF CONTROLLER
OOFD EC 317 IN AL,DX J ••• IS IN THE SYSTEM WIT
OOFE 240F 318 ANO AL,OFH
0100 leOF 31. CHP AL,OfH
0102 7406 320 J' BOl( ON
0104 C7066CQOA401 321 HOY TII1ER_LOW,420D J CotrTROlLER IS IN SYSTEH UNIT
OlOA 322 BOX_ON:
010A 8A1302 323 HOY DX,213H ; EXPANSION BOX
0100 BOFF 324 HOY "l,OFFH
OIOF EE 325 OUT DX,Al ; TURN 80X ON
32.
0110 890100 327 MOV ex,. I ATTEMPT NEXT DRIVES
0113 BA6100 328 HOY DX,081H
0116 32' Pl:
0116 ZBCO no sue AX.AX I RESET
0118 CDll nl INT 13N
OllA 7240 332 JC POD_DOHE
Olle B800ll 333 HOv AX,01100H J RECAL
OllF CDll 334 INT 13"
0121 730B 335 JHe P5
0123 AlbeDO 33' MOV AX. TIMER_LOW
01Z6 30BEOI 337 CMP AX,446D 25 SECONDS
0129 72EB 336 JB P3
012B EB2F90 33' JHP POD_DONE
OlZE 340 P5:
012E 880009 341 HOV AX,0900H I INITIALIZE CHARACTERISTICS
0131 tDl3 342 INT 13N
0J33 7227 343 JC POO_DONE
0135 FE067500 344 !tIC HF _HUH ; TALLY ANOTHER DRIVE
0139 81FA8100 345 eHP OX, r eOH + S_MAXJILE - 1)
0130 7310 34. JA' POD_DONE
013F 42 347 INC OX
0140 EBD4 348 JHP P3
34.
350 ;-~--- POD ERROR
351
0142 352 ERROR_EX:
0142 BDOFOO 353 MOV SP.OFH ; POD ERROR FLAG
0145 2BCO 354 SUB AX,AX
0147 88FO 355 HOV 5I,AX
0149 89060090 35. HOV CX,F17L ; MESSAGE CHARACTER CalM
0140 8700 357 HOY BH.O I PAGE ZERO
014F 358 OUT_CH:
Ol4F 2E8A846801 35. HOV Al,CS:Fl71SII I GET BYTE
0154 B40E 360 MOY AH.140 I VIDEO OUT
0156 COlO 361 ItIT 10H I DISPLAY CHARACTER
0158 46 362 INC SI I NEXT CHAR
0159 E2F4 3.3 lOOP OUT_CH I DO MORE
0158 F9 364 STC
DISC 36~ POD_DONE:
015C FA 36. ClI
0150 E421 367 IN Al.021H ; BE SURE TIMER IS DISABLED
015F OCOI 368 OR AL,OlH
0161 E621 36. OUT 021H.AL
0163 FB 370 STI
0164 E8A500 371 CAll DSBL
0167 CB 372 RET
373
0168 31373031 374 Fl7 .B '1701' ,ODH,OAH

LOC OBJ LINE SOURCE
Olbt 00
0160 0'\
0006 375 F17l EOU $-F17
37.
016E 377 HD_RESET_I PROt NEAR
016E SI 378 PUSH ex ; SAVE REGISTER
016F 52 379 PUSH ox
0170 Fe 3.0 CLC I CLEAR CARR'(
0171 890001 381 MOV eX,OIDOH I RETRY COlJt.lT
0174 382 L6:
0174 E80706 383 CALL PORT_I
0177 EE 384 OUT DX,Al ; RESET CARD
0178 Ee,030b 385 CAll PORT_l
0178 EC 38. IN AL,DX ; C!lEeK STATUS
Ol7t 2402 387 ANIl AL,2 I ERROR BIT
Ol7E 7403 388 JZ R3
0160 E2F2 389 LOOP L.
0182 F9 390 STC
01133 J9l R3:
0183 5A. 392 POP ox , RESTORE REGISTER
0184 59 393 POP CX
0185 Cl 394 RET
395 HD_RESET_l ENDP
39.
:97 DISK_SETUP ENOP
398
399 ,----- INT 19 -----------------------------------------".---------
400
401 1 INTERRUPT 19 BOOT STRAP LOADER
402
403 THE fIXED DISK BIOS REPLACES THE !IlrERRUrT 19
404 BOOT STRAP VECTOR IHTH A POINTER 10 THIS Boor RUUHNE
405 RESET THE DEFAULT DISK ANO DISKETTE PARAMETER VECTOOS
406 THE BOOT BLOCK TO BE READ IN WILL BE ATTEMPrED FROM
407 CYLINDER 0 SECTOR 1 OF THE DEVICE.
408 THE BOOTSTRAP SEQUENCE IS:
409 ;;> ATTEMPT TO LOAD FROM THE DISKETTE INTO THE BOOT
410 LOCATION (0000:7COO) ANO TRAtlSFER cmUROl THERE
411 > If THE DISKETTE FAILS THE FIXED DISK IS TRIED FOR A.
412 VALID BOOTSTRAP BLOCK. A VALID BOOT BLOCK ON THE
413 FIXED DISK CONSISTS OF THE BYTES 055H OAAH AS THE
414 LAST TWO BYTES OF TIlE BLOCK
415 > IF THE ABOVE FAILS CONTROL IS PASSED TO RESIDENT BASIC
41.
417 1----------- --- -------------------------- ------ ------------------
418
0186 419 BOOT_STRAP:
420 ASSUME OS: DUt1MY I ES:OUNMY
0166 28CO 4" SUll AX,AX
0188 8E08 422 MaV OS,AX I ESTABLI511 SEGMENT
423
4Z4 ;----- RESET PARAME1ER VECTORS
4ZS
018A FA. 42. CLI
0188 C7060401E703 427 MaV WORD PTR HF_TBL_VEC. OFFSET FO_TBL
0191 8eOf0601 428 HOV I~ORD PTF! HF _TBl_VEC.Z. CS
0195 C70678000102 429 MOV WORD PTR DISKETTE_PARH, OFFSET DISKETTE_TBl
0198 8COE7... 00 430 MOV HORD PTR DISKETTE_PARM.Z, CS
019F FB 431 srr
432
433 ;----- ATTEMPT BOOTSTRAP FROM DISKETTE
434
DIAD 890300 435 MOV CX,3 I SET RETRY COUNT
01A3 43. HI: ; IPl_SYSTEM
01A3 51 437 PUSH CX I SAVE RETRY COUNT
OlA4 2BOl 438 SUll DX,OX ; DRIVE ZERO
OlA6 28CO 439 SUll AX,AX I RESET THE DISKETTE
01A8 tOl3 440 INT IlH ; FILE 10 CAll
OlAA nOF 441 JC H2 I IF ERJ;!OR. TRY AGAIN
OlAe B80102 442 HOV AX,02:01H I READ IN THE SINGLE SECTOR
443
OlAF 2B02 444 SUB OX,DX
01Bl 8EC2 445 tlOV ES,DX ; ESTABLISH SEGMENT
0183 BB007e 446 HOV BX.OFFSET BOOT_LOCN
447
0186 890100 448 MOV C)(tl I SECTOR 1. TRACK 0
0189 COB 449 INT 13H I FILE 10 CAll
A·92 Fixed Disk BIOS

LOC OBJ LINE SOURCE
OlBB 59 450 HZ: POP ex I RECOVER RETRY COUNT

OIBC 730", 451 JtlC H4 I CF SET BY UNSUCCESSFUL READ
OIBE sOFeae 452 CNP "H.80H I IF TIME OUT. NO RETRY
01e1 740"' 4" JZ H5 ; TRY fIXED DISK
01C3 EZOE 454 LOOP HI I 00 IT FOR RETRY TINES
01C5 E80690 455 JNP H5 I UNABLE TO IFL FROM THE DISKETTE
01C8 456 H4: I IPL WAS SUCCESSFUL
01C6 EA007tOOOO 457 JMP
458
459 1----- ATTEMPT BOOTSTRAP FROM FIXED DISK
460
OlCo 461 H5:
Oleo 2BCO 462 SUB AX.AX I RESET DISKETTE
OleF 2:B02 463 SUB OX.OX
0101 con
0103 890300
464
465
rur
MOV
"M
eX.3 ; SET RETRY COUNT
0106 466 H6: I IPL_SYSTEM
0106 51 467 PUSH ex I SAVE RETRY COUNT
0107 BASCDD 468 MOV ox.ooaOH I FIXED DISK ZERO
OIDA ZBCD 469 SUB AX,AX J RESET THE FIXEO DISK
Oloe COB 470 UIT 13" ; FILE 10 CALL
OlOE 7212 471 JC H7 I IF ERROR. TRY AGAIN
DIED B80102 472 MOV AX.0201H J READ IN THE SIt«iLE SECTOR
01E3 ZBDS 473 SUB BX,ex
01E5 8EC3 474 MOV ES,BX
0lE7 BB007e 475 MOV BX.OFFSET BOOT_LOCH I TO THE BOOT LOCATION
OlEA 8A6000 476 MOV OX,eOH i DRIVE NUtlOER
DIED 890100 477 MOV CX.l I SECTOR 1. TRACK 0
DIFO COB 4i8 INT 13H I FILE 10 CALL
DIF2 S9 479 H7: POP ex I RECOVER RETRY COUNT
DIF3 7208 480 JC H8
OIFS AIFE7D 481 NOV AX,wmw FTR BOOT_lOCN+SIOD
DIFe 3D55AA 482 CMP AX,OAA,55H I TEST FOR GENERIC BOOT BLOCK
DIFB 74CB 483 Jl. H4
DIFD 484 H6:
DIFD H07 485 LOOP H6 i DO IT fOR RETRY TIMES
486
487 1------ UNABLE TO IPL FROM THE DISKETTE OR FIXED DISK
488
OlFf C018 489 INT IBN I RESIDENT BASIC
490
0201 491 DISKETTE_TBl:
492
0201 Cf 493 DB 110011118 I SIH=C, HD UNLOAD:::OF - 1ST SPEC BYTE
0202 02 494 DB 2 I HD LOAD:::l, HOOE:::DMA - 2ND SPEC BYTE
0203 25 495 DB 25H i WAIT AFTER DFN TIL HOTOR OFF
0204 02: 496 DB ; 512 BYTES PER SECTOR
0205 08 497 DB i EDT (LAST seCTOR ON TRACK)
0206 2.4. 498 DB 02.4.H I GAP LENGTH
0207 FF 499 DB OFFH I OTL
0206 50 500 DB 050H , GAP LENGTH FOR FORMAT
0209 F6 501 DB OF6H I FILL BYTE FOR FORMAT
020A 19 502 DB 25 I HEAD SETTLE TIME (MILLISECONDS I
020B 04 503 DB ; MOTOR START TIME 11/8 SECOND I
504
505 ;----- MAKE SURE TliAT All HOUSEKEEPING IS DONE BEfORE EXIT
506
Oloe 507 DSBL PROC NEAR
508 ASSUME DS: OAT A
ozoe IE 509 PUSH OS I SAVE SEGMENT
0200 884000 510 NOV AXtOAT.&.
0210 8ED6 511 MOV OS,AX
512
0212 8A267700 513 MOV
0216 SO 514 PUSH AX i SAVE OFFSET
515
0217 C606770000 516
OZlt E86905 517 CALL PORT_l
OZlF 2ACO 518 SUB Al,Al
0221 EE 519 OUT OX,AL , RESET INT IOMA MASK
0222 C606770004 52. MOV PORT_OFF .4"
0227 E85E05 521 CALL PORT_l
02:2A 2ACO 522 SUB AL,AL
OllC EE 523 OUT aX,AL ; RESET !HT10NA MASK
022.0 (606770008 524 MOV PORT_OFf,aH
02:32 E85305 525 CAlL PORT_3
02:35 2ACO 526 SUB Al.AL

LaC OBJ LINE SOURCE
0237 EE 527 OUT DX,Al ; RESET INT/DHA MASK

0238 C606770DOC 528 MOV PORT_OFf , OCH
0230 E84605 529 CALL PORT_3
0240 2ACO 530 SUB AL.AL
0242 EE 531 OUT DX.Al J RESET !NT IOMA MASK
0243 B007 532 HOV Al,07H
0245 E60 .... 533 OUT OMA+! 0 I AL I SET DMA MODE TO DISABLE
0247 fA. 534 ell I DISABLE INTERRUPTS
0246 E4Zl 535 IH Al,OZIH
024A De20 53. OR Al,OZOH
024C E621 537 OUT 02.1H,AL ; DISABLE INTERRUPT 5
024£ FB 538 STI I ENABLE INTERRUPTS
024F 58 539 POP I RESTORE OFFSET
0250 88267700 540 MOV
0254 IF 541 ; RESTORE SEGMENT
0255 C3 542 RET
543 OS8L EHOP
544
545 1-------------- ------------ - ---- ---------
546 FIXED DISK BIOS ENTRY POINT
547 1--------------------- -------- -----------
548
0256 54'
550 AssurlE DS:HOTHING,ES:NOTHIUG
0256 eOF A80 551 CHP OL.BOH I TEST FOR FIXED DISK DRIVE
0259 7305 552 JAE HARD_DISK ; YES. HAtIDLE HERE
0258 C040 553 INT 40H ; DISKETTE HANOLER
0250 554
0250 (A0200 555 RET , BACK TO CALLER
0260 55.
557 ASSUNE DS:DAU
0260 FB 558 STI ; ENABLE ItHEPRUPTS
0261 OAE4 559 OR AH,AH
0263 7509 5.0 JtlZ AJ
0265 C040 5.1 INT 40" I RESET NEC WIlEN AH=O
0267 2AE4 5.2 SUB AH.AH
0269 BOFA81 5.3 eMP DL'(80H + S_MAX_FIlE - 11
D2bt 77EF 504 JA
026E 5.5
026E aOftOe 5 •• eMP AH,08 I GET PAPAMETERS IS .. SPECIAL CASE
0271 7503 507 JHZ A2
0,73 E9l.l.01 5.8 JMP
0276 5.9 .&.2:
0276 53 570 PUSH ex I SAVE REGISTERS DURING OPERATION
0277 51 571 PUSH ex
0276 52 572 PUSH ox
0279 1£ 573 PUSH as
027A 06 574 PUSH ES
0278 56 575 PUSH S1
Ol7t 57 570 PUSH 01
577
0270 £86AOO 578 I PERFORM THE OPERATION
579
0280 50 580 PUSH AX
0281 E888FF 581 CALL QSBl I BE SURE DISABLES OCCURRED
0284 864000 582 MOV AX,DATA
0287 6E08 583 tIOV OS.AX I ESTABLISH SEGMENT
0289 58 584 POP AX
028A 6"267400 585 MOV ; GET STATUS FROM OPERATION
028E SOFCDI 58. eMP ,6,H.l I SET THE CARRY FLAG TO INDICATE
0291 F5 587 el1C I SUCCESS 00 FAILURE
0292 SF 588 POP 01 I RESTORE REGISTERS
029] 5£ 589 POP S1
0294 07 590 POP ES
0295 IF 591 POP OS
0296 SA 592 POP OX
0297 59 593 POP ex
0298 58 594 POP 8X
0299 CA0200 595 RET 2 I THROW AWAY SAVED FLAGS
597
0290 598 M1 LABEL WORD I F~CTION TRANSFER TABLE
D29C 3803 59' OW DISK_RESET I OOOH
029[ 4003 .00 DW RETUIHCSTATUS I OOIH
02AO 5603 601 OW DISK_READ I 002:H
02A2 6003 .02 OW DISK_WIBlE I 003H
020'.4 6AD3 .03 ow DISK_VERF I 004H

LOC OSJ LINE SOURCE
DZAb 7203 60' OW fMT_TRK I 005H

02A8 7903 60S OW FMT_BAO I 006H
02AA 8003 606 ow FMT_ORV , 007H
02At ]003 607 ow BAD_COMMAND I OOSH
02AE 2704 608 ow IHIT_DRV I 009H
0280 eFO'!- 60. ow RD_LONG I OOAH
02B2 0004 610 ow WR_LONG I OOBH
0284 f204 611 ow DISK_SEEK I OOCH
0286 3803 61' ow DISK_RESET I OOOH
02B8 F904 613 ow RD_BUFF I OOEH
02BA 0705 614 ow WR_BUFF I OOFH
OZBC 1505 615 ow TST_ROV I OIOH
OlBE 1C05 616 ow HDISK_RECAL I 011H
02tO 2305 617 ow RAM_DIAG I 012H
02e2 ZAOS 618 ow ; 013H
02C4 3105 61. ow ; 014H
ooa 620 H1L EQ"
621
02e6 6" SETUP _A PROC NEAR
6"
02t6 C606740000 62. I RESET THE STATUS INDICATOR
02C8 51 6" PUSH CX J SAVE CX
626
627 ;----- CALCULATE THE PORT OFFSET
628
02ec 8AEA. 629 HOV CH,OL J SAVE Dl
02eE 80CAOI 630 OR DL,l
0201 FEeA 631 DEC OL
0203 DOE2 6" SIlL DL,l ; GEtIERATE OFFSET
0205 88167700 633 HOV ; STORE OFFSET
0209 8AD5 634 HOV DL,eH ; RESTORE DL
0208 80E201 63S AHO OL,l
636
OlOE 8105 637 HOV CL,S J SHIFT COUNT
02EO 02E2 638 SHL OL,CL I DRIVE NI..It1BER {O,lI
02E2 OAD6 63. DL,DH I HEAD tU1BER
02E4 88164300 640 NOV CND_BLOCK+l,DL
02E8 59 641 pop ex
02E9 C3 64' RET
644
02EA 64S
02EA 50 646 PUSH AX
02E8 884000 647 NOV AX,DATA
OHE 8ED8 648 HOV OS,AX I ESTABLISH SEGMENT
DHO 58 64. POP AX
DlFl aOFCOI 650 eHP AH,OIH ; RET~N STATUS
OlF4 7503 651 JHZ .4
02f6 E85590 652 JHP RETURN_STATUS
02F9 653 A4:
OlF9 80EA80 654 SUB OL ,80H J CONVERT DRIVE NUMBER TO 0 BASED RANGE
02fC BOfMa 655 eHP OL,MAXJIlE J LEGAL DRIVE TEST
02FF 732F 656 JAE BA~_COMMAND
657
0301 E8C2FF 658
659
660 ; ----- SET UP COMMAND BLOCK
661
0304 FEC9 662 DEC ; SECTORS 0-16 FOR CONTROLLER
0306 C606420000 663 NOV
0308 880E4400 664 MOV CHO_BLOCK+2,CL I SECTOR AND HIGH 2 BITS C'l'LItIDER
OJOF 882E4500 665 NOV CMD_BLoeK+3,CH I CYlINDER
0313 A24600 666 HOV CHO_BLOCK ... 4,AL J INTER LEAVE I BLOCK COUNT
0316 A01600 667 MOV AL,CQtffROl_BYTE ; CONTROL BYTE (STEP OPTION I
0319 A24700 668 HOV CHO_BLOCK+5,AL
ollt SO 669 PUSH AX I SAVE AX
0310 8AC4 670 HOV AL,AH I GET INTO LOW BYTE
031F 32E4 671 XOR Ali,AH ; ZERO HIGli BYTE
0321 DIED 6n SAL AX,1 I *2 FOR TABLE LOOKUP
0323 BBFO 673 MaV SI,AX ; PUT INTO SI FOR BR.A.HCH
0325 302.4.00 674 CMP AX,MIL ; TEST WITHIN RANGE
0328 56 675 pop AX , RESTORE AX
0329 7305 676 JHB BAD_COMMAND
0328 2:EFFA49C02 677 JHP WORD PTR CS: [SI ... OFFSET HI J
0330 678
0330 C606740001 67. DISK_STATUS ,8AO_Cf1O ; COHM.A.t.() ERROR
0335 BOOO 680 AL,O

LOC OBJ LINE SOURCE
0337 Cl 681 RET

682 DISK_IO_CONT ENOP
683
664 ; ------------------------------------------------
665 RESET THE DISK SYSTEM (AH = OOOH)
666 J------------------------------------------------
687
o:na 688 DISK_RESET PROt NEAR
0338 E84304 689 CALL PORT_l ; RESET PORT
033B EE 69. OUT OX.Al , ISSUE RESET
033C E83F04 691 CALL PORT_l I CONTROllER HARDWARE STATUS
033F EC 692 IN AL,DX ; GET STATUS
0340 2402 693 MID AL,2 ; ERROR BIT
0342 7406 694 JZ OR!
0344 C606740005 695 HOV DISK_STATUS, BAD_RESET
0149 C3 696 RET
034A 6?7 DRI:
034" E9OAOO 698 JHP INIT_DRV • SET THE DRIVE PARAMETERS
699 DISK_RESET 'NOP
700
701 1------------------------------------------------
7" DISK STATUS ROlJTINE (AH = OOIH)
703 ,-------------------- ----------------------------
704
0340 705 RETURN_STATUS FRoe NEAR
0340 ... 07400 706 MOV AL,DISK_STATUS ; OBTAIN PREVIOUS STATUS
0350 C606740000 707 HOV ; RESET STATUS
0355 C3 708 RET
709 RETURN_STATUS ENOP
710
711 ; ---------------------- ------- -------------------
712 DISK READ ROUTINE (AH = 002H)
713 1--------------------- -------- ----------- --------
714
0356 715 PRoe NEAR
0356 B047 716 HOV AL,OHA_READ 1 MOOE BYTE FOR OMA READ
0356 C60b420008 717 MOV
0350 E9E501 718 JHP
719 [NDP
720
721 ; --------------- -- --- ------------------- ---------
722 DISK WRITE ROUTINE (AH = 003H)
723 1------------------------------------------------
724
0360 725 PROC NEAR
0360 B048 72. MOV AL ,DNA_WRITE I HOoE BYTE fOR DMA. WRITE
0362 C60642000A 727 HOV CMO_BLOCK-tO ,WRITE_cm
0367 E9DBOl 126 JHP
729
730
731 ;------------------------------------------------
732 DISK VERIfY (AH = 004H)
733 ; --- ---------------------- -----------------------
734
036A 735 PROC NEAR
036A C606420005 736 MOV
036F E9C401 737 JMP
738 'IIDP
739
740 1-------- ----------------------------------------
741 FORMATTIHG (AH = OOSH 006H 007H I
742 ;------------------------------------------------
743
0372 744 1 FORMAT TRACK (AH = OOSH)
0372 C606420006 745
0377 EBOC 746 JHP SHORT FMT_CONT
747 FMT_TRK ENDP
748
0379 749 FHT_BAD PROC NEAR ~ FORMAT BAD TRACK (AH = 006H)
0379 C6, " ... 20007 750 MOV CMD_B LOCK. FMTBAD_CMD
037E EB05 751 JHP SHORT FMT_CotlT
752 FMT_BAD ENDP
753
0380 754 FMT _DRV PROC NEAR ~ FORMAT DRIVE (AH = OQ7H)
0380 C606420004 755 MOV
756 FNT_ORV ENOP
757

LaC OBJ LINE SOURCE
0385
0385 ... 04400 759 MOV AL,CMO_BLOCK-t, I ZERO OUT SECTOR FIELD
0388 24CO 760 AND Al.llOOOOOOB
038A A24400 761 HOV CI'Il_BLOCK.Z,AL
0380 E9A601 76. JHP NOHA_OP"
763
764 1------------------------------------------------
765 GET PARAMETERS (AH = 8)
766 1------------------------------------------------
767
0390 766 GET_PARM_N LABEL NEAR
0390 769 GET_PARM p,oc FA, J GET DRIVE PARAMETERS
0390 IE 770 PUSH as J SAVE REGISTERS
0391 06 77l PUSH ES
0392 53 772 PUSH BX
773
77' ASSUME DS: DUtfHY
0393 2BtO 775 SUB AX,AX I ESTABLISH ADDRESSING
0395 8E08 776 "OV OS.AX
0397 C41E0401 777 LES BX.HF _TBL_VEe
776 ASSUME 05:0.6.1"
0398 884000 779 MOV AX.DATA
039E 8EDe 760 MOV OS,AX I ESTABLISH SEGNENT
781
03,.1..0 8OEA80 782 SUB Ol.aOH
03A3 80FA08 763 CMP Dl,MAX_FILE ; TEST WITHIN RANGE
OJA6 732F 78. JAE O'
765
OlAS E8tBFF 766 CALL SETUP _A
767
03A6 EBOFO] 768 CALL SW2_0FFS
03AE 7227 769 JC G,
03BO 0308 790 ADO eX,AX
791
03B2 268B07 792 HOV AX,ES:[BX] ; MAX NUt!BER OF CYLIt4)ERS
0385 200200 793 SUB AX.2 I ADJUST FOR O-N
79. ; AND RESERVE LAST TRACK
03B6 8Af8 795 MOV CH,AL
03BA 250a03 796 AtlD AX,0300H I HIGH nlO BITS OF en
03BO OlEB 797 SH' AX,I
OlBF DIE8 796 SH' AX,l
03el oell 799 OR Al,OllH I SECTORS
03e3 8AC8 600 MOV CL,AL
801
03es 268A7702 80. MOV DH,ES:[BXJ[l] ; HEADS
03C9 FEtE 603 DEC DH I O-N RANGE
03te 8.60167500 80. "OV Ol,HF _HUM ; DR IVE COUNT
OleF 2BCO 605 SUB AX.AX
0301 806 G5:
0301 58 607 POP BX ; RESTORE REGISTERS
0302 07 608 POP ES
0303 IF 809 POP os
03D4 CA0200 810 RET
0307 811 64:
0307 C606740007 612 HOV DISK_STATUS ,INITJAIl , OPERATION FAILED
OlOC 6407 8" HOV AH,INIT_FAIL
030E U.CO 81' SUB AL,AL
03EO 2B02 815 SUB OX,OX
03E2 2Be9 816 S,", CX,CX
03E4 F9 8" STC I SET ERROR fLAG
03E5 EBEA 818 JHP OS
819 GET_PARM ENDP
8"
821 1--------------------------------------------------------
822 • INITIALIZE DRIVE CHARACTERISTICS
6"
824 i fIXED DISK PARAMETER TABLE
825
826 I - THE TABLE IS COMPOSED OF A BLOCK DEFINED AS:
827
626 (I WORD) - MAXIt1Ut1 NUMBER Of CYLINDERS
8.9 (1 BYTE) - HAXlt1Ut1 ~ER OF HEADS
630 (1 WORD I - STARTING REDUCED WRITE CURRENT cn
831 (1 WOF1D I - STARTING WRITE PRECOMPENSATION CYl
8" (1 BYTE I - MAXlt1Ut1 ECC OAT A BURST LENGTH
8" (1 BYTE I - CONTROL BYTE (DRIVE STEP OPTION)
.,.
83. BIT
BIT
7 DISABLE DISK-ACCESS RETRIES :
6 DISABLE ECC RETRIES

LOC OBJ LINE SOURCE
8l' BHS 5-] ZERO

8" BITS 2-0 DRIVE OPTION
8'8 (l BYTE) - STAHDARD TIME OUT VALUE (SEE BELOW)
6"
840
11 BYTE) - TIME OUT VAlUE FOR FORMAT DRIVE
11 BYTE I - TIME OUT VALUE FOR CHECK DRIVE
8"
842
(4 BYTES I
- RESERVED FOR FUTURE USE
84'
84. - TO DYNAMICALLY DEFINE A SET OF PARAMETERS
84. BUIlO A TABLE OF VALUES At-Il PLACE TliE
8" CORRESPOUDIHG VECTOR INTO INTERRUPT 41.
847
8.8 NOTE:
849 THE DEFAULT TABLE 15 VECTORED IN FOR
8" AN INTERRUPT 19H (BOOTSTRAP I

8.,
852 ,
853 I ON TIfE CARD SWITCH SETTINGS
8.4
8 •• DRIVE 0 DRIVE 1
8 ••
8.7 ON
8.8 : -1- -2- I -3- -4-:
8 •• Off
8.0
6.,
6.'
6.3 TRANSLATION TABLE
8 ••
8 •• 1/3 : 214 : TABLE ENTRY
6 ••
6.7 ON ON
•• 8 ON Off
8.'
870
Off
Off
ON
Off
8"
672 1-----------------------------------------------------__ _
8n
03E7 8,.
67.
876 1----- DRIVE TYPE 00
877
OlE7 32.01
03E9 02-
03EA 3201
.7.
678
.80
ow
DB
OW
03060
020
03060
03EC 0000 .81 OW 00000
GlEE 08
OlEF 00
•••
853
oli
DB
O.H
0011
Q3FO DC 884 DB OCH I STAUOARO
03Fl B4 8.5 DB OMH I FORHAT DRIVE
03f, 28 86. DB 028H ; CHECK DRIVE
03f] 00000000 887 D. 0.0,0,0
888
869 1----- DRIVE TYPE 01
690
03F7 7701 8n ow 03750
03F9 08 8" DB OBO
03FA 7701 8" Ow 03750
03FC 0000 8.4 DH 00000
03FE DB 8 •• 08 OBH
03FF 05 8 •• DB O.H
0400 DC 897 DB OCH I STAtlDARD
OttO I 84 8.8 DB OB4H 1 FORHAT DRIVE
0402 28 8 •• DB 028H ; CHECK DRIVE
0403 00000000 .00 DB 0,0,0,0
.01
902 1----- DRIVE TYPE 02
.03
0407 3201 .04 ow 03060
0409 06
04QA 8000
040C 0001
.0.'0'
.07
DB
ow
OW
0.0
Olzeo
02560
040E DB
040F 05 .0.
.08 DB
DB
OBH
B5H
0410 DC
0411 84
"0
.11
08
DB
OtH
064H
I STAt.JDARD
I FORMAT DRIVE

LOC OBJ LINE SOURCE
0412 28 .12 DB 026H J CHECK DRIVE

0413 00000000 '13 DB 0,0,0,0
91.
915 1----- DRIVE TYPE 0]
91.
0417 3201
.,.
917 OW 03060
0419 04
041A 3201 .,.
...
DB
OW
"0
03060
041C 0000 OW 00000
.., 'SH
041E DB '21 DB
041F 05 .22 DB OSH
0420 DC
0421 Bit .,. DB
DB
'CH
OB4H
I STANDARD
I FORMAT DRIVE
0422 28 .25 DB 028H I CHECK DRIVE
0423 00000000 92. D. 0,0.0,0
0427 ...
927
92.
IHIl_DRY PROC NEAR
." 1----- DO DRIVE ZERO
0427 C60642000C
042C C606430000
0431 E81000
........,
." MOV
MOV
CALL
CMD_BLOCK"O. INIT_DRY_tHD
tHO_BLOCK+l,O
INIT_DRV_R
0434 nOD
...
."
. .7
JC
1----- DO DRIVE ONE

INIT_DRY_OUT
0436 C60642000C
0438 (6064)0020
...
"6
9.,
MOV
MeV
CHD_BLOCK+D .INlT_DRV_CI'1D
CMD_BlOCK+l.OOlOOOOOB
0440 E80100 .41 CALL INIT_DRY_R
0443 942 INIT_DRY_OUT:
0443 C3 94> RET
944 INIT_DRY ENOP
.45
0444 '4. INIT_DRV..;,R PRoe NEAR
947 ASSUHE ES:COOE
0444 2ACO .46 SUB AL,AL
0446 E81901
0449 7301
0448 C]
...
94.
951
CALL
JHe
RET
COMMA,.,
.1
I ISSUE THE COMMAND
044C .52 81:

044C 11:: 95> PUSH OS I S.6.VE SEGMENT
.5. ASSlIt1E DS:Out1NY
0440 28CO '55 SUB AX,AX
044F SEOS 95. MOV OS,AX I ESTABLISH SEGMENT
0451 C41E0401 957 LES BX, HF _ TBL_VEt
0455 If .58 POP OS I RESTORE SEGMENT
0456 £83403
0459 7257
%.
.5.
9'1
ASSlR1E
CALL
JC
DS:OATA
.,
SW2_DFFS
045B 0308 962 AOD BX,AX

9"
9.4 1----- SEI-IJ DRIVE PARAMHERS MOST SIGNIfICANT BYTE FIRST
'.5
0450 BfOlOO
0460 E85FOO
0463 7240
9.,
•• 7
•• 6
•••
MOV
CAll
JC .,
01,1
INIT_ORV_S
0465 BFODDO 97. MOV 01,0

0466 E85700 .71 CAll lNIT_ORV_S
046B 7245 '12 JC B'
9n
0460 8FD200 974 MOV 01,2
0470 E64FOO
0473 7230
975
97'
CAll
JC .,
1NIT_DRV_S
977
0475 8F0400 976 MOV 01,4
0478 E84700 .7. CAll INIT_DRV_S
0478 7235 '8' JC B'
.61
0470 BF030D 962 MOV 01,3
0480 E83FOD
0483 7220
96'
.64
CALL
Jt .,
IH1T_DRV_S
0485 8F0600
'B'
9Sb MCV 01,6
0486 E83700
0488 7225
987
966
CAll
JC .,
INIT_DRV_S

LaC OBJ LINE SOURCE
0480 BF05DO ...

.8'
.91
MOV 01,5
......",
0490 E8HOO CALL IHIT_DRV_S
0493 7210 JC BJ
0495 BFQ700 MOV 01.7

0498 E82700
0498 7H5
0490 BroeDO
.....,
•• 5
••8
CALL
JC
MOV
UllT_DRV_S
BJ
01,8 I DRIVE STEP OPTION

04AO 268.4.01
04A3 A27600
•••
10DD
MOV
MOV
AL,ES:[BX + OIl
CONTROL_BYTE tAL
1001
04.&.6 26C9 1002 SUB CX,CX
04A8 1003 85:
04A8 E80302:
04A8 EC
1004
1005
CALL
IN
PORT I
Al,OX
-
04AC Aeo, 1006 TEST Al,Rl_ IOManE I STATUS INPUT MOOE
04AE 7509 1007 JtlZ B.
0480 E2F6 1008 lOOP B5
0482 1009 83:
0482: C606740007 1010 MOV DISK_STATUS. IHIT_FAIl I OPERATIQH FAILED
0467 f9 1011 STC
0488 C3 1012- RET
lOll
0489 1014 66:
0489 E8850, 1015 CALL PORT_D
04BC EC 1016 IN Al,DX
0480 2402- 1017 AND AL.2 , MASK ERROR BIT
a4Br 75Fl 1018 JNZ B3
04Cl CJ 1019 RET
1020 ASSUME ES:NOTHING
1021 INIT_DRV_R ENOP
10<:2
102:3 1----- SEHD ll-IE BYTE OUT TO THE CONTROLLER
1024
04C2: 1025 IIIIT_DRV_S PROC NEAR
04C2 E8C501 1026 CALL Ho_WAIT_REQ
04C5 7207 1027 Je 01
04C7 E8A702 1028 CALL PORT_O
04CA 2b8AOI 102:9 MOV AL.ES:{8X + OIl
04CO EE 1030 OUT DX,AL
04CE 1031 Dl:
04CE C3 1032 RET
1033 UHT_DRV_S EHOP
1034
1035 ;----------------------------------------
103b READ LONG IAH = OAH,
1037 ;----------------------------------------
1038
04CF 1039 RO_LONG PROC NEAR
04CF E81900 1040 CALL CHK_LONG
0402: 72bB 1041 JC G8
0404 CbOb42:00E5 1042 MOV CMD_BLOCK+O, RD_LONG_Ctll
0409 B047 1043 MOV AL,ONA_READ
040B EBb8 1044 JMP SHORT DHA_OPN
1045 RD_LOHG EHOP
1046
1047 1-------- -- ------- ----- ------ ------------
1048 WRITE LONG tAH ,. OBH)
1049 1----------------------------------------
1050
0400 1051 WR_LOHG PROe HEAR
04Do E80BOO 1052 CALL C~IK
- LONG
04EO 7250 1053 JC G8
04E2 Cb064200Eb 1054 'lOY CMD_BLOCK+ O. WR_LONG_CMO
04E7 6048 1055 MOV AL.oMA_WRITE
04E9 E85A 1056 JMP SHORT OMA_OPN
1057 ""_ LONG ENOP
1058
04EB 1059 CHK_LOHG PROC HEAR
04E8 A04600 lObO MOV AL,CI1O_BlOCK+4
04EE 3ceo lObi CtlP AL.080H
04FO FS 10b2: eMe
04F 1 C3 1063 RET
1064 CHK_LONG EtIDP
1065
A-tOO Fixed Disk BIOS

lOC OBJ LINE SOURCE
1066 1----------------------------------------
1067 SEEK (AH = OCH)
1068 1----------------------------------------
1069
04F2 1070 DISfCSEEK PROC NEAR
04F2 C60642000B 1071 CMO_BlOCK.SEEK_Ctl)
04F7 EB3D 1072 SHORT tl)11A_DPH
1073 ENDP
1074
1075 1-------- ----------------------------------------
1076 READ SECTOR BUFFER IAH = OEH)
1077 ; ------------------------------------------------
1078
04F9 1079
04F9 C60642000E 1080
04FE C606460001 1081 NOV CMD_BlOCK.J-4,l I ONLY ONE BLOCK
0503 8047 1082 HOV
0505 EBlE 1083 JMP
1085
1086 1------------------------------------------------
1087 WRITE SECTOR BUFFER IAH = OFH)
1068 f------------------------------------------------
1069
0507 1090 WR_BUFF PROC NEAR
0507 C60642DCOF 1091
osoe C606460001 1092 MOV CHD_BLOCK+4.1 ; ONLY ONE BLOCK
0511 B048 1093 HOV AL.DMA_WRITE
0513 E630 1094 JMP SHORT OMA_OPN
1095 WR_BUF F EHOP
1096
1097 ;------------------------------------------------
1096 TEST DISK READY (Aft OlOHI =
1099 1-- ----------------------------------------------
1100
OS15 1101
0515 C606420000 1102
OSIA EBIA 1103
1105
1106 i ------------------------------------------------
1107 RECALIBRATE (AH = 011H)
1106 ; ------------------------------------------------
1109
051C 1110 HDISK_RECAl PROC HEAR
OSlC C606420001 1111 MOV CtID_BLOCK .RECAl_CMD
0521 EBl3 1112 JMP SHORT NDMA_OPN
1113 ENDP
1114
1115 ; --------------------------------------------------------
1116 CONTROLLER RAM DIAGNOSTICS IAH = 012HI
111"1 J --------------------------------------------------------
1116
0523 1119 PROC HEAR
0523 C6064200EO 1120 CMD_BlOCK+O ,RAI''-DIAG_CMD
0528 EBOC 1121 JMP SHORT t-IlHA_OPN
1122 ENDP
1123
1124 1------------------------------------------------
1125 DRIVE DIAGNOSTICS (AH = 013H)
1126 J ------------------------------------------------
1127
0524 1126 CHK_DRV PRot NEAR
0524 C6064200E3 1129 HOV CMD_BLOCK+O .CHK_ORV_CMD
052f EB05 1130
1132
1133 i ----------------------------------------------------------
1134 CONTROLLER INTERNAL DIAGNOSTICS I AH = 014H)
1135 ,----------------------------------------------------------
1136
0531 1137 CNTLR_DIAG PROC NEAR
0531 t60642:00£4 1138 MOV CND_BLOCK + O. CHTlR_DIAG_CMD
1139 CHTLR_DIAG EtilP
1140
Fixed Disk BIOS A-IOI

LOC OBJ LINE SOURCE
1141 J ------- -------------------------------------------------

1142 SUPPORT ROUTINES
1143 1--------------------------------------------------------
1144
0536 1145
0536 8002 1146 HOV
0538 £82700 1147 CALL COMMAtI) ISSUE THE COtt1At-aJ
0538 7221 1148 JC G11
0530 £B16 1149 IN" SHORT G3
053F 1150 68:
053F C606740009 1151 MOV
0544 C3 usz RET
0545 1153
0545 E85701 1154 CALL OHA_SETUP I SET UP fOR DNA OPERATION
0548 72f5 1155 JC G8
054 ... B003 1156 MOV ..u.03H
054C f81300 1157 CAll CDt1MAUO I ISSUE THE COHHAND
054F nOD 1156 JC GIl
0551 BODl 1159 HOV AL,03H
0553 E60A 1160 OUT OMAHO,AL I INITIALIZE THE DISK CHANNEL
0555 1161 63:
0555 E421 1162 AL,021H
0557 240F 1163 ANO Al,OOFH
0559 [621 1164 OUT 021H,AL
0558 E8A.4.01 1165 CAll WAIT_IHT
055E 1166 G11:
OSSE E83800 1167
0561 C3 1168 RET
1169
1170 ; ------ ---------- -- ---------- ---------------- ------------
1171 I COMHAHD
1172 THIS ROUTINE OUTPUTS THE COMMAN!) BLOCK
1173 ; INPUT
1174 AL = CONTROLLER DHA/INTERRUPT REGISTER HASK
1175
1176 1---------------- ------ --------- -------- -----------------
1177
0562 1178 COMt1AI'IJ PROC UEAR
0562 8E4200 1179 MOV SI.OFFSET CND_BLOCK
0565 E81B02 1180 CALL PORT_2
0566 EE 1181 OUT DX,Al I CONTROLLER SELECT PULSE
0569 E81C02 1182 CALL PORT_3
056C EE 1183 OUT OX,AL
0560 28C9 1184 SUB CX,CX I WAIT COiA'lT
056F E80C02 1185 CALL PORT_l
0572 1186
0572. EC 1187 AL,DX I GET STATUS
0573 ,40F 1188 AHD Al,OfH
0575 3eoo 1189 CH" Al,Rl_BVSY OR Rl_BUS OR Rl_REQ
0577 7409 1190 JE Cl
0579 E2F7 1191 lOOP
0578 C606740080 lin NOV
0580 f9 1193 STC
0581 C3 1194 RET 1 ERROR RETURN
0582 1195
0562 Fe 1196 ClD
0583 890600 1I97 NOV CX,6 I BYTE COUNT
058& 1198 CH1:
0586 [8E601 1199 CALL PORT_O
0589 At 12.00 LOOSB I GET TilE HEXT COHMAND BYTE
05SA. EE 1201 OUT OX,AL ; OUT IT GOES
0588 E2F9 1202 lOOP CM3 I 00 MORE
1201
0560 E8EEOI 1204 CALL PORT_I I STATUS
0590 EC 1205 IN AL,OX
0591 AMI 1206 TEST AL,Rl_REQ
0593 7406 1207 JZ CM7
0595 C606740020 1208 NOV
059,A, F9 1209 STC
0598 1210 eM7:
0596 C3 1211 RET
1212 COMMAND EHOP
1211
1214 1------------------------------------------------
1215 SENSE STATUS BYTES
1216
1217 I BYTE 0
A·I02 Fixed Disk BIOS

LOC OBJ LINE SOURCE
1218 BIT ADDRESS VALID. WHEN SET

1219 BIT SPARE I SET TO lERO
122.0 BITS 5-4 ERROR TYPE
1221 BITS 3-0 ERROR CODE
1222
1223 I BYTE 1
1224 BITS 7-6 lERD
1225 BIT DRIVE 10-11
1226 BITS 4-0 HEAD tu'BER
1227
12:28 I BYTE 2
1229 BITS 7-5 CYLlNDER HIGH
1230 BITS '+-0 SECTOR MJt1BER
1231
1232 I BYTE 3
1233 BITS 7-0. CYlINDER lOW
1234
1235 1- - -.-.- - ------ ----- ------ -- ----- --- ------ -------
1236
059C 1237 ERROR_CHK PROC HEAR
12:38 ASSlI1E ES:DATA
059C ... 07400 1239 HOV Al.DISK_STATUS I CHECK IF THERE WAS AN ERROR
059F OACO 1240 OR AL,AL
05.1.1 7501 1241 JHZ 021
OSA3 C3 1242 RET
1243
1244 1----- PERFORM SENSE STATUS
1245
05.1.4 12:46 G21:
05Aft 884000 1247 HOV AX.DATA
05A7 8EtO 1248 HOV ES,AX ; ESTABLISH SEGMENT
05"9 28tO 12:49 !Ml AX,AX
05"B 88F8 12:50 HOV Dl,AX
05AO C606420003 1251 HOV CtIJ_BlOCK+O.SENSE_CtIJ
0582 2ACO 1252 SUB .U,AL
05B4 E8ABFF 12:S3 CALL COt1MAND I 15SUE SENSE STATUS CotI1AND
05B7 7223 12:54 JC SENSE_ABCRT I CANNOT RECOVER
0589 B90400 1255 HOV CX,it
05BC
...
1Z56 G22:
05BC E8CBOO 1257 CALL liD_WAlT_REq
05BF 7220 12:58 JC
05CI E8AD01 1259 CALL PORT_O
QSCit EC 1260 IN AL.DX
OSCS 26884542 1261 HOV ES:HD_ERROR[DI J,AL I STORE AWAY SENSE BYTES
OSC9 47 1262 INC DI
OSC'" E8B101 1263 CAll PORT_l
oseD E2ED 1264 LOOP 022
OSCF E8B800 1265 CAll HV_WAlT_REQ
05D2 720D 1266 JC 0. .
05D4 E89AOl 1267 CAll PORT_O
05D7 EC 1268 IN AL.OX
0508 A802 1269 TEST AL,2
OSDA 740F 1270 JZ STAT_ERR
05DC 1271 SENSE_ABORT:
05DC C6067400FF 1272 HOV DISK_STArus.SEHSE]AIL
05El 1273 &24:
05El F9 1274 STC
05E2 C3 1275 RET
1276 ERROR_CHK Et<lP
1277
05E3 lA06 1278 T_O OW TYPE_O
05E5 2706 1279 T_I OW TYPE_l
05E7 6A06 1280 T_' OW TYPE_2
05E9 7706 1281 T_' DW TYPE_l
1282
05EB 1283 STAT_ERR:
05E8 268AIE4200 I'" MOV BL.ES:HD_ERROR I GET ERROR BYTE
OSFO 8AC3 1285 HOV AL.Sl
05F2 240F I'" .'" AL,OFH
05F4 80E330
OSF72AFF
1287
1288
'SUB
NIl BL,00110000B
SH.BH
; ISOLATE TYPE
OSF9 B103 1289 HOV Cl,3

05FB 03EB 1290 SHR BX.CL I ADJUST
OSFD 2EFFA7E30S 1291 JHP WORD PTR Cs:[ax ... OFFSET T_OJ
1292 ASSUtlE ES:NOTHING
1293
0602 1294- TYPED_TABLE LABEL BYTE
Fixed Disk BIOS A-I03

LOC OSJ LINE SOURCE
0602 00204020800020 1295 D. o.BAD_CNTLR. BAD_SEEK. 8AD_CNTLR. TIME_OUT. 0 .BAD_CNTLR

0609 0040 lZ96 D. OoBAD_SEEK
0009 1297 TYPED_LEN EQU '-TYPED_TABlE
0608 12.98 TYPE I_TABLE LABEL BYTE
0608 1010020004 1299 D. BAD_ECC .BAD_ECC. BAD_ADDR_MARK. O. RECORD_HOTJt4)
0610 400000110B 1300 D. BAD_SEEK, 0.0. DA TA._CORRECTED ,8AO_TRACK
OOOA 1301 TYPEl_lEH EQU $-TYPEl_TABlE
0615 no, TYPE,_TABLE LABEL BYTE
0615 0102 1303 D. BAD_tHO .BAD_ADDR_MARK
0002 1304 TYPE2_lEtl EOU $-TYPE,_TABlE
0617 nos TYPEl_TABLE LABEL BYTE
0617 202010 1306 D. BAD_CNTLR. BAD_CNTlR. BAD3CC
0003 1307 TYPE3_lEN EOU $- TYPE3_ TABLE
1308
}J09 ;----- TYPE 0 ERROR
1310
06lA. 1311 TYPE_a:
06lA. 880206 1312 MOV BX,OFfSET TYPED_TABLE
0610 3C09 1313 CMP AL, TYPED_LEN I CHECK IF ERROR IS DEFINED
QolF 7363 1314 JAE UNDEF _ERR_l
0621 2ED7 1315 XLAT CS:TYPEO_TABlE j TABLE lOOKUP
0623 A27400 1316 MOV DISK_STATUS,Al I SET ERROR CODE
0626 C3 1317 RET
1316
1319 j------ TYPE 1 ERROR
1320
0627 1321 TYPE_l :
0627 BBOB06 1322 MOV BX,OFFSET TYPE I_TABLE
062A 68C6 1323 HOV eX,AX
062e 3COA 1324 CMP Al, TYPE I_LEN J CHECK IF ERROR IS OEFWEa
062E 7354 1325 JAE lMDEF _ERR_L
0630 2E07 1326 XLAT CS:TYPEl_TABLE I TABLE LOOKUP
0632 A27400 1327 MOV DISK_STATUS,Al 1 SET ERROR CODE
0635 80EI08 1328 A"O CL,08H 1 CORRECTED ECC
0638 80F908 1329 CMP CL,08H
063B 752 ... 1330 J"Z 630
1331
1332 1----- OBTAIN ECC ERROR BURST LENGTH
1333
0630 C606420000 1334 MOV CHD_BLOCK+O. RD_ECC_CI1D
0642 2ACO 1335 SUB AL,AL
0644 E8lBFF 1336 CALL COHMAND
0647 721E 1337 JC .3.
0649 E83EOO 1338 CALL HD_W,I,IT_REQ
064C 72.19 1339 JC 63.
064E E82001 1340 CAll PORT_O
0651 EC 1341
0652 8AC8 1342 '"
MOV
AL,DX
CL.Al
0654 E83300 1343 CALL HO_WAIT_REQ
0657 720E 1344 JC 63.
0659 E81501 1345 CAll PORT_O
065C EC 1346 II. AL,DX
0650 A801 1347 TEST Al,OlH
065F 7406 1348 JZ 63.
0661 C606740020 1349 MOV DISK_STATUS, BAD_CHTLR
0666 F9 1350 STC
0667 1351 G30:
0667 8ACI 1352 MOV AL,CL
0669 C3 1353 RET
}354
1355 ; ----- TYPE 2 ERROR
1356
066A 1357 TYPE_2:
066A B61506 1358 MOV 8X,OFFSET TYPE2_TABLE
0660 3C02 1359 CMP AL. TYPE2_LEN I CHECK IF ERROR IS DEFINED
066F 7313 1360 JAE UHDEF _ERR_L
0671 2ED7 1361 XLAT CS:TYPEl_TABLE I TABLE LOOKUP
0673 "27400 1362 NOV DISK_STATUS,Al I SET ERROR CODE
0676 C3 1363 RET
1364
1365 ; ----- TYPE 3 ERROR
1366
0677 1367 TYPE_3:
0677 B61706 1368 MOV eX,OFFSET TYPEl_TABlE
067A 3C03 1369 CMP AL, TYPE3_lEt~
067C 7306 1370 JAE UHOEF _ERR_L
067E 2E07 1371 XLAT CS:TYPE3_TAeLE

LaC OBJ LINE SOURCE
0660 A27400 1372 HOV DISK_STATUS ,At

0681 C3 1373 RET
1374
0684 1375 UNDEF _ERR_L:
0664 C:606740088 1376 HOV OISK_STATUS,UNOEF _ERR
0669 C3 1377 RET
1378
068A 1379 HD_WAIT_REQ PROC NEAR
066... 51 1380 PUSH ex
Ob88 lBe9 1381 SUB ex.ex
0680 E6EEOO 1382 CALL POOT_I
0690 1383 ll:
0690 EC 1384 IN AL,OX
0691 A801 1385 TEST Al,Rl_REQ
0693 7508 1386 JHZ L2
0695 ElF9 1387 LOOP Ll
0697 (606740080 1388 HOV DISK_STATUS, TIME_OUT
069C f9 1389 STe
0690 1390 LZ:
0690 59 1391 POP ex
069E C3 1392: RET
1393 HD_WAIT_REQ ENDP
1394
1395 1--------------------------------------------------------
1396 ; DHA_SETUP
1397 THIS ROUTINE SETS UP FOR OHA OPERATIONS.
1398 I INPUT
1399 (At) = MODE BYTE FOR TIlE OMA
1400 , (ES:BXl = ADDRESS TO REAO/WRITE THE DATA
1401 I OUTPUT
1402 (AX) DESTROYED
1403 ;--------------------------------------------------------
069F 1404 DNA_SETUP PROC NEAR
069F 50 1405 PUSH AX
06AO A04600 1406 MOV AL,CHO_BLOCK+4
06A3 3CSI 1407 eHP AL.SlH ; BLOCK COUNT OUT OF RANGE
06A5 58 1408 POP AX
06A6 7202 1409 JB J1
06A8 F9 1410 STe
06A9 C3 1411 RET
06AA 1412 Jl:
06AA 51 1413 PUSH ex , SAVE THE REGISTER
06AB FA 1414 eLI ; NO MORE INTERRUPTS
06AC EbOC 1415 OUT ONA+12.AL I SET THE FIRST/LAST F/F
06AE 50 1416 PUSH AX
06AF 58 1417 POP AX
06BO F.60B 1418 OUT DNA..tll.Al ; OUTPUT THE MODE BYTE
06B2 8CCO 1419 HOV AX.ES I GET THE ES VALUE
0664 BI04 1420 HOV CL.4 ; SH IF T COUNT
06B6 03CO 1421 ROL AX.Cl I ROTATE lEFT
0666 8Af8 1422 HOV CH.Al ; GET HIGHEST NYBBlE OF ES TO CH
06BA 24FO 1423 ANO AL.OFOH ; ZERO THE LOW N'tBBlE FROM SEGMENT
06Bt 03C3 1424 AOO AX.BX ; TEST FOR CARRY FRaN ADDITION
06BE 7302 1425 JHe J3l
06CO FEC5 1426 INe eH I CARRY MEANS HIGH 4 BITS MUST BE INC
06C2 1427 J33:
06C2 SO 1428 PUSH AX I SAVE START ADDRESS
06C3 E606 1429 OUT DMA+6.AL I OUTPUT LOW ADDRESS
06CS 8AC4 1430 HOY AL.AH
06C7 E606 1431 OUT DMM6.AL ; OUTPUT HIGH ADDRESS
06t9 8AC5 1432 HOV Al,CH I GET HIGH 4 BITS
06CB 240F 1433 ANO AL,OFH
06CD E682 1434 OUT DMA_HIGtt.AL I OUTPUT THE HIGH 4 BITS TO PAGE REG
1435
1436 j------ DETERMINE COUNT
1437
ObCF A04600 1438 HOV AL,CHD_BLOCK+4 I RECOVER BLOCK COUNT
Ob02 ODED 1439 SHL AL.! I MULTIPLY BY 512 BYTES PER SECTOR
0604 FEte 1440 OEe AL AND DECREMENT VALUE BY ONE
0606 8AEO 1441 HOV AH,AL
0608 BOFF 1442 HOV AL.OFFH
1443
1444 1----- HANDLE READ AHD WRITE LONG (Sl6D BYTE BLOCKS)
144S
06DA 50 1446 PUSH AX ; SAVE REGISTER
0608 A04200 1447 HOV AL.CI'Il_BLOCK+O J GI;:T COtf1At-C
06DE 3CES 1448 eHP AL.RD_LONG_CHO
Fixed Disk BIOS A-lOS

LOC OBJ LINE SOURCE
06EO 7407 1449 JE .lD04

06£2: 3eE6 1450 CMP Al,WR_lONG_Ctll
06E4 7403 1451 JE AOD4
06£6 58 1452 POP AX I RESTORE REGISTER
06E7 EBll 1453 JMP SHORT J2.
06£9 1454 ADD4:
06E9 58 1455 POP AX I RESTORE REGISTER
06EA 880402 1456 MOV AX.S16D I ONE BLOCK (512) PLUS 4 BYTES ECC
06EO 53 1457 PUSH BX
06E£ 2AFF 1458 SUB SH.BH
06FO 6Al£4&00 1459 MOV BL.CHD_BLOCK+4
06F4 52 1460 PUSH OX
06F5 F7E3 1461 I1UL BX I BLOCK COUNT TIMES 516
06F7 5A 1462 POP OX
06f8 58 1463 rop BX
06F9 48 1464 DEC AX I ADJUST
06FA 1465 J20:
1466
06FA 50 1467 PUSH AX I SAVE COUNT VALUE
06FB £607 1468 OUT QHA+7,AL I LOW BYTE OF COUNT
06FD 8AC4 1469 MOV .U.AH
06Ff £607 1470 OUT DtiA+7.AL ; HIGH BYTE OF cOlA"n
0701 FB 1471 STI J INTERRUPTS BACK ON
0702: 59 1472 POP CX I RECOVER COUNT VALUE
0703 58 1473 POP AX ; RECOVER ADDRESS VALUE
0704 03el 1474 ADD Ax.ex I ADD. TEST FOR 64K OVERflOW
0706 59 1475 POP CX • RECOVER REGISTER
0707 C3 1476 RET I RETURN TO CALLER, CFl SET BY ABOVE IF ERROR
1477 DNA_SHUP EHOP
1478
1479 ;------------------------------------------------
1480 I WAIT_INT
1481 THIS ROUTINE WAlTS F~ THE FIXED DISK
1482 CONTROLLER TO SIGNAL THAT AN INTERRUPT
1483 HAS OCCURRED.
1484 ;------------------------------------------------
0708 1485 WAIT_INT PROC NEAR
0708 FB 1486 STI I TURN ON INTERRUPTS
0709 53 1487 PUSH BX I PRESERVE REGISTERS
070A 51 1486 PUSH CX
070B 06 1489 PUSH ES
070C 56 1490 PUSH 51
0700 IE 1491 PUSH OS
1492 ",SSUHf OS:DUMt1Y
070E 28CO 1493 SLOl AX,AX
0710 BE08 1494 I1bv OS,AX I ESTABLISH SEGMENT
0712 C4360401 1495 LES SI,HF_TB~VEC
1496 ASSUHE DS:DATA

0716 IF 1497 pop OS
1498
1499 1----- SET TII1~OUT VALUES
1500
0717 2AFF 1501 SUB BH,BH
0719 268A5C09 1502 110V BL,BYTE PTR ES:[SI)(9J I ST AHOARO TIME OUT
0710 8A264200 1503 MOV
0721 60FC04 1504 C"P All, FMTORV_Ctro
072:4 7506 1505 JHZ
"5
~726 268A5COA
072"'E809
onc 80Fcn
1506
1507
1508 W5:
MOV
JMP
CMP
SHORT ...
BL,BYTE P1R ES:[SIHOAHI
AH,CHK_ORV_CHO
I FORHAT DRIVE
072F 7504 1509 JHZ "4

0731 268A5C08 1510 MOY SL,BYTE PTR ES:[SIHOBHl I CHECK DRIVE
0735 1511 ... '
0735 2BC9 1512 SUB CX,CX
1513
1514 1----- WAIT FOR INTERRUPT
1515
0737 1.516 WI:
0]37 E84400 1517 CALL PORT_l
073A EC 1518 IN AL,DX
0738 2420
0730 le20
1519
1520
.",
CMP
Al,020H
AL.020H I DID INTERRUPT OCCUR
073F 740" 152.1 JZ "2
0741 E2F4 1522 LOOP H1 I INNER lOOP
0743 46 1523 DEC BX
0744 7SF 1 1524 JHZ HI I OUTER LOOP
0746 C606740060 1525 MOV DISK_STATIJS, TINE_OUT
074B ~526 W2:

LOC OBJ LINE SOURCE
074B E8ll0D 1527 CALL PORT_O

014E EC 1528 IN Al,DX
074F 2402
0751 08067400
1529
1530
.""
OIl
ALI2
DISK_STATUS,A.L
I ERROR BIT
, SAVE
0755 £83000 1531 CALL PORT_l I INTERRUPT HASK REGISTER
0758 32CO 153Z XOR Al.AL. I ZERO
075A EE 1533 OUT DX .... L I RESET MASK
0758 5f 1534 POP SI I RESTORE REGISTERS
07St 07 1535 pop EO
0750 59 1536 POP CX
075E 58 1537 POP ex
075F C3 1538 R'T
1539 WAIT_INT ,NOP
1540
0760 1541 HD_IHT PROC NEAR
0760 50 1542 PUSH AX
0761 BOZO 1543 MOV AL,EOl I END OF INTERRUPT
0763 £620 1544 OUT INT_CTL_PORT ,AL
0765 B007 1545 MaV AL.07H J SET DNA HOOf TO DISABLE
0767 E60A. 1546 OUT OHA .. I0 ,AL
0769 f421 1547 IN Al,DZlH
0768 OC20 1548 OR AL,OlOH
0760 £621 1549 OUT Q21H.AL
076F 58 1550 POP AX
0770 Cf 1551 IRET
1552 HO_INT 'NDP
1553
1554 1-- - -- - ------ - - - -- -- - - - - - ---------- ------
1555 I PORTS
1556 GENERATE PROPER PORT VALUE
1557 BASED ON THE PORT OFFSET
1558 1-- - --- - - --------- - - -- ----- - - -- - -- -- -----
1559
0771 1560 PORT_O PROC NEAR
0771 BA2003 1561 MaV OX,HF _PORT 1 BASE VALUE
0774 50 156:!: PUSH AX
0775 2"E4 1563 SUB AH,AH
0777 A07700 1564 MOV AL,PORT_OFF 1 ADD IN THE OFFSET
077A 0300 1565 ADO OX,AX
onc 58 1566 POP AX
0770 C3 1567 RET
1568 PORT_O ,,,,,P
1569
onE 1570 PORT_l PROC NEAR
077E E8FOFF 1571 CALL PORT_O
0781 42 1572 It«: ox , INCREMENT TO PORT ONE
0782 C3 1573 RET
1574 PORT_l ENOP
1575
0783 1576 PORT_2 PROC NEAR
0783 E8F8FF 1577 tALL PORT_l
0786 42 1578 INC ox INCREMENT TO PORT TWO
0787 C3 1579 RET
1560 PORT_2 ,""P
1581
0786 1562 PORT_3 PROt NEAR
0788 E8FaFF 1583 CALL POOT_2
078B 42 1584 INC ox 1 INCREMENT TO PORT THREE
D7ac C3 1585 RET
1566 PORT_3 ENOP
1567
1586 1------------------------------------------------
1589 I SW2_0FFS
1590 DETERMINE PARAMETER TABLE OFFSET
a91 USING CONTROLLER PORT TWO At-m
Isn DRIVE tU1BER SPECIFIER (O-I)
1593 1-------- - -------- - - - - --- --- --- - -------- ---------
IS94
0780 1595 SW2_0FFS PROC NEAR
0780 E8F3FF 1596 CALL PORT_2
0790 EC 1597 IN AL,OX , READ PORT 2
0791 50 1598 PUSH AX
0792 E8E9FF 1599 CALL PORT_l
0795 EC 1600 IN AL,OX
0796 2402 16Ql AND AL,2 ; CHECK FOR ERROR
0798 58 1602 POP AX
0799 7516 1603 JNZ SW2_0FFS_ERR
0798 8A264300 1604 I10V AII,CHO_BLOCK.1
Fixed Disk BIOS A-to7

LOC OBJ LINE SOURCE
079F BOE4Z0 1605 ANIl AH,OOIOOOOOB J DRIVE 0 OR 1

07 .... 2 7504 1606 JHZ SW2j.tro
07.1.4 DOES 1607 SHR Al,l J ADJUST
07....6 DOE8 1606 SH. AL,I
07A6 1609 SW,_AND:
07A6 2403 1610 ANIl .... L.QlIB ; ISOLATE
07AA 8104 1611 HOV CL.4
07At OlEO 1612 SHL Al.CL I ADJUST
07AE 2A.E4 1613 SUS AH,AH
0780 C3 1&14 RET
07Bl 1615 SW2_ OFFS_ERR:
07Bl F9 1~16 STC
0782 C3 1617 RET
1618 SW2_0FFS ENOP
1619
0783 30382F31362:F38 1620 DB '08/16/82' ; RElEASE MARKER
32
162:1
0786 1622 END_ADDRESS LABEl BYTE
1623 CODE ENIlS
1624 E..,
A-I08 Fixed Disk BIOS

APPENDIX B: 8088 ASSEMBLY
INSTRUCTION SET REFERENCE
8088 Instruction Reference B-1

8088
Register Model
AX: AH AL Accumulator
BX: BH BL Base
CX: CH CL Count
DX: DH DL Data
General
Register File
SP I Stack Pointer
BP Base Pointer
~--------------------~
~__________S_I__________~ Sou rce Index
~=====D=I=====~ Destination Index

I--__________Ir-P__________.-,II nstruction Pointer
FLAGSH FLAGSL Status Flags
~----------~--------~
CS I Code Segment
DS Data Segment Segment
I------------------------i
I--__________S_S__________.-, Stac k Seg ment } Register File
ES
L -____________________ ~ Extra Segment
Instructions which reference the flag register file as a 16-bit object

use the symbol FLAGS to represent the file:
15 7 0
, X , X , X , X , OF , DF 'IF' TF , SF , ZF , X , AF , X , PF , X , CF ,
x = Don't Care
AF: Auxiliary Carry - BCD

CF:
PF:
SF:
ZF:
Carry Flag
Parity Flag
Sign Flag
Zero Flag
} 8080 Flags
DF: Direction Flag (Strings)

IF:
OF:
TF:
Interrupt Enable Flag
Overflow Flag (CF E9 SF)
Trap - Single Step Flag
} 8088 Flags
B-2 8088 Instruction Reference

Operand Summary
"reg field Bit Assignments:

16-Bit Iw=l) B-Bit (w=O) Segment
000 AX 000 AL 00 ES
001 CX 001 CL 01 CS
010 OX 010 OL 10 SS
011 BX 011 BL 11 OS
100 SP 100 AH
101 BP 101 CH
110 SI 110 OH
111 01 111 BH
Second Instruction Byte Summary

Imod I xxx I rim I
mod Displacement
00 OISP=O*, disp-Iow and disp-high are absent
01 OISP=disp-low sign-extended to 16-bits, disp-high is absent
10 OISP=disp-high: disp-Iow
11 rim is treated as a "reg" field
rim Operand Address

000 (BX) + (SI) + OISP
001 (BX) + (01) + OISP
010 (BP) + (SI) + OISP
011 (BP) + (01) + OISP
100 (SI) + OISP
101 (01) + OISP
110 (BP) + OISP*
111 (BX) + OISP
OISP follows 2nd byte of instruction (before data if required).

*except if mod = 00 and rim = 110 then EA = disp-high: disp-Iow.

Memory Segmentation Model
7 0
logical
.t.r--,:t. FF F FFH
Memory Space
f
sr B }
Code Segment
XXXXOH
"'.::::: ~
DisPlac~me~
15 0 I ......
Offset
I :"
Addre ss r---
,, r--iI
i=
I MSB
15 : 0 I Word {
lSB
Selected
Segment
Register
CS.SS.DS.ES
CS
SS
OS
ES
0000
0000
0000
"'""
0000 I---
. :
BYTE
~
or none I 1---,,
for 1/0. INT II
I
I
I
,,
I
,
I
ill.
T""
7"
,
I
:I Adder
I
I
,
I
.
Yj-
}
Extra Data
Segment
OOOOOH
I T
~
I I
19 0 Physical
I I Address
latch
Segment Override Prefix
I 0 0 1 reg 1 1 0
Use of Segment Override
Operand Register Default With Override Prefix

IP (Code Address) CS Never
SP (Stack Address) SS Never
BP (Stack Address or Stack Marker) SS BP + OS or ES, or CS
SI or 01 (not including strings) OS ES, SS, or CS
SI (Implicit Source Address for Strings) OS ES,SS, orCS
01 (Implicit Destination Address for Strings) ES Never

Data Transfer
MOV = Move
Register/memory to/from register
11 0 0 0 1 0 d w 1 mod reg r/ m
Immediate to register/memory
11 1 0 0 0 1 1 w 1 mod 0 0 0 r / m data data if w=1 1
Immediate to register
11 0 1 1 w reg data data if w=1 1
Memory to accumulator
11010000wl addr-Iow addr-high
Accumulator to memory
11010001wl addr-Iow addr-high
Register /memory to segment register

11 0 0 0 1 1 1 0 1 mod 0 reg r / m
Segment register to register/memory

11 0 0 0 1 1 0 0 mod 0 reg r/ m
PUSH = Push
Register /memory
1111111 mod 1 10 rim
Register
I0 1 0 1 0 reg
Segment register
10 0 0 reg 1 0 1
POP = Pop
Register/memory
1100011 1 1 mod 0 0 0 r /m
Reg ister
10 1 0 1 1 reg
Segment register
10 0 0 reg 1

XCHG =Exchange
Registerlmemory with register
11 0 0 0 0 1 1 w 1 mod reg rIm
Register with accumulator

11 0 0 1 0 reg 1
IN = Input to ALI AX from

Fixed port
11 1 1 0 0 1 0 w 1 port
Variable port (DX)

11110110wl
OUT = Output from ALI AX to

Fixed port
11 1 1 0 0 1 w I port
Variable port (DX)
11110110wl
XLAT = Translate byte to AL

1110101111
LEA = Load EA to register

11 0 0 0 1 1 0 1 mod reg rIm
LOS = Load pointer to DS

11 1 0 0 0 1 0 1 mod reg rIm
LES = Load pointer to ES

11 . 1 0 0 0 1 0 0 1 mod reg rIm 1
LAHF = Load AH with flags

1100111111
SAHF = Store AH into flags

11 0 0 1 1 1 1 0
PUSHF = Push flags

11 0 0 1 1 1 0 0
POPF = Pop flags

11 0 0 1 1 1 0 1

Arithmetic
ADD = Add
Register /memory with register to either
I0 0 0 0 0 0 d w I mod reg rIm
Immediate to register /memory

I1 0 0 0 0 0 s w I mod 0 0 0 rIm data I data if s:w=01
Immediate to accumulator
I0 0 0 001 0 w I data data if w=1
ADC = Add with carry

Register /memory with register to either
I0 0 0 1 0 0 d w I mod reg rIm
I1 0 0 0 0 0 s w I mod 0 1 0 r /m data data if s:w=01
10001010wl data data if w=1
INC = Increment
Register /memory
1111111 w I mod 0 0 0 rIm
Register
1 0 1 0 0 0 reg
AAA = ASCII adjust for add

1001101111
DAA = Decimal adjust for add

1001001111
SUB = Su btract
Register/memory and register to either
10 0 1 0 1 0 d w I mod reg r / m
Immediate from register/memory

I1 0 0 0 0 0 s w I mod 1 0 rIm data data if s:w=01
Immediate from accumulator

1 0 0 1 0 1 1 0 w 1 data data if w=1

SBB = Subtract with borrow
1 0 0 0 1· 1 0 d w 1 mod reg r/ m
Immediate from register/memory

11 0 0 0 0 0 s w 1 mod 0 1 rIm data data if s:w=01
Immediate from accumulator

10 0 0 1 1 1 0 w 1 data data if w=1
DEC = Decrement
Register/memory
1111111 w 1 mod 0 0 1 r /m
Register
1 0 1 0 0 1 reg
NEG = Change sign

1111101 w I mod 0 1 1 rIm
CMP = Compare
Register/memory and register
10 0 1 1 1 0 d w 1 mod reg r/ m
Immediate with register/memory

11 0 0 0 0 0 s w 1 mod 1 1 rIm data data if s:w=01
Immediate with accumulator

I0 0 1 1 1 1 0 w 1 data data if w=1
AAS = ASCII adjust for subtract

100111111\
DAS = Decimal adjust for subtract

100101111\
MUl = Multiply (unsigned)

11 1 1 1 0 1 1 w 1 mod 1 0 0 rIm
IMUl = Integer multiply (signed)

11 1 1 1 0 1 1 w 1 mod 1 0 1 r /m
AAM = ASCII adjust for multiply

1 1 101010010000100
DlV = Divide (unsigned)

11 1 1 1 0 1 1 w 1 mod 1 1 0 r / m 1

IDIV = Integer divide (signed)
11 1 1 1 0 1 1 w 1 mod 1 1 1 rim
AAD = ASCII adjust for divide

1110101011000010101
CBW = Convert byte to word

1100110001
cwo = Convert word to double word

110011001
logic
NOT = Invert
11 1 1 1 0 1 1 w mod 0 1 0 rim
SHLISAL = Shift logicallarithmetic left

11 1 0 1 0 0 v w 1 mod 1 0 0 rim
SHR = Shift logical right

11 1 0 1 0 0 v w 1 mod 1 0 1 rim
SAR = Shift arithmetic right

11 1 0 1 0 0 v w 1 mod 1 1 1 rim
ROL = Rotate left

11 1 0 1 0 0 v w mod 0 0 0 rim
ROR = Rotate right

11 1 0 1 0 0 v w mod 0 0 1 rim
RCL = Rotate through carry left

11 1 0 1 0 0 v w 1 mod 0 1 0 rim
RCR = Rotate th rough carry right

11 1 0 1 0 0 v w 1 mod 0 1 1 rim
AND = And
Registerlmemory and register to either
I0 0 1 0 0 0 d w 1 mod reg rim
Immediate to registerlmemory
11 0 0 0 0 0 0 w 1 mod o 0 rim data data if w=1
10010010w data data if w=1

TEST = And function to flags, no result
Register/memory and register
11 a a a a 1 Owl mod reg rim
Immediate data and register/memory

11 1 1 1 a 1 1 w I mod aaa r /m data data if W=1
Immediate data and accumulator

11 a 1 a 1 a a w I data data if w=1
OR = OR
10 a a a 1 a d w I mod reg rim
11 a a a a a a w I mod a a 1 rim data data if w=1
10000110wl data data if w=1
XOR = Exclusive or
Ia a 1 1 a a d w I mod reg r /m
11 a a a a a a w I mod 1 1 a r /m data data if w=1
10 a 110 10 w data data if w=1
String Manipulation
REP = Repeat
11 1 1 1 0 01 z
MOVS = Move String

11010010wl
CMPS = Compare String

ITO 10 a 11 w
SCAS = Scan String

11010111 w
B-lO Instruction Reference

LOOS = Load String
110 1 0 1 1 0wl
STOS = Store String

1101010 wi
Control Transfer
CALL = Call
Direct within segment
11 1 1 0 1 0 0 0 1 disp-Iow disp-high
Indirect within segment

1111111 mod 0 1 0 rim
Direct intersegment
110011010 offset-low offset-high
seg-Iow seg-high
Indirect intersegment
11111111 mod 0 1 1 rim
JMP = Unconditional Jump

Direct within segment
11 1 1 0 1 0 0 1 1 disp-Iow disp-high
Direct within segment-short

11 1 1 0 1 0 1 disp
Indirect within segment

11 1 1 1 1 1 mod 1 0 0 rim
Direct intersegment
111101010 offset-low offset-high
seg-Iow seg-high
Indirect intersegment
11111111 mod 1 0 1 rim
8088 Instruction Reference B-II

RET = Return from CALL
Within segment
1110000111
Within segment adding immediate to SP

11 1 0 0 0 0 1 01 data-low data-high
Intersegment
1110010111
Intersegment, adding immediate to SP

11 1 0 0 0 0 1 0 1 data-low data-high
JE/JZ =Jump on equal/zero

10 1 1 1 0 1 0 0 1 disp
JL/JNGE = Jump on less/not greater or equal

I0 1 1 1 1 1 0 0 1 disp 1
JLE/JNG = Jump on less or equal/not greater

10 1 1 1 1 1 1 0 1 disp 1
JB/JNAE = Jump on below/not above Or equal

10 1 1 1 0 0 1 Old is P 1
JBE/JNA = Jump on below or equal/not above

10 1 1 1 0 1 1 0 1 disp I
JP/JPE = Jump on parity/parity even
10 1 1 1 1 0 1 0 I disp
JO =Jump on overflow
I 0 1 1 1 0 0 0 oI disp
JS =Jump on sign
10 1 1 1 1 0 0 oI disp
JNE/JNZ = Jump on not equal/not zero

I0 1 1 1 0 1 0 1 1 disp
JNL/JGE = Jump on not less/greater or equal

I0 1 1 1 1 1 0 1 I disp I

JNlE/JG = Jump on not less or equal/greater
I0 1 1 1 1 1 1 1 I disp I
JNB/JAE = Jump on not below/above or equal
I0 1 1 1 0 0 1 1 I disp I
JNBE/JA = Jump on not below or equal/above
I0 1 1 1 0 1 1 1 I disp
JNP/JPO = Jump on not parity/parity odd

I0 1 1 1 1 0 1 1 I disp
JNO =Ju mp on not overflow

I0 1 1 1 0 0 0 1 disp
JNS =Jump on not sign

I0 1 1 1 1 0 0 disp
lOOP = Loop ex times

11 1 1 0 0 0 1 0 disp
lOOPZllOOPE = Loop while zero/equal

11 1 1 0 0 0 0 1 I disp
lOOPNZllOOPNE = Loop while not zero/not equal

11 1 1 0 0 0 0 0 I disp I
JCXZ = Jump on ex zero
11 1 1 0 0 0 1 1 dis p

8088 Conditional Transfer Operations
Instruction Condition Interpretation
JE or JZ ZF =1 "equal" or "zero"
JL or JNGE (SF xor OF) =1 "less" or "not greater or equal"
JLE or JNG ((SF xor OF) or "less or equal" or "not greater"
ZF) =1
JB or JNAE or JC CF =1 "belo~" or "not above or equal"
JBE or JNA (CF orZF) =1 "beloW or equal" or "not above"
JP or JPE PF =1 "parity" or "parity even"
JO OF =1 "overflow"
JS SF =1 "sign"
JNE or JNZ ZF =0 "not equal" or "not zero"
JNL or JGE (SF xor OF) =0 "not less" or "greater or equal"
JNLE or JG ((SF xor OF) or "not less or equal" or "greater"
ZF) =0
JNB or JAE or JNC CF =0 "not below" or "above or equal"
JNBE or JA (CF or ZF) =0 "not below or equal" or "above"
JNP or JPO PF =0 "not parity" or "parity odd"
JNO OF =0 "not overflow"
JNS SF =0 "not sig n"
'''Above'' and "below" refer to the relation between two unsigned values, while
"greater" and "less" refer to the relation between two signed values.
INT = Interrupt
Type specified
11 1 0 0 1 1 0 1 type
Type 3
11 10011001
INTO = Interrupt on overflow

1110011101
IRET = Interrupt return

11 100111

Processor Control
ClC = Clear carry STC = Set carry
1 1 1 1 1 a a 01 1 1 1 11 1001
CMC = Complement carry NOP = No operation

111101011 1100100001
ClD = Clear direction STO = Set direction

1 1 1 1 1 1 0 01 111 11 1101
CLI =Clear interrupt STI =Set interrupt

~1_1__1__1__1__
0 ___0~1 11 1 1 1 1 a 1 1
Hl T = Halt WAIT = Wait

1 1 1 1 0 1 0 01 110011011
lOCK = Bus lock prefix ESC = Escape (to external device)

1 1 1 10 a a 01 1 1 a 1 1 x x x I mod x x x r/ m I
Footnotes:
if d =1 then "to"; if d =a then "from"
if w =1 then word instruction; if w =a then byte instruction
if s:w = 01 then 16 bits of immediate data from the operand
if s:w = 11 then an immediate data byte is sign extended to form the 16-bit operand
if v = a then "count" = 1; if v =1 then "count" in (Cl)
x = don't care
z is used for some string primitives to compare with ZF FLAG
AL = 8-bit accumulator
AX = 16-bit accumulator
CX = Count register
DS = Data segment
DX = Variable port register
ES = Extra segment
Above/ below refers to unsig ned value
Greater = more positive;
Less = less positive (more negative) signed values

8088 Instruction Set Matrix
LO
HI 0 1 2 3 4 5 6 7
0 ADD ADD ADD ADD ADD ADD PUSH POP
b,t,r/m w,t,r/m b,t,r/m w,t,r/m b,ia w,ia ES ES
1 ADC ADC ADC ADC ADC ADC PUSH POP
b,t,r 1m w.t,r/m b,t,r/m w,t,r/m b,i w,i SS SS
2 AND AND AND AND AND AND SEG DAA
b,t,r/m w,t,r/m b,t,r/m w,t,r/m b,i w,i =ES
3 XOR XOR XOR XOR XOR XOR SEG AAA
b,t,r 1m w,t,r/m b,t,r/m w,t,r/m b,i w,i =SS
4 INC INC INC INC INC INC INC INC
AX CX DX BX SP BP SI DI
5 PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH
6
7 JO JNO JBI JNBI JEI JNEI JBEI JNBEI

JNAE JAE JZ JNZ JNA JA
8 Immed Immed Immed Immed TEST TEST XCHG XCHG
b,r/m w,r/m b,r/m is,rlm b,r/m w,r/m b,r/m w,r/m
9 NOP XCHG XCHG XCHG XCHG XCHG XCHG XCHG
CX DX BX SP BP SI DI
A MOV MOV MOV MOV MOVS MOVS CMPS CMPS
m AL m AL AL m AL m b W b W
B MOV MOV MOV MOV MOV MOV MOV MOV

i AL i CL i DL i BL i AH i CH i DH i BH
C RET RET LES LDS MOV MOV
(i+SP) b,i,r/m w,i,r/m
D Shift Shift Shitt Shift AAM AAD XLAT
b W b,v w,v
E LOOPNZI LOOPZI LOOP JCXZ IN IN OUT OUT
LOOPNE LOOPE b W b W
F LOCK REP REP HLT CMC Grp 1 Grp 1

z b,r/m w,r/m
b = byte operation m = memory

d = direct rim = EA is second byte
t = tromCPU reg si = short intrasegment
i = immediate sr = segment register
ia = immed. to accum. t = to CPU reg
id = indirect v = variable
. is = immed. byte, sign ext. W = word operation
I = long ie. intersegment z = zero

8088 Instruction Set Matrix
LO 8 9 A B C D E F
HI
0 OR OR OR OR OR PUSH
b,f,r/m w,f,r/m b,t,r/m w,t,r/m b,i w,i CS
1 SBB SBB SSB SBB SBB SBB PUSH POP
b,f,r/m w,f,r 1m b,t,r 1m w,t,r/m b,i w,i DS DS
2 SUB SUB SUB SUB SUB SUB SEG= DAS
3 CMP CMP CMP CMP CMP CMP SEG= AAS
4 DEC DEC DEC DEC DEC DEC DEC DEC
5 POP POP POP POP POP POP POP POP
6
7 JS JNS JPI JNPI JLI JNLI JLEI JNLEI

JPE JPO JNGE JGE JNG JG
8 MOV MOV MOV MOV MOV LEA MOV POP
b,f,r/m w,f,r/m b,t,r/m w,t,r/m sr,t,r/m sr,f,r/m rim
9 CBW CWD CALL WAIT PUSHF POPF SAHF LAHF
I,d
A TEST TEST STOS STOS LODS LODS SCAS SCAS
b,i w,i b W b W b W
B MOV MOV MOV MOV MOV MOV MOV MOV

i AX i CX i DX i BX i SP i BP i SI i DI
C RET RET INT INT INTO IRET
1,(i+SP) I Type 3 (Any)
D ESC ESC ESC ESC ESC ESC ESC ESC
0 1 2 3 4 5 6 7
E CALL JMP JMP JMP IN IN OUT OUT
d d I,d si,d v,b V,W v,b V,W
F CLC STC CLI STI CLD STD Grp 2 Grp 2

b,r/m w,r/m
where:
modor/m 000 001 010 011 100 101 110 111
Immed ADD OR ADC SBB AND SUB XOR CMP
Shift ROL ROR RCL RCR SHLISAL SHR - SAR
Grp 1 TEST - NOT NEG MUL IMUL DIV IDIV
Grp 2 INC DEC CALL CALL JMP JMP PUSH -
id I,id id I,id

Instruction Set Index
Mnemonic Page Mnemonic Page Mnemonic Page

AAA 8-7 JG 8-13 MOV 8-5
AAD 8-9 JGE 8-12 MOVS 8-10
AAM 8-8 JL 8-12 MUL 8-8
AAS 8-8 JLE 8-12 NEG 8-8
ADC 8-7 JMP 8-11 NOP 8-15
ADD 8-7 JNA 8-12 NOT 8-9
AND 8-9 JNAE 8-12 OR 8-10
CALL 8-11 JN8 8-13 OUT 8-6
C8W 8-9 JN8E 8-13 POP 8-5
CLC 8-15 JNE 8-12 POPF 8-6
CLD 8-15 JNG 8-12 PUSH 8-5
CLI 8-15 JNGE 8-12 PUSHF 8-6
CMC 8-15 JNL 8-12 RCL 8-9
CMP 8-8 JNLE 8-13 RCR 8-9
CMPS 8-10 JNO 8-13 REP 8-10
CWD 8-9 JNP 8-13 RET 8-12
DAA 8-7 JNS 8-13 ROL 8-9
DAS 8-8 JNZ 8-12 ROR 8-9
DEC 8-8 JO 8-12 SAHF 8-6
DIV 8-8 JP 8-12 SAL 8-9
ESC 8-15 JPE 8-12 SAR 8-9
HLT 8-15 JPO 8-13 S88 8-8
IDIV 8-9 JS 8-12 SCAS 8-10
IMUL 8-8 JZ 8-12 SHL 8-9
IN 8-6 LAHF 8-6 SHR 8-9
INC 8-7 LDS 8-6 STC 8-15
INT 8-14 LEA 8-6 STD 8-15
INTO 8-14 LES 8-6 STI 8-15
IRET 8-14 LOCK 8-15 STOS 8-11
JA 8-13 LODS 8-11 SU8 8-7
JAE 8-13 LOOP 8-13 TEST 8-10
J8 8-12 LOOPE 8-13 WAIT 8-15
J8E 8-12 LOOPNE 8-13 XCHG 8-6
JCXZ 8-13 LOOPNZ 8-13 XLAT 8-6
JE 8-12 LOOPZ 8-13 XOR 8-10

APPENDIX C: OF CHARACTERS,
KEYSTROKES, AND COLOR
As Text Attributes
Color / Graphics IBM

Value As Characters Monitor Adapter Monochrome
Display
Hex Dec Symbol K, Mod~_ Background I£O!ilg round Adapter
00 0 Blank Ctrl 2 Black Black Non-Display

(Null)
01 1 g Ctrl A Black Blue Underline
03 3 •• Ctrl C
I
Black
GI
Cyan
Normal
Normal
04 4
+ Ctrl D Black Red Normal
05 ~ Black Magenta No
06
07
08
6
8
•
• Ctrl G
Ctrl H,
Black
Black
Black
Brown
Light Grey
Dark Grey
Normal
Normal
Non-Display
Backspace,
Shift
Backspace
09 9 Ctrl I Black Light Blue High Intensity

0 Underline
OA 10 Ctrl J, Black Light Green High Intensity

Ctrl~
OB 11 cJ Ctrl K Black Light Green High Intensity
OC 12 9 Ctrl L, Black Light Red High Intensity
OD 13 Ctrl M,..-J, Black Light High Intensity

)l Shift.-J Magenta
OE 14 ~ Ctrl N Black Yellow High Intensity
OF 15 -P: CtrlO Black White High Intensity
10 16 ~ Ctrl P Blue Black Normal
11 17 ..... Ctrl Q Blue Blue Underline
12 18 t Ctrl R Blue Green Norma
13 19 !! Ctrl S Blue Cyan Normal
14 20 IT Ctrl T Blue Red Normal
15
16
17
21
22
23
-
~
~ Ctrl U
Ctrl V
Ctrl W
Blue
Blue
Magenta
Brown
Light Grey
Normal
Normal
Normal
Of Characters, Keystrokes, and Colors Col

As Text Attributes
Color/Graphics IBM
Display
Hex Dec Symbol Keystrokes Modes Background Foreground Adapter
18 24 t Ctrl X Blue Dark Grey High Intensity
19 25 j Ctrl Y Blue Light Blue High Intensity

Underline
1A 26 - Ctrl Z Blue Light Green High Intensity
1B 27 Ctrl [, Blue Light Cyan High Intensity
- Esc, Shift
Esc, Ctrl
Esc
1C 28 L Ctrl \ Blue Light Red High Intensity
10 29 Ctrl J Blue Light High Intensity

+--+
Magenta
1E 30 ... Ctrl6 Blue Yellow High Intensity
1F 31 T Ctrl - Blue White High Intensity
20 32 Blank Space Bar, Green Black Normal

Space Shift,
Space,
Ctrl Space,
Alt Space
21 33 ! ! Shift Green Blue Underline
22 34
.. .. Shift Green Green Normal
23 35 # # Shift Green Cyan Normal
24 36 $ $ Shift Green Red Normal
25 37 % % Shift Green Magenta Normal
26 38 & & Shift Green Brown Normal
27 39 Green Light Grey Normal
28 40 ( ( Shift Green Dark Grey High Intensity
29 41 ) ) Shift Green Light Blue High Intensity

Underline
2A 42 * * Note 1 Green Light Green High Intensity
28 43 + + Shift Green Light Cyan High Intensity
2C 44 Green Light Red High Intensity
20 45 - - Green Light High Intensity

Magenta
2E 46 Note 2 Green Yellow High Intensity
C-2 Of Characters, Keystrokes, and Colors

As Text Attributes
Color /Graphics IBM

Value As Characters Monitor Adapter
Monochrome
Display
2F 47 / / Green White High Intensity
30 48 0 0 Note 3 Cyan Black Normal
31 49 1 1 Note 3 Cyan Blue Underline
32 50 2 2 Note 3 Cyan Green Normal
33 51 3 3 Note 3 Cyan Cyan Normal
34 52 4 4 Note 3 Cyan Red Normal
35 53 5 5 Note 3 Cyan Magenta Normal
36 54 6 6 Note 3 Cyan Brown Normal
37 55 7 7 Note 3 Cyan Light Grey Normal
38 56 8 8 Note 3 Cyan Dark Grey High Intensity
39 57 9 9 Note 3 Cyan Light Blue High Intensity

Underline
3A 58 Shift Cyan Light Green High Intensity
3B 59 Cyan Light Cyan High Intensity
3C 60 < < Shift Cyan Light Red High Intensity
3D 61 = = Cyan Light High Intensity

Magenta
3E 62 > > Shift Cyan Yellow High Intensity
3F 63 ? ? Shift Cyan White High Intensity
40 64 @ @ Shift Red Black Normal
41 65 A A Note 4 Red Blue Underline
42 66 B B Note 4 Red Green Normal
43 67 C C Note 4 Red Cyan Normal
44 68 D D Note 4 Red Red Normal
45 69 E E Note 4 Red Magenta Normal
46 70 F F Note 4 Red Brown Normal
47 71 G G Note 4 Red Light Grey Normal
48 72 H H Note 4 Red Dark Grey High Intensity
49 73 I I Note 4 Red Light Blue High Intensity

Underline
4A 74 J J Note 4 Red Light Green High Intensity
Of Characters, Keystrokes, and Colors C-3

As Text Attributes
Color/Graphics IBM
Monochrome
Display
4B 75 K K Note 4 Red Light Cyan High Intensity
4C 76 L L Note 4 Red Light Red High Intensity
4D 77 M M Note 4 Red Light High Intensity

Magenta
4E 78 N N Note 4 Red Yellow High Intensity
4F 79 0 0 Note 4 Red White High Intensity
50 80 P P Note 4 Magenta Black Normal
51 81 Q Q Note 4 Magenta Blue Underline
52 82 R R Note 4 Magenta Green Normal
53 83 S S Note 4 Magenta Cyan Normal
54 84 T T Note 4 Magenta Red Normal
55 85 U U Note 4 Magenta Magenta Normal
56 86 V V Note 4 Magenta Brown Normal
57 87 W W Note 4 Magenta Light Grey Normal
58 88 X X Note 4 Magenta Dark Grey High Intensity
59 89 Y Y Note 4 Magenta Light Blue High Intensity

Underline
5A 90 Z Z Note 4 Magenta Light Green High Intensity
5B 91 [ [ Magenta Light Cyan High Intensity
5C 92 \ \ Magenta Light Red High Intensity
5D 93 1 1 Magenta Light High Intensity

Magenta
A
5E 94 A
Shift Magenta Yellow High Intensity
5F 95 - - Shift Magenta White High Intensity
60 96 Yellow Black Normal
61 97 a a Note 5 Yellow Blue Underline
62 98 b b Note 5 Yellow Green Normal
63 99 c c Note 5 Yellow Cyan Normal
64 100 d d Note 5 Yellow Red Normal
65 101 e e Note 5 Yellow Magenta Normal
66 102 f f Note 5 Yellow Brown Normal

As Text Attributes
Color/Graphics IBM
Display
67 103 g g Note 5 Yellow Light Grey Normal
68 104 h h Note 5 Yellow Dark Grey High Intensity
69 105 i i Note 5 Yellow Light Blue High Intensity

Underline
6A 106 j j Note 5 Yellow Light Green High Intensity
6B 107 k k Note 5 Yellow Light Cyan High Intensity
6C 108 I I Note 5 Yellow Light Red High Intensity
6D 109 m m Note 5 Yellow Light High Intensity

Magenta
6E 110 n n Note 5 Yellow Yellow High Intensity
6F 111 0 0 Note 5 Yellow White High Intensity
70 112 p p Note 5 White Black Reverse Video
71 113 q q Note 5 White Blue Underline
72 114 r r Note 5 White Green Normal
73 115 s s Note 5 White Cyan Normal
74 116 f f Note 5 White Red Normal
75 117 u u Note 5 White Magenta Normal
76 118 v v Note 5 White Brown Normal
77 119 w w Note 5 White Light Grey Normal
78 120 x x Note 5 White Dark Grey Reverse Video
79 121 y y Note 5 White Light Blue High Intensity

Underline
7A 122 z z Note 5 White Light Green High Intensity
7B 123 { { Shift White Light Cyan High Intensity

I I
7C 124 I I Shift White Light Red High Intensity
7D 125 l l Shift White Light High Intensity

Magenta
7E 126 ~ ~
Shift White Yellow High Intensity
7F 127 /:;. Ctrl - White White High Intensity
Of Characters, Keystrokes, and Colors C-S

As Text Attributes

Display
* * * * 80 to FF Hex are Flashing in both Color & IBM Monochrome * * * *

80 128 c;: Alt 128 Note 6 Black Black Non-Display
81 129 U Alt 129 Note 6 Black Blue Underline
82 130 e Alt 130 Note 6 Black Green Normal
83 131 Ii Alt 131 Note 6 Black Cyan Normal
84 132 ii Alt 132 Note 6 Black Red Normal
85 133 a Alt 133 Note 6 Black Magenta Normal
86 134 a Alt 134 Note 6 Black Brown Normal
87 135 c; Alt 135 Note 6 Black Light Grey Normal
88 136 e Alt 136 Note 6 Black Dark Grey Non-Display
89 137 e Alt 137 Note 6 Black Light Blue High Intensity

Underline
8A 138 e Alt 138 Note 6 Black Light Green High Intensity
8B 139 'I Alt 139 Note 6 Black Light Cyan High Intensity
8C 140 1 Alt 140 Note 6 Black Light Red High Intensity
8D 141 i Alt 141 Note 6 Black Light High Intensity

Magenta
8E 142 A Alt 142 Note 6 Black Yellow High Intensity
8F 143 A Alt 143 Note 6 Black White High Intensity
90 144 E Alt 144 Note 6 Blue Black Normal
91 145 ae Alt 145 Note 6 Blue Blue Underline
92 146 AE Alt 146 Note 6 Blue Green Normal
93 147 6 Alt 147 Note 6 Blue Cyan Normal
94 148 ii Alt 148 Note 6 Blue Red Normal
95 149 b Alt 149 Note 6 Blue Magenta Normal
96 150 Q Alt 150 Note 6 Blue Brown Normal
97 151 U Alt 151 Note 6 Blue Light Grey Normal
98 152 Y Alt 152 Note 6 Blue Dark Grey High Intensity
99 153 ii Alt 153 Note 6 Blue Light Blue High Intensity

Underline
9A 154 U Alt 154 Note 6 Blue Light Green High Intensity

As Text Attributes

Display
9B 155 ¢ Alt 155 Note 6 Blue Light Cyan High Intensity
9C 156 £ Alt 156 Note 6 Blue Light Red High Intensity
9D 157 ¥ Alt 157 Note 6 Blue Light High Intensity

Magenta
9E 158 Pt Alt 158 Note 6 Blue Yellow High Intensity
9F 159 J Alt 159 Note 6 Blue White High Intensity
AO 160 a Alt 160 Note 6 Green Black Normal
A1 161 f Alt 161 Note 6 Green Blue Underline
A2 162 6 Alt 162 Note 6 Green Green Normal
A3 163 U Alt 163 Note 6 Green Cyan Normal
A4 164 Ii Alt 164 Note 6 Green Red Normal
A5 165 N Alt 165 Note 6 Green Magenta Normal
A6 166 i!. Alt 166 Note 6 Green Brown Normal
A7 167 .£ Alt 167 Note 6 Green Light Grey Normal
A8 168 t. Alt 168 Note 6 Green Dark Grey High Intensity
A9 169 r- Alt 169 Note 6 Green Light Blue High Intensity

Underline
AA 170 -, Alt 170 Note 6 Green Light Green High Intensity
AB 171 Y, Alt 171 Note 6 Green Light Cyan High Intensity
AC 172 Y, Alt 172 Note 6 Green Light Red High Intensity
AD 173 i Alt 173 Note 6 Green Light High Intensity

Magenta
AE 174 « Alt 174 Note 6 Green Yellow High Intensity
AF 175 » Alt 175 Note 6 Green White H ig h Intensity

---
BO 176 Alt 176 Note 6 Cyan Black Normal
---
Bl 177 i Alt 177 Note 6 Cyan Blue Underline
B2 178
I Alt 178 Note 6 Cyan Green Normal
B3 179 Alt 179 Note 6 Cyan Cyan Normal
B4 180 - Alt 180 Note 6 Cyan Red Normal
B5
B6
181
==
182 ----l
Alt 181
Alt 182
Note 6
Note 6
Cyan
Cyan
Magenta
Brown
Normal
Normal

As Text Attributes
Color / GraphicsIBM
Monochrome
Display
B7 183
--n Alt 183 Note 6 Cyan Light Grey Normal
B8 184 Alt 184 Note 6 Cyan Dark Grey H ig h Intensity

==i
B9 185 .-l Alt 185 Note 6 Cyan Light Blue High Intensity
I Underline
BA 186 Alt 186 Note 6 Cyan Light Green High Intensity
BB 187 Alt 187 Note 6 Cyan Light Cyan High Intensity

===il
BC 188 ==::!J Alt 188 Note 6 Cyan Light Red High Intensity
BD 189
~ Alt 189 Note 6 Cyan Light
Magenta
High Intensity
BE 190
P Alt 190 Note 6 Cyan Yellow High Intensity
BF 191 Alt 191 Note 6 Cyan White High Intensity

II
CO 192 L- Alt 192 Note 6 Red Black Normal
C1 193 I Alt 193 Note 6 Red Blue Underline
C2 194 Alt 194 Note 6 Red Green Normal
C3 195
~ Alt 195 Note 6 Red Cyan Normal
C4 196 Alt 196 Note 6 Red Red Normal
C5 197 Alt 197 Note 6 Red Magenta Normal
C6 198
== Alt 198 Note 6 Red Brown Normal
C7 199 Jr- Alt 199 Note 6 Red Light Grey Normal
C8
C9
200
201
'-== Alt 200
Alt 201
Note 6
Note 6
Red
Red
Dark Grey
Light Blue
High Intensity
High Intensity
---.J L -
Ii Underline
CA 202 Alt 202 Note 6 Red Light Green High Intensity
CB 203 Alt 203 Note 6 Red Light Cyan High Intensity

-----, r -
CC 204
I~ Alt 204 Note 6 Red Light Red High Intensity
CD 205 Alt 205 Note 6 Red Light High Intensity

Magenta
CE 206
~~ Alt 206 Note 6 Red Yellow High Intensity
CF 207 Alt 207 Note 6 Red White High Intensity
DO 208 1 Alt 208 Note 6 Magenta Black Normal

As Text Attributes
Color/Graphics IBM
Value As Characters Monochrome
Monitor Adapter
Display
Hex IDec Symbol '~y~"v~~~ Modes Background Foreground Adapter
1209 6 Mag' i
D2 210 Alt 210 Note 6 Magenta Green Normal

II
D3 211 LL- Alt 211 Note 6 Magenta Cyan Normal
D4 1212 t:::::: Alt 212 Note 6 Magel
D5 213 Alt 213 Note 6 Magenta Magenta Normal

F
D6 214 Alt 214 Note 6 Magenta Brown
r-
D7 215 I Alt 215 Note 6 Magenta Light Grey Normal
D8 216 Alt 216 Note 6 Magenta Dark Grey High Intensity
D9 217 Alt 217 Note 6 Magenta Light Blue High Intensity

f-- Underline
DA 218 Alt 218 Note 6 Magenta Light Green H ig h Intensity
1219 219 6 1ge1 .igl Cyal High Intensity
DC 220 Alt 220 Note 6 Magenta Light Red High Intensity
DD 221 Alt 221 Note 6 Magenta Light High Intensity

Magenta
DE 222 Alt 222 Note 6 Magenta Yellow High Intensity
DF 223 Alt 223 Note 6 Ma! White High II msity
EO 224 O! Alt 224 Note 6 Yellow Black Normal
225 f3 Alt 225 6 Yellow Blue Underline
E2 226 r Alt 226 Note 6 Yellow Green Normal
E3 1227 6 Cyan NOI II
E4 228 2: Alt 228 Note 6 Yellow Red Normal
E5 1229 Alt 229 Note 6 Yellow Mag' rmal
E6 1230 AI 230 Note 6 Yellow Brown NOr!
E7 231 T Alt 231 Note 6
E8 232 1> Alt 232 Note 6 Yellow Dark Grey High Intensity
E9 233 e Alt 233 Note 6 Yellow Light Blue High Intensity

Underline
EA 234 n Alt 234 Note 6 Yellow Light Green High Intensity
EB 235 0 Alt 235 Note 6 Yellow Light Cyan High Intensity

As Text Attributes

Display
EC 236 00 Alt 236 Note 6 Yellow Light Red High Intensity
ED 237 <P Alt 237 Note 6 Yellow Light High Intensity

Magenta
EE 238 E Alt 238 Note 6 Yellow Yellow High Intensity
EF 239 n Alt 239 Note 6 Yellow White High Intensity
FO 240 -= Alt 240 Note 6 White Black Reverse Video
F1 241 ± Alt 241 Note 6 White Blue Underline
F2 242 ?: Alt 242 Note 6 White Green Normal
F3 243 :S Alt 243 Note 6 White Cyan Normal
F4 244
r Alt 244 Note 6 White Red Normal
F5 245 J Alt 245 Note 6 White Magenta Normal
F6 246 Alt 246 Note 6 White Brown Normal
F7 247 = Alt 247 Note 6 White Light Grey Normal
F8 248 0 Alt 248 Note 6 White Dark Grey Reverse Video
F9 249
• Alt 249 Note 6 White Light Blue High Intensity
Underline
FA 250 • Alt 250 Note 6 White Light Green High Intensity
FB 251 r Alt 251 Note 6 White Light Cyan High Intensity
FC 252 1] Alt 252 Note 6 White Light Red High Intensity
FD 253 2 Alt 253 Note 6 White Light High Intensity

Magenta
FE
FF
254
255
•
BLANK
Alt 254
Alt 255
Note 6
Note 6
White
White
Yellow
White
High Intensity
High Intensity
C-IO Of Characters, Keystrokes, and Colors

NOTE 1 Asterisk (*) can easily be keyed using two methods:
I I
1) hit the Prt. Sc key or 2) in shift mode hit the
rID key.
NOTE 2 Period (.) can easily be keyed using two methods:
1) hit theLE!key or 2) in shift or Num Lock
I
mode hit the D~II key.
NOTE 3 Numeric characters (0-9) can easily be keyed

using two methods: 1) hit the numeric keys on the
top row of the typewriter portion of the keyboard
or 2) in shift or Num Lock mode hit the numeric
keys in the 1O-key pad portion of the keyboard.
NOTE 4 Upper case alphabetic characters (A-Z) can easily

be keyed in two modes: 1) in shift mode the
appropriate alphabetic key or 2) in Caps Lock
mode hit the appropriate alphabetic key.
NOTE 5 Lower case alphabetic characters (a-z) can easily

be keyed in two modes: 1) in '"normal" mode hit
the appropriate key or 2) in Caps Lock
combined with shift mode hit the appropriate alphabetic
key.
NOTE 6 The 3 digits after the Alt key must be typed from
the numeric key pad (keys 71-73, 75-77, 79-82).
Character codes 000 through 255 can be entered in
this fashion. (With Caps Lock activated, Character
codes 97 through 122 will display upper case
rather than lower case alphabetic characters.)
Of Characters, Keystrokes, and Colors C-ll

Character Set (OO-7F) Quick Reference
DECIMAL
lv, . 0 16 32 48 64 80 96 112
• I~~~I~AL 0 1 2 3 4 5 6 7
p , P
IVALUE
0 0 BLANK
(NULL) ~
BLANK
(SPACE)
0 @
1 1 g ...... .I 1 A Q a q
2
3
2
3 -• " !
..
I I
=#=
2
3
B
C
R b r
S c s
4 4
+ err $ 4 D T d t
5 5 ~ § <Yo 5 E U e u
6
7
6
7
•-
• !
&
,
6
7
F
G
V f v
W g W
8 8 i ( 8 H X h x
•
9 9 0 1 ) 9 I Y 1. y
•
10 A --+
* • J Z J z
11 B cf ....- + , •
K [ k {
12 C ~ L , < L "'- I
I
I
13 0 ) ...-.. - - M ] m }
14 E ~ ... • > N 1\ n ~
15 F -¢; ... / ?
• 0 - 0 L:,.

Character Set (80-FF) Quick. Reference
DECIMAL
VALUE
•
•
HEXA
~!~luMtL
128 144 160 176 192 208 224 240
8 9 A B C 0 E F
, ..
0 0 <; E a, ... """"
"
"
I ex ---
1 1 U ce 1 ~~~
••
, ,
(J +
-
2 2 e IE 0, I II r-' >
-
3 3
1\
a 01\ u - lL 1T -<
4 4 a,•• 0,•• n -
~
b ~ r
5 5 a 0 N= F a J
..
a u, a y
0 1\
6 6 -
---t ~ r- -
7 7 ~ 0 T ,......",.,
U 11 ,......",.,
1\ ••
e y•• G
0
Q
0
8 8 ~
9 9 e,•• 0 I d - e •
10 A
••
e U -, f-L n •
~ :1
••
11 B 1 ¢ r--
0 -r
12 c 1, £ ~ d 00 n
13 0
1 ¥ ,U
0
cJ> 2
14 E A Pt « bd ~ E I
15 F A f' » n n BLANK
'FF'

Notes:

APPENDIX D: LOGIC DIAGRAMS
System Board (16/64K) .............................. D-2

System Board (64/256K) ............................ D-12
Keyboard - Type 1 ................................. D-22
Keyboard - Type 2 ................................. D-24
Expansion Board ................................... D-25
Extender Card ..................................... D-26
Receiver Card ..................................... D-29
Printer ............................................ D-32
Printer Adapter .................................... D-35
Monochrome Display Adapter ....................... D-36
Color/Graphics Monitor Adapter ..................... D-46
Color Display ...................................... D-52
Monochrome Display ............................... D-54
5-1/4 Inch Diskette Drive Adapter ................... D-55
5-1/4 Inch Diskette Drive - Type 1 ................... D-59
5-1/4 Inch Diskette Drive - Type 2 ................... D-62
Fixed Disk Drive Adapter ........................... D-64
Fixed Disk Drive - Type 1 ................ . . . . . . . . .. D-70
Fixed Disk Drive - Type 2 .......................... D-73
32K Memory Expansion Option ...................... D-76
64K Memory Expansion Option ...................... D-79
64/256K Memory Expansion Option .................. D-82
Game Control Adapter .............................. D-86
Prototype Card .................................... D-87
Asynchronous Communications Adapter ............... D-88
Binary Synchronous Communications Adapter .......... D-89
SDLC Communications Adapter ..................... D-91
Logic Diagrams D-l

~~~~
;:;:;:;: ~~
....;....;
~~
!£i!£i
p
~
§~~~
o
....
'0
........
Q)
Q)
..r::.
en
~
,.,.
I~~ I;)
~ ~I~ <
~ §£:i oc N
D-2 Logic Diagrams

~~ ~
- '"
,;. - ;;:
" ~ - §[ ;;:
:;
I~ Ii ~I:::l Ii ~ I; ~
[il !
~
'S ~
~ ;
~
~I~I
Ii 1>l1;;;1~lg ::;: I~ ::l
Ii
;:j
'S
[il
Ii .. . .:
~
.: ~
Ii
~ §:§: ;;: ;;: - §:ff '" -
" " ::::.::::.::::.::::. - §[
" §[
Logic Diagrams D-3

!!~§s ,. ;r: ;;: ;;: !2:!2:!2:EE !!!!2: Ef:: !ff!!H:H!!ff@
ii i
~
g
;i~~ II ~~B~5 ~ I~ ~ § ~flE~~eE
IIIIII
'\
'-- '\
I~
'--
'\
'\ ~
!l ~ .'\
- = = = "- ~
~~
.s. iii
; "-
~J ~~ ~\~ '1: ~ '1: "-
'\
........o
o
'\
~~5!l~ I -
IE
1"-1>--
1"-
M
...
'" "iE-
QI
'\
~l=~
zl<: QI
..c:
"
~;:-
>---
'\
'\
'\
II ~
...
"'C
1["'
~
~ l' ~ l' ~ ~ >0 1"-

~~~
."
o
~~
== = :!
;;;
-N~i
c
!il
= ~ ;; iii I~
=~=
= I"
1"- :~ !Xl
8 ,. E
~=~ Of
L.:::::==, L1----<,\ 1>- ...
QI
I" £
It"'
l- ~
~
I"
~
L---- I"
I"
-- ....
CD
- -- - --
~",~l'il'~:e>o
J
>---
= "
~["' ~ l' ~ ; ~ ~ >0]
-- --
g[",~l'~l'~:e >0
:~I:lm
---l-=~
",~l' ~l' ~:e >0 1
~ = c
~ ~ Ci
l<:~
~~
_ ~cmu ::J~~~
"~cmu ~
~ 5~~ =oemu ~ ~~~
_
COlI u
= =
~N
- ~l~ -N "lj;I- _
4~= NI~I
=T~ =
N
~
~
=1
I-
~ I
co
~
<0 .... 01
!! S ~ ~s
i
~=
ecce
Ii Cc C
II; ;!
e!ff ;;: ;;: e ~ e ~~=:=: ;;: -- ;r: - !ff~ ;;:
0-4 Logic Diagrams

Ii
...o
....o
~~~<
~cc\:!;\~\;I~ ""...
<Il
<Il
c::>c:>c:::>c:::.c::>==<=> .J:
§~cccccccd~ ~
---- ...
"'0
~ I~;"~ ~ ro;~~I;~~I;;;~
~I~~:
-
c:;> _ <'? c:;> O_N<":> .... " ' l Q .... CIl
~~ ~ ~~ ~><~~SSSS o
III
'" ...E
<Il
en
>
en
~
~
...
co
II 111111
:!~:l8 1;!g;I~I~lili [~~~~ !HHHl1H'i~~

II
'ili
111111111111111111
~eee ff~~~§ee~ ~~~~= eeeeeeee ~~
Logic Diagrams D-5

1111111 111111
if 5
L
~
z~ o
.-
~~
....o
~
...
Ll'l
I
r§=~a;:!ai§:;
; Q)
Q)
.J::.
rt
I en
r - ~
_x
ill §>< ['l -~
['l
:~;;:~~::~~<~~:i::i~~ ['l
~ ~ ~ ~
~~~['l -- ~-
"-------L- t -
.....
~WJ~~
~[~»~i~ ~~
cc<cc<c""c61~
J,.,
~
~~~~~>~~
~
- ' « « « < ... i<!i~
~I
~~I~~
~=====~==
;;;!;~ ~l
««~«CClt:lS
::::l
~I
~
....J
-~ -~
««
~
S
ICO
C<:
C
I
---- =~~Nl" N~~~=""':=-T=L" -~~~~~-~"r-L N~ ~~
,.~~
1i'ilrlllll~I~Ii'l 5 I'Ti
~:;C~::l;::!:E~:.o:
::!l!"";,~::l;
gc~g;,g:g~::;
~;
Ii
'i-~~1!:i
Ii
=:=:=:=:=:=:=:=: §§:§:§:ffi2 =:=:~=:=:=:~~ =:=:=:=:=:=::=:=:
" ---- E
0-6 Logic Diagrams

E4'~--------~'~E mE
-6 z.n
~ ~~ Ern
:! !r;:::~C---;;
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Logic Diagrams D-37

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TESTOSC:===+==+===!j +XACK (SliT 6)

(SKT 7J -HRES +10 READY (SliT 1)
[SKT 2J HA3
DOTCLK (SliT 7.101
RoMAll [SliT 10)
-elR VIDEO (SliT 5.7.101

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·DlSPU OLl (SliT 7)

+OISPEN OLY (SliT 7)
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Logic Diagrams D-39

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0-40 Logic Diagrams

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D-42 Logic Diagrams

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Logic Diagrams D-43

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Logic Diagrams D-45

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D-46 Logic Diagrams

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Logic Diagrams 0-47
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0-48 Logic Diagrams

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Logic Diagrams D-49

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D-50 Logic Diagrams

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Logic Diagrams 0-51

DANGER
HAZARDOUS VOLTAGES
UP TO 450 VOLTS EXIST
ON THE PRINTED
CIRCUIT BOARDS
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Color Display (Sheet 1 of 1 )
0-52 Logic Diagrams

NOTES:
DANGER 1. RESISTOR VALUES ARE IN OHMS K = 1000 OHMS.
2. ALL RESISTORS ARE 112 WATT EXCEPT WHERE
OTHERWISE IN01CATEO.
HAZARDOUS VOLTAGES 3. CAPACITOR VALUES ARE IN ilF UNLESS OTHERWISE
UP TO 450 VOLTS EXIST INDICATED P= PF.
4. ALL CAPACITORS ARE 50 VOLTS UNLESS OTHERWISE
ON THE PRINTED IN01CATED.
CIRCUIT BOARDS
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Logic Diagrams D-53

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I HAZARDOUS VOLTAGES
DUALla 8211. C507 I I
112W ~V I I
UP TO 450 VOLTS EXIST
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ON THE PRINTED
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I 111. - 111 ..J I _T 2ZOJi Ions
+ C405 : I 50V ® - I 25' 1,RES1STORVALUESAREINIOHM)al(- 100001- 1.000,0000
2. ALL RESISTOR ARE 1/4WEXCEPT WHEIIE OTHERWISE INDIC.l.TEIi.
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PUSE= BLACK/BROnWIRE
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Monochrome Display (Sheet 1 of 1)

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UTEPI 20 I '+:r "I
462
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE IN OHMS. 1/4 W,
5%,
2. ALL CAPS ARE IN tkO.
3. ALL DIODES ARE IN 4446.
4. ALL TRANSISTORS MPM ARE 2n4124 iii
PNP ARE 2..4125.
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D-62 Logic Diagrams

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0-66 Logic Diagrams

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D-84 Logic Diagrams

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Logic Diagrams D-85

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Logic Diagrams 0-87

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RECEIVE DATA
Asynchronous Communications Adapter (Sheet 1 of 1)

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Logic Diagrams 0-91

SOLC Communications Adapter (Sheet 1 of 2)
D-92 Logic Diagrams

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SDLC Communications Adapter (Sheet 2 of 2)
Logic Diagrams D-93

Notes:
0-94 Logic Diagrams

APPENDIX E: SPECIFICATIONS
System Unit
Size:
Length--19.6 in (SOO mm)
Depth--16.1 in (410 mm)
Height--S.S in (142 mm)
Weight:
20.9 lb (9.S kg) Without a diskette drive unit
2S.0 lb (11.4 kg) With one diskette drive unit
Power Cable:
Length--6 ft (1.83 m)
Size--18 A WG
Environment:
Air Temperature
System ON, 60 0 to 90 0 F (1S.6° to 32.20 C)
System OFF, SOD to 110 0 F (10 0 to 43 0 C)
Humidity
System ON, 8% to 80%
System OFF, 20% to 80%
Heat Output:
1083 BTU/hr
Noise Level:
S6 dB Without printer
66 dB With printer
Electrical:
Nominal--120 Vac
Minimum--l04 Vac
Maximum--127 Vac
kVA--0.317S (maximum)
Keyboard
Size:
Length--19.6 in (SOO mm)
Depth--7.87 in (200 mm)
Height--2.2 in (S7 mm)
Weight:
6.S lb (2.9 kg)
Specifications E-l
Color Display
Size:
Length--15.4 in (392 mm)
Depth--1S.6 in (407 mm)
Height--11.7 in (297 mm)
Weight:
26lb (11.8 kg)
Heat Output:
240BTU/hr
Power Cable:
Size--18 AWG
Signal Cable:
Length--S ft (1.S m)
Size--22 A WG
Expansion Unit
Size:
Depth--16.1 in (410 mm)
Height--S.S in (142 mm)
Weight:
33lb (14.9 kg)
Power Cable:
Size--18 AWG
Signal Cable:
Length--3.28 ft (1 m)
Size--22 AWG
Environment:
Air Temperature
System ON, 60° to 90° F (lS.6° to 32.2° C)
System OFF, SOo to 110° F (10° to 43° C)
Humidity
System ON, 8% to 80%
System OFF, 20% to 80%
Heat Output:
717 BTU/hr
Electrical:
Nominal--120 Vac
Minimum--104 Vac
Maximum--127 Vac
E-2 Specifications
Monochrome Display
Size:
Depth--13.7 in (350 mm)
Height--ll in (280 mm)
Weight:
17.3 lb (7.9 kg)
Heat Output:
325 BTU/hr
Power Cable:
Size--18 AWG
Signal Cable:
Size--22 A WG
80 CPS Printers
Size:
Length--15 .7 in (400 mm)
Depth--14.5 in (370 mm)
Height--4.3 in (110 mm)
Weight:
12.91b (5.9 kg)
Power Cable:
Length--6 ft (1.83 mm)
Size--22 A WG
Heat Output:
341 BTU/hr (maximum)
Electrical:
Nominal--120 Vac
Minimum--104 Vac
Maximum--127 Vac
Specifications E-3
tr1
~
I Front View (Component Side)
liB) (')
...c..
OJ
en
"C
til I I---------~
m
n
'0
(1) ~ Loc. Ho)e ::;;
(') n'
s
(')
0.125 ± .002 (3.175 ± .05)
...0'
OJ
:::I
o·~
II>
0.125 +
_. 005 (3.175 ± .127) iii iii
=
00
iii
'"
to
0 '"'
'S"'
0
Copper Pad
(To Ground)
~
<t
coi
.. .
0
N
0.4 (10.16) t
0.705 (17.907)
12.B (325.12) o 3.190±.005 (Bl.026±.127)
13.13± .020 (333.502 ± .50B
Notes:
1. All Card Dimensions 2. Max. Card Length is 13.15 (334.01) 4. 31 Gold Tabs Each Side. 5. Numbers in Parentheses
are ± .01 0 (.254) Tolerance Smaller Length is Permissible 0.100 ± .0005 (2.54 ± .0127) Center are in Millimeters All Others
(With Exceptions Indicated 3. Loc. and Mounting Holes are to Center, 0.06 ± .0005 (1 .524 ± .0127) are in Inches.
on Drawing or in Notes). Non-Plated Thru. Width
(Loc. 3X. Mtg. 2X).
APPENDIX F: COMMUNICATIONS
Information processing equipment used for communications is
called data terminal equipment (DTE). Equipment used to
connect the DTE to the communications line is called data
communications equipment (DCE).
An adapter is used to connect the data terminal equipment to the
data communications line as shown in the following illustration:
Data Communications
Data Communications Line
Terminal Equipment
Equipment
Z-
Voice Line
EIA/CCITT Cable Conforming to EIA

Adapter or CCITT Standards
The EIA/CCITT adapter allows data terminal equipment to be

connected to data communications equipment using EIA or
CCITT standardized connections. An external modem is shown
in this example; however, other types of data communications
equipment can also be connected to data terminal equipment using
EIA or CCITT standardized connections.
EIA standards are labeled RS-x (Recommended Standards-x) and
CCITT standards are labeled V.x or X.x, where x is the number
of the standard.
The EIA RS-232 interface standard defines the connector type,
pin numbers, line names, and signal levels used to connect data
terminal equipment to data communications equipment for the
purpose of transmitting and receiving data. Since the RS-232
standard was developed, it has been revised three times. The three
revised standards are the RS-232A, the RS-232B, and the
presently used RS-232C.
The CCITT V.24 interface standard is equivalent to the RS-232C
standard; therefore, the descriptions of the EIA standards also
apply to the CCITT standards.
Communications F -1
The following is an illustration of data terminal equipment
connected to an external modem using connections defined by the
RS-232C interface standard:
Data
Terminal
Equipment
Communications
Line
~...==--------
--~----~'"," . . . . '"
"
Adapter ,,/ Cable Conforming "" '
///// To RS-232C Standards """""" """"
... EIA/CCITT Telephone Co.

/----< Line Name Lead Number .......----..,;....
Protective Ground @-AA/101
Signal Ground 0--AB/102
Transmitted Data ®--- BAI 103

Received Data ®-BB/104
Request to Send @-CA/105

Clear to Send @--CB/106
Data Set Ready ®--CC/107
Data
Terminal Data Terminal Ready @--CD/108.2 Modem
Equip- Connect Data Set to Line ------@--"/108.1
ment
Received Line Signal Detector CF 1109
Speed Select CH/111

Transmit Signal Element Timing ~ DB/114
Receive Signal Element Timing ~ DD/115
Select Standby @-- ** 1116
Ring Indicator @--DE/125
Test ~**I'**
I
External Modem Cable Connector
131211109 8 765 4 3 2 1
+
0 0 0 0 0 0 0 0 0 0 0 0 0/
\ ooooooooooooj
252423222120191817161514
1_ . ___ .Dat~ Terminal .___ 6~~:~~~~~~ications --'

I Equipment Equipment-I
Pin Number
'Not used when business machine clocking is used.

'*Not standardized by EIA (Electronics Industry Association).
'**Not standardized by CCITT
F -2 Communications
Establishing a Communications Link
The following bar graphs represent normal timing sequences of
operation during the establishment of communications for both
switched (dial-up) and nonswitched (direct line) networks.
Switched Timing Sequence
Data Terminal Ready
Data Set Ready ~r-----------------------------
Request to Send
Clear to Send ________ ~------------IL--
Transmitted Data
Nonswitched Timing Sequence
Data Terminal Ready ~r--------------------------------
Data Set Ready
Request to Send ______s----------------,L--

Clear to Send ______ ~------------~L
Transmitted Data
The following examples show how a link is established on a

nonswitched point-to-point line, a nonswitched multipoint line,
and a switched point-to-point line.
Communications F-3
"t1
I Establishing a Link on a Nonswitched Point-to-Point Line
~
(l 1. The terminals at both locations activate the 'data terminal ready' 11. Terminal A and modem A now become receivers and wait for a
0 linesaand • . response from terminal B, indicating that all data has reached
3 2. Normally the 'data set ready' linesElandllfrom the modems are
terminal B. Modem A begins an echo delay (50 to 150
3 active whenever the modems are powered on. milliseconds) to ensure that all echoes on the line have
=
....
=
()
3. Terminal A activates the 'request to send' linea, which causes
diminished before it begins receiving. An echo is a reflection of
the transmitted signal. If the transmitting modem changed to
the modem at terminal A to generate a carrier signal. receive too soon, it could receive a reflection (echo) of the signal it
~
.... just transmitted.
4. Modem B detects the carrier, and activates the 'received line
0
=
~
signal detector' line (sometimes called data carrier detect)m.
Modem B also activates the 'receiver signal element timing' line
12, Modem B deactivates the 'received line signal detector' linelm
and, if necessary, deactivates the receive clock signals on the
(sometimes called receive clock)lIIto send receive clock signals to 'receiver signal element timing, linelll,
the terminal. Some modems activate the clock signals whenever
13. Terminal B now becomes the transmitter to respond to the
the modem is powered on,
request from terminal A. To transmit data, terminal B activates the
5, After a specified delay, modem A activates the 'clear to send' line 'request to send' linem, which causes modem B to transmit a
II, which indicates to terminal A that the modem is ready to carrier to modem A.
transmit data.
14. Modem B begins a delay that is longer than the echo delay at
6. Terminal A serializes the data to be transmitted (through the modem A before turning on the 'clear to send' line. The longer
serdes) and transmits the data one bit at a time (synchronized by delay (called request-to-send to clear-to-send delay) ensures that
the transmit clock) onto the 'transmitted data' linellto the modem A is ready to receive when terminal B begins transmitti~
modem, data. After the delay, modem B activates the 'clear to send' linelU
7. The modem modulates the carrier signal with the data and to indicate that terminal B can begin transmitting its response.
tra nsmits it to the modem B II. 15. After the echo delay at modem A. modem A senses the carrier
8. Modem B demodulates the data from the carrier signal and sends from modem B (the carrier was activated in step 13 when terminal
it to terminal B on the 'received data' linem, B activated the 'request to send' line) and activates the 'received
line Signal detector' line.to terminal A.
9. Terminal B deserializes the data (through the serdes) using the
receive clock signals (on the 'receiver signal element timing' line) 16, Modem A and terminal A are now ready to receive the response
IDfrom the modem. from terminal B. Remember, the response was not transmitted
until after the request-to-send to clear-to-send delay at modem B
10, After terminal A completes its transmission, it deactivates the (step 14).
'request to send' Iinea,whiCh causes the modem to turn off the
carrier and deactivate the 'clear to send' linell.
Term~na~ _ = ==~ Terminal B
r;:======ll
rr--- .
Communications I
I
II Communications I
Modem B Adapter
II Adapter II ____ -,
Modem A Communications
II i I
U
r-----, II III
L.._Sup~~...l
II ipower.: I Power I
II I Supply I
Data Terminal Read r-'
L _ _ _ _ ..J
Data Set ReadvD
1c :
G.ne~a~J
) a I
II r-c-;';;;';--j I n I
r~ iT.';;;s~~-'
II II i'I :I
II
III
III; L---J,
I Clrc",'s J
" L_J
r
I a I
'I :
rr
9
"I:
II"
IIII
""
____ -, I.,I I I" I
II"
I r Modem I I
J ": iI
II II
III
II'
Transmitted
Da'a
III
I Clock
L___
~_J
I ~ I
I _____ ,
III I" Echo
III
I
I
L ___
Delay
=___ ,
'I---l~
III r Receive
C.;'.~l ~
(") ' , "".,. C "
o III 'i ."
3
"! II iI:; ! II
~
~::I ",
' , ".._J
---- "
"
, II,
'II
,
"._m"n,e :,d~D:; a:. ,: a-;

'" L___ _ " '.
r;" "II,I ,-o.moo",-"",_J "" ,, • _J ""
"i L___
~
0" III
::I
!;Il
' ,I
II L_ __
II
II II II II
'T1
I
VI ~======:J L.::======:J
d x!pU;}ddV
'Tj
I
Establishing a Link on a Nonswitched Multipoint Line
0'1
1. The control station serializes the address for the tributary or 6. After a short delay to allow the control station modem to receive
(') secondary station (AA) and sends its address to the modem on the the carrier, the tributary modem activates the 'clear to send' line
o 'transmitted data' lineD. II·
3 2. Since the 'request to send' line and, therefore, the modem carrier, 7. When station A detects the active 'clear to send' line, it tansmits
~::s is active continuouslyll, the modem immediately modulates the its response. (For this example, assume that station A has no data
....
(")
carrier with the address, and, thus, the address is transmitted to
all modems on the line.
to send; therefore, it transmits an EDTII.)
8. After transmitting the EDT, station A deactivates the 'request to
~
o·
::s
3. All tributary modems, including the modem for station A,
demodulate the address and send it to their terminals on the
send' lineD. This causes the modem to deactivate the carrier and
the 'clear to send' linell.
r;"
'received data' lineD.
9. When the modem at the control station (host) detects the absence
4. Only station A responds to the address; the other stations ignore of the carrier, it deactivates the 'received line signal detector' line
the address and continue monitoring their 'received data' line. To
respond to the poll, station A activates its 'request to send' linea,
EI·
10. Tributary station A is now in receive mode waiting for the next
which causes the modem to begin transmitting a carrier signal.
poll or select transmission from the control station.
5. The control station's modem receives the carrier and activates the
'received line signal detector, linelland the 'receiver signal
element timing' linell(to send clock signals to the control
station). Some modems activate the clock signals as soon as they
are powered on.
Tributary or Secondary Station A
Terminal
rr======llII
II Communications
Host Modem Communications
L;
Modem II td.p,e, II
Data Terminal r-----, r-----, OataTerminal
II
r-' Ready' I Power I I Power I Readyl II r-'
I
lei Data Set Read y l
I On
1..-_-, .J
I I On
L _ ........ __ .J
I
lei
I II
I 0 I Data Set Ready' I 0 I
: n I Request to Send'. r Carrier -1 :n : II
1'1
r II JIGene,.,el
_____ .....J II 1'1
I r I
sj II
, I II
I I
lot II r, ____ AA _____ lReceived Line Signa
I 0 I
III
r ., r
L-"
I I
I
Clear to Sendl
I I
II
D I
let
III
: Transmit
L ____ ~
~
1
Receiver I
L ____ J I
Detector' I I I
"L_~
I II
II
I I '--- Rece;ve, 8;9 nol
II I a I r-M- - ., Element Timingl II
IVI M' I adem
II c_J :: L~~c':_J III II II
Transmitter Signal I I r - - - - - --a Received Data II
~ I Element Timingl
,-----,-
liB
r
I
AAL ____
::.1I-M" d - -,
CI~C:m
-'I,I
I I Demodulator
L _______ --' II
II
II
II
Transmitted Data I 0 : II I
cU iii I
II f'c;;-ri;,. -.., Request to Send II
~
1111
Received Line Signall
Detector r----.,
I
~====~ ~ I:rt,
Gene,.'e II II
Clear to Send
II
II
C":l II !!
Receiver Signal
I L~:;:l'
i__ _ ~ ~ LIT':~m~J :~!
~_,=-_.J
I:
Transmitter Signal
II
II
o Element Timing1 r Modem i i Modem"" Element Timing II
9 Art, ~_C~o':k_J ~':~c~_J r
g II
II
II
II i8
II
II
...
::I
()
II
III ,
II
8 :
re II
d I
II
II
r------
IL...... _Demodulator
_____
--,
...JI
r
LI __
------,
Modulator
_ _ _ _ ....JI II
II
II er
I d
II
II
~ Iq
I e I
•:
I e
o·::I II L_ LrJ
II
II III
II
II
:s
LT
II
_J II
III II 1 Received Data EOT Transmitted Data I II
II II II II
'T1
I
-....l t..=======~
1These lines are active continuously
L.::======:J
d X!pU~ddV
71 Establishing a link on a Switched Point-To-Point line
00
1. Terminal A is in communications mode; therefore, the 'data 8. The autoanswer circuits in modem B activate the 'off hook' line to
(') terminal ready' lineais active. Terminal B is in communication the couplerEl.
o mode waiting for a call from terminal A.
9. The coupler connects modem B to the communications line through
3 2. When the terminal A operator lifts the telephone handset, the the 'data tip' and 'data ring' linesllland activates the 'coupler cut-
§ 'switch hook' line from the coupler is activated D. through' linellto the modem. Modem B then transmits an
.....
::1 answer tone to terminal A.
3. Modem A detects the 'switch hook' line and activates the 'off
(')
hook' linea, which causes the coupler to connect the telephone 10. The terminal A operator hears the tone and sets the exclusion key
~
o·
::1
set to the line and activate the 'coupler cut-through' linellto the
modem.
or talk/data switcr. to the data position (or performs an equivalent
operation) to connect modem A to the communications line
til through the 'data tip' and 'data ring' linesll.
4. Modem A activates the 'data modem ready' linellto the coupler
(the 'data modem ready' line is on continuously in some modems). 11. The coupler at terminal A deactivates the 'switch hook' line II.
This causes modem A to activate the 'data set ready' lineD
5. The terminal A operator sets the exclusion key or talk/data switch
indicating to terminal A that the modem is connected to the
to the talk position to connect the handset to the communications
communications line.
line. The operator then dials the terminal B number.
The sequence of the remaining steps to establish the data link is
6. When the telephone at terminal B rings, the coupler activates the
the same as the sequence required on a nonswitched point-to-
'ring indicate' line to modem Bim. Modem B indicates that the '
point line. When the terminals have completed their transmission,
'ring indicate' line was activated by activating the 'ring indicator'
they both deactivate the 'data terminal ready' line to disconnect
linellto terminal B.
the modems from the line.
7. Terminal B activates the 'data terminal ready' line to modem Bm,
which activates the autoanswer circuits in modem B. (The 'data
terminal ready' line might already be active in some terminals.)
Terminal A Terminal B
r;:======:;-JII
II Communications CBS CBS
r;:======,-,II
Communications
II
Coupler II
II Ada.'., II
D
Modem A
r-----' IIr
Coupler
-, Modem B
r~i ~-An;~;rl II
II
II
Adapter
II
'" :ur-:
II II Switch Hook Switch Hook
J----rr
I Carrier I r-1
II rC' Data Terminal I Generate I iSFii Data Terminal CI II
ISHI _I -~eady
:~I D:::~.' it '0 ,
II _ Off Hook IOH)1I Off Hook II I Data Set Ready
nl _, II
II
III •
rSIt I I 'I
~:~~~sttoSendl rill
Ie I
Ml
10 I Coupler II
IOH)
Coupler II
10 I
la I
n
I I
r--'
10 I
e
I I
Aeceived Line
Si nal Detector _i'i
I' ,
S II
t II
,0 I
i id ,
II: ~
III 0
III
I 0 1,
l~J
1\.,le8r to ;,eno
II
II
I,
18 I
L~J
Iu I
:I Ia I,
Cut-Through
6~~T~Odemll
Cut-Through
ICCTI
Data Modem
Is J
: w:
lei
Iml Aing Indic110rlll
10 I
H II
L~J
II
a II
9 II
9 II Ready (oA) Ready IDA) Ir I Iu I II
r-' r-l
Iii· II " , I,eRtI I R)
I eI
Aing II!! L_J I' I
Ia I
II II
11\ II
Transmit Data
10:
1'1 B III 'II
Indicate (A)
1'1
II
Aeceived Data
II
III
,' I i Data Tip (DT)II 10 II
III
II
II
II
1
L_
Data Tip lOT)
Data
Data Ring (DAI
Ia
Y,
's ,
L_J
IY
a I
IS,
LJ
Data
Data Ring (DR)
, I
_J II 1 II
II
II II II
r--, II
II II IE CI
II II Ic I I III
II II Ih •
10 ml
i II
I II , • I II
L __ .J
II II
r~l II r-M-od;mj iM~~;l II III
ISI
• I II L_c.:o~~J I Clock
L_~_....J
I II III
(") , I II ill
o d i II i"
• I III
3 L_
s I
L_J
II II
II _J II
~::s
II
Transmit Clock Aeceive Clock II
.... II II II
L':======::J
II
(')
~=======.J
~
o·::s Communications
Line
Vl
'Tl
,
1.0
d X!pU~ddV
Notes:
F -10 Communications
APPENDIX G: SWITCH
SETTINGS
The following switch settings are divided between two groups. The
first group contains the switch settings for the 16/64K system
board. The second group contains the 64/256K system board
switch settings.
Determine the system board type and refer to the appropriate

group of switch settings for all applications.
Switch Settings (l6KB-64KB CPU) .................. G-3
Switch Settings (64KB-256KB CPU) ................. G-29
Switch Settings G-l

Notes:
0-2 Switch Settings

Switch Settings (16KB-64KB CPU)
System Board Switch Settings ...................... G-5

System Board Switch Settings .................... G-5
5-1/ 4" Diskette Drives Switch Settings ............ G-6
Display Type Switch Settings .................... G-6
Math Coprocessor Switch Settings ................ G-7
Memory Option Switch Settings .................... G-S

16K Total Memory ........................... G-S
32K Total Memory ........................... G-S
48K Total Memory ........................... G-S
64K Total Memory ........................... G-S
96K Total Memory ........................... G-9
12SK Total Memory ........................... G-lO
160K Total Memory ........................... G-ll
192K Total Memory ........................... G-12
224K Total Memory ........................... G-13
256K Total Memory ........................... G-14
2SSK Total Memory ........................... G-15
320K Total Memory ........................... G-16
352K Total Memory ........................... G-17
3S4K Total Memory ........................... G-lS
416K Total Memory ........................... G-19
44SK Total Memory ........................... G-20
4S0K Total Memory ........................... G-21
512K Total Memory ........................... G-22
544K Total Memory ........................... G-23
576K Total Memory ........................... G-24
60SK Total Memory ........................... G-25
640K Total Memory ........................... G-26
Extender Card Switch Settings ...................... G-27
Switch Settings G-3

Notes:
G-4 Switch Settings

Switch Setting Charts
System Board Switches
WARNING: Before you change any switch settings,

make a note of how the switches are
presently set.
Switch Block 1
~DDOOODDO
Switch Function
1,7,8 Number of 5-1/4 inch diskette drives installed

2 Math Coprocessor
3,4 System board memory switches
5,6 Type( s) of display( s) connected
Switch Block 2
Switch Function
1,2,3,4,5 Amount of memory options installed

6,7,8 Always in the Off position
Switch Settings G-S

Number of 5-1/4 Inch
Diskette Drives Installed
Switch Block 1 Switch Block 2
0- Drives ;~DDDDO~~ ;DDDDOQQQ

1- Drive ;~DDDOO~~ ;DDDDOQQQ
2 - Drives ;~DDDOOQ~ ;DDDDOQQQ
Type(s) of display(s) connected

WARNING: If an IBM Monochrome Display is
connected to your system. Switch Block
1, switches 5 and 6, must always be Off.
Damage to your display can result with
any other switch settings.
IBM Monochrome
Display (or IBM
Monochrome Display
plus another display)
~tDDDDQ~OO 40x25
Color Display (Do not
use if an IBM ;DDDDOQQQ Mode
Monochrome ' , 3 , 0 , , ,
80x25
Display is connected) mDDD~~DD ;DDDDOQQQ Mode
Note: The 40x25 mode means there will be 40 characters

across the screen and 25 lines down the screen. The 80x25 mode
means there will be 80 characters across the screen and 25 lines
down the screen. The 80x25 mode, when used with home
televisions and various displays, can cause loss of character
quality.
G-6 Switch Settings

Math Coprocessor
With Math Coprocessor ~D ~ 000000 ~DDODOQQQ

Without Math Coprocessor ~D Q000000 iDODDOQQQ
Switch Settings 0-7

900 Memory Switch Settings
(16KB-64""KB CPU) System Board
til
.........
~ 16K Total Memory
~
=-
til System Board Switches Switch Block 1 I~DD~~DDDD I Switch Block 2 I~~~~~~QQQ I
n>
;:::::
s·
(JQ
v.> 32K Total Memory

Switch Block 1 I~DDQ~DDDD I Switch Block 2
I~~~~~~QQQ I
48K Total Memory
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 B
System Board Switches Switch Block 1

mD~~DDDD Switch Block 2
;~~~~~~~~
-- --- - ---
64K Total Memory
1 2 3 4 5 6 7 6 1 2 3 4 5 6 7 B
mD~~DDDD ;~~~~~~~~
System Board Switches Switch Block 1 Switch Block 2
96K Total Memory
32K + (64K on System Board)

Switch Block 1 I~ODQQDDOD I Switch Block 2 I~Q~~~~QQ_~
64/256K Option 64K Option 32K Option

Card Switches Card Switches Card Switches
I 1 - 32K option
I~~~~Q~~~~ I
r.tl
~,
.....
(')
::r
r.tl
~
::::
5'
(JQ
rI>
91.0
D X!pU~ddV
o
-
o
I
rJ}
128K Total Memory
~
~.
System Board Switches Switch Block 1 I~DDQQDDDD I Switch Block 2 ~~Q~~~QQQ
t:r'
rJ}
(1) 64/256K Option 64K Option 32K Option
~ Card Switches Card Switches Card Switches
5·
I~~~~Q~QQQ I
OQ
[Il
1 - 64/256K option with 64K installed
1 - 64K option
1~~~~Q~~~~ I
2 - 32K options
I~~~~Q~~~~ I
I~~~~QQ~~~ I
- --
l60K Total Memory
System Board Switches Switch Block 1 I~DD~QDDDD I Switch Block 2 I~QQ~~~QQQ I

I;~~~Q~QQQ I I~~~Q~~~~~ 1
1 - 32K option
l;~~~Q~~~~ I I~~~Q~~~~~ I
1 - 64K option
1 - 32K option
I;~~~Q~~~~ I
I;~~~QQ~~~ I
Vl 3 - 32K options
-
:.E
.....
( ')
t:r'
Vl I~~~Q~~~~~ 1
~
::::
iJ'
I:Il
o
-I
D x!pu~ddV
o
-
N
I
192K Total Memory
til
....
~
....
()
::r
I _S~itch Block 1 ~DDQQOODO 1 Switch Block 2 ~~~Q~~~~Ql
til 64/256K Option 64K Option 32K Option
(I) Card Switches Card Switches Card Switches
~
5'
I~~~~Q~QQQ I If~~Q~~~~~ I
1 . 64/256K option with 64K option installed
(JQ
~ 1 . 64K option
2 . 64K options
li~~~Q~~~~ I
I~~~Q~~~~~ I
I;~~Q~~~~~ j
I~~~~Q~QQQ I
1 . 64/256K option with 64K installed
2 . 32K options
~~~Q~Q~~~J
I;~~Q~~~~~ I
I;~~~Q~~~~ I
1 . 64K option
2 . 32K options
If~~Q~Q~~~ I
1 . 64/256K option with 128K installed
I;~~~QQ~QQ I
224K Total Memory
1 2 34 S 6 7 8

mOQQOOOO Switch Block 2
;~~~~~~~~
1 - 64K option
1 - 32K option l;~~~Q~QQOJ l;~~Q~~~~~J I;~~QQ~~~~
l;~~~Q~~~~J
I;~~QQ~~~~J
2 - 64K options
1 - 32K option
~~~Q~~~~~ I
tZl
I;~~~QQ~QQJ I;~~QQ~~~~J
:i.
..... 1 - 32K option
()
=-
tZl
"'::::
s·
(JQ
t;IJ
o
-I
tH
D X!pU;)ddy
o
-
256K Total Memory
I 192K + (64K on System Board)
.j:;o.
System Board Switches I Switch Block 1 I~DOQQDDDD I I Switch Block 2 I;~QQ~~QQQ I

-
CIl
~
.....
n 64/256K Option 64K Option 32K Option
::r Card Switches Card Switches Card Switches
CIl
~
::+
5'
(JQ
I;~~~QQQ~Q I
[Il
I;~~~QQ~QQ I I;~~QQ~~~~ I
1 - 64K option
I;~~Q~~~~~ I
,
I;~~~Q~QQQ I
2 - 64K options
I;~~QQ~~~~ I
I
I
I;~~~Q~~~~ I i
3 - 64K options
I;~~Q~~~~~ I
I;~~QQ~~~~ I
I;~~QQ~~~~ I
I;~~~QQ~QQ j
1 - 64/256K option: with 128K installed
2 - 32K options
I;~~QQQ~~~ I
288K Total Memory
I;~QQ~~QQQ
1 2 3 4 5 6 7

---- ----- ----- - - - -
64/256K Option 32K Option I

64K Option
I;~~~QQQ~Q I I;~Q~~~~~~ I
1 - 32K option

1 - 64K option
1 - 32K option I;~~~QQ~QQ I I;~~QQ~~~~ I I;~Q~~~~~~ I
~- -_.. -- --- - _ ... - L-. _ _ _ .. ____ __ ___ _
- -- --
\I'.l
~
~.
t:r'
\I'.l
('!)
::::
s·
(JCl
(Il
-
o I
VI
D X!pU;}ddV
o
-I
0'1
320K Total Memory
Vl
~
~.
System Board Switches Switch Block 1 I~DDQQDDDD I Switch Block 2 I;~~~Q~QQQJ I
::r'
Vl 64/256K Option 64K Option 32K Option
~ I
:::: Card Switches Card Switches Card Switches
I
S·
(JQ
l~~~~Q~~~~ I
(Il
I~~~~QQ~QQ I
2 - 64K options
I;~Q~~~~~~ I
I~~~~QQQ~Q I I;~Q~~~~~~ I
1 - 64K option
I;~Q~~~~~~ I
I;~~~QQQ~Q I
2 - 32K options
I;~Q~~Q~~~ I
I;~~~QQQQ~ I - - - -----
I
_ _ _ _ ~I
352K Total Memory

Switch Block 1 GDD~QOODO I Switch Block 2
I;~~~Q~QQQ I
Card Switches Card Switches Card Switches I

1 - 64K option
1 - 32K option
l1~~~QQQ~QJ 11~Q~~~~~~ I~~Q~Q~~~~ I
l;~~~QQQQ~ J I;~Q~Q~~~~ I
1 - 32K option
CZl
~ .
.....
~
=-
CZl
('1)
::::
S·
(JQ
~
-9
- .l
D X!pU;}ddV
o. 384K Total Memory
-
00 -- _ .. ----_ .. _ - - ---------
1 :2 3 4 5 6 7 8 1:2345678
Vl
....
~
~~~~~~~~~
- ... - --- ----
f)
=-
Vl
64/256K Option
Card Switches
64K Option
Card Switches
32K Option
Card Switches
,
Q
::::
....
I~~Q~~~~~~ I
::s
0Cl
I~~~~QQQ~Q I
rIl
2 - 64K options
I~~Q~Q~~~~ I
1 - 64/256K option with 256K installed I;~~~QQQQ~ I

I;~~~Q~~O~ I
I~~~~QQQQ~ I I~~Q~Q~~~~ I
1 - 64K option
I~~Q~Q~~~~ I
2 - 32K options I~~~~QQQQ~ I
1;~Q~QQ~~~ I
416K Total Memory

I~ODQQOOOO I Switch Block 2
l~QQ~Q~QQQ I
1 - 64/256K option with 256K installed I;~~~QQQQ~ I

1 - 32K option I;~QQ~~~~~ I
I~~Q~Q~QQQ I
C/:l
:;;.....
1 - 64K option
1 - 32K option I;~~~QQQQ~ I;~Q~Q~~~~ I I;~QO~~~~~ I
.....
~
=-
C/:l
~
.....
.....
s·
(JQ
til
-
<;1
\0
D X!pU~ddV
oI
448K Total Memory
N
o
Vl 1 2 3 4 5 6 7 8
~
~.
~DDQQDDDO Switch Block 2
~~~~~~~~~
=-
~
....
~ Card Switches Card Switches Card Switches
=
rl~~~QQQQ~ I
(JQ
~
11~QQ~~~~~l
r~~Q~Q~QQQ l
1 - 64K option
11~Q~Q~~~~l
1 - 641256K option with 256K installed
2 - 64K options rl~~~QQQQ~l
11~QQ~~~~~l
1 - 64/256K option with 256K installed 11~~~QQQQ~ I

11Q~~QQ~QQ 1
480K Total Memory

I~DD~QOOOO I Switch Block 2
I~Q~QQ~QQQ I
I;~~~QQQQ~ I
I;~Q~Q~~~~ I
I;~Q~QQ~QQ I
1 - 32K option
til
§.
.....
(')
t:r'
til
('I)
::::
s·
(JQ
!;Il
9N
- D X!pUJddV
oI
512K Total Memory
N
N
r.Il 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
~
~.
;DD~~DDDD Switch Block 2
m~~~~~~~
::r
r.Il
~ 64/256K Option 64K Option 64K Option
::+ Card Switches Card Switches Card Switches
5·
(JQ
r~~~~QQQQ~ I
v.I
I~~QQQ~~~~l
I~~Q~QQOWJ
1 - 64K option
1 - 64/256K option with 256K installed I~~~~QQOQ~ I

I~~Q~QQQ~O I
- - - - - _ .. _ - - - _ .. _ - - -
544K Total Memory

Switch Block 1 I~DDQQDDDDJ Switch Block 2 I;QQQQ~QQQ I

I~~~~QQQQ~ I
[;Q~~~~~~~ I
I;~Q~QQQ~Q I
1 - 32K option
- - - - - - _.. -
-
til
~
....
( ')
t:T'
til
('t>
::::
s·
OQ
tI>
o
N
~
D X!pU~ddV
576K Total Memory
9N 512K + (64K on System Board)
"'"
~O~~QQQQ I
Vl
~
g.
System Board Switches Switch Block 1 IrDOQQOODO I Switch Block 2
::r'
~
~
5·
I~~~~QQQQ~ I
(JQ
Vl
I~Q~~~~~~~ I
I;~Q~QQQ~Q I
1 - 64K option
2 - 64/256K option with 256K installed I~~~~QQQQ~ I

I;~~~QQQQ~ I
- --
60aK Total Memory

I;ODQ~DDDD I Switch Block 2 I;~~~~QQ~Q I

2 - 64/256K option with 256K installed I;~~~~QQQ~ I

1 - 32K option
I;Q~~Q~~~~ I
I;~Q~~QQQ~ I
- -------
CIl
~.
....
n
:r
CIl
~
~
5'
(JQ
~
9N
Ul
D X!pU;}ddV
o I
640K Total Memory
N
0'\
~DDQQDDDD I
-
CI:l
~. System Board Switches Switch Block 1 Switch Block 2 ~~Q~~QQQQ
( ')
::r
CI:l 64/256K Option 64K Option 32K Option
~
:::: Card Switches Card Switches Card Switches
5'
0Cl
I~~~~QQQQ~ I
(/l
1 - 64K option
I;Q~~Q~~~~ I
I~~Q~QQQQ~ I
2 - 64/256K option with 256K installed I~~~~QQQQ~J

I;~Q~QQQQ~ I
I;Q~~Q~QQQ I
Extender Card Switch Settings
Extender Card
System Memory Switch Block Memory Segment
16K to 64K 11 ~~~~ 1
96K to 128K 11 ~~~~ 2
160K to 192K 11 ~ ~ ~ ~I 3
224K to 256K 11 ~~~D 4
288K to 320K \1 D ~ ~ ~I 5
352K to 384K
11 D ~ ~ DI 6
416K to 448K II D ~ ~~ 7
480K to 512K 11 ~~~D 8
544K to 576K
11 ~~~~ 9
608K to 640K
~I~~~DI A
Switch Settings G-27

Notes:
G-28 Switch Settings

Switch Settings (64KB-256KB CPU)
System Board Switch Settings ...................... G-31

System Board Switch Settings .................... G-31
5-1/4" Diskette Drives Switch Settings ............ G-32
Display Type Switch Settings .................... G-32
Math Coprocessor Switch Settings ................ G-32
Memory Option Switch Settings .................... G-34

64K Total Memory ........................... G-34
128K Total Memory ........................... G-34
192K Total Memory ........................... G-34
256K Total Memory ........................... G-34
288K Total Memory ........................... G-35
320K Total Memory ........................... G-36
352K Total Memory ........................... G-37
384K Total Memory ........................... G-38
416K Total Memory ........................... G-39
448K Total Memory ........................... G-40
480K Total Memory ........................... G-41
512K Total Memory ........................... G-42
544K Total Memory ........................... G-43
576K Total Memory ........................... G-44
608K Total Memory ........................... G-45
640K Total Memory ........................... G-46
Extender Card Switch Settings ...................... G-47

Notes:
G- 30 Switch Settings
Switch Setting Charts
WARNING: Before you change any switch settings,

make a note of how the switches are
presently set.
Switch Block 1
~DDDDDDDD
Switch Function
1,7,8 Number of 5-1/4 inch diskette drives installed

2 Math Coprocessor
3,4 System board memory switches
5,6 Type( s) of display( s) connected
Switch Block 2
Switch Function
1,2,3,4,5 Amount of memory options installed

6,7,8 Always in the Off position

Number of 5-1/4 Inch
Diskette Drives Installed
0- Drives ~~DDDDD~~ ~DDDDDQQQ

1 - Drive ~~DDDDD~~ ~DDDDDQQQ
2 - Drives ~QDDDDDQ~ lDDDDDQQQ
Type(s) of display(s) connected

WARNING: If an IBM Monochrome Display is
connected to your system. Switch Block
1, switches 5 and 6, must always be Off.
Damage to your display can result with
any other switch settings.

IBM Monochrome
Display (or IBM
Monochrome Display
plus another display)

Color Display (Do not 1 2 3 4 5 6 7 8 1 2 3 4 " 6 7 8
40x25
use if an IBM mDDD~~DD mDDDD~~~ Mode
Monochrome 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
80x25
Display is connected) mDDD~~DD mDDDD~~~ Mode
Note: The 40x25 mode means there will be 40 characters

across the screen and 25 lines down the screen. The 80x25 mode
means there will be 80 characters across the screen and 25 lines
down the screen. The 80x25 mode, when used with home
televisions and various displays, can cause loss of character
quality.

Math Coprocessor
With Math Coprocessor ~D ~ 000000 ~DDDDDQQQ

Without Math Coprocessor ~DQDDDDDD ~DDDDDQQQ

o I Memory Switch Settings
~
.j::o. (64KB-256KB CPU) System Board
I.f.l
~
.... 64K Total Memory
.....
n
=-
I.f.l System Board Switches Switch Block 1 I~DOQQDDDD I Switch Block 2 1~~~~~~Q~Q I
til
;::::
s·
(JQ
U':l 128K Total Memory
1 2 :3 4 5 6 7 8 1 2 3 4 5 6 7 8

~~~~~~~~~
- -----
192K Total Memory
System Board Switches Switch Block 1 1;00 QQ0000I Switch Block 2 I;~~Q~~QQQ I
-- ---- -- --
256K Total Memory
System Board Switches Switch Block 1 I;DoQQOOoOJ Switch Block 2 I;~QQ~~QQQ I

288K Total Memory
System Board Switches Switch Block 1 I~DDQQDDDD I Switch Block 2 I~QQQ~~QQQ I

Card Switches Card Switches Card Switches I
1 - 32K option
l~~Q~~~~~~J I
I.f.l
~
g.
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~
::::
5·
(JQ
tI.>
o I
(H
VI
D X!puaddV
320K Total Memory
<;) 64K + (256K on System Board)
w
0'1
til
~
System Board Switches Switch Block 1 l~ODQQDDDDJ Switch Block 2 ~~~~Q~QQQ I
~.
:::r' 64/256K Option 64K Option 32K Option
til Card Switches Card Switches Card Switches
~
::::
s·
(JQ
~
I~~Q~~~QQQ I
1 - 64K option
I;~Q~~~~~~ I
2 - 32K options
~~Q~~~~~~J
I~~Q~~Q~~~ I
352K Total Memory
System Board Switches Switch Block 1 ImoQQoDDDJ Switch Block 2 I;Q~~Q~QQQ I

64f256K Option 64K Option 32K Option
II
I;~Q~~~QQQ I I;~Q~Q~~~~ I
,
1 - 64f256K option with 64K installed
1 - 32K option
I;~Q~~~~~~J I;~Q~Q~~~~ I
1 - 64K option
1 - 32K option
I;~Q~~~~~~ I
I;~Q~~Q~~~ I
-
til 3 - 32K options
~.
( ')
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til
~ I;~Q~Q~~~~ I
::::
s·
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rJl
oI
I.H
-...J
D X!pU;JddV
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384K Total Memory
<.H
I l
00
til
~
Switch Block 1 ~ODQ~OODO_ Switch Block 2 I~~~~]~Q~
....
.....
(')
::r 64/256K Option 64K Option 32K Option
~
:=:
s· I;~Q~~~QQQ I I~~Q~Q~~~~ I
1 - 64/256K option with 64K option installed
(JQ 1 - 64K option
(I>
2 - 64K options
I;~Q~~~~~~ I
I~~Q~Q~~~~ I
I~~Q~Q~~~~I
1;~Q~~~QQQ I
2 - 32K options
I;~Q~QQ~~~ I
I~~Q~Q~~~~ I
I;~Q~~~~~~ I
1 - 64K option
2 - 32K options
I;~Q~QQ~~~ I
I;~Q~~Q~QQ I
416K Total Memory
160K + (256K on System Boardl
System Board Switches Switch Block 1 I~DDQQDDDD I Switch Block 2

I~QQ~Q~QQQ I
1 - 64K option
1 - 32K option
l;~Q~~~QQQ I I;~Q~Q~~~~ I I;~QQ~~~~~ I
I~~Q~~~~~~ I
2 - 64K options
1 - 32K option l;~QQ~~~~~ I
I~~Q~Q~~~~ I
I~~Q~~Q~QQ I ~~QQ~~~~~J
~ 1 - 32K option
~
....
.....
(")
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~
.....
(D
.....
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rIl
oI
W
\0
D X!pU~ddV
o 448K Total Memory
~
o
CJ)
System Board Switches I Switch Block 1 I~ODQQDDDD I I Switch Block 2 I~~~QQ~QQQ I
~.
....
n 64/256K Option 64K Option 32K Option
t:r Card Switches Card Switches Card Switches
CJ)
I~~Q~~QQ~QI
~
:::: 1 - 64/256K option with 192K installed
5'
(JQ
I~~Q~~Q~QQ I I;~QQ~~~~~ I
~ 1 - 64/256K option with 128K installed
1 - 64K option
I;~Q~Q~~~~ I
I;~Q~~~QQQ I
2 - 64K options
I;~QQ~~~~~ I
l;~Q~~~~~~ I
3 - 64K options
I;~Q~Q~~~~ I
I;~QQ~~~~~ I
I;~QQ~~~~~ I
I~~Q~~Q~QQ I
1 - 64/256K option with 128 installed
2 - 32K options
I;~QQ~Q~~~ I
~--
-
480K Total Memory
System Board Switches Switch Block 1 I~DDQQDDDD I Switch Block 2

I~Q~QQ~QQQ I
-- - - - _ .. _- -

I~~Q~~QQ~Q I I~~QQQ~~~~ I
1 - 32K option

1 - 64K option
1 - 32K option
I~~Q~~Q~QQ I I~~QQ~~~~~ I I~~QQQ~~~~ I
CIl
:i,
.....
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CIl
~
.....
.....
5'
(JQ
Vl
o
-
~
D X!pU;)ddy
oI
.j::o.
512K Total Memory
256K + (256K on System Boardl
N
Vl
~
System Board Switches Switch Block 1 l~DDQQDDDD I Switch Block 2 11~QQQ~QQQ I
~.
::r'
Vl Card Switches Card Switches Card Switches
~
::::
S·
(JQ
rn l1~QQ~~~~~J
11~Q~~Q~QQ I
2 - 64K options
11~QQQ~~~~ I
I~~Q~~QQ~Q I ~~QQQ~~~~ I
1 - 64K option
I~~QQQ~~~~ I
I~~Q~~QQ~Q I
2 - 32K options
11~QQQQ~~~
l~~Q~~QQQ~ I
544K Total Memory
288K + (256K on System Board I

Switch Block 1 I~DDQQDDDD I Switch Block 2 I~~QQQ~QQQ I


1 - 64K option
1 - 32K option
I~~Q~~QQ~Q I I;~QQQ~~~~ I I;Q~~~~~~~ I
~~Q~~QQQ~ I I~Q~~~~~~~ I
1 - 32K option
CI.l
~
.....
(')
.
::r
CI.l
.....
~
.....
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(fQ
rIl
o,i.
w
D X!pU~ddV
576K Total Memory
Q 320K + (256K on System Board)
J;..
~
til
~
~.
I Switch Block 1
1 2
;oD~~DDDD
J 4 5 6 7 8
I Switch Block 2
~~~~~QQ~Q -l
::r' 64/256K Option 64K Option 32K Option
~
::+
s·
(JQ 1~~QQQ~~~~ I
'" 1 - 64/256K option with 192K installed
2 - 64K options 1~~Q~~QQ~Q I
I~Q~~~~~~~ I
1 - 64/256K option with 256K installed l~~Q~~OQQ~ I

I~Q~~~~QQQ I
1;~Q~~OQQ~ I I~Q~~~~~~~ J
1 - 64K option
I~Q~~~~~~~
2 - 32K options I~~Q~~QQQ~ I
I~Q~~~O~~~ J
- - --_._- -- - -
608K Total Memory

I~ODQQOODO I Switch Block 2
I~~~~~QQQQ I
1 - 64/256K option with 256K installed I~~Q~~QQQ~ I

1 - 32K option l;Q~~Q~~~~ I
I;Q~~~~QQQ I
Vl
1 - 64K option
1 - 32K option I~~Q~~QQQ~ I I;Q~~~~~~~ I I;Q~~Q~~~~
~.
~
- - - - - - _.. - - - - - - - - - - - -
('l
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~
~
S·
(JQ
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o
,i:..
til
D X!pU;}ddV
o 640K Total Memory
~
0\ - - - - - _ .. _ - - - _.. ---- ---- ---
CI.l
~.
liDOQQODDD I Switch Block 2
l;~Q~~QQQQ I
.....
n
:T 64/256K Option 64K Option 32K Option
CI.l Card Switches Card Switches Card Switches
(1) I
::+ I
:r
(JQ
1 - 64/256K option with 256K installed I;~Q~~QQQ~ I
I;Q~~Q~~~~ I
t:Il
1 - 64/256K option with 64K installed !
I;Q~~~~QQQ I
1 - 64K option
I;Q~~~~~~~J
I;~Q~~QQQ~ I
2 - 64K options
I;Q~~Q~~~~ I
1 - 64/256K option with 256K installed I;~Q~~QQQ~ I

I;Q~~~Q~QQ I
Extender Card Switch Settings
System Memory Extender Card

Memory Segment
Switch Block
16K to 64K
r~~~~1 1
96K to 128K
r~~~~1 2
160K to 192K
r~~~~1 3
224K to 256K
r~~~~1 4
288K to 320K 1~~~~1 5
352K to 384K 1~~~~1 6
416K to 448K 1~~~~1 7
480K to 512K
r~~~~1 8
544K to 576K
r~~~~1 9
608K to 640K r~D~~1 A

Notes:

GLOSSARY
J.Ls: Microsecond.
adapter: An auxiliary system or unit used to extend the operation

of another system.
address bus: One or more conductors used to carry the binary-

coded address from the microprocessor throughout the rest of the
system.
all points addressable (APA): A mode in which all points on a

displayable image can be controlled by the user.
alpanumeric (A/N): Pertaining to a character set that contains

letters, digits, and usually other characters, such as punctuation
marks. Synonymous with alphanumeric.
American Standard Code for Information Interchange

(ASCII): The standard code, using a coded character set
consisting of 7-bit coded characters (8 bits including parity
check), used for information interchange among data processing
systems, data communication systems and associated equipment.
The ASCII set consists of control characters and graphic
characters.
A/N: Alphanumeric.
analog: (1) pertaining to data in the form of continuously variable

physical quantities. (2) Contrast with digital.
AND: A logic operator having the property that if P is a

statement, Q is a statement, R is a statement, ... ,then the AND of
P, Q, R, .. .is true if all statements are true, false if any statement is
false.
APA: All points addressable.
Glossary H-l
ASCII: American Standard Code for Information Interchange.
assembler: A computer program used to assemble. Synonymous

with assembly program.
asynchronous communications: A communication mode in

which each single byte of data is synchronized, usually by the
addition of start/stop bits.
BASIC: Beginner's all-purpose symbolic instruction code.
basic input/output system (BIOS): Provides the device level

control of the major I/O devices in a computer system, which
provides an operational interface to the system and relieves the
programmer from concern over hardware device characteristics.
baud: (1) A unit of signaling speed equal to the number of

discrete conditions or signal events per second. For example, one
baud equals one-half dot cycle per second in Morse code, one bit
per second in a train of binary signals, and one 3-bit value per
second in a train of signals each of which can assume one of eight
different states. (2) In asynchronous transmission, the unit of
modulation rate corresponding to one unit of interval per second;
that is, if the duration of the unit interval is 20 milliseconds, the
modulation rate is 50 baud.
BCC: Block-check character.
beginner's all-purpose symbolic instruction code (BASIC): A

programming language with a small repertoire of commands and a
simple syntax, primarily designed for numerical application.
binary: (1) Pertaining to a selection, choice, or condition that has

two possible values or states. (2) Pertaining to a fixed radix
numeration system having a radix of two.
binary digit: (1) In binary notation, either of the characters 0 or

1. (2) Synonymous with bit.
binary notation: Any notation that uses two different characters,

usually the binary digits 0 and 1.
H-2 Glossary
binary synchronous communications (BSC): A standardized
procedure, using a set of control characters and control character
sequences for synchronous transmission of binary.:.coded data
between stations.
BIOS: Basic input/output system.
bit: In binary notation, either of the characters 0 or 1.
bits per second (bps): A unit of measurement representing the

number of discrete binary digits which can be transmitted by a
device in one second.
block-check character (BCC): In cyclic redundancy checking, a

character that is transmitted by the sender after each message
block and is compared with a block-check character computed by
the receiver to determine if the transmission was successful.
boolean operation: (1) Any operation in which each of the

operands and the result take one of two values~ (2) An operation
that follows the rules of boolean algebra.
bootstrap: A technique or device designed to bring itself into a

desired state by means of its own action; that is, a machine routine
whose first few instructions are sufficient to bring the rest of itself
into the computer from an input device.
bps: Bits per second.
BSC: Binary synchronous communications.
buffer: (1) An area of storage that is temporarily reserved for use

in performing an input/output operation, into which data is read or
from which data is written. Synonymous with I/O area. (2) A
portion of storage for temporarily holding input or output data.
bus: One or more conductors used for transmitting signals or

power.
byte: (1) A binary character operated upon as a unit and usually

shorter than a computer word. (2) The representation of a
character.
Glossary H-3
CAS: Column address strobe.
cathode ray tube (CRT): A vacuum tube display in which a

beam of electrons can be controlled to form alphanumeric
characters or symbols on a luminescent screen, for example by
use of a dot matrix.
cathode ray tube display (CRT display): (1) A device that

presents data in visual form by means of controlled electron
beams. (2) The data display produced by the device as in (1).
CCITT: Comite Consultatif International Telegrafique et

Telephonique.
central processing unit (CPU): A functional unit that consists

of one or more processors and all or part of internal storage.
channel: A path along which signals can be sent; for example,

data channel or I/O channel.
characters per second (cps): A standard unit of measurement

for printer output.
code: (1) A set of unambiguous rules specifying the manner in

which data may be represented in a discrete form. Synonymous
with coding scheme. (2) A set of items, such as abbreviations,
representing the members of another set. (3) Loosely, one or more
computer programs, or part of a computer program. (4) To
represent data or a computer program in a symbolic form that can
be accepted by a data processor.
column address strobe (CAS): A signal that latches the column

addresses in a memory chip.
Comite Consultatif International Telegrafique et Telephonique

(CCITT): Consultative Committee on International Telegraphy
and Telephony.
computer: A functional unit that can perform substantial

computation, including numerous arithmetic operations, or logic
operations; without intervention by a human operator during the
run.
H-4 Glossary
configuration: (1) The arrangement of a computer system or
network as defined by the nature, number, and the chief
characteristics of its functional units. More specifically, the term
configuration may refer to a hardware configuration or a software
configuration. (2) The devices and programs that make up a
system, subsystem, or network.
conjunction: (1) The boolean operation whose result has the

boolean value 1 if, and only if, each operand has the boolean
value 1. (2) Synonymous with AND operation.
contiguous: (1) Touching or joining at the edge or boundary.

(2) Adjacent.
CPS: Characters per second.
CPU: Central processing unit.
CRC: Cyclic redundancy check.
CRT: Cathode ray tube.
CRT display: Cathode ray tube display.
CTS: Clear to send. Associated with modem control.
cyclic redundancy check (CRC): (1) A redundancy check in

which the check key is generated by a cyclic algorithm. (2) A
system of error checking performed at both the sending and
receiving station after a block-check character has been
accumulated.
cylinder: (1) The set of all tracks with the same nominal distance
from the axis about which the disk rotates. (2) The tracks of a
disk storage device that can be accessed without repositioning the
access mechanism.
daisy-chained cable: A type of cable that has two or more

connectors attached in series.
data: (1) A representation offacts, concepts, or instructions in a

formalized manner suitable for communication, interpretation, or
processing by humans or automatic means. (2) Any
representations, such as characters or analog quantities, to which
meaning is, or might be assigned.
Glossary H-5
decoupling capacitor: A capacitor that provides a low-
impedance path to ground to prevent common coupling between
states of a circuit.
Deutsche Industrie Norm (DIN): (1) German Industrial

Norm. (2) The committee that sets German dimension standards.
digit: (1) A graphic character that represents an integer, for

example, one of the characters 0 to 9. (2) A symbol that
represents one of the non-negative integers smaller than the radix.
For example, in decimal notation, a digit is one of the characters
from 0 to 9.
digital: (1) Pertaining to data in the form of digits. (2) Contrast

with analog.
DIN: Deutsche Industrie Norm.
DIN connector: One of the connectors specified by the DIN

standardization committee.
DIP: Dual in-line package.
direct memory access (DMA): A method oftransferring data

between main storage and I/O devices that does not require
processor intervention.
disk: Loosely, a magnetic disk unit.
diskette: A thin, flexible magnetic disk and a semi-rigid

protective jacket, in which the disk is permanently enclosed.
Synonymous with flexible disk.
D MA: Direct memory access.
DSR: Data set ready. Associated with modem control.
DTR: Data terminal ready. Associated with modem control.
dual in-line package (DIP): A widely used container for an

integrated circuit. DIPs are pins usually in two parallel rows.
These pins are spaced 1/ 10 inch apart and come in different
configurations ranging from 14-pin to 40-pin configurations.
H-6 Glossary
EBCDIC: Extended binary-coded decimal interchange code.
ECC: Error checking and correction.
edge connector: A terminal block with a number of contacts

attached to the edge of a printed circuit board to facilitate plugging
into a foundation circuit.
EIA: Electronic Industries Association.
EIA/CCITI: Electronics Industries Association/Consultative

Committee on International Telegraphy and Telephony.
end-of-text-character (ETX): A transmission control character

used to terminate text.
end-of-transmission character (EOT): A transmission control

character used to indicate the conclusion of a transmission,
which may have included one or more texts and any associated
message headings.
EOT: End-of-transmission character.
EPROM: Erasable programmable read-only memory.
erasable programmable read-only memory (EPROM): A

storage device whose contents can be changed by electrical
means. EPROM information is not destroyed when power is
removed.
error checking and correction (ECC): The detection and

correction of all single-bit, double-bit, and some multiple-bit
errors.
ETX: End-of-text character.
extended binary-coded decimal interchange code

(EBCDIC): A set of 256 characters, each represented by eight
bits.
flexible disk: Synonym for diskette.
firmware: Memory chips with integrated programs already

incorporated on the chip.
Glossary H-7
gate: (1) A device or circuit that has no output until it is triggered
into operation by one or more enabling signals, or until an input
signal exceeds a predetermined threshold amplitude. (2) A signal
that triggers the passage of other signals through a circuit.
graphic: A symbol produced by a process such as handwriting,

drawing, or printing.
hertz (Hz): A unit offrequency equal to one cycle per second.
hex: Abbreviation for hexadecimal.
hexadecimal: Pertaining to a selection, choice, or condition that

has 16 possible values or states. These values or states usually
contain 10 digits and 6 letters, A through F. Hexadecimal digits
are equivalent to a power of 16.
high-order position: The leftmost position in a string of

characters.
Hz: Hertz.
interface: A device that alters or converts actual electrical signals

between distinct devices, programs, or systems.
k: An abbreviation for the prefix kilo; that is, 1,000 in decimal

notation.
K: When referring to storage capacity, 2 to the tenth power;

1,024 in decimal notation.
KB: Kilobyte; 1,024 bytes.
kHz: A unit of frequency equal to 1,000 hertz.
kilo (k): One thousand.
latch: (1) A feedback loop in symmetrical digital circuits used to

maintain a state. (2) A simple logic-circuit storage element
comprising two gates as a unit.
LED: Light-emitting diode.
H-8 Glossary
light-emitting diode (LED): A semi-conductor chip that gives
off visible or infrared light when activated.
low-order position: The rightmost position in a string of

characters.
m: (1) Milli; one thousand or thousandth part. (2) Meter.
M: Mega; 1,000,000 in decimal notation. When referring to

storage capacity, 2 to the twentieth power; 1,048,576 in decimal
notation.
rnA: Milliampere.
machine language: (1) A language that is used directly by a

machine. (2) Another term for computer instruction code.
main storage: A storage device in which the access time is

effectively independent of the location of the data.
MB: Megabyte, 1,048,576 bytes.
mega (M): 10 to the sixth power, 1,000,000 in decimal notation.

When referring to storage capacity, 2 to the twentieth power,
1,048,576 in decimal notation.
megabyte (MB): 1,048,576 bytes.
megahertz (MHz): A unit of measure offrequency. 1 megahertz

equals 1,000,000 hertz.
MFM: Modified frequency modulation.
MHz: Megahertz.
microprocessor: An integrated circuit that accepts coded

instructions for execution; the instructions may be entered,
integrated, or stored internally.
microsecond (p,s): One-millionth of a second.
milli (m): One thousand or one thousandth.
milliampere (rnA): One thousandth of an ampere.
Glossary H-9
millisecond (ms): One thousandth of a second.
mnemonic: A symbol chosen to assist the human memory; for

example, an abbreviation such a "mpy" for "multiply."
mode: (1) A method of operation; for example, the binary mode,

the interpretive mode, the alphanumeric mode. (2) The most
frequency value in the statistical sense.
modem: (Modulator-Demodulator) A device that converts serial

(bit by bit) digital signals from a business machine (or data
terminal equipment) to analog signals which are suitable for
transmission in a telephone network. The inverse function is also
performed by the modem on reception of analog signals.
modified frequency modulation (MFM): The process of

varying the amplitude and frequency of the "write" signal. MFM
pertains to the number of bytes of storage that can be stored on
the recording media. The number of bytes is twice the number
contained in the same unit area of recording media at single
density.
modulo check: A calculation performed on values entered into a

system. This calculation is designed to detect errors.
monitor: (1) A device that observes and verifies the operation of

a data processing system and indicates any specific departure
from the norm. (2) A television type display, such as the IBM
Monochrome Display. (3) Software or hardware that observes,
supervises, controls, or verifies the operations of a system.
ms: Millisecond; one thousandth of a second.
multiplexer: A device capable of interleaving the events of two or

more activities, or capable of distributing the events of an
interleaved sequence to the respective activities.
NAND: A logic operator having the property that if P is a

statement, Q is a statement, R is a statement, ... ,then the NAND
of P,Q,R, .. .is true if at least one statement is false, false if all
statements are true.
nanosecond (ns): One-thousandth-millionth of a second.
H-I0 Glossary
nonconjunction: The dyadic boolean operation the result of
which has the boolean value 0 if, and only if, each operand has
the boolean value 1.
non-return-to-zero inverted (NRZI): A transmission encoding

method in which the data terminal equipment changes the signal
to the opposite state to send a binary 0 and leaves it in the same
state to send a binary 1.
NOR: A logic operator having the property that if P is a

statement, Q is a statement, R is a statement, ... ,then the NOR of
P,Q,R, .. .is true if all statements are false, false if at least one
statement is true.
NOT: A logical operator having the property that if P is a

statement, then the NOT of P is true if P is false, false if P is true.
NRZI: Non-return-to-zero inverted.
ns: Nanosecond; one-thousandth-millionth of a second.
operating system: Software that controls the execution of

programs; an operating system may provide services such as
resource allocation, scheduling, input/output control, and data
management.
OR: A logic operator having the property that if P is a statement,

Q is a statement, R is a statement, ... ,then the OR of P,Q,R, .. .is
true if at least one statement is true, false if all statements are
false.
output: Pertaining to a device, process, or channel involved in an

output process, or to the data or states involved in an output
process.
output process: (1) The process that consists of the delivery of

data from a data processing system, or from any part of it. (2) The
return of information from a data processing system to an end
user, including the translation of data from a machine language to
a language that the end user can understand.
overcurrent: A current of higher than specified strength.
overvoltage: A voltage of higher than specified value.
Glossary H-ll
parallel: (1) Pertaining to the concurrent or simultaneous
operation of two or more devices, or to the concurrent
performance of two or more activities. (2) Pertaining to the
concurrent or simultaneous occurrence of two or more related
activities in multiple devices or channels. (3) Pertaining to the
simultaneity of two or more processes. (4) Pertaining to the
simultaneous processing of the individual parts of a whole, such as
the bits of a character and the characters of a word, using separate
facilities for the various parts. (5) Contrast with serial.
PEL: Picture element.
personal computer: A small home or business computer that has

a processor and keyboard that can be connected to a television or
some other monitor. An optional printer is usually available.
picture element (PEL): (1) The smallest displayable unit on a

display. (2) Synonymous with pixel, PEL.
pinout: A diagram of functioning pins on a pinboard.
pixel: Picture element.
polling: (1) Interrogation of devices for purposes such as to avoid

contention, to determine operational status, or to determine
readiness to send or receive data. (2) The process whereby
stations are invited, one at a time, to transmit.
port: An access point for data entry or exit.
printed circuit board: A piece of material, usually fiberglass,

that contains a layer of conductive material, usually metal.
Miniature electronic components on the fiberglass transmit
electronic signals through the board by way of the metal layers.
program: (1) A series of actions designed to achieve a certain

result. (2) A series of instructions telling the computer how to
handle a problem or task. (3) To design, write, and test computer
programs.
programming language: (1) An artificial language established

for expressing computer programs. (2) A set of characters and
rules, with meanings assigned prior to their use, for writing
computer programs.
H-12 Glossary
PROM: Programmable read-only memory.
propagation delay: The time necessary for a signal to travel from

one point on a circuit to another.
radix: (1) In a radix numeration system, the positive integer by

which the weight of the digit place is multiplied to obtain the
weight of the digit place with the next higher weight; for example,
in the decimal numeration system, the radix of each digit place is
10. (2) Another term for base.
radix numeration system: A positional representation system in

which the ratio of the weight of anyone digit place to the weight
of the digit place with the next lower weight is a positive integer.
The permissible values of the character in any digit place range
from zero to one less than the radix of the digit place.
RAS: Row address strobe.
RGBI: Red-green-blue-intensity.
read-only memory (ROM): A storage device whose contents

cannot be modified, except by a particular user, or when operating
under particular conditions; for example, a storage device in which
writing is prevented by a lockout.
read/write memory: A storage device whose contents can be

modified.
red-green-blue-intensity (RGBI): The description of a direct-

drive color monitor which accepts red, green, blue, and intensity
signal inputs.
register: (1) A storage device, having a specified storage
capacity such as a bit, a byte, or a computer word, and usually
intended for a special purpose. (2) On a calculator, a storage
:levice in which specific data is stored.
RF modulator: The device used to convert the composite video

;ignal to the antenna level input of a home TV.
ROM: Read-only memory.
Glossary H-13
ROM/BIOS: The ROM resident basic input/output system,
which provides the device level control ofthe major I/O devices in
the computer system.
row address strobe (RAS): A signal that latches the row

addresses in a memory chip.
RS-232C: The standard set by the EIA for communications

between computers and external equipment.
RTS: Request to send. Associated with modem control.
run: A single continuous performance of a computer program

or routine.
scan line: The use of a cathode beam to test the cathode ray tube
of a display used with a personal computer.
schematic: The description, usually in diagram form, of the

logical and physical structure of an entire data base according to a
conceptual model.
SDLC: Synchronous Data Link Control.
sector: That part of a track or band on a magnetic drum, a

magnetic disk, or a disk pack that can be accessed by the magnetic
heads in the course of a predetermined rotational displacement of
the particular device.
serdes: Serializer/deserializer.
serial: (1) Pertaining to the sequential performance of two or

more activities in a single device. In English, the modifiers serial
and parallel usually refer to devices, as opposed to sequential and
consecutive, which refer to processes. (2) Pertaining to the
sequential or consecutive occurrence of two or more related
activities in a single device or channel. (3) Pertaining to the
sequential processing of the individual parts of a whole, such as
the bits of a character or the characters of a word, using the same
facilities for successive parts. (4) Contrast with parallel.
sink: A device or circuit into which current drains.
H-14 Glossary
software: (1) Computer programs, procedures, rules, and
possibly associated documentation concerned with the operation
of a data processing system. (2) Contrast with hardware.
source: The origin of a signal or electrical energy.
source circuit: (1) Generator circuit. (2) Control with sink.
SS: Start-stop transmission.
start bit: Synonym for start signal.
start-of-text character (STX): A transmission control character

that precedes a text and may be used to terminate the message
heading.
start signal: (1) A signal to a receiving mechanism to get ready

to receive data or perform a function. (2) In a start-stop system, a
signal preceding a character or block that prepares the receiving
device for the reception of the code elements. Synonymous with
start bit.
start-stop (SS) transmission: Asynchronous transmission such

that a group of signals representing a character is preceded by a
start signal and followed by a stop signal. (2) Asynchronous
transmission in which a group of bits is preceded by a start bit that
prepares the receiving mechanism for the reception and
registration of a character and is followed by at least one stop bit
that enables the receiving mechanism to come to an idle condition
pending the reception of the next character.
stop bit: Synonym for stop signal.
stop signal: (1) A signal to a receiving mechanism to wait for the

next signal. (2) In a start-stop system, a signal following a
character or block that prepares the receiving device for the
reception of a subsequent character or block. Synonymous with
stop bit.
strobe: (1) An instrument used to determine the exact speed of

circular or cyclic movement. (2) A flashing signal displaying an
exact event.
STX: Start-of-text character.
Glossary H -15
Synchronous Data Link Control (SLDC): A protocol for the
management of data transfer over a data communications link.
synchronous transmission: Data transmission in which the

sending and receiving devices are operating continuously at the
same frequency and are maintained, by means of correction, in a
desired phase relationship.
text: In ASCII and data communication, a sequence of characters

treated as an entity if preceded and terminated by one STX and
one ETX transmission control, respectively.
track: (1) The path or one of the set of paths, parallel to the
reference edge on a data medium, associated with a single reading
or writing component as the data medium moves past the
component. (2) The portion of a moving data medium such as a
drum, tape, or disk, that is accessible to a given reading head
position.
transistor-transistor logic (TIL): A circuit in which the

multiple-diode cluster of the diode-transistor logic circuit has been
replaced by a multiple-emitter transistor.
TIL: Transistor-transistor logic.
TX Data: Transmit data. Associated with modem control.

External connections of the RS-232C asynchronous
communications adapter interface.
video: Computer data or graphics displayed on a cathode ray

tube, monitor or display.
write precompensation: The varying of the timing of the head

current from the outer tracks to the inner tracks of the diskette to
keep a constant write signal.
H-16 Glossary
BIBLIOGRAPHY
Intel Corporation. The 8086 Family User's Manual

This manual introduces the 8086 family of microcomputing
components and serves as a reference in system design and
implementation.
Intel Corporation. 8086/8087/8088 Macro Assembly Reference

Manualfor 8088/8085 Based Development System
This manual describes the 8086/8087/8088 Macro Assembly
Language, and is intended for use by persons who are familiar
with assembly language.
Intel Corporation.Component Data Catalog

This book describes Intel components and their technical
specifications.
Motorola, Inc.The Complete Microcomputer Data Library.

This book describes Motorola components and their technical
specificaitons.
National Semiconductor Corporation. INS 8250 Asynchronous

Communications Element. This book documents physical and
operating characteristics of the INS 8250.
Bibliography 1-1
Notes:
1-2 Bibliography
INDEX
A
A/N mode (alphanumeric mode) 1-131
AO-AI9 (Address Bits 0 to 19), I/O channel 1-18
adapter card with ROM 2-10
adapter,
asynchronous communication 1-223
binary synchronous communication 1-251
color/graphics monitor 1-131
diskette drive 1-159
fixed disk drive 1-187
game control 1-211
monochrome display and printer 1-129
printer 1-117
synchronous data link control 1-271
Address Bits 0 to 19 (AO-AI9), I/O channel 1-131
Address Bits (asynchronous communication) 1-225
Address Enable (AEN), I/O channel 1-22
Address Latch Enable (ALE), I/O channel 1-20
address map, I/O 1-10
AEN (Address Enable), I/O channel 1-22
ALE (Address Latch Enable), I/O channel 1-20
all points addressable mode 1-129, 1-132
alphanumeric mode, 1-136
high resolution 1-137
low resolution 1-137
alt (keyboard extended code) 2-15
APA mode (all points addressable mode) 1-131, 1-132
asynchronous communications adapter, 1-223
adapter address jumper module 1-249
address bits 1~ 225
block diagram 1-224
connector specifications 1-250
current loop interface 1-227
divisor latch least significant bit 1-237
divisor latch most significant bit 1-238
I/O decode 1-225
INS8250 functional pin description 1-229
INS8250 input signals 1-229
INS8250 input/output signals 1-233
INS8250 output signals 1-232
interface descriptions 1-226
interface format jumper module 1-249
Index J-l
interrupt control functions 1-237
interrupt enable register 1-243
interrupt identification register 1-240
interrupts 1-226
line control register 1-235
line status register 1-239
modem control register 1-244
modem status register 1-246
modes of operation 1-224
programmable baud rate generator 1-237
programming considerations 1-234
receiver buffer register 1-247
reset functions 1-230
transmitter holding register 1-248
voltage interchange information 1-228
attributes, character
(see character attributes)
B
BASIC reserved interrupts 2-7
BASIC,
DEF SEG 2-8
reserved interrupt 2-7
screen editor keyboard functions 2-20
workspace variables 2-8
baud rate generator 1-237
bell (printer) 1-102
bibliography 1-1
binary synchronous communications adapter, 1-251
8251A programming procedures 1-262
8251A universal synchronous/asynchronous
receiver/transmitter 1-252
8253-5 programmable interval timer 1-257
8255A-5 programmable peripheral interface 1-256
block diagram 1-252
command instruction format 1-264
connector information 1-269
data bus buffer 1-253
interface signal information 1-266
interrupt information 1-268
mode instruction definition 1-263
read/write control logic 1-253
receive 1-258
J-2 Index
receiver buffer 1-255
receiver control 1-255
status read definition 1-265
transmit 1-265
transmitter buffer 1-254
transmitter control 1-255
typical programming sequence 1-259
BIOS,
cassette logic (see cassette logic BIOS)
fixed disk ROM A-87
memory map 2-9
parameter passing 2-3
software interrupt listing 2-4
system ROM A-2
use of 2-2
bisync communications
(see binary synchronous communications)
block diagram
8251A universal synchronous/asynchronous
receiver/transmitter 1-252
8273 SDLC protocol controller 1-272
asynchronous communications adapter 1-224
cassette circuits 1-29
color/graphics monitor adapter 1-134
coprocessor 1-37
diskette drive adapter 1-160
expansion board 1-80
extender card 1-87
fixed disk drive adapter 1-188
game control adapter 1-211
keyboard interface 1-75
monochrome display adapter 1-124
printer adapter 1-118
prototype card 1-218
receiver card 1-89
speaker drive system 1-24
synchronous data link control adapter 1-271
system 1-2
break (keyboard extended code) 2-17
BSC adapter
(see binary synchronous communications)
Index J-3
c
cable
communications adapter 1-301
expansion unit 1-79
printer 1-91
cancel (printer) 1-103
cancel ignore paper end (printer) 1-103
cancel skip perforation (printer) 1-109
caps lock (keyboard extended code) 2-16
card dimensions and specifications E-4
card,
dimensions and specifications E-4
extender 1-85
prototype 1-217
receiver 1-88
carriage return (printer) 1-102
cassette circuit block diagram
motor control 1-30
read hardware 1-29
write hardware 1-29
cassette interface, 1-28
cassette logic,
BIOS 2-21
cassette read 2-23
cassette write 2-22
data record architecture 2-24
data record components 2-24
error recovery 2-24
interrupt 2-21
software algorithms 2-28
cassette read 2-23
cassette ROM BIOS 2-21
cassette write 2-22
CCITT, F-l
standards F-l
character attributes
character codes
keyboard 2-11
J-4 Index
character set,
graphics printer (set 1) 1-113
graphics printer (set 2) 1-115
matrix printer 1-111
quick reference C-12
clear printer buffer (printer) 1-110
CLK (system clock), I/O channel 1-19
color display 1-157
operating characteristics 1-157
specifications E-2
color select register 1-149
6845 register description 1-148
alphanumeric mode 1-136
alphanumeric mode (high-resolution) 1-144
alphanumeric mode (low-resolution) 1-142
block diagram 1-134
character attributes 1-140
color-select register 1-149
composite connector specifications 1-155
direct-drive connector specifications 1-155
display buffer basic operation 1-145
graphics mode 1-141
graphics mode (high resolution) 1-144
graphics mode (low resolution) 1-142
graphic mode (medium resolution) 1-142
light pen connector specifications 1-156
major components 1-135
memory requirements 1-154
mode control and status register 1-149
mode register summary 1-152
mode select register 1-151
RF modulator connector specifications 1-156
sequence of events 1-153
status register 1-153
summary of available colors 1-146
colors, summary of available 1-146
command status register 0 1-172
Index J-5
command summary,
communications adapter cable 1-301
communications F-l
establishing a link F-3
component diagram,
system board 1-7
compressed (printer) 1-103
compressed off (printer) 1-103
connector specifications,
binary synchronous communications 1-269
cassette interface 1-31
communications adapter cable 1-302
diskette drive adapter (external) 1-182
diskette drive adapter (internal) 1-181
game control adapter 1-216
connectors,
power supply (system unit) 1-26
power supply (expansion unit) 1-83
considerations, programming
(see programming considerations)
control byte, fixed disk drive adapter 1-194
control codes, printer 1-10 1
control/read/write logic 1-274
coprocessor,
(see math coprocessor)
ctrl (keyboard extended code) 2-15
current loop interface 1-227
D
DO-D7 (data bits 0 to 7), I/O channel 1-18
DACKO-DACK3 (DMA Acknowledge 0 to 3), I/O channel 1-21
Data Bits 0 to 7 (DO-D7), I/O channel 1-18
data flow,
system board 1-8
J-6 Index
data record architecture, cassette 2-24
data record components, cassette 2-24
data register 1-193
data transfer mode register 1-288
DEF SEG (default segment workspace) 2-8
default workspace segment (DEF SEG) 2-8
diagram, block (see block diagram)
digital output register 1-161
adapter input 1-179
adapter output 1-178
block diagram 1-160
command summary 1-166
connector specifications (external) 1-182
connector specifications (internal) 1-181
digital-output register 1-161
DPC registers 1-174
drive A and B interface 1-178
drive constants 1-176
FDC constants 1-176
floppy disk controller 1-162
functional description 1-161
programming summary 1-175
symbol descriptions 1-164
system I/O channel interface 1-176
diskette drive, 1-183
electrical specifications 1-184
mechanical specifications 1-184
switch settings G-1
diskettes 1-1 85
display adapter type switch settings G-1
display,
color 1-157
monochrome 1-123
divisor latch,
least significant bit 1-237
most significant bit 1-238
DMA Acknowledge 0 to 3 (DACKO-DACK3),
I/O channel 1-21
Index J-7
DMA Request 1 to 3 (DRQI-DRQ3), I/O channel 1-21
DOS reserved interrupts 2-9
DOS,
keyboard functions 2-21
reserved interrupts 2-9
double strike (printer) 1-106
double strike off (printer) 1-107
double width (printer) 1-99, 1-103
double width off (printer) 1-103
DPC registers 1-175
DRQI-DRQ3 (DMA Request 1 to 3), I/O channel 1-21
E
EIA, F-l
standards F-l
emphasized (printer) 1-106
emphasized off (printer) 1-106
error recovery, cassette 2-24
escape (printer) 1-104
establishing a communications link F-3
expansion board, 1-79
block diagram 1-80
expansion channel 1-81
expansion unit, 1-79
cable 1-79
expansion board 1-79
expansion channel 1-81
extender card 1-85
interface information 1-90
power supply 1-83
power supply connectors 1-83
receiver card 1-88
specifications E-2
extender card, 1-85
block diagram 1-87
switch settings G-l
J-8 Index
F
FABS 1-44
FADD 1-43
FBLD 1-45
FBSTP 1-46
FCHS 1-46
FCLEX/FNCLEX 1-46
FCOM 1-47
FCOMP 1-47
FCOMPP 1-48
FDECSTP 1-48
FDISI/FNDISI 1-48
FDIV 1-49
FDIVR 1-50
FENI/FNENI 1-51
FFREE 1-51
FICOM 1-51
FICOMP 1-52
FILD 1-52
FINCSTP 1-52
FINIT/FNINIT 1-53
FIST 1-54
FISTP 1-54
fixed disk controller 1-185
fixed disk drive 1-201
block diagram 1-186
command summary 1-193
control byte 1-192
data register 1-191
fixed disk controller 1-185
interface specifications 1-200
programming summary 1-197
ROM BIOS listing A-87
sense bytes 1-187
status register 1-187
system I/O channel interface 1-198
fixed disk drive, 1-201
electrical specifications 1-202
mechanical specifications 1-202
Index J-9
fixed disk ROM BIOS A-87
FLD 1-55
FLDCW 1-55
FLDENV 1-56
FLDLG2 1-56
FLDLN2 1-56
FLDL2E 1-57
FLDL2T 1-57
FLDPI 1-57
FLDZ 1-58
FLDI 1-58
floppy disk controller 1-160
FMUL 1-59
FNOP 1-60
FPATAN 1-60
FPREM 1-60
FPTAN 1-61
FRNDINT 1-61
FRSTOR 1-61
form feed (printer) 1-102
FSAVE/FNSAVE 1-62
FSCALE 1-62
FSQRT 1-62
FST 1-63
FSTCW/FNSTCW 1-63
FSTENV/FNSTENV 1-64
FSTP 1-64
FSTSW/FNSTSW 1-65
FSUB 1-65
FSUBR 1-66
FTST 1-67
FWAIT 1-68
FXAM 1-68
FXCH 1-69
FXTRACT 1-70
FYL2X 1-70
FYL2XPI 1-71
F2XMl 1-71
G
game control adapter, 1-211
block diagram 1-211
J-I0 Index
functional description 1-212
I/O channel description 1-213
interface description 1-214
joy stick schematic diagram 1-215
glossary, H-l
graphics mode, 1-141
high resolution 1-144
low resolution 1-142
medium resolution 1-142
H
hardware interrupt listing 1-11
home head (printer) 1-105
horizontal tab (printer) 1-102
I
I/O address map 1-10
I/O bit map, 8255A 1-12
I/O CH CK (I/O Channel Check), I/O channel 1-20
I/O CH RDY (I/O Channel Ready), I/O channel 1-20
I/O Channel Check (I/O CH CK), I/O channel 1-20
I/O channel interface,
prototype card 1-217
I/O Channel Ready (I/O CH RDY), I/O channel 1-20
I/O channel, 1-17
-I/O Channel Check (I/O CH CK) 1-20
-I/O Read Command (lOR) 1-20
-I/O Write Command (lOW) 1-21
Address Bits 0 to 19 (AO-AI9) 1-20
Address Enable (AEN) 1-21
Address Latch Enable (ALE) 1-20
Data Bits 0 to 7 (DO-D7) 1-20
description 1-20
diagram 1-18
DMA Request 1 to 3 (DRQI-DRQ3) 1-21
I/O Channel Ready (I/O CH RDY) 1-20
Interrupt Request 2 to 7 (IRQ2-IRQ7) 1-20
Memory Read Command (MEMR) 1-21
Index J-11
Memory Write Command (MEMW) 1-21
Oscillator (OSC) 1-19
Reset Drive (RESET DRV) 1-20
System Clock (CLK) 1-20
Terminal Count (T/C) 1-22
I/O Read Command (lOR), I/O channel 1-21
I/O Write Command (IOW),I/O channel 1-21
IBM 10MB Fixed Disk Drive 1-201
IBM 5-1/4" Diskette Drive 1-183
IBM 5-1/4" Diskette Drive Adapter 1-159
IBM 80 CPS Graphics Printer 1-91
IBM 80 CPS Matrix Printer 1-91
IBM 80 CPS Printers 1-91
IBM Asynchronous Communications Adapter 1-223
IBM Binary Synchronous Communications Adapter 1-251
IBM Color Display 1-157
IBM Color/Graphics Monitor Adapter 1-131
IBM Communicatons Adapter Cable 1-301
IBM Fixed Disk Drive Adapter 1-187
IBM Game Control Adapter 1-211
IBM Memory Expansion Options 1-205
IBM Monochrome Display and Printer Adapter 1-223
IBM Monochrome Display 1-129
IBM Personal Computer Math Coprocessor 1-33
IBM Printer Adapter 1-117
IBM Prototype Card 1-215
IBM Synchronous Data Link Controller Adapter 1-271
ignore paper end (printer) 1-104
INS8250,
(see National Semiconductor INS8250)
Intel 8088 microprocessor,
arithmetic B-7
conditional transfer operations B-14
control transfer B-ll
data transfer B-5
hardware interrupt listing 1-8
instruction set index B-18
instruction set matrix B-16
logic B-9
memory segmentation model B-4
operand summary B-15
processor control B-15
register model B-2
J-12 Index
second instruction byte summary B-3
segment override prefix B-4
string manipulation B-I0
use of segment override B-4
Intel 8253-5 Programmable Interval Timer
(see synchronous data link control communications adapter)
Intel 8255A Programmable Peripheral Interface
I/O bit map 1-12
Intel 8255A-5 Programmable Peripheral Interface
Intel 8273 SDLC Protocol Controller
block diagram 1-273
interrupt enable register 1-243
interrupt identification register 1-243
interrupt listing,
8088 hardware 1-11
8088 software 2-4
Interrupt Request 1 to 7 (IRQ2-IRQ7), I/O channel 1-20
interrupts,
8088 hardware 1-11
8088 software 2-4
BASIC reserved 2-7
DOS reserved 2-21
special 2-7
lOR (I/O Read Command), I/O channel 1-20
lOW (I/O Write Command), I/O channel 1-21
IRQ2-IRQ7 (Interrupt Request 2 to 7), I/O channel 1-20
J
joy stick,
positions 1-221
schematic diagram 1-215
jumper module, asynchronous communications adapter 1-249
Index J-13
K
keyboard extended codes,
alt 2-15
break 2-16
caps lock 2-16
ctrl 2-15
pause 2-17
print screen 2-17
scroll lock 2-16
shift 2-15
shift key priorities 2-16
shift states 2-15
system reset 2-16
keyboard 1-73
BASIC screen editor special functions 2-20
character codes 2-11
commonly used functions 2-18
diagram 1-76
DOS special functions 2-20
encoding 2-11
extended functions 2-14
interface block diagram 1-75
interface connector specifications 1-78
scan codes 1-77
specifications E-l
L
light pen connector specifications 1-156
line control register 1-235
line feed (printer) 1-102
line status register 1-239
logic diagrams D-l
M
math coprocessor 1-33
block diagram 1-37
control unit 1-37
control word 1-40
J-14 Index
data types 1-34
exception pointers 1-41
FABS 1-44
FADD 1-44
FBLD 1-45
FBSTP 1-46
FCHS 1-46
FCLEX/FNCLEX 1-46
FCOM 1-47
FCOMP 1-47
FCOMPP 1-48
FDECSTP 1-48
FDISI/FNDISI 1-48
FDIV 1-49
FDIVR 1-50
FENI/FNENI 1-51
FFREE 1-51
FICOM 1-51
FICOMP 1-52
FILD 1-52
FINCSTP 1-52
FINIT/FNINIT 1-53
FIST 1-54
FISTP 1-54
FLD 1-55
FLDCW 1-55
FLDENV 1-56
FLDLG2 1-56
FLDLN2 1-56
FLDL2E 1-57
FLDL2T 1-57
FLDPI 1-57
FLDZ 1-58
FLDI 1-58
FMUL 1-59
FNOP 1-60
FPATAN 1-60
FPREM 1-60
FPTAN 1-61
FRND INT 1-61
FRS TOR 1-61
Index J-15
FSAVE/FNSAVE 1-62
FSCALE 1-62
FSQRT 1-62
FST 1-63
FSTCW/FNSTCW 1-63
FSTENV/FNSTENV 1-64
FSTP 1-64
FSTSW/FNSTSW 1-65
FSUB 1-65
FSUBR 1-66
FTST 1-67
FWAIT 1-68
FXAM 1-68
FXCH 1-69
FXTRACT 1-70
FYL2X 1-70
FYL2XPI 1-71
F2XMl 1-71
hardware interface 1-35
instruction set 1-43
interconnection 1-36
number system 1-42
programming interface 1-34
register stack 1-38
status word 1-39
tag word 1-41
memory expansion options, 1-205
DIP module start address 1-208
memory module description 1-206
memory module pin configuration 1-207
memory option switch settings G-l
R/W memory operating characteristics 1-206
switch-configurable start address 1-208
memory locations,
reserved 2-8
memory map,
BIOS 2-9
system 1-13
Memory Read Command (MEMR), I/O channel 1-21
memory switch settings, G-l
extender card G-I
memory options G-l
system board G-l
J-16 Index
Memory Write Command (MEMW), I/O channel 1-21
(MEMR) Memory Read Command, I/O channel 1-21
(MEMW) Memory Write Command, I/O channel 1-21
microprocessor (see Intel 8088 microprocessor)
mode control and status register 1-149
mode select register 1-151
modem control register 1-244
modem status register 1-246
monochrome display 1-129
monochrome display and printer adapter 1-123
6845 CRT control port 1-127
6845 CRT status port 1-127
block diagram 1-124
character attributes 1-138
I/O address and bit map 1-127
monochrome display, 1-129
operating characteristics 1-129
specifications E-3
Motorola 6845 CRT Controller,
(see color/graphics monitor adapter)
(see monochrome display adapter)
N
National Semiconductor INS8250 Asynchronous
(see asynchronous communications adapter)
functional pin description 1-229
input signals 1-229
input/output signals 1-233
output signals 1-232
null (printer) 1-102
o
one bit delay mode register 1-289
operating mode register 1-289
OSC (oscillator) 1-19
Oscillator (OSC), I/O channel 1-19
over-voltage/over-current (expansion unit) 1-84
over-voltage/over-current (system unit) 1-27
Index J-17
p
parameter passing (ROM BIOS) 2-3
pause (keyboard extended code) 2-17
power good signal (expansion unit) 1-84
power good signal (system unit) 1-27
power supply (expansion unit) 1-82
connectors 1-83
input requirements 1-82
over-voltage/current protection 1-84
pin assignments 1-83
power good signal 1-83
Vac output 1-82
Vdc output 1-82
power supply (system unit) 1-23
connectors and pin assignments 1-26
input requirements 1-24
over-voltage/current protection 1-27
pin assignments 1-26
power good signal 1-27
Vac output 1-25
Vdc output 1-25
print screen (keyboard extended code) 2-17
printer adapter, 1-117
block diagram 1-118
printer control codes, 1-101
1I8-inch line feeding 1-104
1920 bit-image graphics mode 1-110
7!7 2-inch line feeding 1-104
960 bit-image graphics mode normal speed 1-110
bell 1-102
cancel 1-103
cancel ignore paper end 1-105
cancel skip perforation 1-109
carriage return 1-102
clear printer buffer 1-110
compressed 1-103
compressed off 1-103
double strike 1-106
double strike off 1-107
double width 1-103, 1-110
J-18 Index
double width off 1-103
emphasized 1-106
emphasized off 1-106
escape 1-103
form feed 1-102
home head 1-105
horizontal tab 1-102
ignore paper end 1-104
line feed 1-102
null 1-102
printer deselected 1-103
printer selected 1-103
select character set 1 1-104
select character set 2 1-104
set horizontal tab stops 1-106
set lines per page 1-106
set skip perforation 1-109
set variable line feeding 1-105, 1-107
set vertical tabs 1-105
starts variable line feeding 1-105
subscript/superscript 1-109
subscript/superscript off 1-109
underline 1-104
unidirectional printing 1-109
vertical tab 1-102
printer deselected (printer) 1-103
printer selected (printer) 1-103
printer, 1-91
additional specifications 1-93
cable 1-91
connector pin assignment 1-97
control codes 1-101
graphic character set 1 1-113
graphic character set 2 1-115
interface signal descriptions 1-96
matrix character set 1-111
modes 1-100
parallel interface 1-96
parallel interface timirtg diagram 1-96
specifications 1-92, E-3
switch locations 1-94
switch settings 1-94
processor (see Intel 8088 micrprocessor)
programmable baud rate generator 1-237
Index J-19
programming considerations,
binary synchronous communications adapter 1-259
extender card 1-86
receiver card 1-88
SDLC adapter 1-281
prototype card, 1-217
block diagram 1-218
external interface 1-222
I/O channel interface 1-219
layout 1-219
system loading and power limitations 1-221
Q
quick reference, character set C-12
R
receiver buffer register 1-24 7
receiver card, 1-88
block diagram 1-89
register,
6845 description (color/graphic adapter) 1-146
color select (color/graphic adapter) 1-147
command status 0 (diskette drive adapter) 1-172
data (fixed disk drive adapter) 1-192
data transfer mode (SDLC) 1-288
digital output (diskette drive adapter) 1-161
DPC (diskette drive adapter) 1-175
interrupt enable (asynchronous communications) 1-243
interrupt identification (asynchronous communications) 1-241
line control (asynchronous communications) 1-234
line status (asynchronous communications) 1-239
mode control and status (color/graphics) 1-149
J-20 Index
mode select ( color/graphics) 1-151
modem control (asynchronous communications) 1-244
modem status (asynchronous communications) 1-246
one-bit delay mode (SDLC) 1-289
operating mode (SDLC) 1-286
receiver buffer (asynchronous communications) 1-247
serial I/O mode (SDLC) 1-288
status (color/graphics) 1-153
status (fixed disk drive adapter) 1-187
transmitter holding (asynchronous communications) 1-248
reserved interrupts,
BASIC and DOS 2-7
reserved memory locations 2-7
Reset Drive (RESET DRV), I/O channel 1-19
RESET DRV (Reset Drive), I/O channel 1-19
RF modulator connector specifications 1-156
ROM BIOS, 2-2
Cassette A-74
Fixed Disk A-87
System A-2
ROM, adapter cards with 2-10
RS-232C,
interface standards F-2
s
scan codes,
keyboard 1-77
scroll lock (keyboard extended code) 2-16
SDLC (see synchronous data link control)
select character set 1 (printer) 1-104
select character set 2 (printer) 1-104
sense bytes, fixed disk drive adapter 1-189
serial I/O mode register 1-288
set horizontal tab stops (printer) 1-106
set lines per page (printer) 1-106
set skip perforation (printer) 1-109
set variable line feeding (printer) 1-105, 1-107
set vertical tabs (printer) 1-105
shift (keyboard extended code) 2-15
shift key priorities (keyboard code) 2-16
shift states (keyboard extended code) 2-15
speaker connector 1-23
speaker drive system 1-23
speaker interface 1-23
Index J-21
specifications,
80 CPS printers E-3
color display E-2
expansion unit E-2
keyboard E-l
monochrome display E-3
printer 1-92
printer (additional) 1-93
system unit E-l
stack area 2-7
starts variable line feeding (printer) 1-104
status register,
sUbscript/ superscript (printer) 1-109
subscript/superscript off (printer) 1-109
switch settings, G-l
diskette drive G-l
display adapter type G-l
extender card G-l
memory options G-l
printer 1-91
system board G-l
system board memory G-l
synchronous data link control communications adapter, 1-271
8253-5 interval timer control word 1-285
8253-5 progammable interval timer 1-281
8255A-5 port A assignments 1-280
8255A-5 port B assignments 1-280
8255A-5 port C assignments 1-281
8255A-5 programmable peripheral interface 1-280
8273 command phase flow chart 1-292
8273 commands 1-291
8273 control/read/write registers 1-275
8273 data interfaces 1-276
8273 elements of data transfer interface 1-276
8273 mode register commands 1-288
8273 modem control block 1-277
8273 modem control port A 1-277
8273 modem control port B 1-278
8273 modem interface 1-277
8273 protocol controller operations 1-271
8273 protocol controller structure 1-273
8273 register selection 1-274
8273 SDLC protocol controller block diagram 1-273
J-22 Index
8273 transmit/receiver timing 1-279
block diagram 1-271
command phase 1-290
control/read/write logic 1-274
data transfer mode register 1-288
device addresses 1-297
execution phase 1-293
general receive 1-294
initialization/configuration commands 1-286
initializing the SDLC adapter 1-283
interface information 1-298
interrupt information 1-297
one bit delay code register 1-289
operating mode register 1-286
partial byte received codes 1-296
processor interface 1-274
protocol control module features 1-272
protocol controller operations 1-272
result code summary 1-296
result phase 1-291
selective receive 1-295
serial data timing block 1-279
serial I/O mode register 1-288
status register format 1-282
transmit 1-294
system block diagram 1-2
system board, 1-3
component diagram 1-7
data flow 1-8
R/W memory operating characteristics 1-202
switch settings G-l
System Clock (CLK), I/O channel 1-19
system memory map 1-13
system reset (keyboard extended code) 2-16
system ROM BIOS A-2
system unit, 1-3
cassette interface 1-31
I/O channel 1-17
I/O channel diagram 1-18
power supply 1-23
speaker interface 1-22
specifications E-l
system board 1-3
Index J-23
T
T/C (Terminal Count), I/O channel 1-22
transmitter holding register 1-248
u
underline (printer) 1-104
unidirectional printer (printer) 1-109
v
Vac output,
expansion unit 1-82
system unit 1-25
Vdc output,
expansion unit 1-82
system unit 1-25
vectors with special meanings 2-5
vertical tab (printer) 1-102
voltage interchange,
Numerics
1/8 inch line feeding (printer) 1-104
1920 bit-image graphics mode (printer) 1-110
6845,
(see color/graphics monitor adapter)
(see monochrome display adapter)
7/72 inch line feeding (printer) 1-104
8088,
(see Intel 8088 microprocessor)
8250,
(see asynchronous communications adapter)
8253-5,
(see synchronous data link control adapter)
8255A 1-12
8255A-5,
8273,
960 bit-image graphics mode normal speed (printer) 1-110
J-24 Index
---
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What is the warranty period for IBM Personal Computers?

What is the warranty period for IBM Personal Computers?

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LIMITED WARRANTY

The International Business Machines Corporation warrants this IBM Personal

ALL EXPRESS AND IMPLIED WARRANTIES FOR THIS PRODUCT

IF THIS PRODUCT IS NOT IN GOOD WORKING ORDER AS WARRANTED

SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF

WARNING: This equipment has been certified to comply with

Notice: As sold by the manufacturer, the Prototype card does

CAUTION: This product is equipped with a UL-listed and

Revised Edition (April 1983)

© Copyright International Business Machines Corporation, 1981, 1982, 1983

The IBM Personal Computer Technical Reference manual

The information in this pUblication is both introductory and for

You should be familiar with the use of the Personal Computer,

This manual has two sections:

"Section 1: Hardware" describes each functional part of the

"Section 2: ROM BIOS and System Usage" describes the basic

The publication has seven appendixes:

Appendix A: ROM BIOS Listings

A glossary and bibliography are included.

Guide to Operations for the IBM Personal Computer

BASIC for the IBM Personal Computer

Disk Operating System (DOS) for the IBM Personal Computer

Hardware Maintenance and Service for the IBM Personal

MACRO Assembler for the IBM Personal Computer

Related publications are listed in the bibliography.

Section 2: ROM BIOS and System Usage

Appendix A: ROM BIOS Listings .............. A-I

Appendix B: 8088 Assembly Instruction

Appendix E: Specifications ..................... E-l

Section 2: ROM BIOS and System Usage .......... .

Appendix A: ROM BIOS Listings ................. .

Appendix B: 8088 Assembly Instruction

Appendix C: Of Characters, Keystrokes,

Appendix D: Logic Diagrams ..................... .

Appendix F: Communications ..................... .

Appendix G: Switch Settings ...................... .

IBM Personal Computer System Unit ................. 1-3

System Board Expansion Board

8088 Cassette Oscillator

Monochrome 0 isplay Monochrome Oisplay Synchronous Data Link Control

System Block Diagram

1-2 System Unit

Two dual-in-line package (DIP) switches (two eight-switch packs)

The system board consists of five functional areas: the processor

The processor is supported by a set of high-function support

The three programmable timer/counters are used by the system as

1-4 System Unit

The difference between the R/W memory on the two system

System Board Minimum Maximum Memory Soldered Pluggable

16K by 1 Bank 3 Banks

64K by 1 Bank 3 Banks

Memory greater than either system board's maximum is obtained

System Unit 1·5

Both the keyboard and cassette interfaces are 5-pin DIN

The speaker drive circuit is capable of approximately 1/2 watt of