ATmega16A Datasheet Summary

ATmega16A
8-bit Microcontroller with 16K Bytes In-System

Programmable Flash
DATASHEET SUMMARY
Features
z
High-performance, Low-power Atmel AVR 8-bit Microcontroller
Advanced RISC Architecture

131 Powerful Instructions Most Single-clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 16MIPS Throughput at 16MHz
On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments

16KBytes of In-System Self-programmable Flash program memory
512Bytes EEPROM
1KByte Internal SRAM
Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
Data retention: 20 years at 85C/100 years at 25C(1)
Optional Boot Code Section with Independent Lock Bits
z In-System Programming by On-chip Boot Program
z True Read-While-Write Operation
Programming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface

Boundary-scan Capabilities According to the JTAG Standard
Extensive On-chip Debug Support
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG
Interface
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and
Capture Mode
Real Time Counter with Separate Oscillator
Four PWM Channels
8-channel, 10-bit ADC
z 8 Single-ended Channels
z 7 Differential Channels in TQFP Package Only
z 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
Byte-oriented Two-wire Serial Interface
Programmable Serial USART
Master/Slave SPI Serial Interface
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Atmel-8154CS-8-bit-AVR-ATmega16A_Datasheet Summary-07/2014
Special Microcontroller Features

Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby
I/O and Packages

32 Programmable I/O Lines
40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
Operating Voltages
2.7 - 5.5V
Speed Grades
0 - 16MHz
Power Consumption @ 1MHz, 3V, and 25C

Active: 0.6mA
Idle Mode: 0.2mA
Power-down Mode: < 1A
ATmega16A [DATASHEET]
Pin Configurations
Pinout ATmega16A
PDIP
(XCK/T0) PB0
(T1) PB1
(INT2/AIN0) PB2
(OC0/AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP1) PD6
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
PC3 (TMS)
PC2 (TCK)
PC1 (SDA)
PC0 (SCL)
PD7 (OC2)
PB4 (SS)
PB3 (AIN1/OC0)
PB2 (AIN0/INT2)
PB1 (T1)
PB0 (XCK/T0)
GND
VCC
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
TQFP/QFN/MLF
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
NOTE:
Bottom pad should
be soldered to ground.
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
PD3
PD4
PD5
PD6
PD7
VCC
GND
(SCL) PC0
(SDA) PC1
(TCK) PC2
(TMS) PC3
Figure 1-1.
(INT1)
(OC1B)
(OC1A)
(ICP1)
(OC2)
1.
2.
Overview
The ATmega16A is a low-power CMOS 8-bit microcontroller based on the Atmel AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega16A achieves throughputs
approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing
speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
PA0 - PA7
PC0 - PC7
PORTA DRIVERS/BUFFERS
PORTC DRIVERS/BUFFERS
PORTA DIGITAL INTERFACE
PORTC DIGITAL INTERFACE
VCC
GND
AVCC
MUX &
ADC
ADC
INTERFACE
TWI
AREF
PROGRAM
COUNTER
STACK
POINTER
PROGRAM
FLASH
SRAM
TIMERS/
COUNTERS
OSCILLATOR
INTERNAL
OSCILLATOR
XTAL1
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
WATCHDOG
TIMER
OSCILLATOR
XTAL2
X
INSTRUCTION
DECODER
MCU CTRL.
& TIMING
RESET
CONTROL
LINES
ALU
INTERRUPT
UNIT
AVR CPU
STATUS
REGISTER
EEPROM
PROGRAMMING
LOGIC
SPI
USART
+
-
INTERNAL
CALIBRATED
OSCILLATOR
COMP.
INTERFACE
PORTB DIGITAL INTERFACE
PORTD DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
PORTD DRIVERS/BUFFERS
PB0 - PB7
PD0 - PD7
The Atmel AVR core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient
while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega16A provides the following features: 16Kbytes of In-System Programmable Flash Program
memory with Read-While-Write capabilities; 512bytes EEPROM; 1Kbyte SRAM; 32 general purpose I/O lines,
32 general purpose working registers; a JTAG interface for Boundary-scan; On-chip Debugging support and
programming; three flexible Timer/Counters with compare modes; Internal and External Interrupts; a serial
programmable USART; a byte oriented Two-wire Serial Interface, an 8-channel; 10-bit ADC with optional
differential input stage with programmable gain (TQFP package only); a programmable Watchdog Timer with
Internal Oscillator; an SPI serial port; and six software selectable power saving modes. The Idle mode stops the
CPU while allowing the USART; Two-wire interface; A/D Converter; SRAM; Timer/Counters; SPI port; and
interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the
Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save
mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the
device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous
Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with lowpower consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue
to run.
The device is manufactured using Atmels high density nonvolatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional
nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program
can use any interface to download the application program in the Application Flash memory. Software in the
Boot Flash section will continue to run while the Application Flash section is updated, providing true ReadWhile-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega16A is a powerful microcontroller that provides a highly-flexible and costeffective solution to many embedded control applications.
The ATmega16A is supported with a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
2.2
2.2.1
Pin Descriptions
VCC
Digital supply voltage.
2.2.2
GND
Ground.
2.2.3
Port A (PA7:PA0)
Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide
internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics
with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled
low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
2.2.4
Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tristated when a reset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega16A as listed on page 57.
2.2.5
Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tristated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled,
the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs.
Port C also serves the functions of the JTAG interface and other special features of the ATmega16A as listed on
page 59.
2.2.6
Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega16A as listed on page 62.
2.2.7
RESET
Reset Input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the
clock is not running. The minimum pulse length is given in Table 27-2 on page 281. Shorter pulses are not
guaranteed to generate a reset.
2.2.8
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.2.9
XTAL2
Output from the inverting Oscillator amplifier.
2.2.10
AVCC
AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even
if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
2.2.11
AREF
AREF is the analog reference pin for the A/D Converter.
3.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
Note:
4.
1.
Data retention
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over
20 years at 85C or 100 years at 25C.
5.
About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device.
These code examples assume that the part specific header file is included before compilation. Be aware that not
all C Compiler vendors include bit definitions in the header files and interrupt handling in C is compiler
dependent. Please confirm with the C Compiler documentation for more details.
6.
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
$3F ($5F)
SREG
$3E ($5E)
SPH
SP10
SP9
SP8
11
SP4
SP3
SP2
SP1
SP0
11
IVSEL
IVCE
47, 67
$3D ($5D)
SPL
$3C ($5C)
OCR0
$3B ($5B)
GICR
SP7
SP6
SP5
Timer/Counter0 Output Compare Register
INT1
INT0
Page
81
INT2
$3A ($5A)
GIFR
INTF1
INTF0
INTF2
68
$39 ($59)
TIMSK
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
OCIE0
TOIE0
82, 109, 128

82, 110, 128
$38 ($58)
TIFR
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
OCF0
TOV0
$37 ($57)
SPMCR
SPMIE
RWWSB
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
242
$36 ($56)
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
189
$35 ($55)
MCUCR
SM2
SE
SM1
SM0
ISC11
ISC10
ISC01
ISC00
35, 66
$34 ($54)
MCUCSR
JTD
ISC2
JTRF
WDRF
BORF
EXTRF
PORF
41, 67, 236
$33 ($53)
TCCR0
FOC0
WGM00
COM01
COM00
WGM01
CS02
CS01
CS00
79
$32 ($52)
TCNT0
(1)
$31
(1)
($51)
OSCCAL
OCDR
Timer/Counter0 (8 Bits)
81
Oscillator Calibration Register
30
On-Chip Debug Register
218
$30 ($50)
SFIOR
ADTS2
ADTS1
ADTS0
ACME
PUD
PSR2
PSR10
64,84,129,194,212
$2F ($4F)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
FOC1A
FOC1B
WGM11
WGM10
105
$2E ($4E)
TCCR1B
ICNC1
ICES1
WGM13
WGM12
CS12
CS11
CS10
107
$2D ($4D)
TCNT1H
Timer/Counter1 Counter Register High Byte
108
$2C ($4C)
TCNT1L
108
$2B ($4B)
OCR1AH
Timer/Counter1 Counter Register Low Byte

Timer/Counter1 Output Compare Register A High Byte
$2A ($4A)
OCR1AL
Timer/Counter1 Output Compare Register A Low Byte
109
$29 ($49)
OCR1BH
Timer/Counter1 Output Compare Register B High Byte
109
$28 ($48)
OCR1BL
Timer/Counter1 Output Compare Register B Low Byte
109
$27 ($47)
ICR1H
Timer/Counter1 Input Capture Register High Byte
109
$26 ($46)
ICR1L
Timer/Counter1 Input Capture Register Low Byte
$25 ($45)
TCCR2
$24 ($44)
TCNT2
$23 ($43)
OCR2
$22 ($42)
ASSR
$21 ($41)
(2)
$20
(2)
($40)
FOC2
WGM20
COM21
109
109
COM20
WGM21
CS22
CS21
CS20
Timer/Counter2 (8 Bits)
Timer/Counter2 Output Compare Register
125
127
127
AS2
TCN2UB
OCR2UB
TCR2UB
WDTCR
WDTOE
WDE
WDP2
WDP1
WDP0
UBRRH
URSEL
UBRR[11:8]
127
41
162
UCSRC
URSEL
UMSEL
UPM1
UPM0
USBS
UCSZ1
UCSZ0
UCPOL
161
$1F ($3F)
EEARH
EEAR8
20
$1E ($3E)
EEARL
EEPROM Address Register Low Byte
$1D ($3D)
EEDR
EEPROM Data Register
$1C ($3C)
EECR
EERIE
EEMWE
EEWE
EERE
$1B ($3B)
PORTA
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
64
$1A ($3A)
DDRA
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
64
20
20
20
$19 ($39)
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
64
$18 ($38)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
64
$17 ($37)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
64
$16 ($36)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
65
$15 ($35)
PORTC
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
65
$14 ($34)
DDRC
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
65
$13 ($33)
PINC
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
65
$12 ($32)
PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
65
$11 ($31)
DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
65
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
$10 ($30)
PIND
$0F ($2F)
SPDR
SPI Data Register
65
138
$0E ($2E)
SPSR
SPIF
WCOL
SPI2X
138
$0D ($2D)
SPCR
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
137
$0C ($2C)
UDR
$0B ($2B)
UCSRA
USART I/O Data Register
158
$0A ($2A)
UCSRB
$09 ($29)
UBRRL
$08 ($28)
ACSR
ACD
ACBG
$07 ($27)
ADMUX
REFS1
$06 ($26)
ADCSRA
ADEN
$05 ($25)
ADCH
ADC Data Register High Byte
211
$04 ($24)
ADCL
ADC Data Register Low Byte
211
$03 ($23)
TWDR
Two-wire Serial Interface Data Register
$02 ($22)
TWAR
TWA6
$01 ($21)
TWSR
TWS7
$00 ($20)
TWBR
RXC
TXC
UDRE
FE
DOR
PE
U2X
MPCM
159
RXCIE
TXCIE
UDRIE
RXEN
TXEN
UCSZ2
RXB8
TXB8
160
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
194
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
208
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
210
USART Baud Rate Register Low Byte
TWA5
TWS6
TWA4
TWS5
162
191
TWA3
TWS4
TWA2
TWS3
TWA1
TWA0
TWPS1
TWGCE
TWPS0
Two-wire Serial Interface Bit Rate Register
192
191
189
Notes:
1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the
debugger specific documentation for details on how to use the OCDR Register.
2. Refer to the USART description for details on how to access UBRRH and UCSRC.
3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
4. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate
on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
7.
Instruction Set Summary
Mnemonics
Flags
Operands
Description
Operation
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS

ADD
Rd, Rr
Add two Registers
Rd Rd + Rr
Z,C,N,V,H
ADC
Rd, Rr
Add with Carry two Registers
Rd Rd + Rr + C
Z,C,N,V,H
1
2
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl Rdh:Rdl + K
Z,C,N,V,S
SUB
Rd, Rr
Subtract two Registers
Rd Rd - Rr
Z,C,N,V,H
SUBI
Rd, K
Subtract Constant from Register
Rd Rd - K
Z,C,N,V,H
SBC
Rd, Rr
Subtract with Carry two Registers
Rd Rd - Rr - C
Z,C,N,V,H
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd Rd - K - C
Z,C,N,V,H
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl Rdh:Rdl - K
Z,C,N,V,S
AND
Rd, Rr
Logical AND Registers
Rd Rd Rr
Z,N,V
ANDI
Rd, K
Logical AND Register and Constant
Rd Rd K
Z,N,V
OR
Rd, Rr
Logical OR Registers
Rd Rd v Rr
Z,N,V
ORI
Rd, K
Logical OR Register and Constant
Rd Rd v K
Z,N,V
EOR
Rd, Rr
Exclusive OR Registers
Rd Rd Rr
Z,N,V
COM
Rd
Ones Complement
Rd $FF Rd
Z,C,N,V
1
1
NEG
Rd
Twos Complement
Rd $00 Rd
Z,C,N,V,H
SBR
Rd,K
Set Bit(s) in Register
Rd Rd v K
Z,N,V
CBR
Rd,K
Clear Bit(s) in Register
Rd Rd ($FF - K)
Z,N,V
INC
Rd
Increment
Rd Rd + 1
Z,N,V
DEC
Rd
Decrement
Rd Rd 1
Z,N,V
TST
Rd
Test for Zero or Minus
Rd Rd Rd
Z,N,V
CLR
Rd
Clear Register
Rd Rd Rd
Z,N,V
SER
Rd
Set Register
Rd $FF
None
MUL
Rd, Rr
Multiply Unsigned
R1:R0 Rd x Rr
Z,C
MULS
Rd, Rr
Multiply Signed
R1:R0 Rd x Rr
Z,C
MULSU
Rd, Rr
Multiply Signed with Unsigned
R1:R0 Rd x Rr
Z,C
FMUL
Rd, Rr
Fractional Multiply Unsigned
R1:R0 (Rd x Rr) <<
Z,C
FMULS
Rd, Rr
Fractional Multiply Signed
Z,C
FMULSU
Rd, Rr
Fractional Multiply Signed with Unsigned
1
R1:R0 (Rd x Rr) << 1
R1:R0 (Rd x Rr) << 1
Z,C
Relative Jump
PC PC + k + 1
None
Indirect Jump to (Z)
PC Z
None
2
3
BRANCH INSTRUCTIONS
RJMP
IJMP
JMP
Direct Jump
PC k
None
RCALL
Relative Subroutine Call
PC PC + k + 1
None
Indirect Call to (Z)
PC Z
None
ICALL
CALL
RET
Direct Subroutine Call
PC k
None
Subroutine Return
PC STACK
None
Interrupt Return
PC STACK
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC PC + 2 or 3
None
CP
Rd,Rr
Compare
Rd Rr
Z, N,V,C,H
CPC
Rd,Rr
Compare with Carry
Rd Rr C
Z, N,V,C,H
CPI
Rd,K
Compare Register with Immediate
Rd K
Z, N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC PC + 2 or 3
None
RETI
4
1/2/3
1
1/2/3
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PCPC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PCPC+k + 1
None
1/2
BREQ
Branch if Equal
if (Z = 1) then PC PC + k + 1
None
1/2
BRNE
Branch if Not Equal
if (Z = 0) then PC PC + k + 1
None
1/2
BRCS
Branch if Carry Set
if (C = 1) then PC PC + k + 1
None
1/2
BRCC
Branch if Carry Cleared
None
1/2
BRSH
Branch if Same or Higher
None
1/2
BRLO
Branch if Lower
None
1/2
BRMI
Branch if Minus
if (N = 1) then PC PC + k + 1
None
1/2
BRPL
Branch if Plus
if (N = 0) then PC PC + k + 1
None
1/2
BRGE
Branch if Greater or Equal, Signed
if (N V= 0) then PC PC + k + 1
None
1/2
BRLT
Branch if Less Than Zero, Signed
if (N V= 1) then PC PC + k + 1
None
1/2
BRHS
Branch if Half Carry Flag Set
if (H = 1) then PC PC + k + 1
None
1/2
BRHC
Branch if Half Carry Flag Cleared
if (H = 0) then PC PC + k + 1
None
1/2
BRTS
Branch if T Flag Set
if (T = 1) then PC PC + k + 1
None
1/2
BRTC
Branch if T Flag Cleared
if (T = 0) then PC PC + k + 1
None
1/2
10
Mnemonics
Flags
Operands
Description
Operation
#Clocks
BRVS
Branch if Overflow Flag is Set
if (V = 1) then PC PC + k + 1
None
1/2
BRVC
Branch if Overflow Flag is Cleared
if (V = 0) then PC PC + k + 1
None
1/2
BRIE
Branch if Interrupt Enabled
if ( I = 1) then PC PC + k + 1
None
1/2
BRID
Branch if Interrupt Disabled
if ( I = 0) then PC PC + k + 1
None
1/2
Rd Rr
Rd+1:Rd Rr+1:Rr
None
None
DATA TRANSFER INSTRUCTIONS

MOV
Rd, Rr
Move Between Registers
MOVW
Rd, Rr
Copy Register Word
LDI
Rd, K
Load Immediate
Rd K
None
LD
Rd, X
Load Indirect
Rd (X)
None
LD
Rd, X+
Load Indirect and Post-Inc.
Rd (X), X X + 1
None
LD
Rd, - X
Load Indirect and Pre-Dec.
X X - 1, Rd (X)
None
LD
Rd, Y
Load Indirect
Rd (Y)
None
LD
Rd, Y+
Rd (Y), Y Y + 1
None
LD
Rd, - Y
Y Y - 1, Rd (Y)
None
LDD
Rd,Y+q
Load Indirect with Displacement
Rd (Y + q)
None
LD
Rd, Z
Load Indirect
Rd (Z)
None
LD
Rd, Z+
Rd (Z), Z Z+1
None
LD
Rd, -Z
Z Z - 1, Rd (Z)
None
LDD
Rd, Z+q
Load Indirect with Displacement
Rd (Z + q)
None
LDS
Rd, k
Load Direct from SRAM
Rd (k)
None
ST
X, Rr
Store Indirect
(X) Rr
None
ST
X+, Rr
Store Indirect and Post-Inc.
(X) Rr, X X + 1
None
2
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X X - 1, (X) Rr
None
ST
Y, Rr
Store Indirect
(Y) Rr
None
ST
Y+, Rr
(Y) Rr, Y Y + 1
None
ST
- Y, Rr
Y Y - 1, (Y) Rr
None
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q) Rr
None
ST
Z, Rr
Store Indirect
(Z) Rr
None
ST
Z+, Rr
(Z) Rr, Z Z + 1
None
ST
-Z, Rr
Z Z - 1, (Z) Rr
None
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q) Rr
None
STS
k, Rr
Store Direct to SRAM
(k) Rr
None
Load Program Memory
R0 (Z)
None
LPM
LPM
Rd, Z
Load Program Memory
Rd (Z)
None
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd (Z), Z Z+1
None
Store Program Memory
(Z) R1:R0
None
In Port
Rd P
None
1
1
SPM
IN
Rd, P
OUT
P, Rr
Out Port
P Rr
None
PUSH
Rr
Push Register on Stack
STACK Rr
None
POP
Rd
Pop Register from Stack
Rd STACK
None
BIT AND BIT-TEST INSTRUCTIONS

SBI
P,b
Set Bit in I/O Register
I/O(P,b) 1
None
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) 0
None
LSL
Rd
Logical Shift Left
Rd(n+1) Rd(n), Rd(0) 0
Z,C,N,V
LSR
Rd
Logical Shift Right
Rd(n) Rd(n+1), Rd(7) 0
Z,C,N,V
ROL
Rd
Rotate Left Through Carry
Rd(0)C,Rd(n+1) Rd(n),CRd(7)
Z,C,N,V
ROR
Rd
Rotate Right Through Carry
Rd(7)C,Rd(n) Rd(n+1),CRd(0)
Z,C,N,V
ASR
Rd
Arithmetic Shift Right
Rd(n) Rd(n+1), n=0:6
Z,C,N,V
SWAP
Rd
Swap Nibbles
Rd(3:0)Rd(7:4),Rd(7:4)Rd(3:0)
None
BSET
Flag Set
SREG(s) 1
SREG(s)
BCLR
Flag Clear
SREG(s) 0
SREG(s)
BST
Rr, b
Bit Store from Register to T
T Rr(b)
BLD
Rd, b
Bit load from T to Register
Rd(b) T
None
SEC
Set Carry
C1
CLC
Clear Carry
C0
SEN
Set Negative Flag
N1
CLN
Clear Negative Flag
N0
SEZ
Set Zero Flag
Z1
CLZ
Clear Zero Flag
Z0
SEI
Global Interrupt Enable
I1
CLI
Global Interrupt Disable
I0
1
1
SES
Set Signed Test Flag
S1
CLS
Clear Signed Test Flag
S0
SEV
Set Twos Complement Overflow.
V1
CLV
SET
Clear Twos Complement Overflow

Set T in SREG
V0
T1
V
T
1
1
11
Mnemonics
Flags
Operands
CLT
SEH
CLH
MCU CONTROL INSTRUCTIONS
NOP
SLEEP
WDR
BREAK
Description
Operation
#Clocks
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
T0
H1
H0
T
H
H
No Operation
Sleep
Watchdog Reset
Break
(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)
For On-Chip Debug Only
None
None
None
None
1
1
1
1
1
1
N/A
12
8.
Ordering Information
Speed (MHz)
16
Notes:
Power Supply
2.7 - 5.5V
Ordering Code(1)
ATmega16A-AU
ATmega16A-AUR(2)
ATmega16A-PU
ATmega16A-MU
ATmega16A-MUR(2)
Package
Operation Range
44A
44A
40P6
44M1
44M1
Industrial
(-40oC to 85oC)
1. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
2. Tape & Reel.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
40-pin, 0.600 Wide, Plastic Dual Inline Package (PDIP)
44M1
44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
13
9.
Packaging Information
9.1
44A
PIN 1 IDENTIFIER
PIN 1
e
B
E1
A1
A2
D1
D
0~7
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
SYMBOL
MIN
NOM
MAX
1.20
A1
0.05
0.15
A2
0.95
1.00
1.05
11.75
12.00
12.25
D1
9.90
10.00
10.10
11.75
12.00
12.25
E1
9.90
10.00
10.10
0.30
0.37
0.45
0.09
(0.17)
0.20
0.45
0.60
0.75
NOTE
Note 2
Note 2
0.80 TYP
06/02/2014
44A, 44-lead, 10 x 10mm body size, 1.0mm body thickness,

0.8 mm lead pitch, thin profile plastic quad flat package (TQFP)
44A
14
9.2
40P6
D
PIN
1
E1
SEATING PLANE
A1
L
B
B1
e
E
0 ~ 15
COMMON DIMENSIONS
REF
eB
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25mm (0.010").
SYMBOL
MIN
NOM
MAX
4.826
A1
0.381
52.070
52.578
15.240
15.875
E1
13.462
13.970
0.356
0.559
B1
1.041
1.651
3.048
3.556
0.203
0.381
eB
15.494
17.526
NOTE
Note 2
Note 2
2.540 TYP
13/02/2014
40P6, 40-lead (0.600"/15.24mm Wide) Plastic Dual

Inline Package (PDIP)
40P6
15
9.3
44M1
Marked Pin# 1 I D
SE ATING PLAN E
A1
TOP VIE W
A3
A
K
L
Pin #1 Co rner
D2
1
2
3
SIDE VIEW
Pin #1
Triangle
Option A
E2
Option B
Option C
Pin #1
Cham fer
(C 0.30)
Pin #1
Notch
(0.20 R)
B OT TOM VIE W
COMMON DIMENSIONS
SYMBOL
MIN
NOM
MAX
0.80
0.90
1.00
A1
0.02
0.05
A3
0.20 REF
0.18
0.23
0.30
6.90
7.00
7.10
D2
5.00
5.20
5.40
6.90
7.00
7.10
E2
5.00
5.20
5.40
e
Note: JEDEC Standard MO-220, Fig
. 1 (S AW Singulation) VKKD-3 .
NOT E
0.50 BSC
0.59
0.64
0.69
0.20
0.26
0.41
02/13/2014
Package Drawing Contact:
packagedrawings@atmel.com
TITLE
44M1, 44-pad, 7 x 7 x 1.0mm body, lead
pitch 0.50mm, 5.20mm exposed pad, thermally
enhanced plastic very thin quad flat no
lead package (VQFN)
GPC
ZWS
DRAWING NO.
REV.
44M1
16
10.
Errata
The revision letter in this section refers to the revision of the ATmega16A device.
10.1
ATmega16A rev. N to rev. Q
First Analog Comparator conversion may be delayed

Interrupts may be lost when writing the timer registers in the asynchronous timer
IDCODE masks data from TDI input
Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request
1. First Analog Comparator conversion may be delayed

If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than
expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Comparator before the first
conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous
Timer/Counter register (TCNTx) is 0x00.
Problem Fix/Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before
writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register
(TCNTx), or asynchronous Output Compare Register (OCRx).
3. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones
during Update-DR.
Problem Fix / Workaround
If ATmega16A is the only device in the scan chain, the problem is not visible.
Select the Device ID Register of the ATmega16A by issuing the IDCODE instruction or by entering
the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register
and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the
ATmega16A while reading the Device ID Registers of preceding devices of the boundary scan chain.
If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the
ATmega16A must be the fist device in the chain.
4. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an
unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.
17
11.
Datasheet Revision History

Please note that the referring page numbers in this section are referred to this document. The referring revision
in this section are referring to the document revision.
Rev. 8154C 07/2014
1.
Atmel brand style guide and datasheet template of 2014-0502 updated in datasheet including
the last page.
2.
Updated the Ordering Code to include Tape & Reel part numbers.
3.
Removed notes 6 and 7 concerning actual low period in Table 27-4 on page 282.
4.
Changed notes 3, 4 and 5, removed note 6 concerning TQFP/MLF packages in Section 27.2
DC Characteristics on page 278
Rev. 8154B 07/09
1.
Updated Errata on page 17.
2.
Updated the last page with Atmels new addresses.
Rev. 8154A 06/08
1.
Initial revision (Based on the ATmega16/L datasheet revision 2466R-AVR-05/08)

Changes done compared ATmega16/L datasheet revision 2466R-AVR-05/08:
- Updated description in Stack Pointer on page 11.
- All Electrical characteristics is moved to Electrical Characteristics on page 278.
- Register descriptions are moved to sub sections at the end of each chapter.
- Added Speed Grades on page 280.
- New graphs in Typical Characteristics on page 289.
- New Ordering Information on page 13.
18
XXXXXX
Atmel Corporation
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
www.atmel.com
2014 Atmel Corporation. / Rev.: Atmel-8154CS-8-bit-AVR-ATmega16A_Datasheet Summary-07/2014.

Atmel, Atmel logo and combinations thereof, Enabling Unlimited Possibilities, AVR and others are registered trademarks or trademarks of Atmel Corporation in U.S.
and other countries. Other terms and product names may be trademarks of others.
DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right
is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE
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ATmega16A

8-bit Microcontroller with 16K Bytes In-System

High-performance, Low-power Atmel AVR 8-bit Microcontroller

Advanced RISC Architecture

High Endurance Non-volatile Memory segments

JTAG (IEEE std. 1149.1 Compliant) Interface

Special Microcontroller Features

I/O and Packages

Power Consumption @ 1MHz, 3V, and 25C

PORTA DIGITAL INTERFACE

PORTC DIGITAL INTERFACE

PORTB DIGITAL INTERFACE

PORTD DIGITAL INTERFACE

About Code Examples

82, 109, 128

41, 67, 236

Oscillator Calibration Register

On-Chip Debug Register

Timer/Counter1 Counter Register High Byte

Timer/Counter1 Counter Register Low Byte

Timer/Counter1 Output Compare Register A Low Byte

Timer/Counter1 Output Compare Register B High Byte

Timer/Counter1 Output Compare Register B Low Byte

Timer/Counter1 Input Capture Register High Byte

Timer/Counter1 Input Capture Register Low Byte

EEPROM Address Register Low Byte

EEPROM Data Register

SPI Data Register

USART I/O Data Register

ADC Data Register High Byte

ADC Data Register Low Byte

Two-wire Serial Interface Data Register

USART Baud Rate Register Low Byte

Two-wire Serial Interface Bit Rate Register

Instruction Set Summary

ARITHMETIC AND LOGIC INSTRUCTIONS

Add two Registers

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Register and Constant

Set Bit(s) in Register

Clear Bit(s) in Register

Test for Zero or Minus

Multiply Signed with Unsigned

Fractional Multiply Unsigned

R1:R0 (Rd x Rr) <<

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Indirect Jump to (Z)

Relative Subroutine Call

Indirect Call to (Z)

Direct Subroutine Call

Compare, Skip if Equal