Tips And Interview Questions | System Verilog

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Tips and Interview Questions

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In this section you will find the common interview questions asked in system verilog related interview.
Please go below to see the pages with answers or click on the links on the left hand side. You can find
answers to all the below questions by Subash Nayak here : http://learn-systemverilog.blogspot.com

BOOKMARK

Here is my take on these questions with inputs from various sources.

1. What is callback ?
2. What is factory pattern ?
3. Explain the difference between data types logic and reg and wire
4. What is the need of clocking blocks ?
5. What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
6. Explain Event regions in SV.
7. What are the types of coverages available in SV ?
8. What is OOPS?
9. What is inheritance and polymorphism?
10. What is the need of virtual interfaces ?
11. Explain about the virtual task and methods .
12. What is the use of the abstract class?
13. What is the difference between mailbox and queue?
14. What data structure you used to build scoreboard
15. What are the advantages of linkedlist over the queue ?
16. How parallel case and full cases problems are avoided in SV
17. What is the difference between pure function and cordinary function ?
18. What is the difference between $random and $urandom?
19. What is scope randomization
20. List the predefined randomization methods.
21. What is the dfference between always_combo and always@(*)?
22. What is the use of packagess?
23. What is the use of $cast?
24. How to call the task which is defined in parent object into derived class ?
25. What is the difference between rand and randc?
26. What is $root?
27. What is $unit?
28. What are bi-directional constraints?
29. What is solve...before constraint ?
30. Without using randomize method or rand,generate an array of unique values?
31. Explain about pass by ref and pass by value?
32. What is the difference between bit[7:0] sig_1; and byte sig_2;
33. What is the difference between program block and module ?
34. What is final block ?
35. How to implement always block logic in program block ?
36. What is the difference between fork/joins, fork/join_none fork/join_any ?
37. What is the use of modports ?
38. Write a clock generator without using always block.
39. What is forward referencing and how to avoid this problem?
40. What is circular dependency and how to avoid this problem ?
41. What is cross coverage ?
42. Describe the difference between Code Coverage and Functional Coverage Which is more important
and Why we need them
43. How to kill a process in fork/join?
44. Difference between Associative array and Dynamic array ?
45. Difference b/w Procedural and Concarent Assertions?
46. What are the advantages of SystemVerilog DPI?
47. How to randomize dynamic arrays of objects?
48. What is randsequence and what is its use?
49. What is bin?
50. Why always block is not allowed in program block?
51. Which is best to use to model transaction? Struct or class ?
52. How SV is more random stable then Verilog?
53. Difference between assert and expect statements?
54. How to add a new processs with out disturbing the random number generator state ?
55. What is the need of alias in SV?
56. What is the need to implement explicitly a copy() method inside a transaction , when we can simple
assign one object to other ?
57. How different is the implementation of a struct and union in SV.
58. What is "this"?
59. What is tagged union ?

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21-05-2015 12:49

Tips And Interview Questions | System Verilog

2 of 3

http://www.asicguru.com/system-verilog/interview-questions/10/

60. What is "scope resolution operator"?

61. What is the difference between Verilog Parameterized Macros and SystemVerilog Parameterized
Macros?
62. What is the difference between
view source
print?
1.logic data_1;
2.var logic data_2;
3.wire logic data_3j;
4.bit data_4;
5.var bit data_5;
63. What is the difference between bits and logic?
64. Write a Statemechine in SV styles.
65. What is the difference between $rose and posedge?
66. What is advantage of program block over clockcblock w.r.t race condition?
67. How to avoid the race condition between programblock ?
68. What is the difference between assumes and assert?
69. What is coverage driven verification?
70. What is layered architecture ?
71. What are the simulation phases in your verification environment?
72. How to pick a element which is in queue from random index?
73. What data structure is used to store data in your environment and why ?
74. What is casting? Explain about the various types of casting available in SV.
75. How to import all the items declared inside a package ?
76. Explain how the timescale unit and precision are taken when a module does not have any
timescalerdeclaration in RTL?
77. What is streaming operator and what is its use?
78. What are void functions ?
79. How to make sure that a function argument passed has ref is not changed by the function?
80. What is the use of "extern"?
81. What is the difference between initial block and final block?
82. How to check weather a handles is holding object or not ?
83. How to disable multiple threads which are spawned by fork...join

The list of interview questions is taken from this link : http://www.edaboard.com/ftopic315416.html. I

will try to answer these questions one by one. If you know the answers of any questions please leave the
comment below

Index :
-- What is callback : Callback Concept
-- What is factory pattern : Factory Patten Concept
-- Logic Reg wire : Difference between logic, wire, reg
-- Need Clocking Block : What is the need of clocking blocks ?
-- Ways to avoid race : What are the ways to avoid race condition between testbench and RTL using SystemVerilog
-- Coverage Questions : What are the types of coverages available in SV explain
-- OOP : oop concepts
-- Need of virtual interface : What is the need of virtual interfaces ?
-- abstract class : What is the use of the abstract class?
-- Part 1 :
-- Part 2 :

Posted By : Web Development Surrey - Dec. 22, 2009, 5:51 a.m.

Interesting, These are some really helpful questions... Keep up the good work

Posted By : Subash - Feb. 17, 2010, 12:25 p.m.

This is rather a direct copy from here. :) http://learn-systemverilog.blogspot.com/2009/08/system-verilog-interviewquestions.html

Posted By : Pavithra Gokhale - Feb. 24, 2010, 7:57 a.m.

Really nice website..its very useful for beginners..i found it interesting.. thanx a lot Asic Guru:)

Posted By : jigar - Aug. 23, 2010, 4:11 a.m.

Q13- What is the difference between mailbox and queue? As Per http://verificationwithjigar.blogspot.com/2010/04
/sv-question-difference-between-mailbox.html Difference between mailbox and semaphore is very standard question
asked in System Verilog interview,Some times it is asked indirectly. Mailobox,Semaphore can pass the object or
information(variable).For example, there are multiple driver looking to drive same interface(lets call interface A). If
Verifciation environemtn uses Mailbox and provides packet to multiple driver,all of them is allowed access to packet and
henace all can drive the interface A. This will create multiple driver on same interface. In order to avoid this semaphore

21-05-2015 12:49

Tips And Interview Questions | System Verilog

3 of 3

http://www.asicguru.com/system-verilog/interview-questions/10/

can be used which ensures that once driver X has access to object only driver X will be able to drive interface A. driver Y
will have to wait till driver X returns the key so this will avoid multiple driver driving same interface

21-05-2015 12:49