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Uvm Day 1 PDF
Uvm Day 1 PDF
Methodology
Introduction to UVM
UVM
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OVM
Mentor and Cadence jointly came up with OVM(Open)
But synopsys users had a hard time
UVM
UVM Class Library
Benefits of UVM
TLM interfaces - reuse and modularity
UVC - Standardized architecture for all test bench
components
UVM Factory - Change the objects types during run time
High level of Flexibility and Configurability
Automatic test phasing of test bench components
Unified customizable messaging and reporting features
Powerful and Flexible Sequences
What is an UVC
Also called
as Agent
Universal
Verification
Component
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UVC Summary
uvc consists of
Data item : For modeling transaction data
Driver : For driving the stimulus to the DUT
Sequencer : For generating transaction data sequences for the
driver
Monitor : For monitoring the activity on the DUT interface and
collect data for coverage
Agent : To emulate and verify DUT devices by combining driver,
sequencer and monior
Environment : Top level component of the uvc that
encapsulates one or more agents and other components
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UVC Components
Agent
Contains instances of the sequencer,
driver and monitor
uvcs can contain more than one agent
Configurable as active or passive
Active agent can initiate transactions to
the DUT and react to signals from DUT.
Passive agent will never drive any DUT
signals. It mostly monitors an interface
or a group of DUT signals.
Example: Master/Slave agents, TX/RX
agents
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Agent
Environment
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UVM Factory
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UVM Factory
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Component Overriding
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set_inst_override_by_type(env. master0.* ,
driver::get_type(),
driver0::get_type());
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TLM
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Verilog I/O
txn_rdy
Consumer
Producer
yapp packet
Target
TLM API
uvm_get_imp
uvm_get_export
Producer
Initiator
Symbols
yapp packet
uvm_get_port
Consumer
TLM port
TLM export
sub-component
uvm_get_imp
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TLM API
Producer
Target
uvm_put_imp
Uvm_put_export
Consumer
Symbols
TLM port
TLM export
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TLM API
Producer
Target
uvm_put_imp
uvm_put_export
Consumer
Symbols
TLM port
TLM export
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Symbols
TLM port
TLM export
Producer
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Consumer
simple_trans
TLM Examples
Symbols
TLM port
TLM export
txn_req
Producer
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yapp packet
txn_req
Consumer
uvm_put_port
initiator
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packet
tlm FIFO
packet
uvm_get_port
initiator
Communication Model
Producer
Consumer
Symbols
uvm_get_imp
packet
target
uvm_put_port
initiator
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TLM port
initiator
packet
initiator
uvm_put_port
uvm_get_port
TLM export
uvm_put_imp
target
packet
tlm FIFO
packet
uvm_get_port
initiator
Hierarchical Connections
Initiator
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Target
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TLM Interfaces
n
Put interfaces
tlm_nonblocking_put_if
try_put(T trans), can_put()
Get interfaces
tlm_blocking_get_if
get(T trans)
tlm_nonblocking_get_if
try_get(output T trans), can_get()
Peek interfaces
tlm_blocking_peek_if
peek(output T trans)
tlm_nonblocking_peek_if
try_peek(output T trans), can_peek()
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TLM FIFO
tlm_fifo:
Used for buffering transactions between producer(s) and
consumer(s)
Symbols
Implement the following TLM interfaces:
tlm_put_if
TLM port
tlm_get_if
TLM export
tlm_peek_if
Producer
put_port
initiator
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Consumer
packet
tlm FIFO
packet
get_port
initiator
Analysis interface
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Non-blocking
Transaction T is broadcasted to zero, one, or multiple consumers
Intended for non-intrusive monitoring of transactions
Analysis Port/Export
Analysis
port