Synthesis vs. Compilation - Descriptions Mapped To Hardware - Verilog Design Patterns For Best Synthesis
Synthesis vs. Compilation - Descriptions Mapped To Hardware - Verilog Design Patterns For Best Synthesis
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Logic Synthesis
Verilog and VHDL started out as simulation languages, but soon
programs were written to automatically convert Verilog code into
low-level circuit descriptions (netlists).
Verilog
HDL
Synthesis
Tool
circuit
netlist
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1.
Fewer bugs
Improves productivity
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Operators
Logical operators map into primitive
logic gates
Arithmetic operators map into adders,
subtractors,
Unsigned 2s complement
Model carry: target is one-bit wider
that source
Watch out for *, %, and /
Y = ~X << 2
X[3]
Y[5]
X[2]
Y[4]
X[1]
Y[3]
X[0]
Y[2]
No logic involved
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Y[1]
Y[0]
Levels of Representation
High Level Language
Program (e.g., C)
Compiler
61C
Assembly Language
Program (e.g.,MIPS)
Machine Language
Program (MIPS)
Machine Interpretation
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
lw $to,
lw $t1,
sw$t1,
sw$t0,
Assembler
0000
1010
1100
0101
1001
1111
0110
1000
1100
0101
1010
0000
0($2)
4($2)
0($2)
4($2)
0110
1000
1111
1001
1010
0000
0101
1100
Synthesis
1111
1001
1000
0110
0101
1100
0000
1010
Recognizes a target
dependent subset of a
hardware description language
Maps to collection of concrete
hardware resources
Iterative tool in the design
flow
1000
0110
1001
1111
Control Signal
Specification
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Simple Example
module foo (a,b,s0,s1,f);
input [3:0] a;
input [3:0] b;
input s0,s1;
output [3:0] f;
reg f;
always @ (a or b or s0 or s1)
if (!s0 && s1 || s0) f=a; else f=b;
endmodule
Should expand if-else into 4-bit wide multiplexer (a, b, f are 4-bit vectors) and
optimize/minimize the control logic:
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Module Template
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Procedural Assignments
RHS is executed and assignment takes place at the end of the current time step
(not clock cycle); e.g.,
Assume A holds the value 1 A<=2; B<=A; A is left with 2, B with 1.
ii.
iii. Do not mix blocking and non-blocking assignments in the same always block
iv. Do not make assignments to the same variable from more than one always block
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Simply ignored
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Combinational Logic
CL can be generated using:
1.
2.
3.
Always block:
always @ (event_expression)
begin
// procedural assignment statements, if statements,
// case statements, while, repeat, and for loops.
// Task and function calls
end
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Example:
Sel case value 2d2 omitted
Out is not updated when
select line has 2d2
Latch is added by tool to
hold the last value of out
under this condition
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out = foo;
default:
out = 1bx;
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Latch Rule
If a variable is not assigned in all possible executions of
an always statement then a latch is inferred
E.g., when not assigned in all branches of an if or case
Even a variable declared locally within an always is inferred as a
latch if incompletely assigned in a conditional statement
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Encoder Example
Nested IF-ELSE might lead to priority logic
Example: 4-to-2 encoder
always @(x)
begin : encode
if (x == 4'b0001) y = 2'b00;
else if (x == 4'b0010) y = 2'b01;
else if (x == 4'b0100) y = 2'b10;
else if (x == 4'b1000) y = 2'b11;
else y = 2'bxx;
end
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always @(x)
begin : encode
case (x)
4b0001: y = 2'b00;
4b0010: y = 2'b01;
4'b0100: y = 2'b10;
4'b1000: y = 2'b11;
default: y = 2'bxx;
endcase
end
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If the input applied has more than one 1, then this version functions
as a priority encoder -- least significant 1 gets priority (the more
significant 1s are ignored); the circuit will be simplified when possible
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Note now more than one case might match the input
Therefore use parallel case directive: without it, synthesis adds
appropriate matching logic to force priority
Semantics of case construct says that the cases are evaluated from top
to bottom
Only an issue for synthesis when more than one case could match input
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Sequential Logic
Example: D flip-flop with synchronous set/reset:
module dff(q, d, clk, set, rst);
input d, clk, set, rst;
output q;
reg q;
always @(posedge clk)
if (reset)
q <= 0;
else if (set)
q <= 1;
else
q <= d;
endmodule
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d
clk
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s
r
22
(some of
these are to get the right
result, and some just for
readability)
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FSMs (cont.)
/* always block for CL */
always @(state or enable or data_in)
begin
case (state)
/* For each state def output and next */
idle : begin
data_out = 1b0;
if (enable)
next_state = read;
else next_state = idle;
end
read : begin end
write : begin
end
default : begin
next_state = default;
data_out = 1bx;
end
endcase
end
endmodule
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More Help
Online documentation for Synplify
Synthesis Tool:
Under Documents/General Documentation, see
Synplify Web Site/Literature:
http://www.synplicity.com/literature/index.html
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Bottom-line
Have the hardware design clear in your mind when you
write the verilog
Write the verilog to describe that HW
It is a Hardware Description Language not a Hardware
Imagination Language
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