SoC Design Flow & Tools

Pao-Ann Hsiung
Dept of Computer Science & Info. Engineering
National Chung Cheng University
Chiayi, Taiwan

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Contents
„ Introduction
„ System Modeling
„ Hardware-Software Codesign
„ SoC Verification
„ SoC Testing

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System-on-Chip Design Trend
Embedded Software
API

MPU / CPU
Memory
Configurable
Hardware

DSP ASIC
Interface & Core
ADC
Peripherals DAC

RF/IF Subsystem

System-on-Board System-on-Chip
(SoB) (SoC)
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SoC Design Trend

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SoC: System-On-Chip
„ System
A collection of all kinds of components
and/or subsystems that are appropriately
interconnected to perform the specified
functions for end users.
„ An SoC design is a “product creation
process” which
„ Starts at identifying the end-user needs
„ Ends at delivering a product with enough
functional satisfaction to overcome the payment
from the end-user
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SoC Applications
„ Communication
„ Digital cellular phone
„ Networking
„ Computer
„ PC/Workstation
„ Chipsets
„ Consumer
„ Game box
„ Digital Camera

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Benefits of Using SOC
„ Reduced size
„ Reduced overall system cost
„ Lower power consumption
„ Increased performance

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Challenges in SoC Era (1/2)
„ Time-to-market
„ Process roadmap acceleration
„ Consumerization of electronic devices
„ Silicon Complexity
„ Heterogeneous processes
„ Billion Transistors, Deep submicron effects : crosstalk,
wire delays, electromigration, mask costs

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Challenges in SoC Era (2/2)
„ Design Complexity
„ µCs, DSPs, HW/SW, SW protocol stacks, RTOS’s,
digital/analog IPs, On-chips buses
„ System-level architecture
„ Time-in-market
„ Performance/Energy/Cost tradeoff
„ Scalable architecture with unified design environment

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How to Conquer the
Complexity?
„ Use a known real entity
„ A pre-designed component (IP reuse)
„ A platform (architecture reuse)
„ Partition
„ Based on functionality
„ Hardware and software
„ Modeling
„ At different level
„ Consistent and accurate
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IP
„ A predefined, designed/verified, reusable building
block for System-on-Chip
„ Software IP, Silicon IP (Soft IP, Hard IP, …)
„ IP types
„ Foundation IP (cell library, gate array)
„ Standard IP (MPEG2/4, JPEG, USB, IEEE 1394, PCI…)
„ Star IP (ARM, MIPS, Rambus, …)
„ Ancillary characteristics
„ Deliverable at certain level, software/hardware interfaces
„ Modeling at different levels
„ Customizable, Configurable, Parameterizable

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IPs in SoC

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Factors in Selecting IP’s
„ Processor IP selection criteria
„ Power, performance, area, cost
„ Fexibility
„ Hardness (hard IP vs. soft IP)
„ Available system software
„ Development environment
„ Simulation model
„ Support library
„ Support OS
„ Inter-operability with other IP’s

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Challenges for CAD Tools in
IP-based SoC Design
„ Designing at higher levels of abstraction
„ Verification
„ Better and faster verification
„ Timing & Power
„ Better physical design tools and tool integration,
for instance 3D modeling
„ Testing
„ Different testing schemes
„ Capacity
„ To support high number of gate counts
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Challenges for CAD Tools in
IP-based SoC Design
„ IP Integration
„ To support use of commercial IP
„ Hard IP Transition
„ Better physical design tool
„ IP Standards
„ To facilitate use of IP from multiple sources
„ IP security
„ To support various business model

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Platform
„ A fully defined bus structure and a collection
of IP blocks
„ A design methodology to support the feature
of “Plugging and Playing”
„ The definition of a platform is the result of a
trade-off process involving reusability
(programmability and configurability), cost
and performance optimization.
„ Enhance the differentiation
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Reference design Derivative design

Added

Removed Modified

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 SoC Design Flow
Specification

High Level Algorithm Model

C/C++/COSSAP/VCC/MATLAB
System Level
Design

Hardware/Software Partition
N2C/VCC

Communication Refinement Hardware/Software Coverification

N2C/Port-C/VCC N2C/Seamless/"Q/Bridge"

RTOS Device Driver

Hardware

Front End

Software
Design
Design

WinCE/VxWorks Driveway

Back End Embedded

API
Software

Chip
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 SOC Co-design Flow
Design Architecture IP Library

Specification Estimators Description

Language M1
P2
P1

HW/SW Partitioning

HW SW
Verification
VHDL, Verilog
C

Synthesis Compiler

Co-simulation
Rapid design space exploration

On-Chip Processor Quality tool-kit generation

Memory Core

Off-Chip
Memory Design reuse
Synthesized
HW Interface

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SOC Specification
„ Document-based specification
„ Executable specification
„ Precise behavior description
„ No communication overhead
„ No standard yet
„ Stable methodology
„ CAD tool support required

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Specification Languages
„ HDL-based specification language
„ VHDL, Verilog
„ Benefit from existing design flow
„ Good for hardware description
„ HLL-based specification language
„ SystemC, SpecC
„ Typically based on C/C++
„ Good for software/system description
„ Mixed form
„ Superlog, CoWareC

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 Chip Modeling Language Trends

System C/C++
SystemC
SpecC
RTL Verilog
VHDL
Schematic
Gate Entry

1980s 1990s 2000s

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Core Technologies
„ IP Development
„ System Architecture
„ SoC Verification
„ Embedded Software
„ High Speed/Low Power Design

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From Requirement to
Deliverables

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System Architecture Design
„ Specification, Requirement, Functionalities Î
Architecture
„ C-level design, SystemC description and
simulation
„ Advantages
„ Broader design space
performance, power, cost tradeoff
Î scalability, good for time-in-market
„ Early verification
module well-defined, partition, refinement
Î necessary for time-to-market

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 A Typical SOC Architecture
CPU Co-processor Cache
Processor
On-chip bus
CPU
Core Core Bridge System Arbiter
On-chip bus
IP’s with high bandwidth
OCB Peripheral
Core Core Bridge On-chip bus

IP’s with low bandwidth 26

Interfacing IPs
„ PCB (=Processor + Peripheral) shrinks
to SOC
„ Interface between HW and HW
„ FIFO-based interface: I/O
„ On-chip bus is required
„ On-chip bus: System Bus & Peripheral
Bus

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Candidates for Standard On-Chip
Bus
„ ARM (www.arm.com)
„ AMBA (Advanced Microcontroller Bus Architecture)
„ IBM (www.chips.ibm.com)
„ CoreConnect (PLB/OPB/DCR)
„ PALM Chip (www.palmchip.com)
„ M Bus/Palm Bus
„ Mentor Graphics (www.inventra.com)
„ FISP Bus
„ OMI (www.omimo.be)
„ PI (peripheral Interconnect) Bus
„ Fujitsu (www.fujitsu.com)
„ Spcl Bus

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 Scalable Design
Application Software in C/C++

Profiling

Software code Instruction Extension Function Unit Extension ASIC block

Power

Performance

Efficiency

FUE ASIC
IE
FUE
Software code Î Î IE Î
IE
Software code Software code Software code
1st 2nd 3rd Final
product release product release product release product release
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SoC Verification
„ System-level verification
„ concurrent, early software hardware co-simulation
„ testbench setup
„ behavior modeling: instruction set simulator,
bus functional model, memory behavior model,
Verilog or SystemC hardware model
„ A dedicated testbench for every IP
„ Register access test to verify bus
„ Test for checking of blocks interconnected
functionality and block external interfaces
„ Emulation
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What is ISV?
„ ISV = In-System Verification
„ When is ISV required?
„ Design refinement down along the hierarchy
„ Comparison between design levels
„ In-system operation: confirm correct behavior in
system environment
„ Simulation (Chip, I/F)
„ All-software (Software, Software)
„ Emulation (HW[FPGA], HW)
„ Virtual chip (Software, Hardware)

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 Embedded Software Architecture for
SoC Design
Error Memory
MMI/GUI
Host Handling Allocation
Diagnostics
Application Message Task State
Manager controller Machine

Application Program Interface

Display Alarm Event

Services Services Manager
Stack Kernel
Protocol File Data Services
Library
Manager I/O

Device Drivers

Hardware
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High Speed / Low Power
Design
„ Deep submicron effect
„ High speed circuit design
„ Low power / low voltage design
„ Tradeoffs:
„ Cost v/s Functionality
„ Cost v/s Speed
„ Power v/s Speed

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Conclusion
„ SoC產業就是知識經濟
知識： 客戶需求
整合化
功能實現 “SoC產業”
加值化
設計方法

„ 建立Infrastructure、掌握Core
Technologies是我們努力的目標

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