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Verilog Introduction
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The Verilog Language
 Originally a modeling language for a very efficient event-driven

digital logic simulator
 Later pushed into use as a specification language for logic synthesis
 Now, one of the two most commonly-used languages in digital
hardware design (VHDL is the other)
 Virtually every chip (FPGA, ASIC, etc.) is designed in part using one
of these two languages
 Combines structural and behavioral modeling styles
How Verilog Is Used
It is a general purpose HDL with support .
 Allows different levels of abstraction to be mixed in the same design.
 “Synthesis subset”
• Can be translated using Synopsys‟ Design Compiler or others into a netlist.
 Design written in Verilog.
 Simulated to check functionality.
 Synthesized (netlist generated).
 Static timing analysis.
Level of Abstraction
 Verilog supports a design at 4
different levels of abstraction.
Behavioral Highest
• Behavioral Level Abstraction
Level
• Dataflow Level
• Gate Level Dataflow
• Switch level
 Register Transfer Level (RTL)
• A combination of both Gate level
Behavioral & Dataflow constructs.

Lowest
• Acceptable to logic synthesis Abstraction
Switch level Level
Levels of Abstraction (Cont..)
 Behavioral Level :- Used to model the behavior of a design
without describing its actual hardware structure.

 Data Flow Level :- Describes the flow of data between
registers and how a design processes that data.
 Gate Level :- Describes the logic gates and the connections
between logic gates in a design.
 Switch Level :- Describes the transistors and storage nodes
in a device and the connections between :-describes them
Structural Modeling
 When Verilog was first developed (1984) most logic

simulators operated on netlists
 netlist: list of gates and how they’re connected
 A natural representation of a digital logic circuit
 Not the most convenient way to express test benches
Behavioral Modeling
 A much easier way to write testbenches

 Also good for more abstract models of circuits
• Easier to write
• Simulates faster
 More flexible
 Provides sequencing
 Verilog succeeded in part because it allowed both the model and the
testbench to be described together
Modules
 A module is the basic building block in Verilog.
 Elements are grouped into modules to provide the common
functionality that is used at many places in the design.
 A module provides the necessary functionality to the higher-level
block through its port interface (inputs and outputs).
 In Verilog a module is declared by the keyword module.
 A corresponding keyword endmodule must appear at the end of
the module definition.
Modules (contd…)
 Modules CANNOT be nested.
 Rather, one module can instantiate another module.
 Module instantiation is like creating actual objects (Instances)
from the common template (module definition).
 Each instance of module has all the properties of that module.
 Module instantiations are used for:
• connecting different parts of the designs, and
• connecting test bench to the design.
Design Hierarchy
 One top level module
• In which zero or more lower level modules can be instantiated.

• Each low level module can further instantiate still lower level
modules.
 Verilog modules are like modules in schematics or classes in C++.
 Use them to make your design more readable and manageable.
 Debugging individual module is a lot easier than debugging the whole
system together.
Structure of module
module <mod name> (<port list>);
<declarations>; // input, output, inout

// wire, register, etc.
<statements>; // initial, begin, end, always
// dataflow statements
endmodule
Structure of module (contd…)
 The <module name> is an identifier that uniquely names the
module.
 The <port list> is a list of input, inout and output ports which are
used to connect to other modules.
 The <declares> section specifies data objects as registers, memories
and wires as wells as procedural constructs such as functions and
tasks.
 The <statements> may be initial constructs, always constructs,
continuous assignments or instances of modules.
Basic Languages Concepts
Lexical Conventions
Keywords
• In lower case
• Case sensitive
• Delimit tokens, space
 String with double quotes

 Identifier
• A letter or _ can be followed by letters, digits, $ and _
• Max 1024 characters
 Numbers
• [<sign>] [<size>] <base> <num>
• e.g.- 549, „h8ff, „o765, 4‟b11,3‟b10x, -4‟b11
Verilog Comments
 Verilog supports 2 type of comment syntaxes

• Single line comment start with //, and end with
newline.
• Block comment, start with /*, and end with */.
block comment cannot be nested.
Verilog Number Specifications
 Two representations: sized & unsized
 Format:<number of bits><base><number>
<number of bits> Bit length in decimal. This is an optional

value & if not specified, default is host
machine word size. (usually 32 bits)
<base> •.b, ‘B, ‘d, ‘D, ‘o, ‘O, ‘h, ‘H. Default is
‘decimal’
<number> •0-9, a-f, A-F, X, Z, ?, _
(contd…)
 Negative numbers: put minus sign before size.
• Format: -<size><base><number>
• <size> field is always +ve.
• Represented by 2‟s complement internally.
 Often _ (Underscore) is used in between digits of the number
for readability.
(contd…)
 Verilog numbers may have x or z as part of numbers.
 x ? unknown value, z ? high impedance value
 A question mark „?‟ can also be used as an alternative to „z‟.
reg [5:0] Num;
Reg [31:0] data;
..
Num = 6‟b_100x; // Num = 6‟b00100x
data = 32‟bx; // 32 bit no with all x bits
Num = „bz01; // Num = 6‟bzzzz01
Num = „b11??1; // Num = 6‟b011zz1
data = 32„h_x5f3_2693; // data = 32‟hX5f32693
Data Types
 reg: Register
 wire: Wire/net
 Possible Values: 0, 1, x, z
 Default: 1-bit (Scalar)
reg A, B, C;
 Vector:
reg[0:7] A;
reg[7:0] B;
Data Types contd…
 Integer & Real Data Types
• Declaration
integer i, k;
real r;
 Use as registers (inside procedures)
i = 1;
r = 2.9;
k = r; // k is rounded to 3
 Integers are not initialized in Verilog!!
 Reals are initialized to 0.0
Nets
 Nets represent the connections between hardware elements.
 They are always driven by some source.

 Default value for any net type variable is „z‟.
 Usually, declared by the keyword wire.
 Different types: wire, wand, wor, tri, triand, trior, trireg,
etc.
 wire is the most common of all.
Registers
 These correspond to variables in the C language.
 Register data types always retain their value until another

value is placed on them.
 DO NOT confuse with hardware registers built with flip-flops.
 A reg type variable is the one that can hold a value.
 Unlike nets, registers do not need any drivers.
Integers
 A general purpose register data type with default value
having all x bits.

 Declared with keyword integer.
 Usually preferred for arithmetic manipulations over reg.
 Default width: host machine word size (minimum 32 bits).
 Differs from reg type as it stores signed quantities as opposed
to reg storing unsigned quantities.
Real Numbers
 Real number constants declared with a keyword real.
 Real constants have default value of 0.

 Real numbers CANNOT have a range declaration.
 Two notations: Decimal& Scientific notation.
 When a real value is assigned to an integer, the real number
is rounded off to the nearest integer.
Time & Realtime Data types
 time – A special register data type used mainly to store simulation

time.
 time is an unsigned 64-bit by default. Usually, it is used to store
the simulation time.
 realtime is similar to time except that it has initial value of 0.
 Depending upon the timescale specified, realtime provides the
simulation time with the fractional part with given precision.
Four-valued Data
 Verilog‟s nets and registers hold four-valued data
 0, 1
Obvious
Z
Output of an undriven tri-state driver
Models case where nothing is setting a wire‟s value
X
Models when the simulator can‟t decide the value
Initial state of registers
When a wire is being driven to 0 and 1 simultaneously
Output of a gate with Z inputs
Modules and Instances
Basic structure of a Verilog module:
module mymod(output1, output2, input1..);

output output1;
output [3:0] output2;
input input1;
input [2:0] input2;
…
endmodule
Instantiating a Module
 Instances of
module mymod(y, a, b);
 look like
mymod mm1(y1, a1, b1); // Connect-by-position

mymod (y2, a1, b1),
(y3, a2, b2); // Instance names omitted
mymod mm2(.a(a2), .b(b2), .y(c2)); // Connect-by-name
Initial and Always
 Run until they encounter a delay
initial begin
#10 a = 1; b = 0;
#10 a = 0; b = 1;
end
 or a wait for an event
always @(posedge clk) q = d;

always begin wait(i); a = 0; wait(~i); a = 1; end
Blocking vs. Nonblocking
 Verilog has two types of procedural assignment
 Fundamental problem:
• In a synchronous system, all flip-flops sample
simultaneously
• In Verilog, always @(posed clk) blocks run in some
undefined sequence
RTL Coding Guidelines
Basic Goal
 Develop RTL code simple and regular
• Easier to design, code, verify and synthesize
 Consistent coding style, naming conventions and
structure
 Easy to understand
• Comments, meaningful names and constants or
parameters instead of hard coded numbers.
Naming Convention
 Lowercase letters for all signal, variable and port names
e.g. wire clk, rst;
 Uppercase letters for names of constants and user-defined
types
e.g. `define MY_BUS_LENGTH 32
 Meaningful names
• For a RAM address bus, ram_addr instead of ra
Naming Convention (2)
 Short but descriptive
• During elaboration, the synthesis tool
concatenates the names
 clk for clock signal,
• More than one clock? Clk1, clk2 or
clk_interface…
 Active low signals: postfix with „_n‟
 rst for reset signals, if active low rst_n
 When describing multibit buses, use a consistent ordering
of bits
• For Verilog : use (x:0) or (0:x)
 The same or similar names for ports and signals that are
connected
(e.g. a => a or a => a_int)
 Other naming conventions
*_r: output of a register
*_a: asynchronous signal
*_z: tristate internal signal
*_pn: signal used in the nth phase
*_nxt: data before being registered into a register
with the same name
Include Header
// -----------------------------------------------------------
// Copyright Kacper Technologies Pvt.Ltd
// File Name : $RCSfile: DESIGN.v,v $
// Module Name : SHIFTER
// Project : UPF_TC
// Revision : $Revision: 1.3 $
// Date : $Date: 2010/1/27 12:44:52 $
// Module description : Shifter
// ----------------------------------------------------------
Comment
 Placed logically, near the code that describe
 Brief, concise and explanatory
 Separate line for each HDL statements
 Keep the line length to 72 characters or less
• always @(a or b or c or d or e or f or g or h or i)
Indentation
 Improve the readability of continued code lines and nested loops, tab
of 4 is recommended
if(a)
if(b)
if(c)
…
 Port ordering
module my_module(clk,rst, …);
{ // Inputs:
clk, // comment for each
rst, // …
…
// Outputs;
…
}
Port Map
 Use named association rather than
positional association
P_module my_module(
.clk(clk),
.rst(rst),
…
);
Use Function
function [ `BUS_WIDTH-1:0] convert_address;

input input_address, offset;
begin
// … function body
end
endfunction //convert_address
Use Loop and Array
module my_module( … );
…
reg [31:0] reg_file[15:0];
integer tmp;
always @ (posedge clk or posedge rst)

if (rst)
for(tmp=0; tmp<16; tmp++)
reg_file[tmp]<=32‟d0;
…
Meaningful Label
 Helpful for debug
• Label each process block
<name>_PROC
• Label each instance U_<name>
Portability
 Create code technology-independent, compatible with
various simulation tools and easily translatable between
Verilog and VHDL
 Constants instead of hard-coded value
`define MY_BUS_SIZE 8
reg [ `MY_BUS_SIZE-1:0] my_out_bus;
 Keep the `define statements for a design in a single

separate file and name the file DesignName_params.v
Technology Independent
 Avoid embedding dc_shell scripts
exception : the synthesis directives to turn
synthesis on and off must be embedded in the code
in the appropriate places.
 Use Design Ware Foundation Libraries
 Avoid instantiating gates
 If you must use technology-specific gates, then
isolate these gates in a separate module
Clock and Reset
 Simple clocking structure: a single global clock and
positive edge-triggered flops as the only sequential
devices
clk
Mixed Clock Edges
 Avoid!
• Duty cycle of the clock become a critical issue in
timing analysis
• Most scan-based testing methodologies require
separate of positive and negative-edge triggered
flops
 If you must use both,
• Model the worst case duty cycle
• Document the assumed duty cycle
• If you must use many, separate them into different
modules
Clock Buffer
 Avoid hand instantiating clock buffers in RTL code.
They are normally inserted after synthesis as part of the
physical design.
 Avoid internally generated clocks and reset, all the
registers in the macro should be reset at the same time
Gated Clock
 Avoid coding gated clocks in RTL
• Cannot be use part of a scan chain
• If you must use, keep the clock and/or reset
generation circuitry as a separate module at the
top level of the design or model it using
synchronous load registers
always @(posedge clk)

if(p1_gate)
…
Infer Register
 Use reset signal to initialize registered signal instead

of use an initial statement.
 Avoid using any latches
• Assign default value for all path
• Assign outputs for all input conditions
• Use else for the final priority branch
 Avoid combinational feedback.
Sensitivity List
 Specify complete sensitivity list avoid difference
between pre-synthesis and post-synthesis netlist in
combinational blocks
 Include clock and reset in sequential blocks.
 Avoid unnecessary signals in list.
always @(a)
c=a or b;
a a
a
c
b b b
c c
pre-synthesis Synthesized netlist post-synthesis
Case Vs if-then-else
 A case statement infers a single-level multiplexer, while an if-then-else
one infers a priority-encoder, cascaded combination of multiplexers.
 Synopsis directive about case statement case (sel) //synopsis parallel_case
full_case
 if-then-else can be useful if you have a late arriving signal
 For large multiplexers, case is preferred because faster in cycle-based
simulator
 Conditional assignment;
e.g.
assign z1=(sel_a) ? a : b;
State Machines
 Separate state machine into two processes : combinational
and sequential.
• Poor coding style:
a<=b+c;
• Recommended coding style:
always @(b or c)
a_nst = b+c;
a <= a_nst;
Partition for Synthesis
 Good partition provides advantages:

• Better synthesis results
• Faster compile runtime
• Ability to use simpler synthesis strategies to meet
timing
Register Output
 For each block of a hierarchical design, register all output
signals
• Output drive strengths equal to the drive
strength of the average flip-flop.
• Input delays predictable
 Keep related combinational logic together in the same
module
C.A C.B C.C
Different Design Goals
 Keep critical path logic in a separate module, optimize the
critical path logic for speed while optimizing the noncritical
path logic for area.
Speed Critical
Optimization Path logic
clk
Area Noncritical
Optimization Path Logic
clk
Asynchronous Logic
Avoid asynchronous logic

• If required, partition in a separate module from the
synchronous logic
 Merging resources
• mux input than mux output for complicated
processing unit.
Partition for Synthesis Runtime
 Most important considerations in partition: logic
function, design goals and timing and area
requirements.
 Grouping related functions together
 Eliminate glue logic at the top level
Conclusion
 Practice makes perfect

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Verilog Introduction

 Originally a modeling language for a very efficient event-driven

Behavioral & Dataflow constructs.

without describing its actual hardware structure.

 When Verilog was first developed (1984) most logic

 A much easier way to write testbenches

• In which zero or more lower level modules can be instantiated.

module <mod name> (<port list>);

<declarations>; // input, output, inout

 String with double quotes

 Verilog supports 2 type of comment syntaxes

<number of bits> Bit length in decimal. This is an optional

 Nets represent the connections between hardware elements.

 They are always driven by some source.

 These correspond to variables in the C language.

 Register data types always retain their value until another

 A general purpose register data type with default value

having all x bits.

 Real number constants declared with a keyword real.

 Real constants have default value of 0.

 time – A special register data type used mainly to store simulation

module mymod(output1, output2, input1..);

module mymod(y, a, b);

mymod mm1(y1, a1, b1); // Connect-by-position

 or a wait for an event

always @(posedge clk) q = d;

 Verilog has two types of procedural assignment

function [ `BUS_WIDTH-1:0] convert_address;

always @ (posedge clk or posedge rst)

 Keep the `define statements for a design in a single

always @(posedge clk)

 Use reset signal to initialize registered signal instead

 Good partition provides advantages:

C.A C.B C.C

Avoid asynchronous logic

 Practice makes perfect

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