Cell-Based IC Physical Design and Verification - SOC Encounter

i~

CIC 2004/07

Class Schedule
Day1
Design Flow Over View Prepare Data Getting Started Importing Design Specify Floorplan Power Planning Placement Synthesize Clock Tree

Day2
Timing Analysis Trial Route Power Analysis SRoute NanoRoute Fill Filler Output Data DRC LVS extraction/nanosim
2

Chapter1

Cell-Based Physical Design SOC Encounter 3.2

Cell-Based Design Flow

Tape out

Verilog VHDL synthesis

Post layout simulation DRC LVS Gate level netlist

GDSII

Place & Route

Routed design

Add LVS/Nanosim text Replace layout

4

SOC Encounter P&R flow

IO, P/G Placement

Specify Floorplan

Hight

Width

Amoeba Placement

Scan Chain Reorder

Power Planning

10

Clock Tree Synthesis

11

Power Analysis

12

Add Filler

13

Power Route

14

Routing

15

Prepare Data

Gate-Level netlist (verilog) Physical Library (LEF) Timing Library (LIB) Timing constraints (sdc) IO constraint

16

Preparing Data : gate-level netlist

If designing a chip , IO pads , power pads and Corner pads should be added before the netlist is imported. Make sure that there is no assign statement and no *cell* cell name in the netlist.
Use the synthesis command below to remove assign statement. set_boundary_optimization Use the synthesis commands below to remove *cell* cell name define_name_rules name_rule map {{\\*cell\\* cell}} change_names hierarchy output name_rule

17

Prepare Data : LEF -- Process Technology

Layers POLY Design Rule Parasitic Resistance Capacitance Net width Net spacing Contact Area Enclosure Metal1 Wide metal Via1 slot Metal2 Antenna Current density

18

Prepare Data: LEF -- APR technology

Unit Site Routing pitch Default direction Via generate Via stack

19

Prepare Data: LEF -- APR technology : SITE

The Placement site give the placement grid of a family of macros

a row

a site

20

Row Based PR
VDD

VSS

VDD

VSS

21

Prepare Data: LEF -- APR technology : routing pitch , default direction

metal1 routing pitch Horizontal Vertical routing routing Metal1 Metal3 Metal5 Metal2 Metal4 Metal6
22

metal2 routing pitch

Prepare Data: LEF -- APR technology : via generate

To connect wide metal , create a via array to reduce via resistance Defines formulas for generating via arrays
Layer Metal1 Direction HORIZONTAL OVERHANG 0.2 Layer Metal2 Direction VERTICAL OVERHANG 0.2 Layer Via1 RECT 0.14 0.14 0.14 0.14 SPACING 0.56 BY 0.56
23

Prepare Data: LEF -- APR technology : via stack

Without via stack

With via stack

Higher density routing Easier usage of upper layer Must Follow minimum area rule
24

Prepare Data: LEF -- APR technology : Physical Macros

Define physical data for
Standard cells I/O pads Memories other hard macros

describe abstract shape

Size Class Pins Obstructions
25

Prepare Data: LEF -- APR technology : Physical Macros cont.

VDD MACRO ADD1 CLASS CORE ; FOREIGN ADD1 0.0 0.0 ; ORIGEN 0.0 0.0 ; LEQ ADD ; SIZE 19.8 BY 6.4 ; SYMMETRY x y ; SITE coresite PIN A DIRECTION INPUT ; PORT LAYER Metal1 ; RECT 19.2 8.2 19.5 10.3 END END A OBS END END ADD1 26

VSS

Prepare Data: LIB

Operating condition
slow, fast, typical

Pin type
input/output/inout function data/clock capacitance

Path delay Timing constraint

setup, hold, mpwh, mpwl, recovery
27

Prepare Data: Timing constraint

Create clock Input delay Output delay Input drive Output loading

28

Prepare Data: Timing constraint -- Create Clock

create_clock [-name clock_name] -period period_value [-waveform edge_list] [clock_source_list]
20 I_CLK 10

CHIP

create_clock name CLK1 period 20 waveform {0 10} [get_ports I_CLK]

29

Prepare Data: Timing constraint -- create_generated_clock

create_generated_clock -add -master_clock [-name clock_name] -source master_clock_root [-multiply_by mult] [-divide_by div] [-duty_cycle dc] [-invert] [-edges edge_list] [-edge_shift edge_shift_list] clock_root_list
create_generated_clock name CLK2 source [get_ports I_CLK] divide_by 2 [get_pins DF/QN]
30

Prepare Data: Timing constraint --set_input_delay

set_input_delay delay_value [-min] [-max] [-rise] [-fall] [-clock clock_name] [-clock_fall] [-add_delay] [-network_latency_included] [-source_latency_included] port_pin_list

CLK1 delay In1 .. In7 In1 In2 : Design : I_CLK

set_input_delay 1 clock [get_clocks {CLK1}] [getports {In1}]

31

Prepare Data: Timing constraint --set_output_delay

set_output_delay delay_value [-min] [-max] [-rise] [-fall] [-clock clock_name] [-add_delay] [-network_latency_included] [-source_latency_included] port_pin_list

CLK1 delay Out1 Out1 : Design : CLK1

CLK1

set_output_delay 1 clock [get_clocks {CLK1}] [getports {Out1}]

32

Prepare Data: Timing constraint --set_drive

5 In1 In1

3,2,4,3 In2

In2

set_drive [-min] [-max] [-rise] [-fall] drive_strength port_list

rise_min, rise_max, fall_min, fall_max

set_drive 1 [get_ports {In1}]

33

Prepare Data: Timing constraint --set_load

Out1 5f

Out2

4~5f

set_load [-min] [-max] [-pin_load] [-wire_load] load_value port_list

set_load 1 [get_ports {Out1}]

34

Prepare Data: IO constraint

Create an I/O assignment file manualy using the following template:

Version: 1 MicronPerUserUnit: value Pin: pinName side |corner Pad: padInstanceName side|corner [cellName] Offset: length Skip: length Spacing: length Keepclear: side offset1 offset2

35

Prepare Data: IO constraint cont.

Version: 1 Pad: CORNER0 NW Pad: PAD_CLK N Pad: PAD_HALT N Pad: CORNER1 Pad: PAD_X1 Pad: PAD_X2 NE W W
PAD_CLK PAD_HALT

CORNER0

CORNER1

PAD_X2

PAD_VSS1

Pad: CORNER2 SW Pad: PAD_IOVDD1 S Pad: PAD_IOVSS1 S Pad: CORNER3 SE Pad: PAD_VDD1 E Pad: PAD_VSS1 E

PAD_X1

PAD_VDD1

PAD_IOVDD1

PAD_IOVSS1

CORNER2

CORNER3

36

Tips to Reduce the Power/Ground Bounce

Dont use stronger output buffers than what is necessary Use slew-rate controlled outputs Place power pad near the middle of the output buffer Place noise sensitive I/O pads away from SSO I/Os Place VDD and VSS pads next to clock input buffer Consider using double bonding on the same power pad to reduce inductance

37

Cadence On-Line document

unix% /usr/cadence/SOC/cur/tools/bin/cdsdoc & unix% /usr/cadence/IC/cur/tools/bin/cdsdoc & unix% /usr/cadence/LDV/cur/tools/bin/cdsdoc & .. html browser must be installed do not set the proxy in html browser

38

Getting Started
Source the encounter environment:
unix% source /usr/cadence/cic_setup/soc.csh

Invoke soc encounter in 64 bit mode:

unix% encounter -64

Do not run in background mode. Because the terminal become the interface of command input while running soc encounter. The Encounter reads the following initialization files:
$ENCOUNTER/etc/enc.tcl ./enc.tcl ./enc.pref.tcl

Log file:
encounter.log* encounter.cmd*
39

GUI
menus tool widgets switch bar

design display area design views

display control

name of selected object

auto query
40 cursor coordinates

Tool Wedgits

Design Import

Fit

Hierarchy Zoom Previous Down/Up

Calculate Attribute Xwindow Fence Editor dump/undump Density

Zoom In/Out

Zoom Select

Redraw

Undo/Redo Design Browser

Summary Report

41

Design Views
FloorplanView
displays the hierarchical module and block guides,connection flight lines and floorplan objects

Amoeba View
display the outline of modules after placement

Placement View
display the detailed placements of cells, blocks.

42

Display Control
Select Bar

43

Common Used Bindkeys

Key q f z Z Arrows Delete Esc Action Edit attribute Fits display Zoom in Zoom out pans design area in the direction of the arrow Removes the last ruler Removes all rulers Looking for more bindkey: Design->Preference, Binding Key
44

Key d e T 0-9 h H

Action popup Delete popup Edit editTrim View layer [0-9] hierarchy up hierarchy down

Import Design
Design Design Import

Max Timing Libraries

containing worst-case conditions for setup-time analysis

Min Timing Libraries

containing best-case conditions for hold-time analysis

Common Timing Libraries

used in both setup and hold analysis

IO Assignment File:
get a IO assignment template: Design Save I/O File
45

Import Design cont.

Buffer Name/Footprint:
specifies the buffer cell family to be inserted or swapped. required to run IPO and TD placement. Footprint Example:

Delay Name/Footprint:
required to run a fix hold time violation

Inverter Name/Footprint:
required to run IPO and TD placement.

Get footprint of library cells by:

Timing Report Cell Footprint

For Cells: BUFXL BUFX1 BUFX2 BUFX3 BUFX4 BUFX8 BUFX12 BUFX16 BUFX20 Footprint : buf
46

Import Design -- Timing

Default Delay Pin Limit:
Nets with terminal counts greater than the specified value are assigned the default net delay and net load entries.

Default Net Delay:

Set the delay values for a net that meets the pin limit default.

Default Net Load:

Set the load for a net that meets the pin limit default.

Input Transition Delay:

Set the Primary inputs and clock nets.
47

Import Design -- Power

Specify the names of Power Nets and Ground Nets

48

Global Net Connection

Floorplan Gloval Net Connections

49

Specify Floorplan
Floorplan Specify Floorplan

50

Specify Floorplan Doube back rows

Double-back rows:

Row Spacing > 0

Row Spacing = 0

51

Core Limit, I/O Limnt

52

Place Blocks
Floorplan Place Blocks/Modules Place

automatic place blocks ( blackboxes and partitions) and hard macros at the top-level design. Block halo
Specifies the minimum amount of space around blocks that is preserved for routing.

53

Manually Place Block

Move/Resize/Reshape floorplan object. Use functions in : Floorplan Edit Floorplan to edit floorplan.

Set placement status of all pre-placed block to preplaced in order to avoid these blocks be moved by amoebaPlace later. Floorplan Edit Floorplan Set Block Placement Status
54

Add Halo To Block

Floorplan Edit Block Halo

Prevent the placement of blocks and standard cells in order to reduce congestion around a block.

Top Left Right

Bottom

55

Block Placement
Flow step
I/O pre-placed Run quick block placement Throw away standard cell placement Manually fit blocks

Block place issue

power issue noise issue route issue
56

Block Placement
Preserve enough power pad Create power rings around block Follow default routing direction rule Reserve a rounded core row area for placer

block

Default direction
57

Power Planning: Add Rings

Floorplan Power Planning AddRings

Use wire group to avoid slot DRC error

58

Power Planning: Wire Group

Use wire group no interleaving number of bits = 2 Use wire group interleaving number of bits = 2

59

Power Planning: Block Ring

60

Power Planning: Block Ring cont.

61

Power Planning: Add Stripes

62

Edit Route

Duplicate wire

Fix wire wider than max width

Change layer

Split wire Trim wire Merge wire

Clear DRC markers

63

Change width

Delete wire

Edit Route cont.

Move Wire Add Wire

Cut Wire Stretch Wire

64

Placement
Place Place Prototyping : Runs quickly, but components may not be placed at legal location. Timing Driven:
Build timing graph before place. meeting setup timing constraints with routability. Limited IPO by upsizeing/downsizing instances.

Ignore Scan Connection

nets connected to either the scan-in or scan-out are ignored.

Check placement after placed

place Check Placement
65

Floorplan Purposes
Develop early physical layout to ensure design objective can be archived
Minimum area for low cost Minimum congestion for design routable Estimate parasitic for delay calculation Analysis power for reliability

gain early visibility into implementation issues

66

Guide , Region, Fence

Placement constraint Create guide for timing issue A critical path should not through two different modules The more region, the more complicated floorplanning

67

Difference Floorplan Difference Performance

68

Wire Load After Placement

Logical

wire load after placement

69

Module Constraint

Soft Guide Guide Region Fence

Soft Guide

Guide

Region

Fence

70

Specify Scan Chain

encounter > specifyScanChain scanChainName start {ftname | instPinName} stop {ftname | instPinName} Specifies a scan chain in a design. The actual tracing of the scan chain is performed by the scanTrace or scanReorder command ftname
The design input/output pin name

instPinName
The design instance input/output pin name

71

Scan Chain Reorder

Place Reorder Scan

No Skip
Buffers and inverters remain after the scan chain reorder

Skip Buffer
Ignores buffers in the scan chain.

Skit Two Pin Cell

Ignores buffers and inverters in the scan chain
72

Clock Problem
Clock problem
Heavy clock net loading Long clock insertion delay Clock skew Skew across clocks Clock to signal coupling effect Clock is power hungry Electromigration on clock net

Solutions of these problems may be conflict Clock is one of the most important treasure in a chip, do not take it as other use.
73

Clock Tree Topology

74

Synthesize Clock Tree

Create Clock Tree Spec
clock spec

Specify Clock Tree Synthesis Clock Tree Display Clock Tree

Modify

netlist synthesis report clock nets routing guide

75

Create Clock Tree Spec.

Clock Create Clock Tree Spec

76

CTS
CTS traces the clock starting from a root pin, and stops at:
A clock pin A D-input pin An instance without a timing arc A user-specified leaf pin or excluded pin

Write a CTS spec. template:

specifyClockTree -template

77

CTS spec.
A CTS spec. contain the following information.
Timing constraint file (optional) Naming attributes (optional) Macro model data (optional) Clock grouping data (optional) Attributes used by NanoRoute routing solution (optional) Requirement for manual CTS or utomatic,gated CTS

78

CTS spec. --Naming Attributes Section

TimingConstraintFile filename
define a timing constraint file for use during CTS

NameDelimiter delimiter
name delimiter used when inserting buffers and updating clock root and net names. NameDelimiter # create names clk##L3#I2 default clk__L3_I2

UseSingleDelim YES|NO
YES NO clk_L3_I2 clk__L3_I2 (default)
79

CTS Spec. -- NanoRoute Attribute Section

RouteTypeName name
RouteTypeName CK1 END

NonDefaultRule ruleName
Specify LEF NONDEFAULTRULE to be used

PreferredExtraSpace [0-3]
add space around clock wires

Shielding PGNetName
Defines the power and ground net names
80

CTS Spec. -- Macro Model Data Section -- Clock Grouping Section

MacroModel
MacroModel port R64x16/clk 90ps 80ps 90ps 80ps 17pf MacroModel pin ram1/clk 90ps 80ps 90ps 80ps 17pf delay_and_capacitance_value: maxRise minRise maxFall minFall inputCap

ClkGroup
Specifies tow or more clock domains for which you want CTS to balance the skew. ClkGroup +clockRootPinName1 +clockRootPinName2 ..
81

CTS Spec. --Manually Define Clock Tree Topology

ClockNetName netName LevelNumber number
Specify the clock tree level number

LevelSpec levelNumber numberOfBuffers bufferType

levelNumber
Specify the level number in the clock tree

numberOfBuffer
the total number of buffers CTS should allow on the specified level

Example:
LevelSpec 1 2 CLKBUFX2 LevelSpec 2 2 CLKBUFX2

End
82

CTS Spec. -- Automatic Gated CTS Section

AutoCTSRootPin clockRootPinName MaxDelay number{ns|ps} MinDelay number{ns|ps} SinkMaxTran number{ns|ps}
maximum input transition time for sinks(clock pins)

BufMaxTran number{ns|ps}
maximum input transition time for buffers (defalut 400)

MaxSkew number{ns|ps}

83

CTS Spec. -- Automatic Gated CTS Section cont.

NoGating {rising|falling|NO}
rising : stops tracing through a gate(include buffers and inverters) and treats the gate as a rising-edge-triggered flip-flop clock pin. falling: stops tracing through a gate(include buffers and inverters) and treats the gate as a falling-edge-triggered flip-flop clock pin. No: Allows CTS to trace through clock gating logic. (default)

AddDriverCell driver_cell_name
Place a driver cell at the cloest possible location to the clock port location .

84

CTS Spec. -- Automatic Gated CTS Section cont.

MaxDepth number RouteType routeTypeName RouteClkNet YES|NO
Specifies whether CTS routes clock nets.

PostOpt YES|NO
whether CTS resizes buffers of inverters , refines placement,and corrects routing for signal and clock wires. default YES

Buffer cell1 cell2 cell3

Specifies the names of buffer cells to use during CTS.
85

CTS Spec. -- Automatic Gated CTS Section cont.

LeafPin + pinName rising|falling +
Mark the pin as a leaf pin for non-clock-type instances. LeafPin + instance1/A rising + instance2/A rising A

LeafPort + portName rising|faling +

Mark the port as a leaf port for non-clock-type instances

86

CTS Spec. -- Automatic Gated CTS Section cont.

ExcludedPin + pinName + .. ExcludedPort + portName +
Treats the port as a non-leaf port, and prevents tracing and skew analysis of the pin.

87

CTS Spec. -- Automatic Gated CTS Section cont.

ThroughPin + pinName + ..
Traces through the pin, even if the pin is a clock pin

PreservePin + inputPinName + .

Preserve

Preserve the netlist for the pin and pins below the pin in the clock tree.
88

CTS Spec. -- Automatic Gated CTS Section cont.

DefaultMaxCap capvalue
CTS adheres to the following priority when using maximum capacitance value:
MaxCap statements in the clock tree specification file DefaultMaxCap statement in the clock tree specification file Maximum capacitance values in the SDC file maximum capacitance values in the .lib file

MaxCap + bufferName1 capValue1{pf|ff} + bufferName2 capValue2{pf|ff} + ..

Buffer should be inserted if the given capacitance value is exceeded
89

Synthesize Clock Tree

Clock Synthesize Clock Tree

Reconvergence clock

Crossover clock
90

Clock Synthesis report

Summary report and detail report
number of sub trees rise/fall insertion delay trigger edge skew rise/fall skew buffer and clock pin transition time detailed delay ranges for all buffers add to clocks

Clock nets
Saves the generated clock nets used to guide clock net routing

Clock routing guide

Saves the clock tree routing data used as preroute guide while running Trial Route
91

Display Clock Tree

Clock Display Display Clock Tree

92

Display Clock Tree -- by level

93

Display Clock Tree --by phase delay

94

Clock Tree Browser

Clock Clock Tree Brower

Display trig edge, rise/fall delay, rise/fall skew, input delay, input tran of each cell. Resize/Delete leaf cell or clock buffer Reconnect clock tree
95

In-Place Optimization
Timing In-Place Optimization

IPO
setup time hold time DRV (Design Rule Violation)

96

Congestion Optimization
encounter > congOpt [ -nrIterInCongOpt nrIter ] [ -maxCPUTimeInCongOpt time ]

Reduces congestion after placement in an iterative way. Parameters

nrIterInCongOpt nrIter
Specifies the total number of iteration in congestion optimization. (default 1)

maxCPUTimeInCongOpt
specifies the maximum CPU time in congestion optimization,in hours.

97

Balance Slew
encounter > balanceSlew [ -selNetFile selNetFileName ] [ -excNetFile excNetFileName ]

Speeds up or slows down the transition time if it is greater or less than the specified maximum transition time. Parameters
selNetFile selNetFileName
Specifies th file that contains the hierarchical net names that are excluded from the IPO pperation

excNetFile excNetFileName
Specifies the file that contains the hierarchical net (path) names for the IPO operations. Only these net names are considered.
98

Useful Skew
encounter > setAnalysisMode -usefulSkew encounter > skewClock encounter > optCritPath

99

Trial Route
perform quick routing for congestion and parasitics estimation Prototyping:
Quickly to gauge the feasibility of netlist. components in design might no be routed at legal location

100

Trial Route Congestion Marker

visually check the congestion statistics. dump congestion area:
BLOCK

dumpCongesArea -all file_name

V=25/20 H=16/18

The vertical (V) overflow is 25/20 (25 tracks are required , but only 20 tracks are available) . The Horizontal (H) overflow is 16/18 (16 tracks are required , and18 tracks are available) .
101

Trial Route Congestion Marker cont.

Level 1 2 3 4 5 6 and higher

Color Blue Green Yellow Red Magenta Grey to White

Overflow Value One more track required Two more track required Three more track required Four more track required Five more track required Six or more track required

102

Timing Analysis
Timing Specify Analysis Condition Specify RC Extraction Mode Timing Extract RC Timing Timing Analysis

No Async/Async:
recovery, removal check

No Skew/Skew:
check with/without clock skew constraint

103

Slack Browser
Timing Timing Debug Slack Browser

104

Power Analysis
Timing Extract RC Power Edit Pad Location Power Edit Net Toggle Probability

105

Statistical Power Analysis

Power Power Analysis Statistical

analysis report:
A power graph report contains
average power usage worst IR drop worst EM violation

instance power file instance voltage file boundary voltage file

106

Simlation-Based Power Analysis

Power Power Analysis Simulation-Based save netlist for simulation
Design Save Netlist

simulation and dump vcd file.

$dumpvars; $dumpfile(wave.vcd);

Input vcd file for power analysis

107

Display IR Drop
Power Display Display IR Drop

108

Display Electron Migration

Power Display Display EM

109

SRoute
Route Special Net (power/ground net)
Block pins Pad pins Pad rings Standard cell pins Stripes (unconnected)

110

Add IO filler
addIoFiller addIoFiller addIoFiller addIoFiller cell cell cell cell PFILL prefix IOFILLER PFILL_9 prefix IOFILLER PFILL_1 prefix IOFILLER PFILL_01 prefix IOFILLER -fillAnyGap

Connect io pad power bus by inserting IO filler. Add from wider filler to narrower filler.

ADD IO FILLER

111

Add IO filler cont.

In order to avoid DRC error
The sequence of placing fillers must be from wider fillers to narrower ones. Only the smallest filler can use -fillAnyGap option.

112

NanoRoute
Route NanoRoute

113

NanoRoute Attributes
Route NanoRoute/Attributes

114

Crosstalk
Crosstalk problem are getting more serious in 0.25um and below for: Smaller pitches Greater height/width ratio Higher design frequency

115

Crosstalk Problem
Delay problem
Aggressor original signal impacted signal

Noise problem

Aggressor original signal

impacted signal 116

Crosstalk Prevention
Placement solution
Insert buffer in lines Upsize driver Congestion optimization
Add buffer

Upsize

Routing solution
Limit length of parallel nets Wider routing grid Shield special nets

117

Antenna Effect
In a chip manufacturing process, Metal is initially deposited so it covers the entire chip. Then, the unneeded portions of the metal are removed by etching, typically in plasma(charged particles). The exposed metal collect charge from plasma and form voltage potential. If the voltage potential across the gate oxide becomes large enough, the current can damage the gate oxide.

118

Antenna Ratio
metal2 via2

Plasma + + + + + ++ + + +

metal2

Plasma

metal1 + + +

via1 poly gate oxide

Antenna Ratio =

Area of process antennas on a node Area of gates to the node

119

Antenna Problem Repair

Add jumper Add antenna cell (diode) Add buffer

metal2

via1

metal1 poly gate oxide

120

Add Core Filler

Place Filler Add Filler

Connect the NWELL/PWELL layer in core rows. Insert Well contact. Add from wider filler to narrower filler.

121

Add bonding pads (stagger IO pads only)

Linear IO pad
PIN Logic and driver

Stagger IO pad Abutted Stagger IO

PR boundary

Bonding matel

Inner Bonding

Outer Bonding

122

Add bonding pads (stagger IO pads only)

For the limitation of bonding wire technique , the stagger IO pads are used in order to reduce IO pad width. We have to add the bonding pads after APR is finished if stagger IO pads is used. But SE does not provide a built-in function for add bonding pads, CIC reaches this purpose by the way of importing DEF. CIC provides a perl script to calculate the bonding pad location. The full flow is described in next page

123

Add bonding pads flow (stagger IO pads only)

A placed and routed design in encounter

Export DEF (In encounter)

routed.def routed.def

bondPads.cmd bondPads.cmd addbonding.pl addbonding.pl addbonding.pl routed.def (In unix terminal) bondPads.eco bondPads.eco source bondPads.cmd (In encounter terminal)

ioPad.list ioPad.list

finish

124

Output Data
Design Save GDS Design Save->Netlist Design Save->DEF

Export GDS for DRC,LVS,LPE,and tape out. Export Netlist for LVS and simulation. Export DEF for reordered scan chain.

125

Chapter2

Post-Layout Verification DRC/ERC/LVS/LPE

Post-Layout Verification Overview

Post-Layout Verification do the following things :
DRC ( Design Rule Check ) ERC (Electrical Rule Check ) LVS (Layout versus Schematic ) LPE/PRE (Layout Parasitic Extraction / Parasitic Resistance Extraction) and Post-Layout Simulation.

127

Post-Layout Verification Overview cont.

DRC LVS
vdd!

zn

compare with

zn

gnd!

ERC
vdd! short clk

LPE/PRE
vdd!

extract i zn i zn

128
gnd!

Post-Layout Verification Overview

Layout Database Schematic Netlist

DRC

Extract Devices

optional

ERC

LVS

LPE/PRE

Extracted Netlist with Parasitic Elements

Text and Graphical Error Reports

Post-Layout Simulation

129

DRC flow
Prepare Layout
stream in gds2 add power pad text stream out gds2

Prepare command file run DRC View DRC error (DRC summary/RVE)

130

Prepare Layout
Stream In design Stream In core gds2 DFII Library Stream In IO gds2 LEF in RAM lef Add power Text Stream Out
131

GDSII GDSII

Prepare Layout: Stream In GDSII

Require:
technology file display.drf

File->import->stream

132

Prepare Layout: Add Power Text

Add power text for LVS and Nanosim For UMC18/artisan library
Add text DVDD for IO power pad Add text DGND for IO ground pad Add text VDD for core power pad Add text GND for core ground pad

133

Prepare Layout: Stream Out GDSII

File->Export->stream..

134

Prepare command file

Prepare DRC Command file:

0.18 (CBDK018_UMC_Artisan) Calibre
180nm_layers.cal G-DF-IXEMODE_RCMOS18-1.8V-3.3V-1P6M-MMC-Calibre-drc-2.2-p1

135

Prepare Calibre Command file

Edit runset file
LAYOUT PATH CHIP.gds2 LAYOUT PRIMARY CHIP LAYOUT SYSTEM GDSII DRC SELECT CHECK NW.W.1 NW.W.2 DRC UNSELECT CHECK NW.S.1Y NW.S.2Y DRC ICSTATION YES INCLUDE Calibre-drc-cur
136

Submit Calibre Job

Submit Calibre Job
calibre drc umc18DRC.cal

Result log
CHIP.drc.summary (ASCII result) CHIP.drc.results (Graphic result)

137

Using Calibre RVE

Add in .cdsinit
setSkillPath(. ~/ /usr/memtor/Calibre_ss/cur/shared/pkgs/icb/tools/queryskl) load(calibre.skl)

138

Using Calibre RVE

139

Using Calibre RVE

140

LVS Overview
Layout Data
VDDclk rst cin sel GNDVDD

Schematic Netlist

a<0> a<1> a<2> a<3> a<4> a<5> VDD

b<0> b<1> b<2> b<3> b<4> b<5> gnd! a<5:0> b<5:0> clk rst cin sel carry s<5:0>

GND s<0> s<1>. . . . .

GND

141

Initial Correspondence Points

Initial correspondence points establish a starting place for layout and schematic comparison. Create initial correspondence node pairs by
adding text strings on layout database. all pins in the top of schematic netlist will be treated as an initial corresponding node if calibre finds a text string in layout which matches the node name in schematic.
VDD

global pin : VDD and GND

...
a<0> b<0> initialcorresponding node pairs

a<0> b<0>

...

...

142

Black-Box LVS
Calibre black-box LVS
One type of hierarchical LVS. Black-box LVS treats every library cell as a black box. Black-box LVS checks only the interconnections between library cells in your design, but not cell inside. You need not know the detail layout of every library cells. Reduce CPU time.

143

Black-Box LVS vs. Transistor-Level LVS

Transistor Level LVS
VDD

i1 i2

i1 vs. i2

GND

Black-Box LVS
inv0d1
VDD

nd02d1 z

inv0d1
i1

nd02d1
z GND

i1 vs. i2

144
i2

LVS flow
Prepare Layout
The same as DRC Prepare Layout

Prepare Netlist
v2lvs

Prepare calibre command file run calibre LVS View LVS error (LVS summary/RVE)

145

Prepare Netlist for Calibre LVS

Prepare Netlist Verilog Verilog CHIP.v CHIP.v v2lvs umc18lvs.spi umc18lvs.spi
CHIP.spi CHIP.spi v2lvs v CHIP.v l umc18lvs.v o CHIP.spi s umc18lvs.spi s1 VDD s0 GND If a macro DRAM64x16 is used v2lvs v CHIP.v l umc18lvs.v l DRAM64x16.v o CHIP.spi s umc18lvs.spi s DRAM64x16.spi s1 VDD s0 GND
146

umc18lvs.v umc18lvs.v

CIC Supported Files (0.18)

CIC supports the following files in our cell library design kit.
Calibre LVS runset file
umc18LVS.cal

Calibre LVS rule file

G-DF-MIXEDMODE_RFCMOS18-1.8V_3.3V-1P6M-MMCCALIBRE-LVS-1.2-P3.txt

Black-box LVS relative files

pseudo spice file
umc18LVS.spi pseudo verilog file umc18LVS.v
147

Black Box related file

Pseudo spice file
.GLOBAL VDD VSS .SUBCKT AN2D1 Z A1 A2 VDD GND .ENDS

Pseudo verilog file

module AN2D1 (Z, A1, A2); output Z; input A1; input A2; endmodule

148

Prepare command file for Calibre LVS

Edit Calibre LVS runset
LAYOUT PATH CHIP.calibre.gds LAYOUT PIMARY CHIP LAYOUT SYSTEM GDSII SOURCE PATH CHIP.spi SOURCE PRIMARY CHIP INCLUDE /calibre/LVS/Calibre-lvs-cur

Edit Calibre LVS rule file

LVS BOX PVSSC LVS BOX PVSSR LVS BOX DRAM64x4s
149

Submit Calibre LVS

calibre lvs spice layout.spi hier auto umc18LVS.cal > lvs.log
layout extract layout.spi verilog v2lvs CHIP.spi

150

Check Calibre LVS Summary

OVERALL COMPAISON RESULTS CELL SUMMARY INFORMATION AND WARNINGS Initial Correspondence Points

151

Check Calibre LVS Summary

OVERALL COMPAISON RESULTS

OVERALL COMPARISON RESULTS

# # # # # # #

################### # # # CORRECT # # # ###################

_ _ * * | \___/

152

Check Calibre LVS Summary

CELL SUMMARY

************************************************* CELL SUMMARY ************************************************* Result ----------CORRECT Layout ----------CHIP Source -------------CHIP

153

Check Calibre LVS Summary

INFORMATION AND WARNINGS
****************************************************************** INFORMATION AND WARNINGS ****************************************************************** Matched Layout ----------11525 Matched Source ----------11525 1 54 79 542 8 ----------10682 Unmatched Unmatched Layout Source -------------- --------------0 0 0 0 0 0 0 0 0 0 .. .. 0 0 -------------- --------------0 0 Component Type --------------

Nets: Instances:

1 54 79 542 8 ----------Total Inst: 10682

ADDFHX1 ADDFHX4 ADDFX2 AND2X1 . XOR3X2 --------------

154

Check Calibre LVS Summary

Initial Correspondence Points

o Initial Correspondence Points: Nets: DVDD VDD DGND GND I_X[2] I_X[3] I_X[4] I_X[5] I_X[6] I_X[7] I_X[8] I_X[9] I_X[10] I_X[11] O_SCAN_OUT O_Z[0] O_Z[1] O_Z[2] O_Z[3] I_HALT I_RESET_ I_DoDCT I_RamBistE I_CLK I_SCAN_IN I_SCAN_EN I_X[0] O_Z[4] I_X[1] O_Z[5] O_Z[6] O_Z[7] O_Z[8] O_Z[9] O_Z[10] O_Z[11]

155

Check Calibre LVS Log

TEXT OBJECT FOR CONNECTIVITY EXTRACTION PORTS Extraction Errors and Warnings for cell CHIP

156

Check Calibre LVS Log

TEXT OBJECT FOR CONNECTIVITY EXTRACTION

-------------------------------------------------------------------------------TEXT OBJECTS FOR CONNECTIVITY EXTRACTION -------------------------------------------------------------------------------O_Z[0] (523.447,31.68) 105 CHIP O_Z[1] (598.068,31.68) 105 CHIP O_Z[2] (821.931,31.68) 105 CHIP O_Z[3] (896.553,31.68) 105 CHIP O_Z[4] (971.175,31.68) 105 CHIP O_Z[5] (1164.455,372.964) 105 CHIP O_Z[6] (1164.455,446.966) 105 CHIP O_Z[7] (1164.455,520.968) 105 CHIP O_Z[8] (1164.455,594.97) 105 CHIP O_Z[9] (1164.455,668.972) 105 CHIP O_Z[10] (1164.455,742.974) 105 CHIP O_Z[11] (1164.455,816.976) 105 CHIP

157

Check Calibre LVS Log

PORTS

-------------------------------------------------------------------------------PORTS -------------------------------------------------------------------------------O_Z[0] (523.447,31.68) 105 CHIP O_Z[1] (598.068,31.68) 105 CHIP O_Z[2] (821.931,31.68) 105 CHIP O_Z[3] (896.553,31.68) 105 CHIP O_Z[4] (971.175,31.68) 105 CHIP O_Z[5] (1164.455,372.964) 105 CHIP

158

Check Calibre LVS Log

Extraction Errors and Warnings for cell CHIP
Extraction Errors and Warnings for cell "CHIP" ---------------------------------------------WARNING: Short circuit - Different names on one net: Net Id: 18 (1) name "GND" at location (330.301,216.95) on layer 102 "M2_TEXT" (2) name "GND" at location (673.2,29.1) on layer 101 "M1_TEXT" (3) name "VDD" at location (748.1,31.5) on layer 101 "M1_TEXT" (4) name "VDD" at location (208.93,274.56) on layer 101 "M1_TEXT" The name "VDD" was assigned to the net.

159

Chapter3

Post-Layout Timing Analysis

-- Nanosim

What Introduce After Place&Route?

Interconnection wires parasitic capacitance.
M2

M1 to substrate capacitance

M1

M1 to M1 capacitance

M1 to M2 capacitance
vdd! vdd!

gnd!

gnd!

161

What Introduce After Place&Route?

Interconnection wires parasitic resistance.
M2

M1 parasitic resistance

VIA

M1

VIA parasitic resistance

vdd!

vdd!

M2 parasitic resistance

gnd!

gnd!

162

Pre-Layout And Post-Layout Design

A pre-layout design (before P&R) and a post-layout design (after P&R)
pre-layout

post-layout

163

Why Post-Layout Simulation?

clock skew

....
critical path delay

critical path delay clk data

...

. . .data

164

Post-layout Timing Analysis Flow

Gate-level Netlist

Gate-level Analysis Tr.-level post-layout timing analysis

Layout

Delay Calculation

Extraction

Tr. Netlist RC Network

RC Network Gate-level post-layout timing analysis

Tr-level Analysis

165

Transistor-level Post-layout Simulation

layout

netlist/parasitic extraction

Calibre LPE/PRE

SPICE netlist

simulation pattern

Post-layout simulation simulation result

Nanosim

166

What is Nanosim
Nanosim is a transistor- level timing simulation tool for digital and mixed signal CMOS and BiCMOS designs. Nanosim handles voltage simulation and timing check. Simulation is event driven, targeting between SPICE ( circuit simulator ) and Verilog ( logic simulator ).

167

Prepare for Post-Layout Simulation

Apply for a CIC account
http://www.cic.org.tw . fill in your personal data and your request.

Install identd program

this program is used to identify yourself when you log into CICs account from remote machine.

Put your DB file to CICs account

168

Replace Layout / LPE

Qentry M {LPE} tech {UMC18 | TSMC18 | TSMC25 | TSMC35} f GDSII T Top_cell_name s Ram_spce_filename t {ra1sd | ra1sh | ra2sd | ra2sh | rf2sh | t18ra1sh | t18ra2sh | t18rf1sh | t18rf2sh | t18rodsh| 18ra1sh_1 | 18ra1sh_2 | 18ra2sh} c {UMC18 | TSMC18 | TSMC25 | TSMC35} i {UMC18 | TSMC18 | TSMC25 | TSMC35} o Netlist_file_name

Example:
Qentry M LPE tech UMC18 f CHIP.gds T CHIP s RAM1.spec t 18ra2sh s RAM2.spec t 18ra1sh_1 s RAM3.spec t 18ra1sh_2 c UMC18 i UMC18 o CHIP.netlist

Use Qstat to check the status of your job. The result is stored in result_# directory.

169

Replace/LPE
INPUT
gds2 ram spec

OUTPUT
output netlist TOP_CELL.NAME nodename spice.header nanosim.run log files for strem in, stream out, lpe
170

Running Nanosim
Qentry M {NANOSIM} n {CHIP.io} nspice CHIP.netlist spice.header nvec CHIP.vec m Top_cell_name c {CHIP.cfg} z {CHIP.tech.z} o Output_file_name out fsdb t Total_simulation_time Example:
Qentry M NANOSIM nspice CHIP.netlist spice.header nvec CHIP.vec m CHIP c CHIP.cfg z CHIP.tech.z o UMC18 t 100

Use Qstat to check the status of your job. The result is stored in result_# directory.
171

Spice Header File

Spice Header File

Modify PVT

.lib 'l18u18v.012' L18U_BJD .lib 'l18u18v.012' L18U18V_TT .lib 'l18u33v_g2.011' l18u33v_tt *epic tech="voltage 3.3 *epic tech="temperature 100"

172

Generate Nanosim Simulation Pattern

Input simulation pattern --- vec format
type vec signal CLOCK,START,IN[7:0] ; time clock start radix 1 1 io i i high 3.3 low 0.0 25 0 0 50 1 0 75 0 0 . . . . .

in<7:0> 44 ii

xx xx xx

173

Generate Nanosim Simulation Pattern

Input simulation pattern --- nsvt format
type nsvt signal CLOCK,START,IN[7:0] ; clock start radix 1 1 io i i period 25 high 3.3 low 0.0 0 0 1 0 0 0 . . . . .

in[7:0] 44 ii

xx xx xx

174

Generate Nanosim Simulation Pattern

You can generate Nanosim simulation pattern from Verilog-XL stimulus.
Verilog test bench file
integer outf; initial begin outf = $fopen("input.dat"); . . . . . $fclose(outf); $finish; end always @(sys_clock or start or in) $fdisplay(outf,"%t %b %b %h",$time,sys_clock,start,in); . . . . .
175

Nanosim Configuration File

Example Nanosim_configuration file bus_notation [ : ] print_node_logic ADRS[0] print_node_logic CLK print_node_logic DATA[0] . . . . . . report_node_power VDD set_node_gnd DGND set_node_gnd GND set_node_v DVDD 3.3 set_node_v VDD 1.8 nodename file ADRS[0] ADRS[1] . . . . . . CLK DATA[0] . . . . . .

176

View Simulation Result --- nWave

NOVAS nWave
a waveform viewer which support Timemill output waveform format.

Environment setup
unix% source /usr/debussy/CIC/debussy.csh

Starting nWave
unix% nWave &

177

Load Simulation Result --- nWave

178

Select Signals --- nWave

Signals Get Signals ...

179

Check Simulation Result --- nWave

180

Power Analysis Result

The power analysis result is stored in Nanosim simulation log (xxx.log) file
. . . . . . Current information calculated over the intervals: 0.00000e+00 Node: VDD Average current RMS current Current Current Current Current Current . . . . . . peak peak peak peak peak #1 #2 #3 #4 #5 1.00010e+03 ns

: -3.53355e+05 uA : 3.53388e+05 uA : : : : : -4.54061e+05 -4.34973e+05 -3.88048e+05 -3.87280e+05 -3.84302e+05 uA uA uA uA uA at at at at at 6.78400e+02 4.00000e-01 2.59000e+01 1.27500e+02 5.77800e+02
181

ns ns ns ns ns