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    Physical design is the process of transforming a circuit description into a physical representation for manufacturing. Synthesis is the process of converting RTL to a technology specific gate level netlist. This involves translating, optimizing, and technology mapping the RTL code. Floorplanning takes the gate level netlist as input and determines the size and shape of the block, places I/Os, creates cell rows, and adds routing and power structures.

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    Physical design is the process of transforming a circuit description into a physical representation for manufacturing. Synthesis is the process of converting RTL to a technology specific gate level netlist. This involves translating, optimizing, and technology mapping the RTL code. Floorplanning takes the gate level netlist as input and determines the size and shape of the block, places I/Os, creates cell rows, and adds routing and power structures.

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    Physical design is the process of transforming a circuit description into a physical representation for manufacturing. Synthesis is the process of converting RTL to a technology specific gate level netlist. This involves translating, optimizing, and technology mapping the RTL code. Floorplanning takes the gate level netlist as input and determines the size and shape of the block, places I/Os, creates cell rows, and adds routing and power structures.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    84 views3 pages

    Input Files Required

    Uploaded by

    srajece
    Physical design is the process of transforming a circuit description into a physical representation for manufacturing. Synthesis is the process of converting RTL to a technology specific gate level netlist. This involves translating, optimizing, and technology mapping the RTL code. Floorplanning takes the gate level netlist as input and determines the size and shape of the block, places I/Os, creates cell rows, and adds routing and power structures.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 3

     physical design is the process of transforming a circuit description into

    the physical representation for manufacturing

    Sythesis:

    Synthesis is process of converting RTL to technology specific gate level netlist.

    Input files required

     .v- RTL code.


     SDC- Timing constraints.
     UPF- power intent of the design.
     Scan config- Scan related info like scan chain length, scan IO, which flops are to
    be considered in the scan chains.
     LEF/FRAM- abstract view of the cell.
     Floorplan DEF- locations of IO ports and macros.
     .lib-timing info of standard cell & macros

    Steps:
    Elaborate
    All the codes and arithmetic operators are converted into Gtech and DW (Design Ware)
    components.

    These are technology independent libraries.


     Gtech- contains basic logic gates &flops.
     DesignWare- contains complex cells like FIFO, counters.
     There are 3 steps in Synthesis:
     Ø  Translation: RTL code is translated to technolohgy independent representation.
    The converted logic is available in boolean equation form.
     Ø  Optimization: Boolean equation is optimized using SoP or PoS optimization
    methods.
     Ø  Technology mapping:  Technology independent boolean logic equations are
    mapped to technology dependant library logic gates based on design constraints,
    library of available technology gates.  This produces optimized gate level
    representation which is generally represented in Verilog.
    Import constraints and UPF
    timing constraints are imported from the SDC file.
    If the design consists of multiple power domains, then using the UPF power domains,
    isolation cells, level shifters, power switches, retention flops are placed.
    Clock gating:
    To avoid dynamic power

    DFT (Design for Testing) insertion

    DFT circuits are used for testing each and every node in the design
    Scan mode is used to test stuck at faults and manufactured devices for delay.
    Scan mode is done using scan chains
    Outputs of Synthesis
     netlist
     SDC
     UPF
     ScanDEF- information of scan flops and their connectivity in a scan chain

    Checklist
     Check if the RTL and netlist are logically equivalent (LEC/FM).
     Check if SDC and UPF are generated after synthesis and also check their
    completeness.
     Check if there are any assign statements.
     Checks related to timing
     Combinational loops
     Un-clocked registers
     unconstrained IO’s
     IO delay missing
     Un-expandable clocks
     Master slave separation
     multiple clocks
     Checks related to design
     Floating pins
     multi driven inputs
     un-driven inputs
     un-driven outputs
     normal cells in clock path
     pin direction mismatch
     don’t use cells

    Floor Planning
    Inputs required
    1. Gate level netlist
    2. LEF,LIB
    3. Timing constraints (SDC)
    4. Power Intent (UPF / CPF)
    5. FP DEF & Scan DEF
    6. RC Co-efficient files
    FLOORPLAN STEPS
    FLOORPLAN STEPS
    1. Size & shape of the block (Usually provided by FC floorplan)
    2. Voltage area creation (Power domains)
    3. IO placement
    4. Creating standard cell rows
    5. Macro-placement
    6. Adding routing & placement blockages (as required)
    7. Adding power switches (Daisy chain)
    8. Creating Power Mesh
    9. Adding physical cells (Well taps, End Caps etc)

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