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Lecture 3 - Design Flow
Lecture 3 - Design Flow
ELEC 5250/6250
ASIC Design Flow
ASIC Design Flow
Behavioral
Verify
Model
Function
VHDL/Verilog
Front-End
Synthesis
Design
DFT/BIST Gate-Level Verify
& ATPG Netlist Function
Std. Cell
Layouts Floorplan Cadence
Chip/Blocks “SOC Encounter”
Libraries
“Virtuoso”
Process data, Plan Rows,
Design rules Place & Route
Std. Cells
IP Vendors:
Hardware Software
IP cores Purchase drivers core design
Purchase
HW cores SW drivers
SoC
Integrated Design specifics Integrated
Hardware Software
HW/SW partitioning
Fabless Vendors:
Functional Prototype on platforms Software SoC design
Simulation e.g. FPGA Simulation
Foundries:
Volume manufacture Chip fabrication
and ship
Device vendors:
PCB manufacture
and device assembly Final products
ASIC CAD tools available in ECE
Modeling and Simulation
Modelsim, Questa-ADMS, Eldo, ADiT (Mentor Graphics)
Verilog-XL, NC_Verilog, Spectre (Cadence)
Active-HDL (Aldec)
Design Synthesis (digital)
Leonardo Spectrum (Mentor Graphics)
Design Compiler (Synopsys), RTL Compiler (Cadence)
Design for Test and Automatic Test Pattern Generation
Tessent DFT Advisor, Fastscan, SoCScan (Mentor Graphics)
Schematic Capture & Design Integration
Pyxis Design Architect-IC (Mentor Graphics)
Design Framework II (DFII) - Composer (Cadence)
Physical Layout
Pyxis IC Station (Mentor Graphics)
SOC Encounter, Virtuoso (Cadence)
Design Verification
Calibre DRC, LVS, PEX (Mentor Graphics)
Diva, Assura (Cadence)
IC Process Design Kits (PDKs)
Foundry-specific data and models for a
specific IC technology
Used by the design tools
Design components for both front-end
& back-end design
Design entry/modeling
Technology/process data
Layer definitions/parameters (Trans, R,C,…)
Design rules
Standard Cell Library
Synthesis library
Simulation models (Verilog, transistor)
Physical designs (LEF models)
Timing models (fast, typical, slow)
Verification (DRC,LVS,PEX)
DFT/test generation
IP and device generators (RAM, etc.)
Global Foundries BiCMOS8HP 130nm PDK
Global Foundries BiCMOS8HP 130nm PDK
EDIF Netlist
Xilinx/Altera/Other
Map, Place Verify
Back-End Tools
& Route Timing
(Technology-Specific)