JESD204B

Physical Layer (PHY)

Texas Instruments High Speed Data Converter Training
Overview
• What is the Physical Layer (PHY)?
• Speed Grades and Compliance Types
• SERDES Interface
• Solutions for Long/Lossy Channels
• Device Clock, SYSREF and SYNC~ Interfaces
• PCB Layout Recommendations

2
What is the Physical Layer (PHY)?
• The “Physical Layer” refers to the serial data transmitter and receiver of
the JESD204B link
• Point-to-point, unidirectional serial interface
• Definition includes electrical and timing characteristics
• This presentation also considers the other signal interfaces

JESD204B Subclass 1 JESD204B Subclass 1

ADC Interfaces DAC Interfaces

SERDES Logic Logic SERDES

ADC Device Device
DAC
SYNC~ SYNC~
DEV. CLOCK

DEV. CLOCK

DEV. CLOCK

DEV. CLOCK
SYSREF

SYSREF

SYSREF

SYSREF
Clock Device Clock Device

3
What is the Physical Layer (PHY)?
JESD204B Tx PHY

Pulse-Shaping /
Parallel-to-Serial
Emphasis
Converter
Bit-Stream (Optional)
Ctrl/Data (10:1 MUX)
Char-Stream Differential
CML Driver

Channel
Serial-to-Parallel
Converter CDR
Equalizer
(1:10 DEMUX) (Clock/Data
(Optional)
Ctrl/Data Bit-Stream Recovery)
Char-Stream Character Differential
Alignment CML Receiver

JESD204B Rx PHY
4
Speed Grades and Compliance
• The JESD204B standard defines 3 speed grade variants
• Based on OIF Optical standards (OIF-CEI-02.0)
• Variants differ most importantly in data rate, eye mask, and BER

Parameter LV-OIF-Sx15 LV-OIF-6G-SR LV-OIF-11G-SR

Data Rates 312.5Mbps – 3.125Gbps 312.5Mbps - 6.375Gbps 312.5Mbps – 12.5Gbps

Differential Output 500 – 1000 (mV) 400 – 750 (mV) 360 – 770 (mV)
Voltage
Output Rise or Fall Time ≥ 50 (ps) ≥ 30 (ps) ≥ 24 (ps)
(20% - 80% into 100Ω
load)
Bit Error Rate (BER) ≤ 1e-12 ≤ 1e-15 ≤ 1e-15

• Compliance refers to AC or DC coupling and impacts the electrical

characteristics of the driver/receiver
5
PHY Electrical Requirements
Zrdiff / 2
Zddiff / 2

• PHY defines the I/O + Ztt

Ztt +
Vdiff
R_Vdiff
--
electrical structure of the +
T_Vcm
--
+
Vtt
- Zddiff / 2 Zrdiff / 2 -
driver and receiver Transmitter Model Recevier Model

Common Mode
Voltage Range

Signal Swing Range

Impedance and
Return Losses

6
PHY Eye/Timing Requirements
• Total jitter is composed of both random and deterministic components
• JESD204B standard identifies requirements for different types of jitter

Data-Correlated Data-Uncorrelated

Total Jitter
(TJ) Unbounded PDF
Bounded PDF

Deterministic Random Jitter

Jitter (DJ) (RJ)
Random Jitter

Data Dependent Periodic Jitter

Jitter (DDJ) (PJ)

Inter-Symbol Duty-Cycle
Interference (ISI) Distortion (DCD)
Deterministic Jitter
* “Analyzing Digital Jitter and its Components,” (Agilent Technologies)
7
PHY Eye/Timing Requirements
• Jitter Units
– ‘peak-to-peak Unit Interval’ [p-p UI]:
• 1 UI is equivalent to 1 bit period at the given transfer rate
– ‘peak-to-peak seconds’ [p-p s]
– ‘peak-to-peak Root-Mean-Square seconds’ [p-p rms]
• Used to describe unbounded random jitter values
• Must specify a BER to indicate probability density function (PDF) bounds
for conversion to [p-p UI] (i.e. 1e-15)

• Combining Jitter Components

– Random Jitter adds as sum of squares (un-correlated)
– Deterministic Jitter sums directly (correlated)
– Total Jitter is a direct sum of Random and Deterministic Components
• TJ = RJ + DJ

8
PHY Eye/Timing Requirements
• TX and RX Eye Masks with amplitude, rise-time, and jitter requirements
• RX must recover signal after channel loss and ISI

Transmit Eye Mask Receive Eye Mask

Deterministic Jitter (DJ)

Random jitter plus

Deterministic Jitter

Bit-Error Rate
 Solutions for Long/Lossy Channels
• Channel dielectric loss degrades the signal integrity of the signal
• Loss reduces the vertical/horizontal Eye opening and edge rate due to
attenuation and inter-symbol interference (ISI)
• Loss Profile mask is specified in the JESD204B standard

JESD204B Acceptable Loss Profile

0
Compliant Example Compliant
2 Insertion Loss Channel Loss
(~8" FR-4 Channel @
SDD21 (dB)

4 6.375 Gb/s)

6 Example Non-Compliant
Channel Loss
8 Non-Compliant (~20" FR-4 Channel @
Insertion Loss 6.375 Gb/s)
10 20in. FR4 channel @ 7.4Gb/s
¼ Baud ½ Baud ¾ Baud
Rate Rate Rate
Frequency (GHz)
10
Solutions for Long/Lossy Channels
• Equalization can be used to pulse-shape
5”
at TX or pulse-correct RX
10”
• High-pass profile of equalization
counteracts low-pass loss profile of 15”
channel Loss profile for
microstrip trace 20”
• Pre-emphasis lengths over FR4

– AMPLIFY HIGH frequencies to achieve

high-pass profile
• De-emphasis
– ATTENUATE LOW frequencies to achieve
high-pass profile
– May require broadband amplification to
meet eye requirements at large de-
emphasis
High-pass emphasis profile (blue)
matches the inverse of the
channel loss profile (pink) 11
Solutions for Long/Lossy Channels
• ADC16DX370 De-Emphasis Waveform @ 5 Gb/s at TX output
De-emphasis disabled Maximum De-emphasis

• Waveform @ 7.4 Gb/s at output of 20-inch FR4 channel

De-emphasis disabled De-emphasis Optimized

12
Solutions for Long/Lossy Channels
• ADC12J4000 Pre-Emphasis Waveform @ 7 Gb/s over 7 inches FR4

Pre-emphasis disabled Pre-emphasis Optimized

13
Device Clock and SYSREF Interfaces
• No strict definition for electrical characteristics
– LVDS, LVPECL are common solutions
• Device clock frequency may be equal to sampling rate or multiple
• Noise on device clock typically sets jitter performance of converter
• Attention required for DC-coupled common-mode compatibility of TX/RX
• Subclass 1
– SYSREF must meet setup/hold relative to device clock
– Electrical characteristics recommended to be consistent between device
clock and SYSREF

• Subclass 2: SYSREF not required

14
SYSREF Interface (Signal Types)
• Periodic Periodic
– SYSREF always ON with periodic edges
– Risk of interferer spurs near IF due to SYSREF
Gapped-Periodic
• Gapped-Periodic
– Send periodic edges for a brief pulse of time
– No spurs One-Shot

• One-Shot
– Single SYSREF pulse and then leave in logic-low state
– No spurs

• SYSREF pulse period equal to integer multiple of multi-frame period

• Disabling and gating the SYSREF signal may be employed

TI Information – NDA Required

TSW1400 Captured Data, SYSREF enabled
• Periodic SYSREF has sub-harmonic relationship to ADC sampling
clock

TI Information – NDA Required

TSW1400 Captured Data, SYSREF disabled

TI Information – NDA Required

SYNC~ Interface
• No strict definition for electrical characteristics
– LVDS, LVPECL, CMOS are common solutions
• DC coupling mandatory
• Subclass 1
– SYNC~ does not have strict timing
• Subclass 2
– SYNC~ must meet setup/hold relative to device clock
– Timing requirements very difficult to meet for device clock rates > 250MHz

18
Differential Interfaces AC-Coupled Serial Lane Interface
0.01uF

(Example circuits) 100-diff 100

PCB Channel

• Serial Lane Interface

Serial Lane Serial Lane
Transmitter Receiver

– AC or DC Coupling DC-Coupled Serial Lane Interface

– 100 differential channel 100-diff 100

– Routing signal integrity is MOST

PCB Channel
critical of all JESD204B interface Serial Lane
Transmitter
Serial Lane
Receiver

signals
AC-Coupled Device Clock / SYSREF Interface

Receiver
0.1uF

• Device Clock / SYSREF Interface 100-diff

– AC or DC Coupling Transmitter
PCB Channel
50 50

VIS = 0.5V

– AC coupling SYSREF requires

10k

DC-Coupled Device Clock / SYSREF Interface

provision for DC balancing at receiver
– 100 differential channel VCMO = 1.2V
R1
R2 Receiver

– Match device clock and SYSREF 100-diff

50 50
interface to meet setup/hold Transmitter
PCB Channel
VIS = 0.5V
10k

requirement 4*R1*R2 + 200*R1 = 1002

R2 / (R1+R2) = 0.55 / VCMO
IDC (Each Side)= VCMO / (R1+R2)
VCMO = 1.2V: R1 = 32.3, R2 = 27.3, IDC = 20.1mA 19
Differential Interfaces (Example Circuits)
• SYNC~ Interface SYNC~
Receiver

– DC Coupling only 100-diff

– 100 differential channel SYNC~

Transmitter
PCB Channel

– Routing VERY critical for subclass 2

– Routing is LEAST critical for subclass 1

20
Generating Device Clocks and SYSREF
• Example: LMK04828
– Subclass 1 capable
– 7 Device CLK / SYSREF pairs
– Low Jitter clock source
– SYSREF Disable feature
– Delay options
– LVPECL, LVDS, HSDS
outputs
– Supports Clock Distribution
mode using external clock
source

21
PCB Recommendations (Differential Pairs)
• Route differential signal as tightly coupled W H1
T
microstrip or stripline lanes (S<=W) S H2

• 100  differential impedance Differential Stripline

T S W
• Avoid 90 turns
– Reduces +/- trace mismatch H
– Reduces impedance discontinuity Differential Microstrip

• Recommend 0201 series components

(AC coupling) to minimize impedance
discontinuity of pads
• Routing on inner layers (stripline) has
0201 AC coupling capacitors
advantages:
– Better impedance control
– No speed issues with Nickel plating
– Less interference/emissions
22

Via stitching
PCB Recommendations (Trace Matching)
• Device Clock, SYSREF, SYNC~, and serial
lanes must be between matched +/- traces

• Device Clock and SYSREF pairs must be

matched to each other
Matched Dev. Clock and SYSREF pairs

• Serial lanes need NOT match to each other

R > 3xW
• Use wiggles to match the lengths of multiple
differential pairs.
– Keep radius of the wiggle > 3 times trace width
– Use equal number of turns in each direction

• Use small jog-outs to correct +/- trace mismatch

Jog-out matches +/- traces
23
PCB Recommendations (Vias)
• Vias in the signal path create impedance
discontinuities that result in signal
reflections/degradation
• Simulate signal path with vias to determine signal Waveform “blip” due to via
integrity before manufacturing in the signal path

• Avoid changing layers where possible, but use

adjacent grounding vias where layer change is
necessary to provide return current path
• Via stitch along sensitive differential signal paths
• Use blind vias or back-drilling to eliminate via stubs Adjacent GND vias

24

Via stitching
PCB Recommendations (Material/Stack-Up)
• Serial lane speeds > 3 Gb/s at length > 8”
– Recommend low-loss, good impedance
consistency dielectric material
– Rogers-4350, Megtron-6.
– Use premium dielectric only where needed

• Serial lane speeds < 3 Gb/s at length < 8”

– Recommend low cost materials
– FR4, 370HR
Material QTY $/board
• Board shop reports that 370HR can be Megtron 6 50 $660
used up to 10 GHz with very short traces 370HR 50 $350
(1-3 inches)

25
PCB Recommendations (Reference Planes)
• Use a ground planes as the signal reference on
adjacent layers
• Avoid splits in the reference plane underneath signals
when possible
– Return current for high-speed signals follows trace on the
reference plane
– Splits require the return current to travel around,
increasing loop inductance, coupling, and interference
• When reference plane splits under differential signals
are necessary:
– Minimize split width
– Ensure tight coupling of differential pair
– Jump split at 90
– Good GND via stitching along channel
– Avoid jumping split in vicinity of other noisy signals
26
PCB Recommendations (Reference Planes)
• Keep analog signals separate from digital signals
– Single ground plane is recommended
1. Split ground plane at DAC/ADC into analog and digital planes
2. Route the signal traces in their respective domains
3. Recombine the two ground planes into one after routing

27
PHY Debug (Test Patterns)
• Test patterns can verify the PHY layer signal integrity
Pattern Use Test
PRBS7 /15 /23 /31 Long pattern performance
Deterministic Jitter (ISI)
01010101010 (D21.5) Random Noise

• PRBS and D21.5 patterns available on all TI JESD204B devices

• Most FPGA giga-bit transceivers have built-in PRBS
generators/detectors

28
Handling Link Errors
Error Type Effect on Serial Link Error Link Response
Stream Detection
Jitter/ISI Single bit error 8b/10b decoding - Output previous good frame
Single bit error fails - SYNC asserted for 2 frames
(not-in-table error)

Jitter/ISI Multi-bit error, - Not-in-table error - Depends on specific error

possibly across many - Disparity error - SYNC asserted >= 2 frames
Multi-bit error frames - Control Char error - Link re-initialization likely*
- Frame alignment
error

ADC Core None. No error detected No change

Erroneous sample is
Sample Error encoded, transmitted,
received as usual.

• The list of errors which require link re-initialization is implementation

specific
29
TI Devices SERDES Summary

Device Max Max Bit Rate Min #Lane/Ch. Emphasis /

Conversion (at full MSPS) Equalization?
Rate
ADC16DX370 370 MSPS 7.4 Gb/s 1 TX De-emphasis
ADS42JB69 250 MSPS 3.125 Gb/s 2 Not needed
ADS42JB46 160 MSPS 3.125 Gb/s 1 Not needed
ADC3K Family 160 MSPS 3.125 Gb/s 1 Not needed
(Preview)
ADC12J4000 4000 MSPS 8 Gb/s * TX Pre-Emphasis
ADC12J2700 2700 MSPS 10 Gb/s * TX Pre-Emphasis
DAC38J84 2500 MSPS 12.5 Gb/s 0.25 RX Adaptive
Equalizer
*Decimation Factor Dependent

30
Summary
• The Physical Layer refers to the electrical and timing characteristics of
the TX and RX and their ability to send and recover data

• Equalization and (pre-/de-) emphasis can be used to enhance signal

integrity of the link for longer lengths and higher bit rates

• Device Clock, SYSREF, and SYNCb interfaces and not strictly defined
in the standard, but common guidelines are provided

• Very high speed layout techniques for the serial lanes are critical to
ensure impedance matching and minimization of signal reflections

• Test patterns such as D21.5 and PRBS usually patterns are available
for physical layer debug

TI Information – NDA Required

 More Educational Resources
www.ti.com/lsds/ti/data-converters/high-speed-adc-greater-10msps-jesd204b.page
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