CD4073BMS, CD4081BMS CD4082BMS: Pinout Features
CD4073BMS, CD4081BMS CD4082BMS: Pinout Features
January 1993
Features
High-Voltage Types (20V Rating) CD4073BMS Triple 3-Input AND Gate CD4081BMS Quad 2-Input AND Gate CD4082BMS Dual 4-Input AND Gate Medium Speed Operation: - tPLH, tPHL = 60ns (typ) at VDD = 10V 100% Tested for Quiescent Current at 20V Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V Standardized Symmetrical Output Characteristics 5V, 10V and 15V Parametric Ratings
A 1 B 2 D 3 E 4 F 5 K=DEF 6 VSS 7
14 VDD 13 G 12 H 11 I 10 L = G H I 9 J=ABC 8 C
A 1
14 VDD 13 H 12 G 11 M = G H 10 L = E F 9 F 8 E
Meets All Requirements of JEDEC Tentative Standard No. 13B, Standard Specications for Description of B Series CMOS Devices
B 2 J=AB 3 K=CD 4
Description
CD4073BMS, CD4081BMS and CD4082BMS AND gates provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates. The CD4073BMS, CD4081BMS and CD4082BMS are supplied in these 14 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD4073B, CD4081B *H4Q *H1B *H3W CD4082B H4H
C 5 D 6 VSS 7
J=ABCD 1 D 2 C 3 B 4 A 5 NC 6 VSS 7
14 VDD 13 K = E F G H 12 H 11 G 10 F 9 E 8 NC
NC = NO CONNECTION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
File Number
3324
7-433
5 F 11 I 12 H 13 G 7 VSS
10
CD4073BMS
VDD 14 A B C D E F G H 1 2 5 6 8 9 12 13 3 4
J K L M
10 11
7 VSS
CD4081BMS
VDD 14 D C B A 2 3 4 5
9 E 10 F 11 G 12 H 7 VSS
13
CD4082BMS
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Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1 2 3 1 2 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, LIMITS TEMPERATURE +25oC +125 C -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 1.5 4 V V V V -55oC
o
SYMBOL IDD
MAX .5 50 .5 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8
UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs.
7-435
Transition Time
NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125 C VDD = 10V, VIN = VDD or GND 1, 2 -55 C, +25 C +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC
oC o o o
MAX .25 7.5 .5 15 .5 30 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -2.6 -2.4 -4.2 3 120 90
UNITS A A A A A A mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V ns ns
+125 Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2
+25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC
IOL10
1, 2
IOL15
1, 2
IOH5A
1, 2
IOH5B
1, 2
IOH10
1, 2
IOH15
1, 2
VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V
1, 2 1, 2 1, 2, 3 1, 2, 3
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MIN -
UNITS ns ns pF
1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25 C +25oC +25oC +25oC +25oC +25oC
o
MAX 2.5 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit
UNITS A V V V V V
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - SSI Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 0.1A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
7-437
TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V -0.5V 50kHz 25kHz
PART NUMBER CD4073BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 6, 9, 10 6, 9, 10 6, 9, 10 1 - 5, 7, 8, 11 - 13 7 7 7 14 1 - 5, 8, 11 - 14 14 1 - 5, 8, 11 - 14 6, 9, 10 1, 5, 8, 11 - 13
PART NUMBER CD4081BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 3, 4, 10, 11 3, 4, 10, 11 3, 4, 10, 11 1, 2, 5 - 9, 12, 13 7 7 7 14 1, 2, 5, 6, 8, 9, 12 - 14 14 1, 2, 5, 6, 8, 9, 12 - 14 3, 4, 10, 11 1, 2, 5, 6, 8, 9, 12, 13
PART NUMBER CD4082BMS Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V 1, 6, 8, 13 1, 6, 8, 13 6, 8 1, 6, 8, 13 2 - 5, 7, 9 - 12 7 7 7 14 2 - 5, 9 - 12, 14 14 2 - 5, 9 - 12, 14 1, 3 2 - 5, 9 - 12
7-438
8 (5, 11)
p n
1 (4, 12)
p n
p p p
2 (3, 13)
VDD n
9 (6, 10)
n VSS
*
2 (5, 9, 12) n p
*
1 (6, 8, 13) n n
n n
VSS
7-439
*
3 (11)
*
2 (12) n n
n n
*
4 (10)
*
5 (9) n n
VSS
10V 10
5V
5V
10
15
20
25
10
20
30
40
50
60
70
80
90
100
7-440
(Continued)
30 25 20 15 10 5
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
0 -5 -10 -15
-10V
-20 -25
-10V
-10
-15V
-30
-15V
-15
AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V 10V 10V 5V
104
8 6 4
150
103
2 8 6 4 2
100 10V 50 5V
102
8 6 4 2
CL = 50pF CL = 15pF
2 4 68 2 4 6 8 2 4 6 8 2 4 6 8
0 0
10 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 1 103 10 102 INPUT FREQUENCY (fI) (kHz)
7-441
CD4081BMS
CD4082BMS
CD4073BMS Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION: PASSIVATION:
AL.
BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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