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DS16F95, DS36F95 EIA-485/EIA-422A Differential Bus Transceiver
DS16F95, DS36F95 EIA-485/EIA-422A Differential Bus Transceiver
June 1998
Features
n n n n n n n n n n n n n n n Meets EIA-485 and EIA-422A Meets SCSI-1 (5 MHZ) specifications Designed for multipoint transmission Wide positive and negative input/output bus voltage ranges Thermal shutdown protection Driver positive and negative current-limiting High impedance receiver input Receiver input hysteresis of 50 mV typical Operates from single 5.0V supply Reduced power consumption Pin compatible with DS3695 and SN75176A Military temperature range available Qualified for MIL-STD 883C Standard Military Drawings (SMD) available Available in DIP (J), SOIC (M), LCC (E), and Flatpak (W) packages
Logic Diagram
DS009629-20
Receiver
Differential Inputs AB VID 0.2V VID 0.2V X
H = High Level L = Low Level X = Immaterial Z = High Impedance (Off)
Enable RE L L H
Output RO H L Z
DS009629
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Units V V
+12
12
V V
mA A mA mA C C
Figure 1
0.2 0.4
0.2
1.0 0.8 20 50 250 150 150 250
V mA A A
IO
mA
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(Continued)
Over recommended supply voltage and operating temperature ranges, unless otherwise specified Conditions DE = 2V, RE = 0.8V Outputs Enabled DE = 0.8V, RE = 2V Outputs Disabled 25 Min Typ Max 28 mA Units
Figure 2
VOL IOZ II Output Voltage LOW High Impedance State Output Line Input Current (Note 9) VID = 200 mV,
Figure 2
VO = 0.4V to 2.4V Other Input = 0V
20
1.0 0.8 20 50 22 85
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(Continued)
Over recommended supply voltage and operating temperature ranges, unless otherwise specified Conditions DE = 2V, RE = 0.8V Outputs Enabled DE = 0.8V, RE = 2V Outputs Disabled 25 All Inputs Open Min Typ Max 28 mA Units
Figure 7
Note 2: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of Electrical Characteristics provide conditions for actual device operation. Note 3: Unless otherwise specified min/max limits apply across the 55C to +125C temperature range for the DS16F95 and across the 0C to +70C range for the DS36F95. All typicals are given for VCC = 5V and TA = 25C. Note 4: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 5: |VOD| and |VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low level. Note 6: In TIA/EIA-422A and TIA/EIA-485 Standards, VOC, which is the average of the two output voltages with respect to ground, is called output offset voltage, VOS. Note 7: The algebraic convention, where the less positive (more negative) limit is designated minimum, is used in this data sheet for common mode input voltage and threshold voltage levels only. Note 8: Hysteresis is the difference between the positive-going input threshold voltage, VT+, and the negative-going input threshold voltage, VT. Note 9: Refer to TIA/EIA-485 Standard for exact conditions. Note 10: Only one output at a time should be shorted.
Order Number:
DS16F95J, NS Package Number J08A DS36F95J, NS Package Number J08A DS36F95M, NS Package Number M08A
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7.0
+12
12
V V
60 400 60 16 55 +125
mA A mA mA C
Note 11: Above TA = 25C, derate E package, J package 8.7 mW/C, W package 125 mW/C.
0.2
0.2
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20
1.0
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Figure 7
Ordering Number:
DS16F95J/883, NS Package Number J08A DS16F95E/883, NS Package Number E20A DS16F95W/883, NS Package Number W10A
SMD Number:
DS16F95J/883 5962-8961501PA DS16F95W-SMD 5962-8961501HA DS16F95E/883 5962-89615012A
DS009629-2
DS009629-3
DS009629-4 DS009629-5
tSKEW = |tPLHDtPHLD|
FIGURE 3. Driver Differential Output Delay and Transition Times (Notes 12, 14)
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(Continued)
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FIGURE 5. Driver Enable and Disable Times (tZH, tHZ) (Notes 12, 13, 14)
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FIGURE 6. Driver Enable and Disable Times (tZL, tLZ, tLZL) (Notes 12, 13, 14)
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DS009629-13
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(Continued)
DS009629-14
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FIGURE 8. Receiver Enable and Disable Times (Notes 12, 13, 15)
Note 12: The input pulse is supplied by a generator having the following characteristics: PRR = 1.0 MHz, 50% duty cycle, tr 6.0 ns, tf 6.0 ns, ZO = 50. Note 13: CL includes probe and stray capacitance. Note 14: DS16F95/DS36F95 Driver enable is Active-High. Note 15: All diodes are 1N916 or equivalent. Note 16: Testing at 20 pF assures conformance to 5 pF specification.
Typical Application
DS009629-19
The line should be terminated at both ends in its characteristic impedance, typically 120. Stub lengths off the main line should be kept as short as possible.
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Connection Diagrams
8-Lead Dual-In-Line Package or Small Outline Molded Package 20-Lead Ceramic Leadless Chip Carrier
DS009629-1
Order Number DS16F95, DS16F95J/883, DS36F95J, DS36F95M See NS Package Number J08A, or M08A
DS009629-21
Order Number DS16F95E/883 See NS Package Number E20A 10-Lead Ceramic Flatpak
DS009629-22
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10
11
Physical Dimensions
20-Lead Ceramic Leadless Chip Carrier (E) Order Number DS16F95E/883 NS Package Number E20A
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12
Physical Dimensions
8 Narrow Lead Ceramic Dual-In-Line Package (J) Order Number DS16F95J, DS16F95J/883 or DS36F95J NS Package Number J08A
8-Lead (0.150" Wide) Molded Small Outline Package, JEDEC Order Number DS36F95M NS Package Number M08A
13
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Physical Dimensions
10-Lead Ceramic Flatpak (W) Order Number DS16F95W/883 NS Package Number W10A
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