Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd Logo
Upload

Welcome to Scribd!

  • 204 views

    ASIC Layout - 2 Standard Cell Flow PDF

    Uploaded by

    EsakkiPonniah
    The document describes the standard cell ASIC design flow using Mentor Graphics tools. It involves generating a component-level netlist from Verilog, creating standard cell layouts in the provided libraries, floorplanning and placing cells using IC Station, routing the design, performing design rule checking for errors, and generating mask data for fabrication. Key steps include converting the Verilog to EDDM format, floorplanning the design, placing standard cells and I/O ports, routing connections between cells, and using Calibre for layout vs schematic checking and design rule checking.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    ASIC Layout - 2 Standard Cell Flow PDF

    Uploaded by

    EsakkiPonniah
    204 views28 pages
    The document describes the standard cell ASIC design flow using Mentor Graphics tools. It involves generating a component-level netlist from Verilog, creating standard cell layouts in the provided libraries, floorplanning and placing cells using IC Station, routing the design, performing design rule checking for errors, and generating mask data for fabrication. Key steps include converting the Verilog to EDDM format, floorplanning the design, placing standard cells and I/O ports, routing connections between cells, and using Calibre for layout vs schematic checking and design rule checking.

    Original Title

    ASIC Layout_2 Standard Cell Flow.pdf

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The document describes the standard cell ASIC design flow using Mentor Graphics tools. It involves generating a component-level netlist from Verilog, creating standard cell layouts in the provided libraries, floorplanning and placing cells using IC Station, routing the design, performing design rule checking for errors, and generating mask data for fabrication. Key steps include converting the Verilog to EDDM format, floorplanning the design, placing standard cells and I/O ports, routing connections between cells, and using Calibre for layout vs schematic checking and design rule checking.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    204 views28 pages

    ASIC Layout - 2 Standard Cell Flow PDF

    Uploaded by

    EsakkiPonniah
    The document describes the standard cell ASIC design flow using Mentor Graphics tools. It involves generating a component-level netlist from Verilog, creating standard cell layouts in the provided libraries, floorplanning and placing cells using IC Station, routing the design, performing design rule checking for errors, and generating mask data for fabrication. Key steps include converting the Verilog to EDDM format, floorplanning the design, placing standard cells and I/O ports, routing connections between cells, and using Calibre for layout vs schematic checking and design rule checking.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 28
    At a glance
    Powered by AI
    The key takeaways are the ASIC design flow involves modeling and simulation, synthesis, physical design including floorplanning, placement and routing of standard cells, and design verification using DRC, LVS and extraction.

    The automated ASIC design flow involves importing a netlist into design tools, floorplanning, placement of standard cells and I/O ports, routing interconnects, DRC checks, and preparing the layout for fabrication.

    The automated layout design flow in IC Station involves importing a netlist, floorplanning, placement of standard cells and I/O ports, routing interconnects, DRC checks to fix any errors, and adding port text before finalizing the layout.

    ASIC Physical Design

    Standard-Cell Design Flow

    Course Web Page Reference: Designing


    Standard Cells ASICs with the ASIC Design Kit
    (ADK) and Mentor Graphics Tools

    ASIC Physical Design (Standard Cell)

    (can also do full custom layout)

    Component-Level Netlist (EDDM format)

    Std. Cell
    Layouts

    Floorplan
    Chip/Block

    Mentor Graphics
    IC Station

    Libraries

    (adk_ic)

    ICblocks
    Process Data
    Design Rules

    Generate
    Mask Data

    Place & Route


    Std. Cells

    Design Rule
    Check
    Calibre

    IC Mask Data

    Backannotate
    Schematic
    Calibre

    Layout vs.
    Schematic
    Check
    Calibre

    Mach TA/Eldo Simulation Model

    Mentor Graphics Analog/Mixed-Signal


    IC Design Flow

    Mentor Graphics Pyxis Tool Set

    ASIC CAD tools available in ECE


    Modeling and Simulation
    Questa ADMS = Questa+Modelsim+Eldo+ADiT (Mentor Graphics)
    Verilog-XL, NC_Verilog, Spectre (Cadence)
    Design Synthesis (digital)
    Leonardo Spectrum (Mentor Graphics)
    Design Compiler (Synopsys), RTL Compiler (Cadence)
    Design for Test and Automatic Test Pattern Generation
    Tessent DFT Advisor, Fastscan, SoCScan (Mentor Graphics)
    Schematic Capture & Design Integration
    Design Architect-IC (Mentor Graphics)
    Design Framework II (DFII) - Composer (Cadence)
    Physical Layout
    IC Station (Mentor Graphics)
    SOC Encounter, Virtuoso (Cadence)
    Design Verification
    Calibre DRC, LVS, PEX (Mentor Graphics)
    Diva, Assura (Cadence)

    Mentor Graphics ASIC Design Kit (ADK)


    We also have ADKs for Cadence tools for several technologies

    Technology files & standard cell libraries


    AMI: ami12, ami05 (1.2, 0.5 m)
    TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25**, 0.18 m) **also have VT Cadence lib
    Current MOSIS Instructional: IBM 180nm CMOS (7RF), ON Semi 0.5um CMOS
    Current MOSIS Unfunded Research: IBM 130nm CMOS (8RF), 130nm SiGE BiCMOS(8HP)
    IC flow & DFT tool support files:
    Simulation models

    VHDL/Verilog/Mixed-Signal models (Modelsim SE/Questa ADMS)


    Analog (SPICE) models (Eldo, ADiT)
    *Post-layout timing (Mach TA) * obsolete: Mach TA replaced by ADiT
    *Digital schematic (Quicksim II, Quicksim Pro) * obsolete: HDL or Eldo now used

    Standard cell synthesis libraries (LeonardoSpectrum)


    Design for test & ATPG libraries (DFT Advisor, Fastscan)
    Schematic capture (Design Architect-IC)
    IC physical design (standard cell & custom)

    Standard cell models, symbols, layouts (IC Station)


    Design rule check, layout vs schematic, parameter extraction (Calibre)

    Automated ASIC Design Flow


    Source: CMOS IC Layout, Dan Clein

    Std Cell ASIC

    Full Custom IC

    IC Station full-custom design flow

    Cell-Based IC

    I/O pads

    Cell-Based Block

    Basic standard
    Cell layout

    Source: Weste CMOS VLSI Design

    Automated Layout Design Flow in


    IC Station
    Import netlist into IC Station

    Floorplan block or chip


    Place std cells
    Place I/O ports

    Route cell interconnects

    Remove space

    DRC, LVS, PEX fix errors

    Preparation for Layout


    Use Design Architect-IC to convert Verilog netlist to Mentor
    Graphics EDDM netlist format

    1.

    Invoke Design Architect-IC (adk_daic)


    On menu bar, select File > ImportVerilog

    Netlist file: count4.v (theVerilog netlist)


    Output directory: count4 (for the EDDM netlist)
    Mapping file $ADK/technology/adk_map.vmp

    Open the generated schematic for viewing

    2.

    Click Schematic in DA-IC palette


    Select schematic in directory named above (see next slide)
    Click Update LVS in the schematic palette to create a netlist to be used later by
    Calibre

    Create design viewpoints for ICstation tools

    3.

    adk_dve count4 t tsmc035

    (V.Ps: layout, lvs, sdl, tsmc035)

    Can also create gate/transistor schematics directly in DA-IC using


    components from the ADK library

    DA-IC generated schematic

    Create a std-cell based logic block in


    IC Station (for icflow 2008 version)
    Invoke: adk_ic
    In IC Station palette, select: Create Cell
    Cell name: count4
    Attach library: $ADK/technology/ic/process/tsmc035
    Process: $ADK/technology/ic/process/tsmc035
    Rules file: $ADK/technology/ic/process/tsmc035.rules
    Angle mode: 45
    Cell type: block
    Select With connectivity
    EDDM schematic viewpoint: count4/layout
    Logic loading options: flat

    Create Cell dialog box

    Floorplanning (Text chap. 15, 16)


    Floorplanning: arrange major blocks prior to detailed layout

    to minimize chip area

    input is a netlist of circuit blocks (hierarchical)


    estimate layout areas, shapes, etc.
    do initial placement of blocks (keep highly-connected blocks

    close)
    decide location of I/O pads, power, clock

    Autofloorplan options
    Aspect ratio defines block shape
    Max dimensions
    #Rows specify or automatic
    Edge gaps between core & external rows (for pins, etc.)
    Route area ratio vertical space between rows
    Internal row layout can flip bottom

    Auto-floorplan the block with ICplan


    place & route > autofp

    cell
    rows

    cell boundary

    Auto-place the std cells


    Autoplc > StdCel

    overflows

    Auto-place ports (signal connections on cell boundaries)


    Autoplc > Ports

    ports

    Options include ability to position ports on top/bottom/sides of the block

    AutoRoute all nets (hand-route unrouted overflows)


    Options: Expert Options select Channel over cell routing
    OCR Options set Operation mode type to Center weighted

    Find and route any overflows


    Overflows are yellow lines between circuit nodes, showing where wires
    need to be created.
    Select all overflows by typing Check overflows (a command window will
    appear as you begin typing) and then in the form that appears, check All
    and OK

    In the Place and Route palette, select Autoroute > Overflow


    If you see the message An object of type Overflow must be selected,
    then there are no overflows all nets were routed
    Otherwise, the overflows should be routed
    In extreme cases, a net cannot be autorouted, and must be routed
    manually

    Add port text: Add > Port Text


    Copies I/O pin names from schematic to ports
    (used by Calibre in LVS and PEX operations)

    16 by 8 divider circuit

    Layout design rule check (DRC)


    Technology-specific design rules specify minimum sizes,

    spacing, etc. of features to ensure reliable fabrication


    Design rules file specified at startup

    Ex. tsmc035.rules
    From main palette, select ICrules
    Click Check and then OK in prompt box

    (can optionally select a specific area to check)


    Rules checked in numeric order

    Common errors detected by DRC


    To fix, click on First in palette to highlight first error
    Error is highlighted in the layout
    Click View to zoom in to the error (see next)
    Example: DRC9_2: Metal2 spacing = 3L
    Fix by drawing a rectangle of metal2 to fill in the gap between
    contacts that should be connected
    Click Next to go to next error, until all are fixed

    NOTE: The layout must be free of DRC errors if MOSIS is


    to fabricate the chip; they will run their own DRC.

    Sample error: DRC9_2 metal2 spacing = 3L

    Draw
    rectangle
    of metal2
    to fill gap

    It also called contact-to-contact metal 2 spacing DRC9_2 error

    You might also like