An Introduction to Synopsys

Design Automation

Jeremy Lee
jslee@engr.uconn.edu
November 7, 2007
Introduction
 Why the need CAD tools?
 Time to market decreasing (< a year)
 Designs are becoming more complex
(System-on-a-chip)

 Synopsys is one of many EDA

vendors vying for designer mind-
share
Introduction (cont.)
 Why do we (in academia) need CAD
tools?
 Keep our research relevant to
industry
 Know what needs improving
(academia on cutting edge)
What will be covered?
 Overview of tools
 What’s available?
 What do the tools do?
 Example Flow

 Will not be a step-by-step how-to.

Getting Synopsys Started at UConn
 Synopsys Linux binaries are available on the
ECS fileserver:
/apps/ecs-apps/software/synopsys
 Releases: Y-2006, Z-2007
 bashrc and cshrc files located at
/apps/ecs-apps/software/synopsys/etc
 Synopsys directory can be mounted directly
using NFS
files:/ApplicationDirectories/nfs/ecs-
apps/software/synopsys
 Tools are location dependent
 Must be in same directory structure as on server
 Gui or console modes
Synopsys Galaxy Platform at
UConn (Y-2006)

Sign-off /
Validation /
Design Automation Verification Design for Test

PrimeTime SI/PX/VX
PrimePower
Design Compiler
Star-RCXT DFT Compiler
JupiterXT
Formality DFT MAX
Astro
VCS TetraMAX
Physical Compiler
Nanosim
HSpice
Design Automation
 Design Compiler
 RTL to gate-level synthesis
 Physical Compiler
 Layout-aware RTL to gate-level synthesis
 JupiterXT
 Floorplanning tool
 Astro
 Placement and routing
Design Compiler (DC)
 Synthesizes gate level netlists from RTL-
level
 Optimizes netlists
 Removes unused or redundant logic
 Tie-off nets that are constant
 Requires standard cell library timing
characterization
 Attempts to meet timing and area
constraints (SDC File)
Libraries
 Supposed to be provided by fab
 Gates in standard cell library
 Operating condition corners
 Gate delays
 Wire load models
 Compensates delay for fan-out
SDC File
 Synopsys Design Constraints (SDC)
 Set up clock period
 Specifies timing and area
requirements that are to be met
during mapping and optimization
SDC Constraints
Input Delay

Output Delay

Driving Cell

Load
DC Flow
Read
Libraries
Libraries

Netlist
Read
Netlist
Map to
Target Library
and Optimize
Map to
Link Library
(if gate-level)
Write-out
Optimized
Netlist
SDC
Apply
Cons. Constraints
JupiterXT
 Floorplanning
 Power/Ground Network Planning
 Pin/Power pad placement
 Blockages
 Memory placement
 Performed through GUI or command
line
Astro
 Placement and routing tool
 Requires physical information of
standard cell library (provided by fab)
 Graphic Data System (GDSII)
 Library Exchange Format (LEF)
 Physical design in multiple formats
 GSDII
 Design Exchange Format (DEF)
Astro Flow
Open
Libraries
Libraries

Routing
Netlist Import
Netlist and
Constraints

Physical
SDC Design
Read/Setup
Cons.
Floorplan

Run
Placement
Synopsys Galaxy Platform at
UConn (Y-2006)

Sign-off /
Validation /
Design Automation Verification Design for Test

PrimeTime SI/PX/VX
PrimePower
Design Compiler
Star-RCXT DFT Compiler
JupiterXT
Formality DFT MAX
Astro
VCS TetraMAX
Physical Compiler
Nanosim
HSpice
Sign-off/Validation/Verification
 Formality
 Verify netlist
 PrimeTime SI/PX/VX
 Timing validation (signal-integrity,
power-aware, variation-aware)
 PrimePower
 Power validation
Sign-off/Validation/Verification
(cont.)
 Star-RCXT
 Extraction tool
 VCS
 HDL simulator
 NanoSim
 HDL simulator w/ parasitics
 HSpice
 Spice simulator
PrimeTime SI/PX/VX (PT-SI/PX/VX)
 Calculates and reports path delays
 Verify operating frequency after logic
synthesis
 Can be back-annotated with
extracted parasitics for post-layout
verification
PT-SI/PX/VX Flow
Parasitics
*New*
Read
Libraries
Libraries Process
Back-annotate Variation
design
Netlist
Read
Netlist
Report
Timing results
Map to
Link Library
(if gate-level)
Meet No
spec? ECO
SDC
Apply
Yes
Cons. Constraints
Next
phase
Putting the Pieces Together
RTL SDC
Logic Physical
Libraries Netlist Cons. Libraries

Physical
Logic Synthesis To
Synthesis Fab

Layout
Gate
Netlist
Extraction

Fails
Sign-off Fails
Sign-off
Passes Passes
Synopsys Galaxy Platform at
UConn (Y-2006)

Sign-off /
Validation /
Design Automation Verification Design for Test

PrimeTime SI/PX/VX
PrimePower
Design Compiler
Star-RCXT DFT Compiler
JupiterXT
Formality DFT MAX
Astro
VCS TetraMAX
Physical Compiler
Nanosim
HSpice
Design for Test
 DFT Compiler
 Scan chain insertion
 DFT Max
 Test compression tool
 TetraMax
 Automatic test pattern generation
(ATPG)
Additional Reading
 Synopsys Website
 www.synopsys.com
 Documentation
 Synopsys OnLine Documenation (SOLD)
 Available on any of the UConn ECS Linux
servers
 Electronic Synopsys Users Group
(ESNUG)
 www.deepchip.com