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Pg073 Axi Apb Bridge
Pg073 Axi Apb Bridge
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TimingDiagram
The timing diagram shown in Table 3-1 illustrates the AXI to APB Bridge core operation for various read and write
transfers. This diagram shows that when both write and read requests are active, the read request is given higher
priority.
X-Ref Target - Figure 3-1
Figure31: AXItoAPBBridgeTiming
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PG073December18,2013
Chapter 4
CustomizingandGeneratingtheCore
This chapter includes information on using the Vivado Design Suite to customize and
generate the core.
If you are customizing and generating the core in the Vivado IP Integrator, see the Vivado
Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 5] for
detailed information. IP Integrator might auto-compute certain configuration values when
validating or generating the design. To check whether the values do change, see the
description of the parameter in this chapter. To view the parameter value you can run the
validate_bd_design command in the Tcl Console.
VivadoIntegratedDesignEnvironment
You can customize the IP for use in your design by specifying values for the various
parameters associated with the IP core using the following steps:
1. Open a project by selecting File > Open Project or create a new project by selecting
File > New Project.
2. In the Vivado IP catalog, expand AXI_Infrastructure in the View by Function pane.
3. Select AXI APB Bridge in the IP catalog.
4. Double-click the IP, or select the Customize IP command from the toolbar or popup
menu.
For details, see:
Working with IP and Customizing IP for the Design in the Vivado Design Suite User
Guide: Designing with IP (UG896) [Ref 4]
Working with the Vivado IDE in the Vivado Design Suite User Guide: Getting Started
(UG910) [Ref 6]
Note: Figures in this chapter are illustrations of the Vivado Integrated Design Environment (IDE).
This layout might vary from the current version.
The Customize IP dialog box for AXI to APB Bridge (Figure 4-1) contains two pages for
configuring the core.
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Chapter4: CustomizingandGeneratingtheCore
Basic
The Basic page contains the basic configurations like number of APB slaves, APB protocol,
and timeout value. See Figure 4-1.
IMPORTANT: Each slave base address/ high address must be configured in the Slave Addresses page.
SlaveAddresses
The Slave Addresses page contains the APB slave base addresses and high addresses.
Note: In IP Integrator, all base and high addresses of all slaves are greyed out and auto-updated when
a slave is connected.
X-Ref Target - Figure 4-1
Figure41: AXIAPBBridgeCoreBasicConfiguration
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Chapter4: CustomizingandGeneratingtheCore
OutputGeneration
For details, see Generating IP Output Products in the Vivado Design Suite User Guide:
Designing with IP (UG896) [Ref 4].
X-Ref Target - Figure 4-2
Figure42: AXIAPBBridgeCoreSlaveAddressesConfiguration
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Chapter 5
Simulation
This chapter contains information about simulating in the Vivado Design Suite
environment.
For comprehensive information about Vivado Design Suite simulation components, as
well as information about using supported third party tools, see the Vivado Design
Suite User Guide: Logic Simulation (UG900) [Ref 8].
For information about simulating the example design, see Simulating the Example
Design.
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Chapter 6
SynthesisandImplementation
This chapter contains information about synthesizing and implementing IP in the Vivado
Design Suite environment.
For details about synthesis and implementation, see Synthesizing IP and
Implementing IP in the Vivado Design Suite User Guide: Designing with IP (UG896)
[Ref 4].
For information about synthesizing and implementing the example design, see
Implementing the Example Design.
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Chapter 7
ExampleDesign
This chapter contains information about the provided example design in the Vivado
Design Suite environment.
Overview
The top module instantiates all components of the core and example design that are
needed to implement the design in hardware, as shown in Figure 7-1. This includes clock
generator (MMCME2) and example design module with logic for AXI transaction generator
and APB transaction checker.
X-Ref Target - Figure 7-1
Figure71: BlockDiagramofExampleDesign
DUT
Clock
Generator
Clock_gen.vhd
clock_in1_p
reset
Pass
clock_in1_n
AX
TRANSACTON
GENERATON
CAPTURE APB
TRANSACTON
<componentname>_exdes.vhd
(top)
X13760
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Chapter7: ExampleDesign
This example design demonstrates transactions on AXI interfaces of the DUT.
Clock generator: MMCME2 is used to generate the clock for the example design. It
generates 100 MHz clock for s_axi_aclk of the DUT. The DUT is under reset until
MMCME2 is locked.
AXI transaction generation: Handles write and read transactions on AXI-lite interface of
the bridge.
Capture APB transaction: Serves as APB slave to the bridge and handles write and read
transactions from the AXI interface of the bridge.
ImplementingtheExampleDesign
After following the steps described in Chapter 4, Customizing and Generating the Core,
implement the example design as follows:
1. Right-click on the core in the Hierarchy window, and select Open IP Example Design.
2. A new window opens where you can specify a directory for the example design. Select
a new directory, or keep the default directory.
3. A new project is automatically created in the selected directory and it is opened in a new
window.
4. Uncomment the IO constraints settings in <component_name>_exdes.xdc specified in
table 8-3.
5. In the Flow Navigator (left side pane), click Run Implementation and follow the
directions.
6. Note that GPIO_LED_7 on the KC705 board glows when the test case in the example
design is passed. For more information, see the KC705 Evaluation Board for the Kintex-7
FPGA User Guide (UG810) [Ref 7].
ExampleDesignDirectoryStructure
In the current project directory, a new project called <component_name>_example is
created and the files are delivered in the <component_name>_example/
<component_name>_example.srcs/ directory. This directory and its subdirectories
contain all the source files that are required to create the AXI to APB Bridge core example
design.
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Chapter7: ExampleDesign
ExampleDesignDirectory
Table 7-1 shows the files delivered in the <component_name>_example/
<component_name>_example.srcs/sources_1/imports/example_design/
directory.
SimulationDirectory
Table 7-2 shows the files delivered in the <component_name>_example/
<component_name>_example.srcs/sources_1/ sim_1/imports/simulation/
directory.
ConstraintsDirectory
Table 7-3 shows the files delivered in the <component_name>_example/
<component_name>_example.srcs/sources_1/ constrs_1/imports/
example_design/ directory.
SimulatingtheExampleDesign
Using the example design delivered as part of the AXI to APB Bridge core, you can quickly
simulate and observe the behavior of the core.
The AXI Transaction generation block generates a write and a read transaction to the DUT.
The DUT then converts the transaction to APB. The APB Transaction is then captured
through the write data and provides the data requested.
Table71: ExampleDesignDirectory
Name Description
<component_name>_exdes.vhd Top-level HDL file for the example design.
clock_gen.vhd Clock generation module for example design.
Table72: SimulationDirectory
Name Description
<component_name>_exdes_tb.vhd Test Bench for Exdes.
Table73: ConstraintsDirectory
Name Description
<component_name>_exdes.xdc Top-level constraints file for the example design.
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Chapter7: ExampleDesign
SettinguptheSimulation
The Xilinx simulation libraries must be mapped into the simulator. To set up the Xilinx
simulation models, see the Vivado Design Suite User Guide: Logic Simulation (UG900)
[Ref 8]. To switch simulators, click Simulation Settings in the Flow Navigator (left pane). In
the Simulation options list, change Target Simulator.
The example design supports functional (behavioral) and post-synthesis simulations. For
information about how to run simulation, see the Vivado Design Suite User Guide: Logic
Simulation (UG900) [Ref 8].
SimulationResults
The simulation script compiles the AXI to APB Bridge core example design, and supporting
simulation files. It then runs the simulation and checks to ensure that it completed
successfully.
If the test passes, the following message is displayed:
Test Completed Successfully
If the test fails, the following message is displayed.
Test Failed !! Test Timed Out.
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Chapter 8
TestBench
This chapter contains information about the provided test bench in the Vivado Design
Suite environment.
Figure 8-1 shows test bench for AXI to APB Bridge core example design. The top level test
bench generates 200 MHz clock and drives initial reset to the example design.
X-Ref Target - Figure 8-1
Figure81: AXItoAPBBridgeCoreExampleDesignTestBench
Clock & reset
generation
TestStatus
<componentname>_exdes.vhd
(top)
clock_in1_p
reset
pass
clock_in1_n
X13761
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Appendix A
MigratingandUpgrading
This appendix contains information about migrating a design from ISE
Design Suite, and for upgrading to a more recent version of the IP core. For
customers upgrading in the Vivado Design Suite, important details (where applicable)
about any port changes and other impacts to user logic are included.
MigratingtotheVivadoDesignSuite
For information on migrating to the Vivado Design Suite, see Vivado Design Suite
Migration Methodology Guide (UG911) [Ref 9].
UpgradingintheVivadoDesignSuite
There are no port or parameter changes.
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Appendix B
Debugging
This appendix includes details about resources available on the Xilinx Support website and
debugging tools.
FindingHelponXilinx.com
To help in the design and debug process when using the AXI to ABP Bridge, the Xilinx
Support web page (www.xilinx.com/support) contains key resources such as product
documentation, release notes, answer records, information about known issues, and links
for obtaining further product support.
Documentation
This product guide is the main document associated with the AXI to ABP Bridge. This guide,
along with documentation related to all products that aid in the design process, can be
found on the Xilinx Support web page (www.xilinx.com/support) or by using the Xilinx
Documentation Navigator.
Download the Xilinx Documentation Navigator from the Design Tools tab on the Downloads
page (www.xilinx.com/download). For more information about this tool and the features
available, open the online help after installation.
AnswerRecords
Answer Records include information about commonly encountered problems, helpful
information on how to resolve these problems, and any known issues with a Xilinx product.
Answer Records are created and maintained daily ensuring that users have access to the
most accurate information available.
Answer Records for this core can also be located by using the Search Support box on the
main Xilinx support web page. To maximize your search results, use proper keywords such
as
Product name
Tool message(s)
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AppendixB: Debugging
Summary of the issue encountered
A filter search is available after results are returned to further target the results.
Master Answer Record for the AXI to ABP Bridge
AR: 54439
ContactingTechnicalSupport
Xilinx provides technical support at www.xilinx.com/support for this LogiCORE IP product
when used as described in the product documentation. Xilinx cannot guarantee timing,
functionality, or support of product if implemented in devices that are not defined in the
documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
To contact Xilinx Technical Support:
1. Navigate to www.xilinx.com/support.
2. Open a WebCase by selecting the WebCase link located under Additional Resources.
When opening a WebCase, include:
Target FPGA including package and speed grade.
All applicable Xilinx Design Tools and simulator software versions.
Additional files based on the specific issue might also be required. See the relevant
sections in this debug guide for guidelines about which file(s) to include with the
WebCase.
Note: Access to WebCase is not available in all cases. Login to the WebCase tool to see your specific
support options.
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AppendixB: Debugging
DebugTools
There are many tools available to address AXI to ABP Bridge design issues. It is important to
know which tools are useful for debugging various situations.
VivadoLabTools
Vivado lab tools insert logic analyzer (ILA) and virtual I/O (VIO) cores directly into your
design. Vivado lab tools allow you to set trigger conditions to capture application and
integrated block port signals in hardware. Captured signals can then be analyzed. This
feature represents the functionality in the Vivado IDE that is used for logic debugging and
validation of a design running in Xilinx devices in hardware.
The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores,
including:
ILA 2.0 (and later versions)
VIO 2.0 (and later versions)
See Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 10].
The interface is not being held in reset, and s_axi_areset is an active-Low reset.
The interface is enabled, and s_axi_aclken is active-High (if used).
The main core clocks are toggling and that the enables are also asserted.
If the simulation has been run, verify in simulation and/or a Vivado Lab tools capture
that the waveform is correct for accessing the AXI4-Lite interface.
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Appendix C
AdditionalResources
XilinxResources
For support resources such as Answers, Documentation, Downloads, and Forums, see the
Xilinx Support website at:
www.xilinx.com/support
For a glossary of technical terms used in Xilinx documentation, see:
www.xilinx.com/company/terms.htm
References
These documents provide supplemental material useful with this product guide:
1. ARM AMBA documentation (infocenter.arm.com/help/index.jsp?topic=/
com.arm.doc.ihi0051a/index.html):
AMBA AXI and ACE Protocol Specification, AXI3, AXI4, and AXI4-Lite, v2.0
NoticeofDisclaimer
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maximum extent permitted by applicable law: (1) Materials are made available AS IS and with all faults, Xilinx hereby DISCLAIMS
ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in
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warranty.htm#critapps.
Copyright 2012 - 2013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated
brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of
their respective owners.
Date Version Revision
07/25/12 1.0 Initial Xilinx release. This release supports Vivado Design Suite 2012.2
and Xilinx Platform Studio. This document replaces DS788, LogiCORE
IP AXI to APB Bridge Data Sheet.
10/02/2013 2.0 Updated core to v2.0.
Added Vivado IP integrator support.
Changed signal names to lowercase.
Removed design parameter descriptions.
Added example design and test bench details.
Added Debugging appendix.
12/18/2013 2.0 Added UltraScale architecture support information.
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