Unit 2: Architecture of Microprocessor
Unit 2: Architecture of Microprocessor
Unit 2: Architecture of Microprocessor
ARCHITECTURE OF MICROPROCESSOR
UNIT 2
OBJECTIVE:
General Objectives :
Specific Objectives:
2.1 draw the block diagram of basic computer system, and describes each
of them.
2.2 describe the evolution of microprocessor.
2.3 state and describe the Data size: Nibble, Byte, Word, Long Word
2.4 explain the fetch and execute cycle
2.5 state and describe the bus system
2.6 explain the Internal structure and basic operation of a microprocessor
2.7 explain the microprocessor clock system
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INPUT-2A
2.0 INTRODUCTION
What you know about your personal computer at home or in the office?
What are the features provided in your computer system? To know the
features of a computer, the easiest way is referring to the specification
sheet provided at the counter of most of the computer shop, or
newspaper advertisement , magazines, etc. Normally the first item in
the list is the micro-processor of the computer system, for instance,
“Intel Pentium-4 1.7G” is the micro-processor of the computer system.
The capability of processor determine the capability of the computer
system, in other word the processor is the key element or heart of a
computer system. Apart from personal computer, microprocessors are
used in many other computerized system in various field, for instance,
industrial automation. This unit will introduce you the architechure and
the construction of a microprocessor.
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1970
4004
8008
8080 6800
1975
8085
8086
6809
1980 8088 68000
80188 80286
68010
80186 68008 68012
68020
80386
1985
68030
80386SX
80486 68040
1990
Pentium
68060
1995
M68000 Family
The comparative details of the various properties of the M68000 family
microprocessor are summarized in Table 2.2. Although all chips have
32-bit CPU registers, the 68000, 68008, 68010 are 16-bit systems,
while the microprocessor starting with 68020 and onwards are 32-bits.
The 68008 has the same architecture as the 68000, but an 8-bit
external data bus.
If a single cell can store 4 bit of data, the cell size is called Nibble.
Subsequently 8 bits is called Byte, 16 bits is Word, and 32 is Long
Word.
A single cell sized 1 bit can store either logic-0 or logic-1. In other
word, two different situations can be stored or represented. Thus the
range of data is 0 – 1.
Data size: n = 1
Data capacity : 2n = 21 = 2
Range : 0 – 1
Figure 2.2 shows the different data sizes in a graphic manner. Please
note that the data size is determined by the number of bit (n) , and is
labelled from 0 to n-1. For the data type Byte, Word and Long Word
allocate the MSB as the sign bit, to determine that value of remaining
bits is positve or negative.
For the data which has more bits, it is easier to divide it into dual-half
portions i.e. upper (MSB section) and lower portions (LSB section).
3 0
Sign 7 4 3 0
Upper Lower
bit
Nibble Nibble
ACTIVITY – 2A
2A-1:
What are the two major microprocessor manufacturers?
2A-2:
What are the features for the microprocessor Pentium (Refer Table 2.1) :
Number of bits: ______
Speed : __________
Number of transistors : ___________
Developed in year: ____________
2A-3:
State the features of microprocessor MC68000 (Refer Table 2.2) :
2A-4:
What is the two main facts to determine the capacity of a microprocessor?
2A-5:
What is the definition of data size?
2A-6:
What do you know about “bit”?
2A-7:
If the smallest size of a single cell is called bit, what are the other cell sizes
with reference to the bits of data shown in the following table:
2A-8:
Please determine the following features of a single cell sized 32 bits?
Data size: n = ____
Data capacity : 2n = ______
Range : ________
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2A-9:
If the sign bit of a byte is at bit b7, and bit 0 to bit 3 is called lower nibble,
what is the sign bit of a long word, and the name of bit 16 to bit 31? (Refer
Figure 2.2)
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FEEDBACK TO ACTIVITY – 2A
2A-1:
What are the two major microprocessor manufacturers?
Intel and Motorola
2A-2:
What are the features for the microprocessor Pentium (Refer Table 2.1) :
Number of bits: 64
Speed : 60 – 166 MHz
Number of transistors : 3.1 million.
Developed in year: 1993
2A-3:
State the features of Attribute MC68000
microprocessor MC68000 Data bus size (bits) 16
(Refer Table 2.2) : Address bus size (bits) 24
Instruction cache -
(in byte)
Data cache (in byte) -
Clock MHz 8 - 16
2A-4:
What is the two main facts to determine the capacity of a microprocessor?
bits of data can be handled at one time,
memory size accessible by the system.
2A-5:
What is the definition of data size?
Data size is a mean of measure to determine how much data can be stored
in a single cell of memory.
2A-6:
What do you know about “bit”?
In digital form, the smallest size of a single cell is called 1 bit.
2A-7:
If the smallest size of a single Bit of data Cell size
cell is called bit, what are the can be stored
other cell sizes with reference (Bit/s)
to the bits of data shown in the 1 Bit
following table: 4 Nibble
8 Byte
16 Word
32 Longword
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2A-8:
Please determine the following features of a single cell sized 32 bits?
2A-9:
If the sign bit of a byte is at bit b7, and bit 0 to bit 3 is called lower nibble,
what is the sign bit of a long word, and the name of bit 16 to bit 31? (Refer
Figure 2.2)
Sign bit is Bit b31
Bit b16 to b31 is upper word.
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INPUT-2B
From
outside
world
Memory Unit
Memory unit stores group of binary digits (word) that can
represent:
a. instructions (program) that the computer is to perform.
b. the data that are to be operated on by the program.
As storage for intermediate and final results of arithmetic
operation (arrow 4)
Operation of the memory (either Read or Write) is controlled by
the control unit (arrow 6).
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Input Unit
Consists of all of the devices used to take information and data
from the external environment to be inputted into the
computer system.
Output Unit
Consists of all of the devices used to transfer information and
data from computer system to the external environment.
Interfacing Unit
The devices that make up the input and output units are called
peripherals because they are external to the rest of the
computer.
The most important aspect of peripherals involves interfacing.
Computer interfacing is specifically defined as transmitting
digital information between a computer and its peripherals in a
compatible and synchronized way.
Control Unit
It directs the operation of all the other units by providing timing
and control signals.
The unit contain logic and timing circuits that generate the
proper signals necessary to execute each instruction in a
program.
The control unit fetches instruction codes (in binary codes)
from memory, then decodes the codes into instructions
subsequently execute operations.
b) Memory Unit
Store data and programs.
Divided into two (2) main categories:
i. Primary memory:
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By comparing the two diagram of Figure 2.4 and 2.5, the MPU
is Intel 8085, and the pins is labeled according to the specific
function group names. For instance, the address lines are
grouped as "A15 - A0"; data lines are grouped as "D0-D7" ; control
lines with individual pin names, etc. All these line groups of the
MPU are connected to the three bus systems and subsequently
to the main function blocks of Memory (RAM and ROM), and
I/O interfaces-devices. On the left side of the MPU is the clock
circuitry to provide timing and sequence control to the MPU and
also the system.
ACTIVITY – 2B
b) _______________________________
c) _______________________________
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FEEDBACK TO ACTIVITY – 2B
INPUT-2C
Data Bus
CPU Address Bus
Control Bus
Data bus:
Bidirectional bus, because data can flow to or from the CPU.
Address bus:
Unidirectional bus, because information flows over it in only one
direction, i.e. from CPU to thememory or I/O elements.
2n = 216 = 65536:
CPU can handle or address 65536 single cells (each cell has 8
bits data size) of memory.
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Control bus:
This is the set of signals that is used to synchronize the activities
of the seperate microcomputer elements.
Control bus consists some individual lines for sending and some
others for receiving signals from CPU, thus control bus is
bidirectional. However, not like data bus that uses the same
lines to send or receive data. In Figure 2.5 two arrows with
opposite direction represents control bus as bidirectional but not
sharing the same lines for both sending and receiving signals.
For instance, CPU sends control signals (Read/Write) to the
memory or I/O devices to tell them either to be set to send or
receive data.
Contrary, CPU receives signal from other elements; for instance,
Reset signal will tell CPU to reset the on going operation, and
INTR signal causes CPU to interrupt an on going process.
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ACTIVITY – 2C
1a-1 Nyatakan tiga ciri motor tiga fasa yang menjadi kelebihan berbanding
motor
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FEEDBACK TO ACTIVITY – 2C
1a-1:
a) faktor kuasa yang lebih baik.
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INPUT-2D
START
Is
No
it aHALT
instruction?
Yes
STOP
Figure 2.9 is the extract from the basic computer system in Figure 2.3,
here we focus on the processes involve the control unit. The control
unit fetches an instruction from memory subsequently executes it by
the following steps:
Example2-1
2-1
Example
b.) Add two data which are stored in memory at address 0001 and 0002.
c.) Store the result in the memory at address 0003.
Show the the above process in terms of fetch and execute cycles.
Solution
Solution2-1
2-1
START
Step 1:
CPU fetches the instruction “ADD” stored
in the memory (in binary codes), CPU then
decodes the instruction code.
Fetch
Step 2: cycle
First data is fetched from the memory (at
address 0001).
Step 3:
Second data is fetched from the memory
(at address 0002).
Step 4:
The two data are added.
Execute
This operation is carried out by ALU.
cycle
The result will be stored in the memory
(at address 0003).
END
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Within the fetch cycle, there are two operations or sub-cycles, i.e.
Read and write.
READ CYCLE
CPU sends a signal via control bus. If the bus is busy, CPU is put
on Wait state.
If the bus is free, CPU will place instruction address on the
address bus.
This address will be decoded or translated by the circuitry in the
memory or I/O interface.
Finally the data at that specific address is obtained, and is placed
on the data bus.
Figure 2.10 shows the the whole Read cycle in the graphical form.
Address Bus
SYSTEM BUS
Data Bus
Control Bus
2 1
REQUEST
MEMORY
Step 1 : Read Request
Address Bus
SYSTEM BUS
Data Bus
Control Bus
3 4
DATA TRANSFER
MEMORY
MPU Step 3 : Receive Data
Step 4 : Signal OK
RAM ROM
WRITE CYCLE
Figure 2.11 shows the the whole Write cycle in the graphical form.
Address Bus
SYSTEM BUS
Data Bus
Control Bus
1
MEMORY REQUEST
MPU
RAM ROM Step 1 : Write Request
2
Address Bus
SYSTEM BUS
3
Data Bus
Control Bus
4
DATA TRANSFER
MEMORY
MPU Step 2 : Send Address
RAM ROM Step 3 : Send Data
Step 4 : Signal OK
ACTIVITY – 2D
1a-1 Nyatakan tiga ciri motor tiga fasa yang menjadi kelebihan berbanding
motor
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FEEDBACK TO ACTIVITY – 2D
1a-1:
a) faktor kuasa yang lebih baik.
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INPUT-2E
Address bus
ALU Register
Section Data bus
Microprocessor
Registers section:
These internal registers serve as temporary data storage,
before, in progress and after the process done by ALU. Data
transfer within these registers is much faster as compared to
the memory.
This section contains various registers (inside the MPU),
each of which performs a special function.
These registers are: general purpose registers array,
accumulator, instruction register, program counter, and flag
register.
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PROGRAMMING MODEL
31 16 15 8 7 0
__ __ D0
__ __ D1
__ __ D2
__ __ D3 Eight
__ __ D4 Data
__ __ D5 Registers
__ __ D6
__ __ D7
31 16 15 8 7 0
__ __ A0
__ __ A1
__ __ A2 Seven
__ __ A3 Address
__ __ A4 Registers
__ __ A5
__ __ A6
The register set is divided into two groups, the data registers
and the address registers.
Data registers:
There are eight registers, denoted by D0-D7.
Each can be used as a source or destination operand in a
typical instruction.
A data register may be accessed as a byte, word, or a
longword.
For a byte operation, only the least significant byte, i.e. bits
7-0, is used as an operand. The remaining 24 bits are not
affected by the operation.
Similarly, for a word operation, only the least significant half
of the register can be used.
Address registers:
The address registers are primarily for generating memory
operand addresses. Therefore, their accesses are more
restrictive when compared to the data registers.
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ACTIVITY – 2E
2 Nyatakan tiga ciri motor tiga fasa yang menjadi kelebihan berbanding
motor
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FEEDBACK TO ACTIVITY – 2E
1a-1:
a) faktor kuasa yang lebih baik.
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INPUT-2F
Extract of
Intel 8085 P
20pF CLOCK
X2
20pF
3 MHz
6 MHz
6 MHz 2
Instruction Cycle
Machine
Cycle M1 M2 M3 M4
T state T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 T1 T2 T3
CLOCK
Type of
machine cycle Memory Read Memory Read Memory Read Memory write
Hex address 0007 0008 from PC; 0009 from PC; 0300, the
from PC; address of address of low address of operand
Address bus op code for STA. byte of the high byte of address.
operand the operand
address. address.
Hex data 32, the op Hex 00, the 03, the high Data byte
Data bus code for STA. low byte of the byte of the from
operand operand accumulator
address. address. register of the
CPU.
Read cycle:
During the first clock cycle (S0/S1), the processor places an
address on address pins A1-A23, specifying the location to
be accessed.
It also sets the R/W pin initially high to indiacate a read
operation and send out a 3-bit function code on pins FC0-
FC2.
At the beginning of the second clock cycle (S2/S3), the
processor asserts the AS pin to indicate a valid address and
maintains it low for the entire bus cycle.
In S2/S3, for read cycle, the processor maintains the R/W
signal high, outputs UDS and LDS, and places data pins
D0-D15 into the high impedance mode.
Write cycle:
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ACTIVITY – 2F
1a-1 Nyatakan tiga ciri motor tiga fasa yang menjadi kelebihan berbanding
motor
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FEEDBACK TO ACTIVITY – 2F
1a-1:
a) faktor kuasa yang lebih baik.
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SELF-ASSESSMENT 2
KENDIRI - U1
You are approaching success. Try all the questions in this self-assessment section
and check your answers with those given in the Feedback on Self-Assessment 1
given on the next page. If you face any problem, discuss it with your lecturer. Good
Luck
1-1:
a. Senaraikan LIMA kebaikan sistem tiga fasa berbanding dengan sistem satu fasa.
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FEEDBACK TO SELF-
ASSESSMENT 2
Have you tried the question?????? If “YES”, check your answer now.
JAWAPAN 1-1:
End of unit 2