68000 Microprocessor

Module 2

Architecture

Dr. Izzeldin Ibrahim

 68000 Microprocessor

68000 Architecture

Aims
 To review the architecture of the 68000 microprocessor.

Intended Learning Outcomes

 At the end of this module, students should be able to:

Briefly explain the history of microprocessor and the 68000 family

Describe the term programming model

Describe the programmer-visible registers in the 68000

Describe how the memory is accessed in the 68000

Describe and use the three simplest addressing modes of the 68000:
direct, absolute and immediate

Be able to access and understand the information presented in the
68000 Programmer’s Reference Manual

Dr. Izzeldin Ibrahim 2-2

 68000 Microprocessor

68000/ColdFire Background

MC68000 introduced by Motorola in 1979.

Notable sightings:
 Used in the Sun, the first ever workstation
 Used in the Macintosh, first ever GUI personal computer
 Used in early versions of PalmPilot PDA

Why 68000 for learning microprocessors?
 Powerful & simple instruction set
 Sophisticated interfacing capabilities
 Able to support high-level language and operating systems
 Flat memory map (versus segmented memory used in Intel 80x86)
 The most popular µP in academia

Internally, MC68000 has 32 bit data paths and 32-bit instructions
 interfaces with external components using a 16-bit data bus. So a programmer
considers it 32-bit chip while a system designer considers it a 16-bit chip.
 Hence the “16-/32-bit chip” designation.

Dr. Izzeldin Ibrahim 2-3

 68000 Microprocessor

68000 Chip Package

The original 68000 was available in 64-bit DIP or 68-pin PLCC.

Dual-In line Package (DIP), (DIL): Plastic leaded chip carrier (PLCC):
Package with a rectangular housing and Four-sided package. PLCC packages
two parallel rows of electrical connecting can be square or rectangular.
pins, usually protruding from the larger
sides of the package and bent downward.

Plastic
Chip case

Pins
End vie
w

Dr. Izzeldin Ibrahim 2-4

 68000 Microprocessor

68000/ColdFire Versions

68000 family has many versions.
 680x0 means 68000, 68008, 68010, 68020, 68030, 68040 and 68060.
 Newer versions are “upward compatible” with older versions.
 The family is also affectionately called 68k or MC68k.
 Most commonly found members are 68000, 68020, CPU32 and ColdFire.

The family includes 16-bit peripherals chips.
 The 68000 can use 68000-type peripherals chips for higher performance or
older 6800-type peripherals for lower cost.

ColdFire is the current version
 ‘RISC’ified 68000 processor core.
 Smaller, less power used than normal 68020.
 A ColdFire chip is an embedded processor with integrated peripherals
 You can find it in some HP laserjet printers

Today, the 68k family is made by Freescale Semiconductors.

Dr. Izzeldin Ibrahim 2-5

 68000 Microprocessor

68k Processor Family

48-pin 52-pin
68000 68010 * 68020 68030 68040 68060
68008 * 68008 *
Data bus (bits) 8 8 8/16 ** 16 32 32 32 32
Address Bus
20 22 24 24 32 32 32 32
(bits)
Data cache
- - - - - 256 4096 8192
(bytes)
Instruction cache
- - - - 256 256 4096 8192
(bytes)
Memory
Management Unit - - - - - On-chip On-chip On-chip

Floating-Point
- - - - Off-chip Off-chip On-chip On-chip
Unit
Max Speed (MHz)
- - 20 - 33 50 40 75

Performance
- - 2 - 10 18 44 110
(MIPS)
* 68008 and 68010 are end-of-lifed (EOL) meaning no longer in production.
** Original 68000 has 16-bit bus. Current 68000 has selectable 8- or 16-bit bus.

Dr. Izzeldin Ibrahim 2-6

 68000 Microprocessor

68000 Hardware

Specifications
 32-bit data and address
registers
 16-bit data bus
 24-bit address bus
 14 addressing modes
 Memory-mapped input-output
 Program counter
 56 instructions
 5 main data types
 7 interrupt levels
 Clock speeds: 4 MHz to 12.5
MHz
 Synchronous and
asynchronous data transfers

Dr. Izzeldin Ibrahim 2-7

 68000 Microprocessor

What is “Microprocessor Architecture”

For our purposes the architecture is the
software or programmer’s model of the
microprocessor
 The CPU registers available to the programmer
 The basic instructions the CPU can perform
 The ways these instructions can specify a memory
location
 The way data is organized in memory
 How the CPU accesses & controls peripheral
devices

Dr. Izzeldin Ibrahim 2-8

 68000 Microprocessor

68000 Programming Model

Name Label Number Size Function

Data
D0-D7 8 32 bit Stores 8-/16-/32-bit data
registers
Stores 16-/32-bit pointers
Address (addresses of data)
A0-A6 7 32 bit
registers

Store a pointer to a
group of data known as
Stack the stack. Also known as
SP 2 32 bit A7. There’s two stack
pointer
pointers: USP and SSP.

Contains the address of

Program the NEXT instruction to
PC 1 32 bit fetch and execute
counter

Contains information on
the results of the last
instruction. Consists of
Status
SR 1 16 bit the system byte and the
Register
condition codes register
(CCR)

Dr. Izzeldin Ibrahim 2-9

 68000 Microprocessor

Control/Status Register

System Byte Status register stores an ”analysis” of the last operation involving the ALU
 Only modifiable is supervisor mode
Register Register
 Details in later modules

User Byte: CCR X
F
N L
 For user-level programs Z A
 Behavior depends on instruction
ALU V
G
C
S

Register

Bit Meaning
C Set if a carry or borrow is generated. Cleared
otherwise.
V Set if a signed overflow occurs. Cleared otherwise.
Z Set if the result is zero. Cleared otherwise.
N Set if the result is negative. Cleared otherwise.

X Retains the carry bit for multi-precision arithmetic

I Systems responds to interrupts with a level higher
than I
S 1 means CPU in supervisor mode, 0 means user
mode
T 0 for normal operation, 1 to stop the CPU after
EVERY instruction for runtime debugging

Dr. Izzeldin Ibrahim 2-10

 68000 Microprocessor

Byte, word and Long-word Addressing

Bytes can be stored in any even or odd
Word must stored at even addresses
location
Attempt to store word at odd address result
in a “trap”
000000 10101010 11000101 000001
Trap : recoverable crash
000002 00011001 11110010 000003
000004 000005 Alamat 15 0 Alamat
0 kata 0 1
2 kata 1 3
4 kata 2 5

FFFFFC 11001000 11111111 FFFFFD

FFFFFE 00011010 01010111 FFFFFF
Long-word can be stored at even address

Long-word requires two memory accesses
Alamat Alamat (two rows in memory map)
genap ganjil Alamat 15 0 Alamat
Alamat Alamat 0 1
kata panjang 0
bait 0 bait 1 2 3
0 1
4 5
2 bait 2 bait 3 3 kata panjang 1
6 7
4 bait 4 bait 5 5 8 9
6 bait 6 bait 7 7
00000016 1010 1011 1100 1101 000000116
00000216 0001 0010 0011 0100 000000316

Dr. Izzeldin Ibrahim 2-11

 68000 Microprocessor

Register Transfer Language (RTL)

A simple notation to describe the operations carried out by
CPU clearly and unambiguously
 We will use it to describe the function of instruction

100 means “#100” or “the number 100”

[M(4)] means “contents stored in memory location 4”
[M(4)] = 100 means “memory location 4 contains #100”
[M(4)] ← 25 means “load number 25 into memory location 4”
[PC] ← 4 means “load number 4 into PC”
[M(4) ← 100+[M(4)] means “add #100 to contents of location 4 and save”

(This slide falls in the “good to know” category.)

Dr. Izzeldin Ibrahim 2-12

 68000 Microprocessor

Instruction Set

The complete list of instructions is known as the instruction set

Instructions are categorized according to basic operation
performed:
 Data transfer
 Arithmetic
 Logic
 Shifts & rotates
 Bit manipulation
 BCD
 Program Control
 System Control

Dr. Izzeldin Ibrahim 2-13

 68000 Microprocessor

Basic Instruction Set

Mnemonic Meaning Mnemonic Meaning
ABCD Add decimal with extend MOVE Move source to destination
ADD Add binary MULS Sign multiply
AND Logical AND MULU Unsigned multiply
ASL Arithmetic shift left NBCD Negate decimal with extend
ASR Arithmetic shift right NEG Negate
Bcc Branch conditionally NOP No operation
BCHG Bit test and change NOT One's complement
BCLR Bit test and clear OR Logical OR
BRA Branch always PEA Push effective address
BSET Bit test and set RESET Reset external devices
BSR Branch to subroutine ROL Rotate left
BTST Bit test ROR Rotate right
CHK Check register with bounds ROXL Rotate left through extend
CLR Clear operand ROXR Rotate right through extend
CMP Compare RTE Return from exception
DBcc Decrement and branch conditionally RTR Return and restore
DIVS Exclusive OR RTS Return from subroutine
DIVU Unsigned divide SBCD Subtract decimal with extend
EOR Jump to subroutine Scc Set conditionally
EXG Exchange registers STOP Stop processor
EXT Sign extend SUB Subtract binary
JMP Jump to effective address SWAP Swap data register halves
JSR Logical shift left TAS Test and set operand
LEA Load effective address TRAP Trap
LINK Link stack TRAPV Trap on overflow
LSL Signed divide TST Test
LSR Logical shift right UNLK Unlink stack

Dr. Izzeldin Ibrahim 2-14

 68000 Microprocessor

Instruction Format

Generic instruction format
<label> opcode<.field> <operands> <;comments>

 <label> pointer to the instruction’s memory location

 opcode operation code (MOVE, ADD, etc)
 <.field> width of operand (B,W,L)
 <operands> data used in the operation
 <;comments> for program documentation

Instruction RTL
MOVE.W #100,D0 [D0] ← 100
MOVE.W $100,D0 [D0] ← [M(100)]
ADD.W D1,D0 [D0] ← [D0] + [D1]
MOVE.W D1,$100 [M(100)] ← D0
DATA DC.B 20 [DATA] ← 20
BRA LABEL [PC] ← label

Dr. Izzeldin Ibrahim 2-15

 68000 Microprocessor

Operands

Operands can be
 Registers
 Constants
 Memory addresses

Operands specify addressing modes such as
 Dn: data register direct MOVE.W D0, D1
 An: address register indirect MOVE.W (A0),D1
 #n: immediate MOVE.W #10,D1
 N: absolute MOVE.W $1000,D1

Operands can be specified in several formats
 Decimal: default
 Hexadecimal: prefixed by $
 Octal: prefixed by @
 Binary: prefixed by %
 ASCII: within single quotes ‘ABC’

Dr. Izzeldin Ibrahim 2-16

 68000 Microprocessor

Addressing Modes

Addressing mode : the mechanism used to compute the operand
address

68000 has sophisticated addressing modes
 Simplifies assembler programming because it reduces the number steps
required to specify an address

68000 has 14 addressing modes but really falls into 6 major categories.
 Register direct
We’ll cover the first
 Immediate
three in this module.
 Absolute The rest will be
 Program counter relative covered later.
 Register indirect
 Inherent

Effective address : the actual address used by the instruction
 Examples:

Data register D1 in the processor

Address $10000 in memory

Dr. Izzeldin Ibrahim 2-17

 68000 Microprocessor

A simple instruction
Format:
CLR.s <ea>
Example:
CLR.W D1 ;Clears lower word of D1
Before After
Effect:
D1 FE ED BE EF D1 FE ED 00 00

Format:
MOVE.s <ea>,<ea>
Example :
MOVE.W D0,D1 ;Copy lower word of D0 to D1
Effect:

Before After
D0 12 34 56 78 D0 12 34 56 78
berubah
D1 78 56 34 12 D1 78 56 56 78

Dr. Izzeldin Ibrahim 2-18

 68000 Microprocessor

Register Direct Addressing

The simplest addressing mode

Source or destination of an operand is a data register or an address
register.

Examples:

Dr. Izzeldin Ibrahim 2-19

 68000 Microprocessor

Immediate Addressing Mode

Can only be used as a source addressing mode. The destination of the data must also be
specified by the destination addressing mode

Indicated by a # symbol in front of the source operand.

Very useful to load constants (values that never change).

Dr. Izzeldin Ibrahim 2-20

 68000 Microprocessor

Absolute Addressing Mode

Effective address : the memory location specified by the instruction

Most addresses are specified in hex so the ‘$’ hex symbol is commonly found when
memory accesses are involved

There are two variation of absolute addressing: Absolute short and Absolute long.
Absolute Short:
1. Used to access data in two specific memory
location. $000000-$007FFF, and $FF8000-
$FFFFFF.
2. Address specified by a 16-bit quantity. 68k
will automatically signed extended the 16-bit
value into 24 bits. The size required for an
address.

Absolute Long:
1. Any address within the range $000000-
$FFFFFF may be used.
2. The full address is used. There is no sign
extension.

Dr. Izzeldin Ibrahim 2-21

 68000 Microprocessor

Absolute Short Addressing Mode

Dr. Izzeldin Ibrahim 2-22

 68000 Microprocessor

Absolute Long Addressing Mode

Dr. Izzeldin Ibrahim 2-23

 68000 Microprocessor

Bytes, Words, and Longwords

D3

1234 1234 1234

1235 1235 1235
1236 1236 1236
1237 1237 1237

MOVE.B $1234,D3 MOVE.W $1234,D3 MOVE.L $1234,D3

[D3(0:7)] ← [M($1234)] [D3(0:15)] ← [M($1234)] [D3] ← [M($1234)]

Dr. Izzeldin Ibrahim 2-24

 68000 Microprocessor

Address Register Indirect Addressing (ARI) Mode

Used to access data that resides in the memory.

Address register holds the memory location that contains the operand data.

68k recognize this addressing whenever the address register is surrounded by
parentheses, as (A0), (A3), and (A7).

Example: CLR.W (A0) clears located in memory, specified by A0.

Dr. Izzeldin Ibrahim 2-25

 68000 Microprocessor

Inherent (Implied) Addressing Mode

In this mode the instruction makes reference to a

processor register (CCR, SR, SP, USP, SSP or PC)
within its mnemonic.

Examples:

 ANDI #$27, SR (AND immediate data to the Status Register).

 MOVE CCR, (A2) (Move a copy of the Condition Code Register to
memory).

Dr. Izzeldin Ibrahim 2-26

 68000 Microprocessor

Machine instruction

Each instruction is at least 1 word, at most 5 words.

The first word is known as the operation word, which
determines:
 Operation required
 Data size: byte, word or longword
 Length of the complete instruction
 Where to find data (effective address)

The method of instruction encoding (how a instruction is
written in binary) is complex!

Dr. Izzeldin Ibrahim 2-27

 68000 Microprocessor

Machine Code Translation

Dr. Izzeldin Ibrahim 2-28

 68000 Microprocessor

Variable Length Instructions

Not only is the 68000 instruction format complex, the number
of bytes in an instruction also varies.

Op-word OP-word Operand1 Operand2

Address
operands
$4000 $33FC MOVE.W #1234,$543210 33FC 1234 0054 3210
$4002 $1234
$4004 $0054
$4006 $3210
$4008 $D082 ADD.L D2, D0 D082
$400A $0003 ORI.B #5,D3
0003 0005
$400C $0005
$400E $4EF9 JMP ($300008) 4EF9 0030 0008
$4010 $0030
$4012 $0008
$4014 $4E70 RESET 4E70
$4016

Dr. Izzeldin Ibrahim 2-29

 68000 Microprocessor

Summary

Register direct addressing is used for variables that can be held in
registers

Literal (immediate) addressing is used for constants that do not change

Direct (absolute) addressing is used for variables that reside in memory

The only difference between register direct addressing and direct
addressing is that the former uses registers to store operands and the
latter uses memory

For Further Info:
 Motorola 68000 From Wikipedia, the free encyclopedia:

http://en.wikipedia.org/wiki/68000
 CPU World - Motorola 68000 microprocessor family:

http://www.cpu-world.com/CPUs/68000
 68000 Programmer’s Reference Manual

http://www.freescale.com/files/archives/doc/ref_manual/M68000PRM.pdf

Dr. Izzeldin Ibrahim 2-30

 68000 Microprocessor

Immediate Addressing Mode

Given D0=12345678, what happens after these instructions:

MOVE #5,D0 D0 =
MOVE #10,D0 D0 =
MOVE #-1,D0 D0 =
MOVE #$1234,D0 D0 =
MOVE #%1011,D0 D0 =
MOVE #@123,D0 D0 =
MOVE #’B’,D0 D0 =
MOVE.L #’HELP’,D0 D0 =

Dr. Izzeldin Ibrahim 2-31

 68000 Microprocessor

Register Addressing Mode

Given D0=12345678 and D1=11112222, what happens after

these instructions:

MOVE D1,D0 D0 =
MOVE D0,D1 D0 =
MOVE.B D1,D0 D0 =
MOVE.L D1,D0 D0 =
CLR.W D1 D0 =
CLR.B D0 D0 =
MOVE.B D1,D1 D0 =
MOVE.L D0,D1 D0 =

Dr. Izzeldin Ibrahim 2-32

 68000 Microprocessor

Opcodes
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0

Bit 15, 14, 13, 12 OPERATION:

0000
0001 MOVE Byte
0010 MOVE Long
0011 MOVE Word
0100 Miscellaneous
0101 ADDQ / SUBQ / Scc / DBcc
0110 Bcc
0111 MOVEQ
1000 OR / DIV / SBCD
1001 SUB / SUBX
1010 (Unassigned)
1011 CMP / EOR
1100 AND / MUL / ABCD / EXG
1101 ADD / ADDX
1110 Shift / Rotate
1111 (Unassiggned)

Dr. Izzeldin Ibrahim 2-33