ATPG - Stuck-At and At-Speed - Semicon Shorts
ATPG - Stuck-At and At-Speed - Semicon Shorts
ATPG - Stuck-At and At-Speed - Semicon Shorts
Random
ATPG generates random patterns and keeps only the ones which can detect faults.
It can miss the faults with low probability of detection.
Deterministic
ATPG picks up some faults and generates patterns to target that fault. Then, it
performs fault simulation to check if the pattern targeted the given fault. It is good
for faults with low probability of detection.
Let us discuss about two most important kinds of testing done by ATPG: stuck-at
and at-speed.
Stuck-at Testing
This is the most common testing done in a scan-based design. The scan enable
signal is used to indicate if the device is in shift or capture mode. It works as follows:
Load test vectors into scan chains, using a slow test clock (shift-in) SE = 1
Pulse a capture clock, which is a high speed functional clock (capture) SE = 0
Unload the scan chains to shift-out the captured values (shift-out) SE = 1
Figure 1
At-speed Testing
hese tests check for the transition faults (slow to rise and slow to fall) and includes
three cycles:
– It can be done for a non-functional path as well, as the transition pattern is shifted
during the SHIFT operation itself. In real design, that transition might never happen
in that path.
Figure 3
As seen, there are two pulses in capture mode (one for launch and one for capture).
+ SE has enough time to get settled and does not need to function at high speed
clock.
+ There can be extra capture pulses with no activity, just to allow scan signals to
There can be extra capture pulses with no activity, just to allow scan signals to
settle.
Avinash
May 25, 2022 at 9:57 pm
Good article!
Liked by 1 person
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