Intel 8042
Intel 8042
Intel 8042
Y
Y
Y
Y
Y
Y
Y
Y
The UPI-C42 is an enhanced CHMOS version of the industry standard Intel UPI-42 family. It is fabricated on
Intels CHMOS III-E process. The UPI-C42 is pin, software, and architecturally compatible with the NMOS UPI
family. The UPI-C42 has all of the same features of the NMOS family plus a larger user programmable memory
array (4K), hardware A20 gate support, and lower power consumption inherent to a CHMOS product.
The UPI-L42 offers the same functionality and socket compatibility as the UPI-C42 as well as providing low
voltage 3.3V operation.
The UPI-C42 is essentially a slave microcontroller, or a microcontroller with a slave interface included on the
chip. Interface registers are included to enable the UPI device to function as a slave peripheral controller in the
MCS Modules and iAPX family, as well as other 8-, 16-, and 32-bit systems.
To allow full user flexibility, the program memory is available in ROM and One-Time Programmable EPROM
(OTP).
290414 1
290414 2
290414 3
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intels Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT INTEL CORPORATION, 1996
December 1995
Order Number: 290414-003
UPI-C42/UPI-L42
Table 1. Pin Description
Symbol
DIP
Pin
No.
PLCC
Pin
No.
QFP
Pin
No.
TEST 0,
TEST 1
1
39
2
43
18
16
Type
I
XTAL 1
19
XTAL 2
20
RESET
22
RESET: Input used to reset status flip-flops, set the program counter to
zero, and force the UPI-C42 from the suspend power down mode.
RESET is also used during EPROM programming and verification.
SS
23
SINGLE STEP: Single step input used in conjunction with the SYNC output
to step the program through each instruction (EPROM). This should be tied
to a 5V when not used. This pin is also used to put the device in Sync
Mode by applying 12.5V to it.
CS
24
CHIP SELECT: Chip select input used to select one UPI microcomputer
out of several connected to a common data bus.
EA
25
RD
26
READ: I/O read input which enables the master CPU to read data and
status words from the OUTPUT DATA BUS BUFFER or status register.
A0
10
27
WR
10
11
28
WRITE: I/O write input which enables the master CPU to write data and
command words to the UPI INPUT DATA BUS BUFFER.
SYNC
11
13
29
OUTPUT CLOCK: Output signal which occurs once per UPI instruction
cycle. SYNC can be used as a strobe for external circuitry; it is also used to
synchronize single step operation.
D0 D7
(BUS)
12 19
14 21
30 37
I/O
P10 P17
27 34
30 33
35 38
2 10
I/O
PORT 1: 8-bit, PORT 1 quasi-bidirectional I/O lines. P10 P17 access the
signature row and security bit.
UPI-C42/UPI-L42
PLCC
Pin
No.
QFP
Pin
No.
21 24
35 38
24 27
39 42
PROG
25
VCC
Symbol
Type
39 42
11, 13 15
I/O
28
43
I/O
40
44
17
VDD
26
29
VSS
20
22
38
P20 P27
290414 4
UPI-C42/UPI-L42
Package
80C42
N, P S
82C42PC
82C42PD
82C42PE
N, P, S
N, P, S
N, P, S
87C42
N, P, S
ROM
OTP
4K
Comments
ROM Device
Phoenix MultiKey/42 firmware, PS/2 style mouse support
Phoenix MultiKey/42L firmware, KBC and SCC for portable apps.
Phoenix MultiKey/42G firmware, Energy Efficient KBC solution
4K
Package
80L42
N, P S
82L42PC
82L42PD
N, P, S
N, P, S
87L42
N, P, S
ROM
OTP
4K
Comments
ROM Device
Phoenix MultiKey/42 firmware, PS/2 style mouse support
Phoenix MultiKey/42L firmware, KBC and SCC for portable apps.
4K
UPI-C42/UPI-L42
290414 5
2. 8 Bits of Status
ST7 ST6 ST5 ST4 F1 F0 IBF OBF
D7 D6 D5 D4 D3 D2 D1 D0
ST4 ST7 are user definable status bits. These
bits are defined by the MOV STS, A single
byte, single cycle instruction. Bits 47 of the
acccumulator are moved to bits 47 of the status
register. Bits 03 of the status register are not
affected.
MOV STS, A
1
D7
290414 7
Op Code: 90H
0
D0
EN FLAGS
Op Code: 0F5H
D7
1
D0
290414 6
290414 8
UPI-C42/UPI-L42
If EN DMA has been executed, P27 becomes
the DACK (DMA ACKnowledge) pin. This pin acts
as a chip select input for the Data Bus Buffer
registers during DMA transfers.
EN DMA
Op Code: 0E5H
D7
D0
6. When EA is enabled on the UPI, the program
counter is placed on Port 1 and the lower four
bits of Port 2 (MSB e P23, LSB e P10). On the
UPI this information is multiplexed with PORT
DATA (see port timing diagrams at end of this
data sheet).
7. The UPI-C42 supports the Quick Pulse Programming Algorithm, but can also be programmed
with the Intelligent Programming Algorithm. (See
the Programming Section.)
UPI-C42 FEATURES
Programmable Memory Size Increase
The user programmable memory on the UPI-C42 will
be increased from the 2K available in the NMOS
product by 2X to 4K. The larger user programmable
memory array will allow the user to develop more
complex peripheral control micro-code. P2.3 (port 2
bit 3) has been designated as the extra address pin
required to support the programming of the extra 2K
of user programmable memory.
The new instruction SEL PMB1 (73h) allows for access to the upper 2K bank (locations 20484095).
The additional memory is completely transparent to
users not wishing to take advantage of the extra
memory space. No new commands are required to
access the lower 2K bytes. The SEL PMB0 (63h)
has also been added to the UPI-C42 instruction set
to allow for switching between memory banks.
290414 30
INTERRUPT ROUTINES
Interrupts always vector the program counter to location 3 or 7 in the first 2K bank, and bit 11 of the
program counter is held at 0 during the interrupt
service routine. The end of the service routine is signaled by the execution of an RETR instruction. Interrupt service routines should therefore be contained
entirely in the lower 2K words of program memory.
The execution of a SEL PMB0 or SEL PMB1 instruction within an interrupt routine is not recommended
since it will not alter PC11 while in the routine, but
will change the internal flip-flop.
UPI-C42/UPI-L42
thereby providing additional user programmable
memory space. This feature is enabled by the
A20EN instruction and remains enabled until the device is reset. It is important to note that the execution of the A20EN instruction redefines Port 2, bit 1
as a pure output pin with read only characteristics.
The state of this pin can be modified only through a
valid D1 command sequence (see Table 1). Once
enabled, the A20 logic will process a D1 command sequence (write to output port) by setting/resetting the A20 bit on port 2, bit 1 (P2.1) without
requiring service from the internal CPU. The host
can directly control the status of the A20 bit. At no
time during this host interface transaction will the
IBF flag in the status register be activated. Table 1
gives several possible GATEA20 command/data sequences and UPI-C42 responses.
Table 1. D1 Command Sequences
A0 R/W DB Pins IBF A20
Comments
SUSPEND
The execution of the suspend instruction (82h or
E2h) causes the UPI-C42 to enter the suspend
mode. In this mode of operation the oscillator is not
running and the internal CPU operation is stopped.
The UPI-C42 consumes s 40 mA in the suspend
mode. This mode can only be exited by RESET.
CPU operation will begin from PC e 000h when the
UPI-C42 exits from the suspend power down mode.
1
0
1
W
W
W
D1h
DFh
FFH(2)
0
0
0
1
0
1
W
W
W
D1h
DDh
FFh
0
0
0
n
0
n
1
1
0
1
W
W
W
W
D1h
D1h
DFh
FFh
0
0
0
0
n
n
1
n
1
1
0
W
W
W
D1h
XXh(3)
DDh
0
1
1
n
n
n
Invalid Sequence
No Change in State
of A20 Bit
NOTES:
1. Indicates that P2.1 remains at the previous logic level.
2. Only FFh commands in a valid A20 sequence have no
effect on IBF. An FFh issued at any other time will activate
IBF.
3. Any command except D1.
UPI-C42/UPI-L42
Table 2 covers all suspend mode pin states. In addition to the suspend power down mode, the UPI-C42
will also support the NMOS power down mode as
outlined in Chapter 4 of the UPI-42AH users manual.
Tristate
Weak Pull-Up
Disabled
Normal
Normal
Macname MACRO
DB 63H
ENDM
Suspend
System Control
(RD, WR,
CS, A0)
Disabled
Reset
Enabled
Crystal Osc.
(XTAL1, XTAL2)
Disabled
New Instructions
The following is a list of additions to the UPI-42 instruction set. These instructions apply only to the
UPI-C42. These instructions must be added to existing code in order to use any new functionality.
Test 0, Test 1
Disabled
Prog
High
Sync
High
EA
Disabled,
No Pull-Up
PC Bit 11 is set to zero on next JMP or CALL instruction. All references to program memory fall within
the range of 0 2047 (0 7FFh).
SS
Disabled,
Weak Pull-Up
k 40 mA
OPCODE
ICC
NOTES:
1. DBB outputs are Tristate unless CS and RD are active. DBB inputs are disabled unless CS and WR are
active.
2. A disabled input will not cause current to be drawn
regardless of input level (within the supply range).
3. Weak pull-ups have current capability of typically 5 mA.
PC Bit 11 is set to one on next JMP or CALL instruction. All references to program memory fall within
the range of 2048 4095 (800h FFFh).
ENA20 Enables Auto A20 hardware
OPCODE
UPI-C42/UPI-L42
This circuitry gives the host direct control of port 2
bit 1 (P2.1) without intervention by the internal CPU.
When this opcode is executed, P2.1 becomes a dedicated output pin. The status of this pin is read-able
but can only be altered through a valid D1 command sequence (see Table 1).
XTAL 2
Clock Input
Reset
Test 0
EA
OPCODE
(E2h)
BUS
P2023
Address Input
Pin
Function
VDD
PROG
WARNING
An attempt to program a missocketed UPI-C42 will result in
severe damage to the part. An indication of a properly
socketed part is the appearance of the SYNC clock output.
The lack of this clock may be used to disable the programmer.
UPI-C42/UPI-L42
flow chart of the Quick-Pulse Programming Algorithm is shown in Figure 6.
The entire sequence of program pulses and byte
verifications is performed at VCC e 6.25V and
VDD e 12.75V. When programming has been completed, all bytes should be compared to the original
data with VCC e VDD e 5V.
A verify should be performed on the programmed
bits to ensure that they have been correctly programmed. The verify is performed with T0 e 5V,
VDD e 5V, EA e 12.75V, SS e 5V, PROG e 5V,
A0 e 0V, and CS e 5V.
In addition to the Quick-Pulse Programming Algorithm, the UPI-C42 OPT is also compatible with Intels Inteligent Programming Algorithm which is used
to program the NMOS UPI-42AH OTP devices.
The entire sequence of program pulses and byte
verifications is performed at VCC e 6.25V and
VDD e 12.75V. When the inteligent Programming
cycle has been completed, all bytes should be compared to the original data with VCC e 5.0, VDD e
5V.
Verify
A verify should be performed on the programmed
bits to determine that they have been correctly programmed. The verify is performed with T0 e 5V,
VDD e 5V, EA e 12.75V, SS e 5V, PROG e 5V,
A0 e 0V, and CS e 5V.
SECURITY BIT
290414 14
10
UPI-C42/UPI-L42
b. Apply access code to appropriate inputs to put
the device into security mode.
c. Apply high voltage to EA and VDD pins.
d. Follow the programming procedure as per the
Quick-Pulse Programming Algorithm with known
data on the databus. Not only the security bit, but
also the security byte of the signature row is programmed.
e. Verify that the security byte of the signature
mode contains the same data as appeared on
the data bus. (If DB0DB7 e high, the security
byte will contain FFH.)
f. Read two consecutive known bytes from the
EPROM array and verify that the wrong data are
retrieved in at least one verification. If the
EPROM can still be read, the security bit may
have not been fully programmed though the security byte in the signature mode has.
Verification
Since the security bit address overlaps the address
of the security byte of the signature mode, it can be
used to check indirectly whether the security bit has
been programmed or not. Therefore, the security bit
verification is a mere read operation of the security
byte of the signature row (0FFH e security bit programmed; 00H e security bit unprogrammed). Note
that during the security bit programming, the reading
of the security byte does not necessarily indicate
that the security bit has been successfully programmed. Thus, it is recommended that two consecutive known bytes in the EPROM array be read and
the wrong data should be read at least once, because it is highly improbable that random data coincides with the correct ones twice.
SIGNATURE MODE
The UPI-C42 has an additional 64 bytes of EPROM
available for Intel and user signatures and miscellaneous purposes. The 64 bytes are partitioned as follows:
A. Test code/checksumThis can accommodate
up to 25 bytes of code for testing the internal
nodes that are not testable by executing from the
external memory. The test code/checksum is
present on ROMs, and OTPs.
B. Intel signatureThis allows the programmer to
read from the UPI-41AH/42AH/C42 the manufacturer of the device and the exact product
name. It facilitates automatic device identification
and will be present in the ROM and OTP versions. Location 10H contains the manufacturer
code. For Intel, it is 89H. Location 11H contains
the device code.
The code is 43H and 42H for the 8042AH/80C42
and OTP 8742AH/87C42, respectively. The
code is 44H for any device with the security bit
set by Intel.
C. User signatureThe user signature memory is
implemented in the EPROM and consists of 2
bytes for the customer to program his own signature code (for identification purposes and quick
sorting of previously programmed materials).
D. Test signatureThis memory is used to store
testing information such as: test data, bin number, etc. (for use in quality and manufacturing
control).
E. Security byteThis byte is used to check
whether the security bit has been programmed
(see the security bit section).
F. UPI-C42 Intel SignatureApplies only to
CHMOS device. Location 20H contains the manufacturer code and location 21H contains the device code. The Intel UPI-C42 manufacturers
code is 99H. The device IDs are 82H for the
OTP version and 83H for the ROM version. The
device IDs are the same for the UPI-L42.
The signature mode can be accessed by setting
P10 e 0, P11 P17 e 1, and then following the programming and/or verification procedures. The location of the various address partitions are as shown in
Table 3.
SYNC MODE
The Sync Mode is provided to ease the design of
multiple controller circuits by allowing the designer
to force the device into known phase and state time.
The Sync Mode may also be utilized by automatic
test equipment (ATE) for quick, easy, and efficient
synchronizing between the tester and the DUT (device under test).
Sync Mode is enabled when SS pin is raised to high
voltage level of a 12 volts. To begin synchronization, T0 is raised to 5 volts at least four clock cycles
after SS. T0 must be high for at least four X2 clock
cycles to fully reset the prescaler and time state
generators. T0 may then be brought down during
low state of X2. Two clock cycles later, with the rising edge of X2, the device enters into Time State 1,
Phase 1. SS is then brought down to 5 volts 4 clocks
later after T0. RESET is allowed to go high 5 tCY (75
clocks) later for normal execution of code.
11
UPI-C42/UPI-L42
Device
Type
No. of
Bytes
Test Code/Checksum
0
16H
0FH
1EH
ROM/OTP
25
Intel Signature
10H
11H
ROM/OTP
User Signature
12H
13H
OTP
Test Signature
14H
Security Byte
1FH
or
15H
ROM/OTP
3FH
ROM/OTP
20H
21H
ROM/OTP
22H
3EH
ROM/OTP
30
ACCESS CODE
The following table summarizes the access codes required to invoke the Sync Mode, Signature Mode,
and the Security Bit, respectively. Also, the programming and verification modes are included for
comparison.
Control Signals
Access Code
Data Bus
Modes
Port 2
T0 RST SS EA PROG VDD VCC 0
Programming
Mode
Verification
Mode
Sync Mode
Signature Prog
Mode
Verify
Security
Bit/Byte
Prog
Verify
1 HV
VDDH VCC
Address
Addr
Data In
Addr
1 HV
VCC VCC
Address
Addr
1 HV
VCC VCC
Data Out
Addr
STB
High
VCC VCC X
HV 0
VDDH VCC
Port 1
0 1 2 3 0 1 2 3 4 5 6 7
a0 a1 X X X X X X
a0 a1 X X X X X X
X X X X
X X X X X X X X
0 0 0
0 1 1 1 1 X X 1
Data In
0 0 0
1 HV
1 HV
VCC VCC
0 0 0
1 HV
VCC VCC
Data Out
0 0 0
1 HV
VDDH VCC
Address
0 0 0
Data In
0 0 0
1 HV
VCC VCC
Address
0 0 0
1 HV
VCC VCC
Data Out
0 0 0
NOTE:
1. a0 e 0 or 1; a1 e 0 or 1. a0 must e a1.
12
UPI-C42/UPI-L42
290414 15
Minimum Specifications
SYNC Operation Time, tSYNC e 3.5 XTAL 2 Clock cycles. Reset Time, tRS e 4 tCY.
NOTE:
The rising and falling edges of T0 should occur during low state of XTAL 2 clock.
APPLICATIONS
290414 12
290414 9
13
UPI-C42/UPI-L42
APPLICATIONS (Continued)
290414 10
290414 11
290414 13
14
UPI-C42/UPI-L42
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
DC CHARACTERISTICS
Symbol
VIL
Parameter
Input Low Voltage
UPI-C42
UPI-L42
Units
Min
Max
Min
Max
b 0.5
0.8
b 0.3
a 0.8
V
V
Notes
All Pins
VIH
2.0
VCC
2.0
VCC a 0.3
VIH1
3.5
VCC
2.0
VCC a 0.3
VOL
0.45
0.45
VOL1
0.45
0.45
VOL2
0.45
0.45
VOH
2.4
2.4
VOH1
2.4
2.4
IIL
g 10
g 10
mA
IOFL
g 10
g 10
mA
ILI
b 50 b 250 b 35
b 175
mA
Port Pins
Min VIN e 2.4V
Max VIN e 0.45V
ILI1
b 40
b 40
mA
VIN s VIL
IHI
5.0
mA
VCC e 3.0V
VIH e 5.0V
IDD
2.5
mA
IOH e b 50 mA UPI-C42
IOH e b 25 mA UPI-L42
15
UPI-C42/UPI-L42
DC CHARACTERISTICS
TA e 0 C to a 70 C, VCC e VDD e a 5V g 10%; a 3.3V g 10% UPI-L42 (Continued)
Symbol
ICC a IDD
UPI-C42
Parameter
Min
Max
UPI-L42
Min
Max
Units
Notes
Typical 14 mA UPI-C42,
9 mA UPI-L42
Osc. Off(1, 4)
30
20
mA
Suspend Mode
40
26
mA
IDD Standby
Power Down
Supply Current
3.5
mA
NMOS Compatible
Power Down Mode
IIH
100
100
mA
VIN e VCC
CIN
Input Capacitance
10
10
pF
TA e 25 C (1)
CIO
I/O Capacitance
20
20
pF
TA e 25 C (1)
NOTE:
1. Sampled, not 100% tested.
Parameter
Min
Max
Units
VDDH
12.5
13
V(1)
VDDL
4.75
5.25
VPH
2.0
5.5
VPL
b 0.5
0.8
VEAH
12.0
13.0
V(2)
VEAL
b 0.5
5.25
IDD
50.0
mA
IEA
1.0
mA(4)
NOTES:
1. Voltages over 13V applied to pin VDD will permanently damage the device.
2. VEAH must be applied to EA before VDDH and removed after VDDL.
3. VCC must be applied simultaneously or before VDD and must be removed simultaneously or after VDD.
4. Sampled, not 100% tested.
16
UPI-C42/UPI-L42
AC CHARACTERISTICS
TA e 0 C to a 70 C, VSS e 0V, VCC e VDD e a 5V g 10%; a 3.3V g 10% for the UPI-L42
NOTE:
All AC Characteristics apply to both the UPI-C42 and UPI-L42
DBB READ
Symbol
Parameter
Min
v
u
tAR
CS, A0 Setup to RD
tRA
tRR
RD Pulse Width
tAD
tRD
RD
tDF
RD
Max
ns
ns
160
Units
ns
130
ns
130
ns
85
ns
Max
Units
DBB WRITE
Symbol
Parameter
Min
0
tWA
v
CS, A0 Hold After WRu
tWW
WR Pulse Width
tDW
Data Setup to WR
tWD
tAW
CS, A0 Setup to WR
u
u
ns
ns
160
ns
130
ns
ns
17
UPI-C42/UPI-L42
AC CHARACTERISTICS
TA e 0 C to a 70 C, VSS e 0V, VCC e VDD e a 5V g 10%; a 3.3V g 10% for the UPI-L42 (Continued)
CLOCK
Min
Max
Units
tCY UPI-C42/UPI-L42
Symbol
Cycle Time
Parameter
1.2
9.20
ms(1)
tCYC UPI-C42/UPI-L42
Clock Period
80
613
ns
tPWH
30
tPWL
30
tR
10
ns
tF
10
ns
ns
ns
NOTE:
1. tCY e 15/f(XTAL)
AC CHARACTERISTICS
DMA
Symbol
Parameter
Min
tACC
DACK to WR or RD
tCAC
RD or WR to DACK
tACD
tCRQ
RD or WR to DRQ Cleared
Max
Units
ns
ns
130
ns
110
ns(1)
NOTE:
1. CL e 150 pF.
AC CHARACTERISTICS
PORT 2
Parameter
f(tCY)(3)
Min
tCP
1/15 tCY b 28
55
ns(1)
tPC
1/10 tCY
125
ns(2)
tPR
tPF
tDP
2/10 tCY
250
ns(1)
tPD
1/10 tCY b 80
45
ns(2)
tPP
6/10 tCY
750
ns
Symbol
NOTES:
1. CL e 80 pF.
2. CL e 20 pF.
3. tCY e 1.25 ms.
18
8/15 tCY b 16
0
Max
Units
650
ns(1)
150
ns(2)
UPI-C42/UPI-L42
Parameter
Min
tWD
u
u
Data in Setup Time to PROGv
Data in Hold Time after PROGu
tPW
tTW
4tCY
tWT
4tCY
tDO
tWW
tr, tf
tCY
tRE
tOPW
2.85
tDE
1tCY
tAW
4tCY
tWA
4tCY
tDW
Max
Units
105
ms
4tCY
4tCY
95
4tCY
4tCY
0.5
100
ms
2.5
3.75
ms
78.75
ms(1)
4tCY
NOTES:
1. This variation is a function of the iteration counter value, X.
2. If TEST 0 is high, tDO can be triggered by RESETu.
INPUT/OUTPUT
290414 16
290414 17
19
UPI-C42/UPI-L42
290414 18
LC OSCILLATOR MODE
L
C
NOMINAL
45 H 20 pF 5.2 MHz
120 H 20 pF 3.2 MHz
290414 19
NOTE:
See XTAL1 Configuration Table.
fe
1
2q0LC
C e
C a 3Cpp
2
Cpp j 5 10 pF
Pin-to-Pin Capacitance
290414 20
Each C Should be Approximately 20 pF, including Stray Capacitance.
C1
C2
C3
290414 21
5 pF (STRAY 5 pF)
(CRYSTAL a STRAY) 8 pF
20 30 pF INCLUDING STRAY
20
2) 10 KX Resistor
to Ground
Recommended configuration for
designs which will use both
NMOS and CHMOS parts. This
configuration limits the additional
current through the XTAL1 pin to
approximately 1 mA, while
maintaining compatibility with the
NMOS device.
3) Not Connected
Low power configuration
recommended for CHMOS only
designs to provide lowest
possible power consumption.
This configuration will not work
with the NMOS device.
UPI-C42/UPI-L42
WAVEFORMS
READ OPERATIONDATA BUS BUFFER REGISTER
290414 22
290414 23
CLOCK TIMING
290414 24
21
UPI-C42/UPI-L42
WAVEFORMS (Continued)
COMBINATION PROGRAM/VERIFY MODE
290414 25
NOTES:
1. A0 must be held low (0V) during program/verify modes.
2. For VIH, VIH1, VIL, VIL1, VDDH, and VDDL, please consult the D.C. Characteristics Table.
3. When programming the 87C42, a 0.1 mF capacitor is required across VDD and ground to suppress spurious voltage
transients which can damage the device.
VERIFY MODE
290414 26
NOTES:
1. PROG must float if EA is low.
2. PROG must float or e 5V when EA is high.
3. P10 P17 e 5V or must float.
4. P24 P27 e 5V or must float.
5. A0 must be held low during programming/verify modes.
22
UPI-C42/UPI-L42
WAVEFORMS (Continued)
DMA
290414 27
PORT 2
290414 28
290414 29
On the Rising Edge of SYNC and EA is Enabled, Port Data is Valid and can be Strobed. On the Trailing Edge of Sync
the Program Counter Contents are Available.
23
UPI-C42/UPI-L42
Description
ACCUMULATOR
ADD A, Rr
Add register to A
Add data memory
ADD A, @ Rr
to A
Add immediate to A
ADD A, data
ADDC A, Rr
Add register to A
with carry
Add data memory
ADDC A, @ Rr
to A with carry
ADDC A, data Add immediate
to A with carry
ANL A, Rr
AND register to A
AND data memory
ANL, A @ Rr
to A
ANL A, data
AND immediate to A
ORL A, Rr
OR register to A
OR data memory
ORL, A, @ Rr
to A
OR immediate to A
ORL A, data
XRL A, Rr
Exclusive OR register to A
Exclusive OR data
XRL A, @ Rr
memory to A
Exclusive OR immeXRL A, data
diate to A
INC A
Increment A
DEC A
Decrement A
CLR A
Clear A
CPL A
Complement A
DA A
Decimal Adjust A
SWAP A
Swap nibbles of A
RL A
Rotate A left
RLC A
Rotate A left through
carry
RR A
Rotate A right
RRC A
Rotate A right
through carry
INPUT/OUTPUT
IN A, Pp
Input port to A
OUTL Pp, A
Output A to port
ANL Pp, data AND immediate to
port
ORL Pp, data OR immediate to
port
IN A, DBB
Input DBB to A,
clear IBF
OUT DBB, A
Output A to DBB,
set OBF
MOV STS, A
A4 A7 to Bits 47 of
Status
MOVD A, Pp
Input Expander
port to A
MOVD Pp, A
Output A to
Expander port
ANLD Pp, A
AND A to Expander
port
ORLD Pp, A
OR A to Expander
port
24
Bytes
Cycles
Mnemonic
1
1
1
1
DATA MOVES
MOV A, Rr
MOV A, @ Rr
2
1
2
1
1
1
1
1
2
1
1
2
1
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
EN I
EN FLAGS
*SEL PMB0
*SEL PMB1
SEL RB0
SEL RB1
MOV A, data
MOV Rr, A
MOV @ Rr, A
MOV Rr, data
MOV @ Rr,
data
MOV A, PSW
MOV PSW, A
XCH A, Rr
XCH A,
@ Rr
XCHD A,
@ Rr
MOVP A,
@A
MOVP3, A,
@A
Description
Bytes
Cycles
Move register to A
Move data memory
to A
Move immediate to A
Move A to register
Move A to data
memory
Move immediate to
register
Move immediate to
data memory
Move PSW to A
Move A to PSW
Exchange A and
register
Exchange A and
data memory
Exchange digit of A
and register
Move to A from
current page
Move to A from
page 3
1
1
1
1
2
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TIMER/COUNTER
MOV A, T
Read Timer/Counter
MOV T, A
Load Timer/Counter
STRT T
Start Timer
STRT CNT
Start Counter
STOP TCNT
Stop Timer/Counter
EN TCNTI
Enable Timer/
Counter Interrupt
DIS TCNTI
Disable Timer/
Counter Interrupt
CONTROL
*EN A20
EN DMA
DIS I
* UPI-C42/UPI-L42 Only.
UPI-C42/UPI-L42
Description
CONTROL (Continued)
*SUSPEND Invoke Suspend Powerdown mode
NOP
No Operation
REGISTERS
INC Rr
Increment register
INC @ Rr
Increment data
memory
DEC Rr
Decrement register
SUBROUTINE
CALL addr
Jump to subroutine
RET
Return
RETR
Return and restore
status
FLAGS
CLR C
CPL C
CLR F0
CPL F0
CLR F1
CPL F1
Clear Carry
Complement Carry
Clear Flag 0
Complement Flag 0
Clear F1 Flag
Complement F1 Flag
Bytes
Cycles
1
1
1
1
2
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
Mnemonic
BRANCH
JMP addr
JMPP @ A
DJNZ Rr, addr
JC addr
JNC addr
JZ addr
JNZ addr
JT0 addr
JNT0 addr
JT1 addr
JNT1 addr
JF0 addr
JF1 addr
JTF addr
JNIBF addr
JOBF addr
JBb addr
Description
Bytes
Cycles
Jump unconditional
Jump indirect
Decrement register
and jump
Jump on Carry e 1
Jump on Carry e 0
Jump on A Zero
Jump on A not Zero
Jump on T0 e 1
Jump on T0 e 0
Jump on T1 e 1
Jump on T1 e 0
Jump on F0 Flag e 1
Jump on F1 Flag e 1
Jump on Timer Flag
e 1, Clear Flag
Jump on IBF Flag
e0
Jump on OBF Flag
e1
Jump on Accumulafor Bit
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
*UPI-C42/UPI-L42 Only.
REVISION SUMMARY
The following has been changed since Revision
-003:
1. Delete all references to standby power down
mode.
The following has been changed since Revision
-002:
1. Added information on keyboard controller product family.
2. Added IHI specification for the UPI-L42.
The following has been changed since Revision
-001:
1. Added UPI-L42 references and specification.
25