SG3525A

Pulse Width Modulator

Control Circuit
The SG3525A pulse width modulator control circuit offers
improved performance and lower external parts count when
implemented for controlling all types of switching power supplies.
The onchip +5.1 V reference is trimmed to
1% and the error
amplifier has an input commonmode voltage range that includes the
reference voltage, thus eliminating the need for external divider
resistors. A sync input to the oscillator enables multiple units to be
slaved or a single unit to be synchronized to an external system clock.
A wide range of deadtime can be programmed by a single resistor
connected between the CT and Discharge pins. This device also
features builtin softstart circuitry, requiring only an external timing
capacitor. A shutdown pin controls both the softstart circuitry and the
output stages, providing instantaneous turn off through the PWM latch
with pulsed shutdown, as well as softstart recycle with longer
shutdown commands. The under voltage lockout inhibits the outputs
and the changing of the softstart capacitor when VCC is below
nominal. The output stages are totempole design capable of sinking
and sourcing in excess of 200 mA. The output stage of the SG3525A
features NOR logic resulting in a low output for an offstate.

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MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648

SG3525AN
AWLYYWW

16

1
1
16
SOIC16L
DW SUFFIX
CASE 751G

16

SG3525A
AWLYYWW

1
1

Features

A
WL
YY
WW

8.0 V to 35 V Operation
5.1 V
1.0% Trimmed Reference
100 Hz to 400 kHz Oscillator Range
Separate Oscillator Sync Pin
Adjustable Deadtime Control
Input Undervoltage Lockout
Latching PWM to Prevent Multiple Pulses
PulsebyPulse Shutdown
Dual Source/Sink Outputs:
400 mA Peak
PbFree Packages are Available*

= Assembly Location
= Wafer Lot
= Year
= Work Week

PIN CONNECTIONS
Inv. Input

16 Vref

Noninv. Input

15 VCC

Sync

14 Output B

OSC. Output

13 VC

CT

12 Ground

RT

11 Output A

Discharge

10 Shutdown

SoftStart

Compensation

(Top View)

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005

January, 2005 Rev. 5

Publication Order Number:

SG3525A/D

SG3525A

16
Vref
15

Reference
Regulator

VCC
12

VC
13

To Internal
Circuitry

Under
Voltage
Lockout

Ground
OSC Output

NOR

4
3

Sync
RT

Output A

F/F

Oscillator

NOR

5
CT
Discharge

14
Output B

7
R
9

Compensation

11

INV. Input
2
Noninv. Input

Error
Amp
+

+
PWM

S
Latch

SG3525A Output Stage

50A
VREF

8
CSoftStart
10
Shutdown

5.0k

5.0k

Figure 1. Representative Block Diagram

ORDERING INFORMATION
Package

Shipping

SG3525AN

PDIP16

25 Units / Rail

SG3525ANG

PDIP16
(PbFree)

25 Units / Rail

SG3525ADW

SOIC16L

47 Units / Rail

SG3525ADWG

SOIC16L
(PbFree)

47 Units / Rail

SG3525ADWR2

SOIC16L

1000 Tape & Reel

SG3525ADWR2G

SOIC16L
(PbFree)

1000 Tape & Reel

Device

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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2

SG3525A
MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Rating

VCC

+40

Vdc

Collector Supply Voltage

VC

+40

Vdc

Logic Inputs

0.3 to +5.5

Analog Inputs

0.3 to VCC

500

mA

50

mA

5.0

mA

Output Current, Source or Sink

IO

Reference Output Current

Iref

Oscillator Charging Current

Power Dissipation
TA = +25C (Note 1)
TC = +25C (Note 2)

PD

mW
1000
2000

Thermal Resistance, JunctiontoAir

RJA

100

C/W

Thermal Resistance, JunctiontoCase

RJC

60

C/W

TJ

+150

Tstg

55 to +125

TSolder

+300

Operating Junction Temperature

Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Derate at 10 mW/C for ambient temperatures above +50C.
2. Derate at 16 mW/C for case temperatures above +25C.

RECOMMENDED OPERATING CONDITIONS

Characteristics

Symbol

Min

Max

Unit

Supply Voltage

VCC

8.0

35

Vdc

Collector Supply Voltage

VC

4.5

35

Vdc

Output Sink/Source Current

(Steady State)
(Peak)

IO
0
0

100
400

mA

Reference Load Current

Iref

20

mA

Oscillator Frequency Range

fosc

0.1

400

kHz

Oscillator Timing Resistor

RT

2.0

150

k

Oscillator Timing Capacitor

CT

0.001

0.2

F

Deadtime Resistor Range

RD

500

Operating Ambient Temperature Range

TA

+70

APPLICATION INFORMATION
Shutdown Options (See Block Diagram, page 2)

latch is immediately set providing the fastest turnoff signal

to the outputs; and a 150 A current sink begins to discharge
the external softstart capacitor. If the shutdown command
is short, the PWM signal is terminated without significant
discharge of the softstart capacitor, thus, allowing, for
example, a convenient implementation of pulsebypulse
current limiting. Holding Pin 10 high for a longer duration,
however, will ultimately discharge this external capacitor,
recycling slow turnon upon release.
Pin 10 should not be left floating as noise pickup could
conceivably interrupt normal operation.

Since both the compensation and softstart terminals

(Pins 9 and 8) have current source pullups, either can
readily accept a pulldown signal which only has to sink a
maximum of 100 A to turn off the outputs. This is subject
to the added requirement of discharging whatever external
capacitance may be attached to these pins.
An alternate approach is the use of the shutdown circuitry
of Pin 10 which has been improved to enhance the available
shutdown options. Activating this circuit by applying a
positive signal on Pin 10 performs two functions: the PWM

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3

SG3525A
ELECTRICAL CHARACTERISTICS (VCC = +20 Vdc, TA = Tlow to Thigh [Note 3], unless otherwise noted.)
Characteristics

Symbol

Min

Typ

Max

Unit

Reference Output Voltage (TJ = +25C)

Vref

5.00

5.10

5.20

Vdc

Line Regulation (+8.0 V VCC +35 V)

Regline

10

20

mV

Load Regulation (0 mA IL 20 mA)

Regload

20

50

mV

Temperature Stability

Vref/
T

20

mV

Vref

4.95

5.25

Vdc

Short Circuit Current (Vref = 0 V, TJ = +25C)

ISC

80

100

mA

Output Noise Voltage (10 Hz f 10 kHz, TJ = +25C)

Vn

40

200

Vrms

Long Term Stability (TJ = +125C) (Note 4)

20

50

mV/khr

2.0

6.0

REFERENCE SECTION

Total Output Variation Includes Line and Load Regulation over Temperature

OSCILLATOR SECTION (Note 5, unless otherwise noted.)

Initial Accuracy (TJ = +25C)
Frequency Stability with Voltage
(+8.0 V VCC +35 V)

fosc
DVCC

1.0

2.0

Frequency Stability with Temperature

fosc
DT

0.3

Minimum Frequency (RT = 150 k, CT = 0.2 F)

fmin

50

Hz

Maximum Frequency (RT = 2.0 k, CT = 1.0 nF)

fmax

400

kHz

Current Mirror (IRT = 2.0 mA)

1.7

2.0

2.2

mA

Clock Amplitude

3.0

3.5

Clock Width (TJ = +25C)

0.3

0.5

1.0

s

Sync Threshold

1.2

2.0

2.8

1.0

2.5

mA

Sync Input Current (Sync Voltage = +3.5 V)

ERROR AMPLIFIER SECTION (VCM = +5.1 V)
Input Offset Voltage

VIO

2.0

10

mV

Input Bias Current

IIB

1.0

10

A

Input Offset Current

IIO

1.0

A

DC Open Loop Gain (RL 10 M)

AVOL

60

75

dB

Low Level Output Voltage

VOL

0.2

0.5

High Level Output Voltage

VOH

3.8

5.6

Common Mode Rejection Ratio (+1.5 V VCM +5.2 V)

CMRR

60

75

dB

Power Supply Rejection Ratio (+8.0 V VCC +35 V)

PSRR

50

60

dB

Minimum Duty Cycle

DCmin

Maximum Duty Cycle

DCmax

45

49

Input Threshold, Zero Duty Cycle (Note 5)

Vth

0.6

0.9

Input Threshold, Maximum Duty Cycle (Note 5)

Vth

3.3

3.6

Input Bias Current

IIB

0.05

1.0

A

PWM COMPARATOR SECTION

3. Tlow = 0
Thigh = +70C
4. Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average
stability from lot to lot.
5. Tested at fosc = 40 kHz (RT = 3.6 k, CT = 0.01 F, RD = 0 ).

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4

SG3525A
ELECTRICAL CHARACTERISTICS (continued)
Characteristics

Symbol

Min

Typ

Max

Unit

SoftStart Current (Vshutdown = 0 V)

25

50

80

A

SoftStart Voltage (Vshutdown = 2.0 V)

0.4

0.6

Shutdown Input Current (Vshutdown = 2.5 V)

0.4

1.0

mA

0.2
1.0

0.4
2.0

18
17

19
18

7.0

8.0

SOFTSTART SECTION

OUTPUT DRIVERS (Each Output, VCC = +20 V)

Output Low Level
(Isink = 20 mA)
(Isink = 100 mA)

VOL

Output High Level

(Isource = 20 mA)
(Isource = 100 mA)

VOH

Under Voltage Lockout (V8 and V9 = High)

VUL

6.0

IC(leak)

200

A

Rise Time (CL = 1.0 nF, TJ = 25C)

tr

100

600

ns

Fall Time (CL = 1.0 nF, TJ = 25C)

tf

50

300

ns

Shutdown Delay (VDS = +3.0 V, CS = 0, TJ = +25C)

tds

0.2

0.5

s

Supply Current (VCC = +35 V)

ICC

14

20

mA

Collector Leakage, VC = +35 V (Note 6)

6. Applies to SG3525A only, due to polarity of output pulses.

Vref

16

PWM
ADJ.

13

Flip/
Flop

O
s
c
i
l
l
a
t
o
r

RT
6
Deadtime

1.5k
7

Ramp

0.009

100

Out A
11

1.0k, 1.0W
(2)

14

0.001

0.1

VC
0.1

Sync

1.0k

VCC
0.1

0.1

Clock

3.0k

15

Reference Regulator

Out B
Comp
10k
1 = VIO
2 = 1(+)
3 = 1()
1
2

V/I Meter
+

12

PWM

GND

0.01
50A

1
3

5.0F

5.0k

E/A
5.0k

1
2
3

Softstart

3
1
2
3

10

Vref
2.0k

DUT

Shutdown

Figure 2. Lab Test Fixture

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5

SG3525A
200
R D , DEAD TIME RESISTOR (
)

500

RT, TIMING RESISTOR (k )

100
50
* RD = 0 

20
10

5.0

RD *

RT

300
200
100

CT

2.0

0
2.0

5.0 10

20

50

100 200 500 1000 2000 5000 10,000

0.2

0.5

1.0

50

100 200

9
CP
RZ

RZ = 20 k

40
20
0
20
1.0

10

100

1.0 k

10 k

100 k

1.0 M

4.0
3.5
2.5
2.0
1.5

Source Sat, (VCVOH)

1.0
Sink Sat, (VOL)

0.5
0
0.01

10 M

VCC = +20 V
TJ = +25C

3.0

f, FREQUENCY (Hz)

0.02 0.03 0.05 0.07 0.1

0.2 0.3
0.5 0.7 1.0
IO, OUTPUT SOURCE OR SINK CURRENT (A)

Figure 5. Error Amplifier Open Loop

Frequency Response

Figure 6. Output Saturation

Characteristics

15

16

VCC
Q5

Q1

Q8
7.4k

Q6

3
Sync
7
Discharge
Q2

Q3

Q3

12
GND

20

Figure 4. Oscillator Discharge Time versus RD

60

CT

10

Figure 3. Oscillator Charge Time versus RT

80

RT

5.0

DISCHARGE TIME (s)

100

Vref

2.0

CHARGE TIME (s)

V sat , SATURATION VOLTAGE (V)

A VOL, VOLTAGE GAIN (dB)

400

2.0k

Q9
2.0k

Ramp
To PWM

14k
Q11

Q10

25k

5.0pF

Blanking
Q14 To Output

400A

Q4

23k
Q7
1.0k

1.0k

Q12

Q13
3.0k

Inverting
Q1
Input
1
Noninverting
Input
2
200A

250

Q4
Q2
To PWM
Comparator
100A

5.8V 30
9

Compensation

4
OSC Output

Figure 7. Oscillator Schematic

Figure 8. Error Amplifier Schematic

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6

SG3525A
13

VCC

VC
Q7

Q5

Q9

Q10

Q4

5.0k
Vref

11, 14
Q11 Output

Q8
Q6

2.0k
Q1

Q2

5.0k
Clock

10k

Q3

Q6 Omitted
in SG3527A

10k

F/F

PWM

Figure 9. Output Circuit

(1/2 Circuit Shown)
Q1

+Vsupply

To Output Filter

+Vsupply

R1

R1
R2

VC A

13
VC

SG3525A

11

GND

Q2
R3

In conventional pushpull bipolar designs, forward base drive is

controlled by R1R3. Rapid turnoff times for the power devices
are achieved with speedup capacitors C1 and C2.

For singleended supplies, the driver outputs are grounded.

The VC terminal is switched to ground by the totempole
source transistors on alternate oscillator cycles.

Figure 10. SingleEnded Supply

Figure 11. PushPull Configuration

+Vsupply

R1

Q1
11

Q1

14

C1

T1
T1

13
11
VC A
SG3525A

SG3525A
GND B

12

12

VC A

T1

Q1
R2
C2
14

14

GND

13

11

SG3525A

+Vsupply

C1

13

Q2
GND B
12

12

R1

T2

Q2
14
C2
R2

The low source impedance of the output drivers provides

rapid charging of power FET input capacitance while
minimizing external components.

Low power transformers can be driven directly by the SG3525A.

Automatic reset occurs during deadtime, when both ends of the
primary winding are switched to ground.

Figure 12. Driving Power FETS

Figure 13. Driving Transformers in a

HalfBridge Configuration

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7

SG3525A
PACKAGE DIMENSIONS
PDIP16
N SUFFIX
CASE 64808
ISSUE T

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.

A
16

S
T

SEATING
PLANE

H
G

16 PL

0.25 (0.010)

T A

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8

DIM
A
B
C
D
F
G
H
J
K
L
M
S

INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0

10

0.020 0.040

MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0

10

0.51
1.01

SG3525A
PACKAGE DIMENSIONS
SOIC16L
DW SUFFIX
CASE 751G03
ISSUE C

D
9

h X 45

0.25
1

16X
M

14X

T A

0.25

NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
DIM MIN
MAX
A
2.35
2.65
A1 0.10
0.25
B
0.35
0.49
C
0.23
0.32
D 10.15 10.45
E
7.40
7.60
e
1.27 BSC
H 10.05 10.55
h
0.25
0.75
L
0.50
0.90
q
0

7

A1

H
8X

16

SEATING
PLANE

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9

SG3525A

ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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Phone: 81357733850

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For additional information, please contact your

local Sales Representative.

SG3525A/D