CS010 308 LOGIC DESIGN LAB

INDEX
Experiment
No:

Name of Experiment

Familiarization of Logic Gates and Realization of

Logic Circuits using basic Gates

Design and implementation of Arithmetic

Circuits:- Half Adder, Full Adder, nbit
RippleCarry Adder, Carry Look ahead Adder,
BCD Adder

Study of Flip Flops:- implementation of RS, JK,

D, T and MS Flip Flops

Design and implementation of Synchronous and

Asynchronous Counters, UP/DOWN Counters

Design and Implementation of Shift Registers,

Counters using Shift Registers Ring Counter and
Johnson Counter

Study of Multiplexers , Demultiplexers, Encoder

and Decoder

Design of Comparators and Parity Generators.

Page No:

Experiment No:1
Familiarization of Logic Gates and Realization of Logic Circuits using basic Gates
1

CS010 308 LOGIC DESIGN LAB

AIM
To familiarize logic gates and realization of logic circuits using basic gates.
COMPONENTS REQUIRED
Item

Component Name

No:

2 input NAND GATE

IC 7400

2 input NOR GATE

IC 7402

INVERTER

IC7404

2 input AND GATE

IC 7408

2 input OR GATE

IC 7432

2 input XOR GATE

IC 7483

IC 747266

IC Trainer Kit

Connecting wires

As required

2 input XNOR GATE

LOGIC SYBOL AND TRUTH TABLE

Inverter

NAND

NOR

CS010 308 LOGIC DESIGN LAB

AND

OR

XOR

OUT

CS010 308 LOGIC DESIGN LAB

1

XNOR

THEORY
Inverter
An inverter or NOT gate is a logic gate which implements logical negation.
NAND Gate
NAND gate is a logic gate which produces an output that is false only if all its inputs are true;
thus its output is complement to that of the AND gate. A LOW (0) output results only if both the
inputs to the gate are HIGH (1); if one or both inputs are LOW (0), a HIGH (1) output results. A
universal gate is a gate which can implement any Boolean function without need to use any other
gate type. The NAND is an universal gate since all basic gates can be implanted using NAND
gate. An AND gate is typically implemented as a NAND gate followed by an inverter. NAND
gate can be used as an inverter with its inputs shorted.
NOR gate
A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or both input is
HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator. NOR
gates are so-called "universal gates" that can be combined to form any other kind of logic gate.
An OR gate is typically implemented as a NOR gate followed by an inverter.
AND gate
A HIGH output (1) results only if both the inputs to the AND gate are HIGH (1). If neither or only one
input to the AND gate is HIGH, a LOW output results.
OR gate

A HIGH output (1) results if one or both the inputs to the gate are HIGH (1). If neither input is
high, a LOW output (0) results.
4

CS010 308 LOGIC DESIGN LAB

PROCEDURE
1. Connections are made as per the circuit diagram
2. Switch on the power supply
3. Apply different combinations of inputs and observe the outputs; compare the outputs with
the truth tables
RESULT
Different logic gates are implemented and their truth tables are verified.
HALF ADDER

FULL ADDER

HALF ADDER USING NAND GATES

HALF ADDER USING NOR LOGIC

CS010 308 LOGIC DESIGN LAB

HALF SUBTRACTOR

FULL SUBTRACTOR

CS010 308 LOGIC DESIGN LAB

Experiment 2
DESIGN AND IMPLEMENTATION OF ARITHMETIC CIRCUITS
AIM
To design and implement arithmetic circuits such as
1. Half adder
2. Full adder
3. nbit RippleCarry Adder
4. Carry Look ahead Adder
5. BCD Adder

HALF ADDER

FULL ADDER

CS010 308 LOGIC DESIGN LAB

n bit ripple carry adder

4 bit carry look ahead adder

Ci=Gi+Pi.Ci
8

CS010 308 LOGIC DESIGN LAB

where
Gi= Ai.Bi
Pi= Ai+Bi = Ai
Sum

Si= C i-1
= Ci-1

Bi

Ai.Bi
Pi

BCD ADDER

CS010 308 LOGIC DESIGN LAB

PROCEDURE
1.Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. Note down the output readings for half/full adder and verify truth table.

10

CS010 308 LOGIC DESIGN LAB

Experiment No: 3

STUDY OF FLIP FLOPS

AIM
To implementat RS, JK, D, T and MS Flip Flops.
CIRCUIT DIAGRAM
SR Flipflop

TRUTHTABLE
S

CLK

INVALID

JK FLIPFLOP

11

CS010 308 LOGIC DESIGN LAB

CLK

T FLIPFLOP

Qn-1

CLK

Qn

D FLIPFLOP

12

CS010 308 LOGIC DESIGN LAB

CLK

MASTER SLAVE FLIPFLOP

CLK

PRE

CLR

13

CS010 308 LOGIC DESIGN LAB

Experiment No:4
COUNTERS
AIM
To design and implement Synchronous and Asynchronous Counters, UP/DOWN Counters
Up/Down counter
COMPONENTS REQUIRED
COMPONENT

SPECIFICATION

QUANTITY

JK FLIPFLOP

IC 7476

4 I/P AND GATE

IC 7411

OR GATE

IC 7432

XOR GATE

IC 7486

Nand gate

IC 7400

NOT GATE

IC 7404

ICTRAINER KIT
CONNECTION WIRES

As required

CIRCUIT DIAGRAM AND TRUTHTABLE

3 BIT SYNCHRONOUS UPCOUNTTER

14

CS010 308 LOGIC DESIGN LAB

2 BIT SYNCHRONOUSUPDOWN COUNTER

When M=1

WHEN M=0

15

CS010 308 LOGIC DESIGN LAB

3BIT ASYNCHRONOUS UPCOUNTER

16

CS010 308 LOGIC DESIGN LAB

3BIT ASYNCHRONOUS DOWN COUNTER

17

CS010 308 LOGIC DESIGN LAB

2 BIT ASYNCHRONOUS UPDOWNCOUNTER

PROCEDURE
18

CS010 308 LOGIC DESIGN LAB

1. Connections are done as per circuit diagram
2. Switch on the power supply
3. Logical inputs are given as per circuit diagram
4. Observe the output and verify the truthtable

SHIFT REGISTERS, COUNTERS USING SHIFT REGISTERS

AIM
To Design and Implement Shift Registers, Counters using Shift Registers Ring Counterand
Johnson Counter
COMPONENT
D FLIPFLOP

SPECIFICATION

QUANTITY

IC 7474

ICTRAINER KIT
CONNECTION WIRES

As required

CIRCUIT DIAGRAM AND TRUTHTABLE

SISO
19

CS010 308 LOGIC DESIGN LAB

SIPO

PISO

PIPO

RING COUNTER

20

CS010 308 LOGIC DESIGN LAB

JOHNSON COUNTER

21

CS010 308 LOGIC DESIGN LAB

PROCEDURE
1. Connections are made as per circuit diagram
2. Switch on power supply
3. Apply clock pulse and note output after each clock pulse
THEORY
Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a
group of D flip-flops connected in a chain so that the output from one flip-flop becomes the input
of the next flip-flop. All the flip-flops are driven by a common clock, and all are set or reset
simultaneously.
Shift registers can be classified according to the way the input data are read in and the
way the output data are readout. There are four types of shift registers:
1. Serial-In-Serial-Out.
2. Serial-In-Parallel-Out.
22

CS010 308 LOGIC DESIGN LAB

3. Parallel-In-Serial-Out.
4. Parallel-In-Parallel-Out.
1. Serial-In-Serial-Out
A basic Serial-In-Serial-Out four-bit shift register can be constructed using four D flip-flops.
1.The register is first cleared, forcing all four outputs of the flip flops to zero.
2. The input data is then applied sequentially to the D input of the first flip-flop on the left.
3. During each clock pulse, one bit is transmitted from left to right. Assume a data word to
be 1001. The least significant bit of the data has to be shifted through the register
2. Serial-In-Parallel-Out
In this type of registers, data bits are entered serially, but outputs are obtained
simultaneously from each flip-flop. Once the data are stored, each bit appears on its respective
output line, and all bits are available at the same time.
3. Parallel-In-Serial-Out
In Parallel-in-Serial-Out shift register, all data bits are available at the shift register inputs
simultaneously but are read out in series (bit by bit). The write / shift input will determine wither
that parallel data is being read in or the data is being shifted in series. If write / shift is 0, then the
data is written to the register in parallel (simultaneously). If write / shift is 1, the data is shifted in
series and the output is read at Q3.

4.Parallel-In-Parallel-Out
For Parallel-in-Parallel-Out shift registers, all data bits appear on the parallel outputs
immediately following the simultaneous entry of the data bits.

23

CS010 308 LOGIC DESIGN LAB

Experiment No:6
STUDY OF MULTIPLEXERS , DEMULTIPLEXERS, ENCODER AND DECODER
AIM
To study about Multiplexers , Demultiplexers, Encoder and Decoder

4x1 MUX

24

CS010 308 LOGIC DESIGN LAB

1X4 DEMULTIPLEXER

25

CS010 308 LOGIC DESIGN LAB

INPUTS

OUTPUTS

Data

Y0

Y1

Y2

Y3

26

CS010 308 LOGIC DESIGN LAB

INPUTS

OUTPUTS

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

2X4 DECODER

27

CS010 308 LOGIC DESIGN LAB

THEORY

Experiment no:7
COMPARATORS AND PARITY GENERATORS
AIM
To design Comparators and Parity Generators.
Item

Component Name

No:

Inverter

IC7404

2 input and GATE

IC 7408

2 input OR GATE

IC 7432

1
28

CS010 308 LOGIC DESIGN LAB

2 input XOR GATE

IC 7483

IC 747266

IC Trainer Kit

Connecting wires

As required

2 input XNOR GATE

CIRCUIT DIAGRAM AND TRUTH TABLE

ONE BIT COMPARATOR

EVEN PARITY GENERATOR

29

CS010 308 LOGIC DESIGN LAB

ODD PARITY GENERATOR

IC PIN CONFIGURATION
IC 7400- NAND GATE

30

CS010 308 LOGIC DESIGN LAB

IC 7402- NOR GATE

IC7404-Inverter

IC 7408-AND GATE

31

CS010 308 LOGIC DESIGN LAB

IC 7432- OR GATE

IC -7483 XOR gate

IC 747266-XNOR

32

CS010 308 LOGIC DESIGN LAB

7410- 3 INPUT NAND GATE

7427- 3 I/P NOR

33

CS010 308 LOGIC DESIGN LAB

74151-8x1 MUX

IC 7476-JK FLIPFLOP

34

CS010 308 LOGIC DESIGN LAB

IC 7474 DFLIPFLOP

35

CS010 308 LOGIC DESIGN LAB

Implementation of basic gates using universal gates

36

CS010 308 LOGIC DESIGN LAB

A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1),
a LOW output (0) results. NOR is the result of the negation of the OR operator. It can also be seen
as an AND gate with all the input

37

CS010 308 LOGIC DESIGN LAB

38