10/19/2015

UsingSystemVerilogAssertionsinRTLCode
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Using SystemVerilog Assertions in RTL Code

ByMichaelSmith,
DoulosLtd.
Introduction
SystemVerilogisasetofextensionstotheVeriloghardwaredescription
languageandisexpectedtobecomeIEEEstandard1800laterin2005.
SystemVerilogAssertions(SVA)formanimportantsubsetof
SystemVerilog,andassuchmaybeintroducedintoexistingVerilogand
VHDLdesignflows.
Assertionsareprimarilyusedtovalidatethebehaviorofadesign.("Isit
workingcorrectly?")Theymayalsobeusedtoprovidefunctionalcoverage
informationforadesign("Howgoodisthetest?").Youcanaddassertions
toyourRTLcodeasyouwriteit"theseform"activecomments"that
documentwhatyouhavewrittenandwhatassumptionsyouhavemade.
Assertionsmayalsobeusedasaformalspecificationlanguage,making
therequirementsclearandunambiguous,andmakingitpossibleto
automatevalidationofthedesignagainstthespecification.

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InSystemVerilogtherearetwokindsofassertion:immediate(assert)
andconcurrent(assertproperty).Coveragestatements(coverproperty)
areconcurrentandhavethesamesyntaxasconcurrentassertions,asdo
assumepropertystatements,whichareprimarilyusedbyformaltools.
Finally,expectisaproceduralstatementthatchecksthatsomespecified
activity(property)occurs.Thethreetypesofconcurrentassertion
statementandtheexpectstatementmakeuseofsequencesthatdescribe
thedesign"stemporalbehavior"i.e.behaviorovertime,asdefinedby
oneormoreclocks.
ImmediateAssertions
Immediateassertionsareproceduralstatementsandaremainlyusedin
simulation.Anassertionisbasicallyastatementthatsomethingmustbe
true,similartotheifstatement.Thedifferenceisthatanifstatement
doesnotassertthatanexpressionshouldbetrue,itsimplychecksthatit
istrue,e.g.:
if(A==B)...//SimplychecksifAequalsB
assert(A==B);//AssertsthatAequalsBifnot,anerrorisgenerated
IftheconditionalexpressionoftheimmediateassertevaluatestoX,Zor
0,thentheassertionfailsandthesimulatorwritesanerrormessage.
Animmediateassertionmayincludeapassstatementand/orafail
statement.Inourexamplethepassstatementisomitted,sonoactionis
takenwhentheassertexpressionistrue.Ifthepassstatementexists:
assert(A==B)$display("OK.AequalsB");

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itisexecutedimmediatelyaftertheevaluationoftheassertexpression.
Thestatementassociatedwithanelseiscalledafailstatementandis
executediftheassertionfails:

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Youmayomitthepassstatementyetstillincludeafailstatement:
assert(A==B)else$error("It'sgonewrong");
Thefailureofanassertionhasaseverityassociatedwithit.Thereare
threeseveritysystemtasksthatcanbeincludedinthefailstatementto
specifytheseveritylevel:$fatal,$error(thedefaultseverity)and
$warning.Inaddition,thesystemtask$infoindicatesthattheassertion
failurecarriesnospecificseverity.
Herearesomeexamples:
ReadCheck:assert(data==correct_data)
else$error("memoryreaderror")
Igt10:assert(I>10)
else$warning("Ihasexceeded10");
ThepassandfailstatementscanbeanylegalSystemVerilogprocedural
statement.Theycanbeused,forexample,towriteoutamessage,setan
errorflag,incrementacountoferrors,orsignalafailuretoanotherpart
ofthetestbench.
AeqB:assert(a==b)
elsebeginerror_count++;$error("AshouldequalB");end
ConcurrentAssertions
Thebehaviorofadesignmaybespecifiedusingstatementssimilarto
these:
"TheReadandWritesignalsshouldneverbeassertedtogether."
"ARequestshouldbefollowedbyanAcknowledgeoccurringnomorethan
twoclocksaftertheRequestisasserted."
Concurrentassertionsareusedtocheckbehaviorsuchasthis.Theseare
statementsthatassertthatspecifiedpropertiesmustbetrue.Forexample,
assertproperty(!(Read&&Write));
assertsthattheexpressionRead&&Writeisnevertrueatanypoint
duringsimulation.
Propertiesareoftenbuiltusingsequences.Forexample,
assertproperty(@(posedgeClock)Req|>##[1:2]Ack);
whereReqisasimplesequence(it"sjustabooleanexpression)and##
[1:2]Ackisamorecomplexsequenceexpression,meaningthatAckis
trueonthenextclock,orontheonefollowing(orboth).|>isthe
implicationoperator,sothisassertionchecksthatwheneverReqis
asserted,Ackmustbeassertedonthenextclock,orthefollowingclock.
Concurrentassertionslikethesearecheckedthroughoutsimulation.They
usuallyappearoutsideanyinitialoralwaysblocksinmodules,interfaces
andprograms.(Concurrentassertionsmayalsobeusedasstatementsin
initialoralwaysblocks.Aconcurrentassertioninaninitialblockisonly
testedonthefirstclocktick.)
Thefirstassertionexampleabovedoesnotcontainaclock.Thereforeitis
checkedateverypointinthesimulation.Thesecondassertionisonly
checkedwhenarisingclockedgehasoccurredthevaluesofReqandAck
aresampledontherisingedgeofClock.
Implication
Theimplicationconstruct(|>)allowsausertomonitorsequencesbased

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onsatisfyingsomecriteria,e.g.attachapreconditiontoasequenceand
evaluatethesequenceonlyiftheconditionissuccessful.Thelefthandside
operandoftheimplicationiscalledtheantecedentsequenceexpression,
whiletherighthandsideiscalledtheconsequentsequenceexpression.
Ifthereisnomatchoftheantecedentsequenceexpression,implication
succeedsvacuouslybyreturningtrue.Ifthereisamatch,foreach
successfulmatchoftheantecedentsequenceexpression,theconsequent
sequenceexpressionisseparatelyevaluated,beginningattheendpointof
thematch.
Therearetwoformsofimplication:overlappedusingoperator|>,and
nonoverlappedusingoperator|=>.
Foroverlappedimplication,ifthereisamatchfortheantecedentsequence
expression,thenthefirstelementoftheconsequentsequenceexpression
isevaluatedonthesameclocktick.
s1|>s2;
Intheexampleabove,ifthesequences1matches,thensequences2must
alsomatch.Ifsequences1doesnotmatch,thentheresultistrue.
Fornonoverlappedimplication,thefirstelementoftheconsequent
sequenceexpressionisevaluatedonthenextclocktick.
s1|=>s2;
Theexpressionaboveisbasicallyequivalentto:
"definetrue1
s1##1"true|>s2;
where`trueisabooleanexpression,usedforvisualclarity,thatalways
evaluatestotrue.
PropertiesandSequences
Intheexampleswehavebeenusing,thepropertiesbeingassertedare
specifiedintheassertpropertystatementsthemselves.Propertiesmay
alsobedeclaredseparately,forexample:
propertynot_read_and_write;
!(Read&&Write);
endproperty
assertproperty(not_read_and_write);
Complexpropertiesareoftenbuiltusingsequences.Sequences,too,may
bedeclaredseparately:
sequencerequest
Req;
endsequence
sequenceacknowledge
##[1:2]Ack;
endsequence
propertyhandshake;
@(posedgeClock)request|>acknowledge;
endproperty
assertproperty(handshake);
AssertionClocking
Concurrentassertions(assertpropertyandcoverpropertystatements)
useageneralizedmodelofaclockandareonlyevaluatedwhenaclock
tickoccurs.Infact,thevaluesofthevariablesinthepropertyaresampled
rightattheendoftheprevioustimestep.Everythinginbetweenclock
ticksisignored.ThismodelofexecutioncorrespondstothewayaRTL
descriptionofadesignisinterpretedaftersynthesis.
Aclocktickisanatomicmomentintimeandaclockticksonlyonceat
anysimulationtime.Theclockcanactuallybeasinglesignal,agated

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clock(e.g.(clk&&GatingSig))orothermorecomplexexpression.When
monitoringasynchronoussignals,asimulationtimestepcorrespondstoa
clocktick.
Theclockforapropertycanbespecifiedinseveralways,ofwhichthe
mostcommonare:
Theclockisexplicitlyspecifiedintheproperty:
propertyp;
@(posedgeclk)a##1b;
endproperty
assertproperty(p);
Theclockisexplicitlyspecifiedintheconcurrentassertion:
assertproperty(@(posedgeclk)a##1b);
Theclockisinferredfromaproceduralblock:
propertyp;
a##1b;
endproperty
always@(posedgeclk)assertproperty(p);
HandlingAsynchronousResets
Inthefollowingexample,thedisableiffclauseallowsanasynchronous
resettobespecified.
propertyp1;
@(posedgeclk)disableiff(Reset)notb##1c;
endproperty
assertproperty(p1);
Thenotnegatestheresultofthesequencefollowingit.So,thisassertion
meansthatifResetbecomestrueatanytimeduringtheevaluationofthe
sequence,thentheattemptforp1isasuccess.Otherwise,thesequence
(b##1c)mustneverevaluatetotrue.
Sequences
Asequenceisalistofbooleanexpressionsinalinearorderofincreasing
time.Thesequenceistrueovertimeifthebooleanexpressionsaretrue
atthespecificclockticks.Theexpressionsusedinsequencesare
interpretedinthesamewayastheconditionofaproceduralifstatement.
Herearesomesimpleexamplesofsequences.The##operatordelays
executionbythespecifiednumberofclockingevents,orclockcycles.
//amustbetrueonthecurrentclocktick
//andbonthenextclocktick
a##Nb
//CheckbontheNthclocktickaftera
a##[1:4] //amustbetrueonthecurrentclocktickand
b
b
//onsomeclocktickbetweenthefirstand
fourth
//afterthecurrentclocktick
a##1b

The*operatorisusedtospecifyaconsecutiverepetitionofthelefthand
sideoperand.
a##1b[*3]##1
c
(a##2b)[*2]
(a##2b)[*1:3]

//Equiv.toa##1b##1b##1b##1
c
//Equiv.to(a##2b##1a##2b)
//Equiv.to(a##2b)
//or(a##2b##1a##2b)
//or(a##2b##1a##2b##1a
##2b)

The$operatorcanbeusedtoextendatimewindowtoafinite,but
unboundedrange.
a##1b[*1:$]##1c//E.g.abbbbc
The[>orgotorepetitionoperatorspecifiesanonconsecutivesequence.
a##1b[>1:3]##1c//E.g.a!bbb!b!bbc

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Thismeansaisfollowedbyanynumberofclockswherecisfalse,andb
istruebetweenoneandthreetimes,thelasttimebeingtheclockbeforec
istrue.
The[=ornonconsecutiverepetitionoperatorissimilartogotorepetition,
buttheexpression(binthisexample)neednotbetrueintheclockcycle
beforecistrue.
a##1b[=1:3]##1c//E.g.a!bbb!b!bb!b!bc
PuttingItAllTogether
Nowthatwehaveseenthebasicsyntax,let"slookatacoupleofpractical
examples.
"Arequest(reqhighforoneormorecyclesthenreturningtozero)is
followedafteraperiodofoneormorecyclesbyanacknowledge(ack
highforoneormorecyclesbeforereturningtozero).ackmustbezeroin
thecycleinwhichreqreturnstozero."
assertproperty(@(posedgeclk)disableiffreset
!req##1req[*1:$]##1!req
|>
!ack[*1:$]##1ack[*1:$]##1!ack);
"Afterarequest,ackmustremainhighuntilthecyclebeforegrantis
high.Ifgrantgoeshighonecycleafterreqgoeshighthenackneednot
beasserted."
assertproperty(@(posedgeclk)disableiffreset
$rose(req)|=>ack[*0:$]##1grant);
where$rose(req)istrueifreqhaschangedfrom0to1.
SummaryandConclusions
Inthistutorial,youhavelearntthebasicsyntaxoftheSystemVerilog
Assertionslanguage.Thisincludesimmediateandconcurrentassertions,
propertiesandsequences.Usingthese,youcanincrementallyadd
assertionstoyourRTLcode,whichmakesbugseasierandquickerto
detect,thusimprovingthequalityofyourdesigns.
FurtherInformation
Doulos'sModularSystemVerilogtrainingprogramprovidesfullscope
traininginSystemVerilogandincludesatrainingmodulespecificallyonthe
useofSystemVerilogassertions.Thecoursesincludefullsupportfor
Synopsystools,includingDesignCompilerandVCS.
PublicModularSystemVerilogclassesarescheduledintheUSAand
Europe,andteambasedtrainingisavailableworldwide.Datesand
locationscurrentlyscheduledarethese:
July26SanJose,CA,USA
Aug1Cambridge,UK
Sept26Austin,TX,USA
Oct17Munich,Germany
Nov14Cambridge,UK
Nov28SanJose,CA,USA
DoulosalsopublishestheSystemVerilogGoldenReferenceGuide,a
comprehensivequickreferencefortheentireSystemVeriloglanguage.A
newSystemVerilogAssertionsGoldenReferenceGuidewillbeavailable
laterintheyear.
AboutMichaelSmith
MichaelSmithisacofounderofDoulosLtd.andhasover20years
experienceintrainingandsupportingASICandFPGAdesignersintheuse
andapplicationofsimulationandsynthesislanguagesandtechnologies.
AboutDoulosLtd.
Doulosisthegloballeaderforthedevelopmentanddeliveryoftraining
solutionsforengineerscreatingtheworld"selectronicproducts.

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