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    Assignment 1

    Uploaded by

    Eren Yeager
    This document provides instructions for a lab task to design combinational logic circuits using Boolean expressions and Verilog modeling. Students are asked to: 1) Derive truth tables and simplify Boolean expressions for functions F and F' using K-maps and Boolean algebra. 2) Draw circuit diagrams implementing the expressions using AND-OR inversion, OR-AND inversion, NAND-NAND, and NOR-NOR logic. 3) Write Verilog code for the circuits and simulate the designs to validate the outputs match the truth tables. 4) Justify which circuit design uses the fewest logical elements.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Assignment 1

    Uploaded by

    Eren Yeager
    30 views3 pages
    This document provides instructions for a lab task to design combinational logic circuits using Boolean expressions and Verilog modeling. Students are asked to: 1) Derive truth tables and simplify Boolean expressions for functions F and F' using K-maps and Boolean algebra. 2) Draw circuit diagrams implementing the expressions using AND-OR inversion, OR-AND inversion, NAND-NAND, and NOR-NOR logic. 3) Write Verilog code for the circuits and simulate the designs to validate the outputs match the truth tables. 4) Justify which circuit design uses the fewest logical elements.

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    Assignment_1

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    This document provides instructions for a lab task to design combinational logic circuits using Boolean expressions and Verilog modeling. Students are asked to: 1) Derive truth tables and simplify Boolean expressions for functions F and F' using K-maps and Boolean algebra. 2) Draw circuit diagrams implementing the expressions using AND-OR inversion, OR-AND inversion, NAND-NAND, and NOR-NOR logic. 3) Write Verilog code for the circuits and simulate the designs to validate the outputs match the truth tables. 4) Justify which circuit design uses the fewest logical elements.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    30 views3 pages

    Assignment 1

    Uploaded by

    Eren Yeager
    This document provides instructions for a lab task to design combinational logic circuits using Boolean expressions and Verilog modeling. Students are asked to: 1) Derive truth tables and simplify Boolean expressions for functions F and F' using K-maps and Boolean algebra. 2) Draw circuit diagrams implementing the expressions using AND-OR inversion, OR-AND inversion, NAND-NAND, and NOR-NOR logic. 3) Write Verilog code for the circuits and simulate the designs to validate the outputs match the truth tables. 4) Justify which circuit design uses the fewest logical elements.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 3

    BECE 102P Digital system design TASK I QP

    LAB TASK I : Realization of Boolean expressions and Verilog modeling of


    Combinational Logic circuits.

    Question:

    Using Reg.no. formulate expressions in SOP and POS for F and F '.use K-Map and Bollean
    laws to simplify the expressions.Write a verilog code to implement F and F’ with a neat circuit
    diagram for all circuits designed using the following forms .

    a. SOP - AND-OR INV logic circuit

    b. POS - OR-AND-INV logic circuit

    c. SOP - NAND-NAND logic circuit

    d. POS - NOR-NOR logic circuit

    Use only two input logic elements for AND,OR,NAND,NOR logic gates.

    Calculate the number of two I/P NAND gates required to design. Providing the proof for
    Justifying your designed circuit requires less number of logical elements to obtain F and F’.

    Calculate the number of two I/P NOR gates required to design Justifying your circuit requires
    only fewer logical elements.

    1. Determine required number of inputs and outputs from the specifications.


    2. Derive the truth table for each of the outputs based on their relationships to the input.
    3. Simplify the Boolean expression for each output. Use Karnaugh-Maps, Laws of Boolean
    algebra.
    4. Draw a logic diagram that represents the simplified Boolean expression. Verify the design
    by analyzing or simulating the circuit.
    5. Write the Verilog code in BL,SL and DFL .
    6. Implement the Verilog code for the circuit in Modelsim and obtain the waveform for the
    expected truth table.
    7. Snip of output obtained with self-explanation of what value of input provided and what
    value of output obtained, validation of output.
    8. Write the aim, procedure, theory, pin diagram, block diagram, truth table Simulation
    output, inference and result.
    9. Write the test bench for testing the functionality of the code.

    *QP for BECE102P DSD TASK I to V and BECE102L Digital Assignment


    1 of 3
    BECE 102P Digital system design TASK I QP

    10. Write the need for real time application of the circuit designed.

    Contents sheet for TASK I to be included in the front sheet of VTOP TASK file document

    Sl.no. Components Page no., Student RA


    Check Check
    mark mark

    1 Aim ✔ ✔

    2 Components Required and Tools


    Required

    3 Procedure and Theory

    4 Pin diagram

    5 Truth Table

    6 SOP Boolean expression in canonical


    form

    7 POS Boolean expression in canonical


    form

    8 Boolean simplification using Boolean laws

    9 Boolean simplification using KMAP


    simplification

    10 Simplified SOP expression in Standard


    form

    11 Simplified POS expression in Standard


    form

    12 Circuit diagram using AOI logic

    13 Circuit diagram using OAI logic

    14 Circuit diagram using NAND logic

    15 Circuit diagram using NOR logic

    16 Multisim / Circuitverse.org Simulation


    link for SOP F and F’ circuit

    17 Multisim live / Circuitverse.org


    Simulation link for POS F and F’ circuit

    *QP for BECE102P DSD TASK I to V and BECE102L Digital Assignment


    2 of 3
    BECE 102P Digital system design TASK I QP

    18 Multisim live / Circuitverse.org


    Simulation link for NAND F and F’
    circuit

    19 Multisim live / Circuitverse.org


    Simulation link for NOR F and F’ circuit

    20 IC inter connection diagram for


    hardware connection in bread board

    21 Justification for optimized circuit NAND


    /NOR /XOR Logic

    22 Verilog code :SL

    23 Verilog code :BL

    24 Verilog code :DFL

    25 Verilog code :Conditional Operator

    26 Test Bench

    27 Snip of Output waveform with respective


    code

    28 Online Verilog code Simulation links

    29 Result

    30 Inference

    *QP for BECE102P DSD TASK I to V and BECE102L Digital Assignment


    3 of 3

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