ADITYA COLLEGE OF ENGINEERING

&
TECHNOLOGY
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

SWITCHING THEORY AND LOGIC DESIGN

LAB MANUAL

(R-19)

II-B.Tech : I-Sem
(ELECTRONICS & COMMUNICATION ENGINEERING)

ADITYA COLLEGE OF ENGINEERING & TECHNOLOGY

Permanently Affiliated to JNTUK, Kakinada, Approved by AICTE, New Delhi, Accredited by NAAC
Recognized by UGC under Section 2(f) of UGC Act 1956
AdityaNagar,ADB Road, Surampalem-533437,E.G.Dt.,PH: 0884-2326212,99591 76665
 CONTENTS
Exp.
Page.
No EXPERIMENT NAME
No

1. Verification of Truth Tables of Logic Gates. 1

2. Design a Simple Combinational Circuit with Four Variables,

6
Obtain Minimal Sop Expression and Verify the Truth Table

Verification of Functional Table Of 3 to 8 Line Decoder / De-

3. 8
Multiplexer

4. Four variable logic function using 8 To 1 Multiplexer. 11

5. Design Full Adder Circuit And Verify Its Functional Table. 14

Verification of Functional Tables of J K Edge Triggered Flip –Flop,

6. J K Master Slave Flip –Flop, D Flip Flop. 15

Design a Four Bit Ring Counter Using D Flip – Flops / JK Flip-flop

7. 19
and Verify Output.

Design a Four Bit Johnson’s Counter Using D Flip-Flops / JK Flip

22
8. Flops and Verify Output.
Verify the Operation of 4-Bit Universal Shift Register
9. 24
for Different Modes of Operation

10. Mod-8 Ripple Counter and Construct A Circuit Using T-Flip-Flops. 26

11. Mod-8 Synchronous Counter Circuit Using T-Flip-Flops. 28

A) One Bit Comparator.

12. 31
B) 7 Segment Display Circuit Using Decoder and 7-Segment Led.

13. 37
BCD Adder Circuit
IC74154 De-Multiplexer
14. 40
 Department of ECE

1. Verification of Truth Tables of Logic Gates

Aim: To study and verify the truth table of logic gates.

Two input (i) OR (ii) AND (iii) NOT (iv) NOR (v) NAND (vi) Exclusive OR
(vii) Exclusive NOR

Components Required:
1. Digital IC trainer kit.
2. IC 7408, IC 7404, IC 7400,IC 7432,IC 7406,IC 7402,IC 7486

3. Connecting wires.

Theory:
In the digital circuits, two discrete voltages are recognized as two logic levels, logic ‘1’ and
logic ‘0’. These are also known as ‘high’ and ‘low’ logic levels. Circuits that process digital signal
and take logical decisions are called logic gates. Each gate has two or more inputs and one output
terminal. The output wave form at any instant depends only upon the input waveform at that
instant. Such circuits are called combinational logic circuit. The logic gates Transistor Logic
(RTL), Diode Transistor Logic (DTL), Transistor Transistor Logic (TTL) and Emitter Coupled
Logic (ECL). The last two types are in wide use and are available in IC version. The three basic
logic gates are OR gate, AND gate, and NOT gate.

AND-Gate:
AND gate has two or more inputs and only one output. If the both the inputs are 1 the
output is 1. If any one of the inputs is 0 the output is 0. Thus the output of the AND Gate is equal
to the product of the input. The output can be expressed Y=A.B.

OR-Gate:
OR gate has two or more inputs and only one output. If the both the inputs are 1 the output
is 1. When both of the inputs are 0 the output is 0. Thus the output of the Or gate is equal to the
sum of the input. The output can be expressed as Y=A+B.

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NOT-Gate:
A NOT gate has only one input and one output. The NOT gate is also known as an Inverter
Gate or Complement. The output of the not gate is complement of input. The output can be
Expressed as Y=A’

NAND-Gate:
NAND gate has two or more inputs and only one output. The NAND operation also be
performed if a combination of an AND gate and a NOT gate. If any one of the input is 0 is the
output is 1. In all other cases the output is 0. The output can be expressed as Y=A.B.

NOR-Gate:
NOR gate has two or more inputs and only one output. The NOR operations can also be
Performed if a combination of an OR gate and a NOT gate. If any one of the input is 1 is the
Output is 0. In all other cases the output is 1. The output can be expressed as Y=A+B.

EX-OR Gate:

The output of an Exclusive-OR gate ONLY goes “HIGH” when its two input terminals are at
“DIFFERENT” logic levels with respect to each other.
An odd number of logic “1’s” on its inputs gives logic “1” at the output. These two inputs can
be at logic level “1” or at logic level “0” giving us the Boolean expression
of: Q = (A ⊕ B) = A.B + A.B

EX-NOR Gate:
Basically the “Exclusive-NOR” gate is a combination of the Exclusive-OR gate and the NOT
gate but has a truth table similar to the standard NOR gate in that it has an output that is normally
at logic level “1” and goes “LOW” to logic level “0” when ANY of its inputs are at logic level “1”.

However, an output “1” is only obtained if both of its inputs are at the same logic level, either
binary “1” or “0”. For example, “00” or “11”. This input combination would then give us the

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Pin Diagrams and Their Truth Tables:

AND Gate:

OR Gate: 7432

NOT Gate: 7404

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NAND gate: 7400

NOR Gate: 7402

EX-OR Gate:7486

EX-NOR Gate: 74266

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Procedure:

1. Check the components for their working.

2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Provide the input data via the input switches and observe the output on output LEDs
5. Tabulate the values for different input combinations.

Result:

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2. Design a Simple Combinational Circuit with Four Variables, Obtain

Minimal Sop Expression and Verify the Truth Table

Aim: Design and implement a simple combinational circuit with four variables and obtain
Minimal SOP expression and verify the truth table using Digital Trainer Kit.

Components Required:
1. Logic gates (IC) trainer kit.

2. Connecting patch chords.

3. IC 7408, IC 7404

Theory:

The minimization will result in reduction of the number of gates (resulting from less number
of terms) and the number of inputs per gate (resulting from less number of variables per term) • the
minimization will reduce cost, efficiency and power consumption.
The minimum sum of products (MSOP) of a function, f, is a SOP representation of f that
contains the fewest number of product terms and fewest number of literals of any SOP
representation of f.
Ex:f= (ABCD +A`BCD+ AB`CD+ …..) Is called sum of products. The + is sum operator
which is an OR gate. The product such as AB is an AND gate for the two inputs A and B.
SOP To minimal SOP:
F=∑ (4, 6, 12, 14)
F=A’BC’D’+A’BCD’+ABC’D’+ABCD’

F=BD’

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Functional Diagram:

Procedure:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Provide the input data via the input switches and observe the output on output LEDs
5. Tabulate the values for different input combinations.

Result:

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3. Verification of Functional Table Of 3 to 8 Line Decoder / De-Multiplexer

Aim: verify the truth table of 3 to 8 line Decoder/De-Multiplexer

Components Required:
1. Digital IC trainer Kit
2. Connecting patch cards
3. IC 74138, IC 74139

Theory:
This decoder circuit gives 8 logic outputs for 3 inputs and has a enable pin. The circuit is
designed with AND and NAND logic gates. It takes 3 binary inputs and activates one of the eight
outputs. 3 to 8 line decoder circuit is also called as binary to an octal decoder.
A de-multiplexer is a combinational logic circuit that receives the information on a single
input and transmits the same information over one of 2 n possible output lines. The bit
combinations of the select lines control the selection of specific output line to be connected to the
input at given instant.

Functional Diagram:
3 to 8 decoder: truth table:

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Pin Diagram(3 to 8 decoder):

Demultiplexer:

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truth table:

Pin Diagram:

Procedure:

1. Check the components for their working.

2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Provide the input data via the input switches and observe the output on output LEDs.
5. Tabulate the values for different input combinations.

Result:

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4. Four variable logic function using 8 To 1 Multiplexer.

Aim: To design and to observe the truth table of an 8:1 Multiplexer (MUX) using IC74153
(MUX).

Components Required:

1. IC 74151
2. Patch Cords & Single Lead Wires

3. Digital IC Trainer Kit.

Theory:
An 8-to-1 multiplexer consists of eight data inputs D0 through D7, three input select lines S2
through S0 and a single output line Y. Depending on the select lines combinations, multiplexer
decodes the inputs. The below figure shows the block diagram of an 8-to-1 multiplexer with enable
input that enable or disable the multiplexer. Since the number data bits given to the MUX are eight
then 3 bits (23=8) are needed to select one of the eight data bits. The truth table for an 8-to1
multiplexer is given below with eight combinations of inputs so as to generate each output corresponds
to input. For example, if S2= 0, S1=1 and S0=0 then the data output Y is equal to D2. Similarly the
data outputs D0 to D7 will be selected through the combinations of S2, S1 and S0 as shown in below
figure.

Functional diagram: truth table:

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Pin Diagram:

For a 4 variable function, there are 16 possible combinations. To implement 4 variable

function using 8:1 MUX, use 3 input as select lines of MUX and remaining 4th input and function
will determine its input of MUX. Let us demonstrate it with an example:

F(B,C,D,A) = Σ(1,5,7,9,10,11,12)

Truth Table for Given Function:

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Procedure:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Provide the input data via the input switches and observe the output on output LEDs.
5. Tabulate the values for different input combinations.

Result:

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5. Design Full Adder Circuit And Verify Its Functional Table.

Aim: To design full adder using logic gates and to verify the truth table.

Apparatus Required:
1. IC7486, IC7408, IC7432.
2. Digital IC Trainer Kit.
3. Patch Chords Single Lead Wires

Theory:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of
three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder
cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken
from OR gate.

Functional Diagram: truth table:

Procedure:

1. Verify the gates.

2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table. Note down
the output readings for half/full adder, Sum and the carry bit for different combinations of
inputs verify their truth tables.

Result:

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6. Verification of Functional Tables of J K Edge Triggered Flip –Flop

J K Master Slave Flip –Flop, D Flip Flop

Aim: To verify the truth table of J-K flip-flop-JK master Slave flip-flop, and D flip-flop.

Apparatus:

1. Digital IC Trainer kit.

2. Patch cards.
3. Single lead wires.
4. JK flip-flop IC7476,
5. D flip flop IC 7474

Theory:

JK Flip-Flop:

This simple JK flip Flop is the most widely used of all the flip-flop designs and is
considered to be a universal flip-flop circuit. The sequential operation of the JK flip flop is exactly
the same as for the previous SR flip-flop with the same “Set” and “Reset” inputs. The difference
this time is that the “JK flip flop” has no invalid or forbidden input states of the SR Latch even
when S and R are both at logic “1”.

The Master-Slave JK Flip-flop:

The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together

in a series configuration with the slave having an inverted clock pulse. The outputs from Q and Q
from the “Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the
“Master” flip flop being connected to the two inputs of the “Slave” flip flop. This feedback
configuration from the slave’s output to the master’s input gives the characteristic toggle of the JK
flip flop as shown in the circuit diagram.

Race-Around Condition In J-K Flip Flop:

Practically, we don’t get toggling. Since, clock pulse is more than the propagation delay, so
within one clock pulse the output will keep on toggling again and again and it may become
indeterminate. This is known as race around condition. Race Around condition occurs because of
the feedback connection.

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D (DELAY) FLIP-FLOP:

The D (Delay) flip-flop is used for storing the information. It is basically an RS flip-
flop with an inverter in the R input. Fig. shows a clocked D flip-flop. NAND gates 1 and 2 from a
basic RS flip-flop and gates 3 and 4 modify it into a clocked RS flip-flop. The D input is to the S
input and its complement through gate 5 is applied to the R input. The D flip-flop is often called a
‘delay flip-flop’. The word ‘delay’ describes what happens to the data or information at input D. In
other words, the data, i.e. 0 or 1 at the input D is delayed by one clock pulse from getting to output
Q.

Functional Diagram:
JK flip flop:

JK master slave flip flop:

D flip flop:

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IC Pin diagram:

NOT GATE:

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Truth Tables: JK Flip flop

Truth Tables: D Flip flop

Procedure:

1. Take the required flip flop IC and place on bread board

2. Connect the JK/D inputs to input switches.

3. Connect the outputs to output LEDS.

4. apply +5V DC power to Vcc and ground Pins of IC

5. Connect the clock and check outputs for each input combinations and tabulate the values.

Result:

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7. Design a Four Bit Ring Counter Using D Flip – Flops / JK Flip-

flop and Verify Output

Aim: verify the truth tables of 4 bit ring counter using D flip-flops

Components Required:

1. IC 7474/7476
2. IC Trainer kit
3. patch cards
4. single lead wires

Theory:
Ring counter is a typical application of Shift resister. Ring counter is almost same as the shift
counter. The only change is that the output of the last flip-flop is connected to the input of the first
flip-flop in case of ring counter but in case of shift resister it is taken as output. Except this all the
other things are same.

Functional diagram:
Four Bit Ring Counter Using D Flip – Flops

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Four Bit Ring Counter Using JK Flip – Flops

Truth Table:

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Procedure:
1. Take corresponding flip flop ICs as required quantity.

2. Place the ICs on trainer kit bread board and interconnect as per circuit diagram.

3. Apply DC power supply to VCC and GND pins of ICs

4. Connect all four outputs to output LEDs and clock from clock output of the kit.

5. And tabulate the output count by applying clock pulses.

Result:

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8. Design a Four Bit Johnson’s Counter Using D Flip-Flops / JK Flip

Flops and Verify Output

Aim: verify the truth tables of four bit Johnson’s counter using D Flip-flop/ JK Flip- flops

Components Required:

1.IC 7474/7476
2.IC Trainer kit
3.patch cards
4.single lead wires

Theory:
Johnson counter also known as creeping counter, is an example of synchronous counter. In
Johnson counter, the complemented output of last flip flop is connected to input of first flip flop
and to implement n-bit Johnson counter we require n flip-flop. It is one of the most important type
of shift register counter. It is formed by the feedback of the output to its own input. Johnson
counter is a ring with an inversion. Another name of Johnson counter are: creeping counter,
twisted ring counter, walking counter, mobile counter and switch tail counter.

Functional Diagram:

Johnson counter using D flip flops:

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Johnson counter using JK flip flops:

Truth Table:

Procedure:
1. Take corresponding flip flop ICs as required quantity.

2. Place the ICs on trainer kit bread board and interconnect as per circuit diagram.

3. Apply DC power supply to VCC and GND pins of ICs

4. Connect all four outputs to output LEDs and clock from clock output of the kit.

5. And tabulate the output count by applying clock pulses.

Result:

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9. Verify the Operation of 4-Bit Universal Shift Register

for Different Modes of Operation

Aim: To verify the operation of 4- Bit Universal Shift Register and observe the same for
Different modes of operation.

Components Required:
1. IC 74LS194
2. Digital IC Trainer kit
3. patch chords
4. single lead wires

Theory:
A register that can store the data and /shifts the data towards the right and left along with the
parallel load capability is known as a universal shift register. It can be used to perform input/output
operations in both serial and parallel modes. Unidirectional shift registers and bidirectional shift
registers are combined together to get the design of the universal shift register. It is also known as
a parallel-in-parallel-out shift register or shift register with the parallel load.

Functional Diagram:

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Pin Diagram: IC 74LS194

Truth Table:

Procedure:

1. Connect the circuit diagram on trainer kit as shown in the diagram.

2. Select the mode by using S0, S1 of the IC to operate register in different modes.

3. Connect all parallel outputs to output LEDS. And parallel inputs to input switches.

4. Connect serial output to output led and serial input to the serial data generator.

5. To shift the data right or left select mode and apply required no. of clock pulses.

6. And observe SISO, SIPO, PISO, PIPO operations.

Result:

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10. Mod-8 Ripple Counter and Construct A Circuit Using T-Flip-Flops

Aim:
Draw the circuit diagram of MOD-8 ripple counter and construct a circuit using T-Flip-Flops
and test it with a low frequency clock and sketch the output waveforms.

Components Required:
1. IC 7476
2. IC Trainer kit
3. patch cards
4. single lead wires

Theory:
Ripple counter is an Asynchronous counter. It got its name because the clock pulse ripples
through the circuit. An n-MOD ripple counter contains n number of flip-flops and the circuit can count
up to 2n values before it resets itself to the initial value.
The modulus of a counter is given as 2n where n is number of flip-flops. So a 3 flip-flop
counter will have a maximum count of 23=8 counting states and would be called a MOD-8 counter.
The maximum binary number that can be counted by the counter is 2n-1 giving a maximum count
of (111) i.e 23-1=7 in binary.

Functional Diagram:

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Truth Table:

Output Waveforms:

Procedure:

1. Place the two JK flip-flop ICs on IC base

2. Short the J&K to get toggle Flip flop operation .interconnect the circuit as shown in the figure.
3. Apply dc power to vcc and gnd pins of ICs ,Connect all outputs to output LEDs
4. And apply clock pulse to get next count.
5. Continue clock giving up to maximum count.
6. And tabulate the working for each clock.

Result:

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11. Mod-8 Synchronous Counter Circuit Using T-Flip-Flops

Aim:
Design MOD-8 synchronous counter and construct a circuit using T-Flip-Flops and verify the
result and sketch the output waveforms

Components Required:

1. IC 7476
2. IC Trainer kit
3. patch cards
4. single lead wires

Theory:
In Synchronous Counter, the external clock signal is connected to the clock input of EVERY
individual flip-flop within the counter so that all of the flip-flops are clocked together
simultaneously (in parallel) at the same time giving a fixed time relationship. In other words,
changes in the output occur in “synchronization” with the clock signal. The result of this
synchronization is that all the individual output bits changing state at exactly the same time in
response to the common clock signal with no ripple effect and therefore, no propagation delay.
The modulus of a counter is given as 2n where n is number of flip-flops. So a 3 flip-flop
counter will have a maximum count of 23=8 counting states and would be called a MOD-8 counter.
The maximum binary number that can be counted by the counter is 2 n-1 giving a maximum count
of (111) i.e 23-1=7 in binary.

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Functional Diagram:

Truth Table:

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Output Waveforms:

Procedure:
1. Place the two JK flip-flop ICs on IC base
2. Short the J&K to get toggle Flip flop operation .interconnect the circuit as shown in the figure.
3. Apply dc power to vcc and gnd pins of ICs ,Connect all outputs to output LEDs
4. And apply clock pulse to get next count.
5. Continue clock giving up to maximum count.
6. And tabulate the working for each clock.

Result:

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12. A) One Bit Comparator

Aim: Draw the circuit diagram of a single bit comparator and test the output.

Components Required:

1.IC 7485, IC 7400, IC 7410, IC 7420, IC 7432, IC 7486, IC 7402, IC 7408, IC 7404,
2.Digital IC Trainer kit
3.patch cards
4.single lead wires

Theory:
Magnitude Comparator is a logical circuit, which compares two signals A and B and
generates three logical outputs, whether A > B, A = B, or A < B. IC 7485 is a high speed 4-bit
Magnitude comparator, which compares two 4-bit words. The A = B Input must be held high for
proper compare operation.

Functional Diagram:

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Pin Diagram:

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Procedure:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Apply two inputs which you want to compare to input switches and ground the all unnecessary
inputs.
5. Connect three comparison outputs A=B, A>B, A<B to output LEDs.
6. Apply different inputs. Observe outputs for different input combinations and tabulate in the
tabular form.

Result:

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12. B) 7 Segment Display Circuit Using Decoder and 7-Segment Led

Aim: Construct 7 Segment Display Circuit Using Decoder and 7 Segment LED and test it.

Components Required:

1.IC Trainer kit

2.patch cards
3.single lead wires
4.IC 7447

Theory:
Seven segment display is an electronic device which consists of seven Light Emitting Diodes
(LEDs) arranged in a some definite pattern (common cathode or common anode type), which is used
to display Hexadecimal numerals (in this case decimal numbers, as input is BCD i.e., 0-9).
Two types of seven segments LED display:
1. Common Cathode Type: In this type of display all cathodes of the seven LEDs are connected
together to the ground or –Vcc (hence, common cathode) and LED displays digits when some
‘HIGH’ signal is supplied to the individual anodes.
2. Common Anode Type: In this type of display all the anodes of the seven LEDs are connected to
battery or +Vcc and LED displays digits when some ‘LOW’ signal is supplied to the individual
cathodes.
But, seven segment display does not work by directly supplying voltage to different segments of
LEDs. First, our decimal number is changed to its BCD equivalent signal then BCD to seven
segment decoder converts that signals to the form which is fed to seven segment display.
Note –

For Common Anode type seven segment LED display, we only have to interchange all ‘0s’ and
‘1s’ in the output side i.e., (for a, b, c, d, e, f, and g replace all ‘1’ by ‘0’ and vice versa) and solve
using K-map.
Output for first combination of inputs (A, B, C and D) in Truth Table corresponds to ‘0’ and last
combination corresponds to ‘9’. Similarly rest corresponds from 2 to 8 from top to bottom.
BCD numbers only range from 0 to 9, thus rest inputs from 10-F are invalid inputs.

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Functional Diagram:

Pin Diagram:

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Truth Table:

Procedure:

1. Check all the components for their working.

2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Apply 4 inputs to the input switches and seven outputs to the 7 segment display.
5. Apply different possible input combinations and observe glowing of LEDS in 7 segment.
6. Tabulate the readings

Result:

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13. BCD Adder Circuit

Aim: Design BCD Adder Circuit and Test the Same using Relevant IC

Components Required:

1.IC Trainer kit

2.patch cards
3.single lead wires
4.IC 7483

Theory:
The digital system handles the decimal number in the form of binary coded decimal numbers
(BCD). A BCD Adder Circuit that adds two BCD digits and produces a sum digit also in BCD.
BCD numbers use 10 digits, 0 to 9 which are represented in the binary form 0 0 0 0 to 1 0 0 1, i.e.
each BCD digit is represented as a 4-bit binary number. When we write BCD number say 526, it
can be represented as

Here, we should note that BCD cannot be greater than 9.

The addition of two BCD numbers can be best understood by considering the three cases that
occur when two BCD digits are added.

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IC internal circuit Diagram:

Pin Diagram:

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Procedure:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Connect the input pins to input switches and outputs to output LEDs
5. Apply two different BCD numbers which you want to add.
6. Observe output sum from output LEDs
Example:
Input: A = 0111 B = 1000
Output: Y = 1 0101
Explanation:
1. Add two BCD numbers using ordinary binary addition.
2. If four-bit sum is equal to or less than 9, no correction is needed. The sum is in proper BCD form.
3. If the four-bit sum is greater than 9 or if a carry is generated from the four-bit sum, the sum is
invalid.
4. To correct the invalid sum, add 01102 to the four-bit sum. If a carry results from this addition, add
it to the next higher-order BCD digit.
Thus to implement BCD Adder Circuit we require:

4-bit binary adder for initial addition

Logic circuit to detect sum greater than 9 and
One more 4-bit adder to add 01102 in the sum if sum is greater than 9 or carry is 1.
The logic circuit to detect sum greater than 9 can be determined by simplifying the Boolean
expression of given BCD Adder Truth Table.

Result:

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14. IC74154 De-Multiplexer

Aim: Design an experimental model to demonstrate the operation of 74154 De-Multiplexer using

LED’s for outputs.

Components Required:

1. IC Trainer kit
2. patch cards
3. single lead wires
4. IC 74154

Theory:
De-multiplexers perform the opposite function of multiplexers. They transfer a small
number of information units (usually one unit) over a larger number of channels under the control
of selection signals. The general de-multiplexer circuit has 1 input signal, n control/select signals
and 2n output signals. De-multiplexer circuit can also be realized using a decoder Circuit with
enable.
Standard De-multiplexer IC packages available are the TTL 74LS138 1 to 8-output de-
multiplexer, the TTL 74LS139 Dual 1-to-4 output de-multiplexer or the CMOS CD4514 1-to-16
output de-multiplexer.

Another type of de-multiplexer is the 24-pin, 74LS154 which is a 4-bit to 16-line de-
multiplexer/decoder. Here the individual output positions are selected using a 4-bit binary coded
input. Like multiplexers, de-multiplexers can also be cascaded together to form higher order de-
multiplexers.

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Pin Diagram:

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Truth Table:

Procedure:

1. Place the appropriate IC in IC base

2. Connect VCC and GND pins to the supply

3. Connect the input to the input switch to apply logic 1 or logic 0

4. Connect the all outputs to the output LEDs

5. Connect selection line to the input switches

6. Apply input and check the output for different selection inputs and tabulate the values

Result:

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