Answer For Tutorial 2

EKT 422: Computer Architecture
Answer Scheme: Tutorial 2

1. A set associative cache consists of 64 lines or slot divided into four-line sets. Main
memory contains 4K blocks of 128 words each. Show the format of main memory
addresses.
The cache is divided into 16 sets of 4 lines each. Therefore, 4 bits are needed to
identify the set number. Main memory consists of 4K = 212 blocks. Therefore, the set
plus tag lengths must be 12 bits and therefore the tag length is 8 bits. Each block
contains 128 words. Therefore, 7 bits are needed to specify the word.
Main memory address =
TAG
SET
WORD
8
4
7
2. For direct-mapped cache, a main memory address is viewed as consisting of three
fields. List and define the three fields.
One field identifies a unique word or byte within a block of main memory. The
remaining two fields specify one of the blocks of main memory. These two fields are a
line field, which identifies one of the lines of the cache, and a tag field, which identifies
one of the blocks that can fit into that line.
3. For set-associative cache, a main memory address is viewed as consisting of two
fields. List and define the two fields.
One field identifies a unique word or byte within a block of main memory. The
remaining two fields specify one of the blocks of main memory. These two fields are a
set field, which identifies one of the sets of the cache, and a tag field, which identifies
one of the blocks that can fit into that set
4. Consider a 32-bit microprocessor that has on-chip 16Kbyte four-way set-associative
cache. Assume that cache has a line size of four 32-bit words. Draw a block diagram
of this cache showing its organization and how the different address fields are used to
determine a cache hit/miss. Where in the cache is the word from memory location
ABCDE7F4 mapped.
Block frame size = 16 bytes = 4 doublewords
Number of block frames in cache = 16 Kbytes
= 1024
16 Bytes
Number of sets =Number of block frames
=1024 = 256 sets
Associativity
4
Tag
Set
Offse
AB CD E
7F
t
4
5. What is the general relationship among access time, memory cost, and capacity?
Faster access time, greater cost per bit; greater capacity, smaller cost per bit; greater
capacity, slower access time.
6. What are the differences among sequential access, direct access and random access?
Sequential access: Memory is organized into units of data, called records. Access must
be made in a specific linear sequence. Direct access: Individual blocks or records
have a unique address based on physical location. Access is accomplished by direct
access to reach the general vicinity plus sequential searching, counting, or waiting to
reach the final location. Random access: Each addressable location in memory has a
unique, physically wired-in addressing mechanism. The time to access a given location
is independent of the sequence of prior accesses and is constant.
7. What is the different between DRAM and SRAM in term of characteristics such as
speed, size and cost?
SRAMs generally have faster access times than DRAMs. DRAMS are less expensive
and smaller than SRAMs.
8. Explain why one type of RAM is considered to be analog and other digital.
A DRAM cell is essentially an analog device using a capacitor; the capacitor can
store any charge value within a range; a threshold value determines whether the
charge is interpreted as 1 or 0. A SRAM cell is a digital device, in which binary values
are stored using traditional flip-flop logic-gate configurations.
9. What are differences among EPROM, EEPROM and flash memory?
EPROM is read and written electrically; before a write operation, all the storage cells
must be erased to the same initial state by exposure of the packaged chip to ultraviolet
radiation. Erasure is performed by shining an intense ultraviolet light through a
window that is designed into the memory chip. EEPROM is a read mostly memory
that can be written into at any time without erasing prior contents; only the byte or
bytes addressed are updated. Flash memory is intermediate between EPROM and
EEPROM in both cost and functionality. Like EEPROM, flash memory uses an
electrical erasing technology. An entire flash memory can be erased in one or a few
seconds, which is much faster than EPROM. In addition, it is possible to erase just
blocks of memory rather than an entire chip. However, flash memory does not provide
byte-level erasure. Like EPROM, flash memory uses only one transistor per bit, and so
achieves the high density (compared with EEPROM) of EPROM.
10. Design a 16-bit memory of total capacity 8192 bits using SRAM chips of size 64 x 1
bit. Give the array configuration of the chips on the memory board showing all
requirement input and output signals for assigning this memory to the lowest address
space. The design should allow for both byte and 16-bit word access.
8192/64 = 128 chips; arranged in 8 rows by 64 columns:
11. Consider a dynamic RAM that must be given a refresh cycle 64 times per mS. Each
refresh operation requires 150nS. What percentage of the memorys total operating
time must be given to refresh?
In 1 ms, the time devoted to refresh is 64 150 ns = 9600 ns. The fraction of time
devoted to memory refresh is (9.6 106 s)/103 s = 0.0096, which is approximately
1%.
12. Briefly define the seven RAID levels.

0: Non-redundant 1: Mirrored; every disk has a mirror disk containing the same data.
2: Redundant via Hamming code; an error-correcting code is calculated across
corresponding bits on each data disk, and the bits of the code are stored in the
corresponding bit positions on multiple parity disks. 3: Bit-interleaved parity; similar
to level 2 but instead of an error-correcting code, a simple parity bit is computed for
the set of individual bits in the same position on all of the data disks. 4: Blockinterleaved parity; a bit-by-bit parity strip is calculated across corresponding strips on
each data disk, and the parity bits are stored in the corresponding strip on the parity
disk. 5: Block-interleaved distributed parity; similar to level 4 but distributes the
parity strips across all disks. 6: Block interleaved dual distributed parity; two different
parity calculations are carried out and stored in separate blocks on different disks.
13. How is redundancy achieved in a RAID system?
For RAID level 1, redundancy is achieved by having two identical copies of all data.
For higher levels, redundancy is achieved by the use of error-correcting codes.
14. What are the major functions of an I/O module?
Control and timing. Processor communication. Device communication. Data
buffering. Error detection.
15. List and briefly explain three techniques for performing I/O.
Programmed I/O: The processor issues an I/O command, on behalf of a process, to an
I/O module; that process then busy-waits for the operation to be completed before
proceeding. Interrupt-driven I/O: The processor issues an I/O command on behalf of
a process, continues to execute subsequent instructions, and is interrupted by the I/O
module when the latter has completed its work. The subsequent instructions may be in
the same process, if it is not necessary for that process to wait for the completion of the
I/O. Otherwise, the process is suspended pending the interrupt and other work is
performed. Direct memory access (DMA): A DMA module controls the exchange of
data between main memory and an I/O module. The processor sends a request for the
transfer of a block of data to the DMA module and is interrupted only after the entire
block has been transferred.
16. The DMA mechanism can be configured in a variety of ways. List and explain the
entire configuration.
Configuration 1: Single Bus, Detached DMA controller
Each transfer uses bus twice

I/O to DMA then DMA to memory
CPU is suspended twice
Configuration 2: Single Bus, Integrated DMA controller
Controller may support >1 device

Each transfer uses bus once
DMA to memory
CPU is suspended once
Configuration 3: Separate I/O Bus
Bus supports all DMA enabled devices

Each transfer uses bus once
DMA to memory
CPU is suspended once
17. A direct memory access module (DMA) module is transferring characters to memory
using cycle stealing, from a device transmitting at 9600 bps. The processor is fetching
instructions at the rate of 1 Million Instruction per Second (MIPS). Based on the
information given, determine how much will the processor be slowed down due to the
DMA activity.
64 KB
18. What is the different between memory-mapped I/O and isolated I/O?
With memory-mapped I/O, there is a single address space for memory locations and
I/O devices. The processor treats the status and data registers of I/O modules as
memory locations and uses the same machine instructions to access both memory and
I/O devices. With isolated I/O, a command specifies whether the address refers to a
memory location or an I/O device. The full range of addresses may be available for
both.
19. What is an Operating system?
The operating system (OS) is the software that controls the execution of programs on a
processor and that manages the processor's resources.
20. What are the major types of operating system (OS) scheduling?
i.
Long-term scheduling: The decision to add to the pool of processes to be executed.
ii.
Medium-term scheduling: The decision to add to the number of processes that are
partially or fully in main memory.
iii.
Short-term scheduling: The decision as to which available process will be executed

by the processor
21. Consider a computer system with both segmentation and paging. When a segment is
in memory, some words are wasted on the last page. In addition, for a segment size s
and a page size p, there are s/p page table entries. The smaller the page size, the less
waste in the last page of the segment, but the larger the page table. What page size
minimizes the total overhead?
22. What is the purpose of a translation lookaside buffer?
The TLB is a cache that contains those page table entries that have been most recently
used. Its purpose is to avoid, most of the time, having to go to disk to retrieve a page
table entry.

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EKT 422: Computer Architecture

Answer Scheme: Tutorial 2

12. Briefly define the seven RAID levels.

Each transfer uses bus twice

Configuration 2: Single Bus, Integrated DMA controller

Controller may support >1 device

Configuration 3: Separate I/O Bus

Bus supports all DMA enabled devices

Short-term scheduling: The decision as to which available process will be executed

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