PEF22558E
PEF22558E
PEF22558E
0 , M a y 20 0 5
OctalFALC TM
Octal E1/T1/J1 Framer and Line Interface
C o m p o n e n t f o r L o n g - a n d S h o r t - H au l
Applications
PEF 22558 E, Version 1.1
Wireline Communications
N e v e r
s t o p
t h i n k i n g .
ABM, ACE, AOP, ARCOFI, ASM, ASP, DigiTape, DuSLIC, EPIC, ELIC,
FALC, GEMINAX, IDEC, INCA, IOM, IPAT-2, ISAC, ITAC, IWE, IWORX,
MUSAC, MuSLIC, OCTAT, OptiPort, POTSWIRE, QUAT, QuadFALC,
SCOUT, SICAT, SICOFI, SIDEC, SLICOFI, SMINT, SOCRATES, VINETIC,
10BaseV, 10BaseVX are registered trademarks of Infineon Technologies AG.
10BaseS, EasyPort, VDSLite are trademarks of Infineon Technologies AG.
Microsoft is a registered trademark of Microsoft Corporation, Linux of Linus Torvalds,
Visio of Visio Corporation, and FrameMaker of Adobe Systems Incorporated.
The information in this document is subject to change without notice.
Edition 2005-05-03
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 Mnchen, Germany
OctalFALCTM
Revision History:
2005-05-03
Previous Version:
Rev. 1.0
Rev. 2.0
Page
46
wg_template_fm5_a5_2003-09-01.fm / DS4
OctalFALCTM
PEF 22558 E
Table of Contents
Page
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
2.1
2.2
Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hardware Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
4.1
4.2
Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Individual Receive Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCO-R/DCO-X Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Reset and Configuring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Interrupt Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
27
27
28
28
28
29
32
6
6.1
6.2
6.3
6.4
Framer Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Remote Defect Indication (E1 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Sending of Transmit Remote Alarm (T1/J1 only) . . . . . . . . . . .
RSC Interrupt (T1/J1 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL-Bit Access (T1/J1 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
33
34
34
7
7.1
7.2
7.3
CAS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic CAS Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Robbing Force One in Cleared Channels (T1/J1 only) . . . . . . . . . . . . .
Bit Robbing Idle (T1/J1 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
36
36
36
HDLC/BOM Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9
9.1
9.2
9.3
9.4
System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Edge Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tristate Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Redundancy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
39
41
41
42
10
10.1
10.2
10.3
10.3.1
10.3.2
Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tunable Transmit Line Output Resistance . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Pulse Shaper and Line Build-Out . . . . . . . . . . . . . . . . . . .
QuadFALC Compatible Programming . . . . . . . . . . . . . . . . . . . . . . . .
Programming with TXP(16:1) Registers . . . . . . . . . . . . . . . . . . . . . . . .
45
45
46
46
46
47
Delta Sheet
OctalFALCTM
PEF 22558 E
Table of Contents
Page
10.4
11
12
12.1
12.2
12.3
12.4
12.4.1
12.5
12.6
12.7
13
Supported Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
14
14.1
14.2
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
15
15.1
15.2
15.3
Register Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Register Compatibility Handling . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pseudo QuadFALC Register GPC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional Registers or Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
17
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
18
18.1
18.2
18.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delta Sheet
61
61
63
64
85
85
86
87
OctalFALCTM
PEF 22558 E
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Delta Sheet
Page
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Basic Operation Modes for Microcontroller interface . . . . . . . . . . . . . . 10
Intel Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Intel Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Intel Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Intel Non Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . 14
Motorola Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Motorola Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SCI interface Application with Point to Point Connections . . . . . . . . . . 19
SCI interface Application with Multipoint to Multipoint Connection . . . 19
SCI Message Structure of OctalFALCTM . . . . . . . . . . . . . . . . . . . . . . . 20
Frame Structure of OctalFALCTM SCI Messages. . . . . . . . . . . . . . . . . 21
Principle of Building of Addresses and RSTA Bytes in the SCI ACK
Message 22
SCI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPI Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Receive Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Principle of Setting Parameters of the DCO-X and DCO-R . . . . . . . . . 29
Flexible Master Clock Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AXRA Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Standard DL-Bit Access in ESF Mode . . . . . . . . . . . . . . . . . . . . . . . . . 35
Optional DL-Bit Access in ESF Mode . . . . . . . . . . . . . . . . . . . . . . . . . 35
HDLC Controller Standard Configuration for all three HDLC Channels 38
HDLC Controller Inverse Configuration for All Three HDLC Channels 38
Principle of System Interface Multiplex Modes, shown for RDO . . . . . 40
Redundancy Application (shown for one channel and using RLM) . . . 43
Long Haul Redundancy Application using the Analog Switch (shown for
one line) 44
Transmit Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Receiver Configuration with Integrated Analog Switch for Receive
Impedance Matching 49
GIS Register Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
VSTR and DSTR Register Compatibility . . . . . . . . . . . . . . . . . . . . . . . 63
Principle of configuration of SEC/FSC Output . . . . . . . . . . . . . . . . . . . 64
PG-LBGA-256-1 (Plastic Green Low Profile Ball Grid Array Package) 84
OctalFALCTM
PEF 22558 E
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Delta Sheet
Page
OctalFALCTM
PEF 22558 E
General
Abstract
This document describes the differences of PEF 22558 E, OctalFALCTM, Version v1.1,
relative to the QuadFALC , Version 2.1. QuadFALC is a registered brand.
General
The number of receive and transmit channels has been increased from four to eight. All
channels can be configured and used independently.
To enable a seamless transition from QuadFALC designs to OctalFALCTM applications,
a compatibility mode is provided. This mode allows software written for the QuadFALC
to be used with the OctalFALCTM without changes.
For new applications, a number of additional features and enhancements are provided.
Compatibility
2.1
Hardware Compatibility
The OctalFALCTM always requires two supply voltages, 1.8 V and 3.3 V. The 3.3 V-only
mode usable with QuadFALC (V1.3 and V2.1) is not supported.
To enable use of PG-LBGA-256-1 package the number of multifunction ports is reduced
to three in receive and two in transmit direction per channel. Furthermore RCLK signals
are provided on multifunction ports instead of separate pins.
To ensure software compatibility unused registers (for example PC4) still exists but are
not used. Figure 1 shows the Logical Symbol of the OctalFALCTM.
Delta Sheet
OctalFALCTM
PEF 22558 E
MCLK
SYNC
SEC/FSC
Receive
System
Interface
SCLKX(8:1)
XDI(8:1)
XPA(8:1)
XPB(8:1)
Transmit
System
Interface
Microcontroller Interface
(asynchronous , SCI- or SPI-Bus)
IM(1:0)
COMP
OctalFALCTM
PEF 22558 E V1.1
PG-LBGA256
XL1/XDOP/XIOD(8:1)
XL2/XDON/XFM(8:1)
XL3(8:1)
XL4(8:1)
VDDX(1:8)
Transmit
Line
Interface
TDI
TMS
TCK
TRS
TDO
SCLKR(8:1)
RDO(8:1)
RPA(8:1)
RPB(8:1)
RPC(8:1)
CS/CS1
WR/RW
RD/DS
BHE/BLE
ALE
DBW
RES
INT2
INT/INT1
READY/TDACK
Boundary
Scan
Interface
RL1/RDIP/ROID(8:1)
RL2/RDIN/RCLKI(8:1)
RLS(8:1)
D(15:0)/SCI
A(10)/CS2
A(9:0)
Receive
Line
Interface
VDDC
VDDP
VDDPLL
VSS
VDDR(1:8)
Compatibility
Mode
Octal_FALC_Logic_symbol
Figure 1
2.2
Logic Symbol
Software Compatibility
The OctalFALCTM can be used in two basic modes. The QuadFALC Compatibility
Mode allows to use the device like two separate QuadFALCs while the OctalFALCTM
Generic Mode handles the device as a single entity. The Compatibility Mode option
allows an easy migration of designs from QuadFALC to OctalFALCTM without the need
for software changes. As for the QuadFALC the register addresses are 10 bits wide.
In the OctalFALCTM Generic Mode the register addresses are 11 bit wide.
Delta Sheet
OctalFALCTM
PEF 22558 E
Compatibility
An overview is given in Table 1.
Additional features are available also in compatibility mode, but are disabled by default
and must be activated by software.
If compatibility mode is selected, the version status register VSTR shows the same value
as in QuadFALC V2.1 while the JTAG boundary scan ID is always the OctalFALCTM
number and not affected by the mode selection. In compatibility mode the behavior of
the clocking system is the same as in the QuadFALC. So the eigenfrequencies and
attunation factors of all PLLs, especially of the DCO-R and DCO-X must be in the near
of the QuadFALC values with the equivalent register programing. Also the multi function
pin RPC must have the function RCLK after reset (Register bits PC1.RPC(3:0)).
Note: In compatibility mode and if microcontroller mode is selected, A(10) - active high is used as second chip select signal (CS2) - active low - for the second pseudo
QuadFALC, see Figure 2 and Table 1. The first pseudo QuadFALC is selected
by CS1. Activation of both chip selects simultaneous is not allowed.
OctalFALC
Generic Mode:
A(10:0)
Ch.1
D(15:0)
Ch.2
Ch.3
P control
OctalFALC
CS
INT
Ch.4
Ch.5
Ch.6
Ch.7
Ch.8
COMP=0
SYNC
QuadFALC
Compatibility
Mode:
SEC/FSC
A(9:0)
D(15:0)
Ch.1.1
Pseudo-QuadFALC 1
P control
CS1
CS2
INT1
INT2
COMP=1
Delta Sheet
Ch.1.3
Ch.1.4
Ch.2.1
Pseudo-QuadFALC 2
Ch.2.2
Ch.2.3
Ch.2.4
SYNC
Figure 2
Ch.1.2
SEC/FSC
OctalFALC_Operation_Mode_1
10
OctalFALCTM
PEF 22558 E
Compatibility
Table 1
Interface
Mode
COMP
CS
A(10)
A(9:0)
Basic
Operation
Modes
Intel or
0x
Motorola
micro
processor
mode
CS1, for
pseudo
QuadFA
LC1
CS
SPI
10
CS
SCI
11
Not
valid
Generic
Mode
In compatibility mode every global register exists one times in both of the pseudo
QuadFALCs : CIS, GPC(1:6), IPC, VSTR, GIS, GCM(1:8), GIMR, GIS2, GLC1,
INBLDTR, DSTR and PRBSTS(1:4).
In compatibility mode (COMP = 1) the registers regarding the central clock PLL,
GCM(1:8), exists one times in both of the pseudo QuadFALCs, but the registers of the
pseudo QuadFALC2 are dummys: Writing and reading is possible but their values are
not taken for any configuration of the PLL and writing on register GCM5 or GCM6 causes
NO reset of the PLL. Only the registers GCM(1:8) of the pseudo QuadFALC1 are taken
for configuration of the PLL and writing on register GCM5 or GCM6 causes a reset of the
PLL as in QuadFALC or FALC56v2.1
In compatibility mode (COMP = 1) the status registers regarding the central clock PLL,
GIS2 and GIMR, exists one times in both of the pseudo QuadFALCs: The status of the
one PLL is doubled and can be masked individually in every of the both pseudo
QuadFALCs.
In generic mode (COMP = 0) the registers GIMR, GIS2 and GCM(1:8) exist only one
times in the whole device.
If compatibility mode is selected, the version status register VSTR shows the same value
as in QuadFALC V2.1 while the JTAG boundary scan ID is always the OctalFALCTM
number and not affected by the compatibility mode selection.
Delta Sheet
11
OctalFALCTM
PEF 22558 E
Microcontroller Interface
Microcontroller Interface
RD
9
8
WR
11
Dx
32
33
30
31
READY
Octal_FALC_F0121
Figure 3
Delta Sheet
12
OctalFALCTM
PEF 22558 E
Microcontroller Interface
CS
8
WR
9
8
RD
16
15
Dx
34
30
31
READY
Octal_FALC_intel_write_cycle
Figure 4
Ax
BHE
5
4
6
ALE
7
7A
1
CS
3
3A
RD
WR
Figure 5
Delta Sheet
ITT10977
13
OctalFALCTM
PEF 22558 E
Microcontroller Interface
Ax
BHE
CS
3
3A
RD
WR
ITT10975
Figure 6
Table 2
No.
Parameter
Limit Values
Min.
Unit
Max.
ns
ns
CS setup time
ns
3A
CS hold time
ns
20
ns
10
ns
30
ns
ns
7A
30
ns
80
ns
70
ns
11
10
15
30
ns
16
10
ns
Delta Sheet
14
30
ns
OctalFALCTM
PEF 22558 E
Microcontroller Interface
Table 2
No.
Limit Values
Min.
Unit
Max.
30
t.b.d.
ns
31
ns
32
ns
33
RD to READY delay
ns
34
WR to READY delay
ns
Ax, BLE
17
18
CS
19
RW
19A
20
21
22
23
DS
25
Dx
44
43
40
41
DTACK
OctalFALC_F0122
Figure 7
Delta Sheet
15
OctalFALCTM
PEF 22558 E
Microcontroller Interface
Ax, BLE
17
18
CS
19
RW
19A
20
21
22A
23
DS
26
27
Dx
42
40
41
DTACK
OctalFALC_mot_write_cycle
Figure 8
Table 3
No.
Parameter
Limit Values
Min.
Unit
Max.
17
15
ns
18
ns
19
ns
19A
ns
20
10
ns
21
ns
22
80
ns
22A
70
ns
23
DS control interval
70
ns
24
Delta Sheet
16
75
ns
OctalFALCTM
PEF 22558 E
Serial Interfaces
Table 3
No.
Limit Values
Min.
Unit
Max.
25
26
30
ns
27
10
ns
40
41
ns
42
ns
43
ns
44
ns
30
t.b.d.
ns
ns
Serial Interfaces
Two additional serial interfaces are included to enable device programming and
controlling:
Slave Serial Control Interface (SCI)
Slave Serial Peripheral Interface (SPI)
By using the SCI Interface, the OctalFALCTM can be easily connected to Infineon
interworking devices like the SDC16. The SCI is used as interface also in the Infineon
SHDSL- and ADSL-PHYs so that implementation of different line transmission
technologies on the same line card easily is possible. The SCI interface is a three-wire
bus and optionally replaces the parallel processor interface to reduce wiring overhead
on the PCB, especially if multiple devices are used on a single board. Data on the bus is
HDLC encapsulated and uses a message-based communication protocol. The
OctalFALCTM SCI interface is always a slave.
If SCI interface with multipoint to multipoint configuration is used, address pins A(5:0) are
used for SCI source (slave) address pin strapping.
In compatibility mode (pin COMP = 1) these both new interfaces are also supported.
The four possible interface modes - two microconroller modes and two serial interface
modes - are selected by using the interface mode selection pins IM(1:0). This selection
is valid immediately after reset becomes inactive.
After changing of the interface mode by IM(1:0), a hardware reset must be applied.
Note that after a reset writing into or reading from OctalFALCTM registers using the SCIor SPI-Interface is not possible until the PLL is locked: If the SCI-Interface is used no
acknowledge message will be send by the OctalFALCTM. If the SPI-Interface is used pin
SDO has high impedance (SDO is pulled up by external resistor). To trace if the SPI
Delta Sheet
17
OctalFALCTM
PEF 22558 E
Serial Interfaces
interface is accessible, the micro controller should poll for example the register DSTR so
long as it read no longer the value FH.
4.1
SCI Interface
Delta Sheet
18
OctalFALCTM
PEF 22558 E
Serial Interfaces
Clk
TxData
RxData
PP SCI_TXD
SCI_RXD
IM(1:0)
OctalFALC
Microprocessor
or
Interworking
Device
Figure 9
Clk
TxData
RxData
IM(1:0)
Clk
TxData
RxData
OctalFALC
IM(1:0)
OctalFALC
OctalFALC_Interfaces_2
oD SCI_TXD
SCI_RXD
IM(1:0)
Micro-processor
or
Interworking
Device
OctalFALC
A(5:0)
Clk
Data
IM(1:0)
Clk
OctalFALC
A(5:0)
Data
IM(1:0)
OctalFALC
A(5:0)
OctalFALC_SCI_halfduplex
Figure 10
The following configurations of the SCI interface of the OctalFALCTM can be set by the
microcontroller by a write command into the SCI configuration register (control bits 10B,
see Table 4, SCI register address is 0000H, see Table 5 and Figure 12):
Half duplex/full duplex (reset value: Half duplex), bit DUP
OpenDrain/push-pull (configuration of output pin to openDrain/push-pull is in
general independent of the duplex mode and must be set appropriately in
application) (reset value: open Drain), bit PP
CRC for transmit and receive on/off (reset value: off), bit CRC_EN
Automatic acknowledgement of CMD messages on/off (reset value: off), bit
ACK_EN
Clock edge rising/falling (reset value: falling ), bit CLK_POL
Clockgating (reset value: off), bit CLK_GAT
Delta Sheet
19
OctalFALCTM
PEF 22558 E
Serial Interfaces
The following SCI configurations are fixed and cannot be set by the microcontroller:
Interrupt feature is disabled, bit INT_EN = 0B
Arbitration always made with LAPD (only SCI applications like in Figure 9 and
Figure 10 are possible), bit ARB = 0B
Recommendation for configuring: Set CRC, automatic acknowledgement and clock
gating to on.
The maximum possible SCI clock frequency is 6 MHz for point to point applications (full
duplex) and about 2 MHz for multipoint to multipoint applications, dependent on the
electrical capacity of the bus lines of the PCB.
Figure 11 shows the message structure of the OctalFALCTM.
HOST
OctalFALC
CMD
ACK
OctalFALC_SCI_message_structure
Figure 11
Every write into or read from a register of the OctalFALCTM is initiated by a command
message CMD from the Host (microconroller) and is then confirmed by an acknowledge
message ACK from the OctalFALCTM if in the SCI configuration automatic
acknowledgement is set (bit ACK_EN, see Table 5).
The frame structure of this messages are shown in Figure 12.
In general the LSB of every byte is transmitted first and lower bytes are transmitted
before higher bytes (regarding the register address).
The HDLC flags mark beginning and end of all messages.
Source and destination addresses are 8 bits long. Only the first 6 bits are really used for
addressing. The bit C/R (Command/Response) distinguishes between a command and
a response. The bit MS (Master/Slave) is 0B for all Slaves and 1B for all masters, see
Table 5 and Figure 12.
The source address is defined by pinstrapping of A5 to A0 after reset, but other values
can be configured by programming of the SCI configuration register.
The payload of the write CMD includes two control bits (MSBs of the payload), which
distinguish between the different kind of commands, see Table 4, the 14 bit wide register
address and the 8 bit wide data whereas the read CMD payload includes only the control
bits and the register address. Register addresses can be either OctalFALCTM register
Delta Sheet
20
OctalFALCTM
PEF 22558 E
Serial Interfaces
addresses or SCI configuration register addresses. Because of the address space of the
OctalFALCTM, really 11 LSBs of the 14 bit address are used in the OctalFALCTM. The 3
MSBs are ignored.
The Frame Check Sequence FCS has16 bits.
The Read Status Byte RSTA of the acknowledge message shows the status of the
received message and is built by the SCI interface of the OctalFALCTM, see Figure 13
and Read Status Byte (RSTA) of the Acknowledge (ACK).
The destination address in the ACK message is always the source address of the
corresponding CMD (the address of the microcontroller), see Figure 13, because no
CMD messages will be sent by the OctalFALCTM SCI interface.
SCI HDLC Basic Frame Structure
Flag
Address
Payload
Source
Address
Destination
Address
Source
Address
14 bit Register
address
8 bit data
FCS
01111110
FCS
01111110
Flag
Control
bits
FCS
Destination
Address
14 bit Register
address
Read
Depth
Source
Address
Destination
Address
MS
RSTA
C/R
FCS
6 bit
address
OctalFALC_SCI_frame_structure
LSB
Figure 12
Delta Sheet
01111110
21
OctalFALCTM
PEF 22558 E
Serial Interfaces
CMD
Source
Address
Destination
Address
ACK
Source
Address
RSTA register
Destination
Address
RSTA
OctalFALC_SCI_acknowledge
Figure 13
VFR
RDO
CRC
RAB
2
SA(1:0)
0 (LSB)
C/R
TA
Field
Bits
Description
VFR
Valid Frame
Indicates whether a valid frame has been received.
0B
VFR_0, received frame is invalid.
1B
VFR_1, received frame is valid.
RDO
Reserved
CRC
CRC Compare/Check
Indicates wether a CRC check is failed or not
0B
CRC_0, CRC error check failed on the received frame.
1B
CRC_1, received frame is free of CRC errors.
RAB
Delta Sheet
22
OctalFALCTM
PEF 22558 E
Serial Interfaces
Field
Bits
Description
SA(1:0),
C/R, TA
[3:0]
Reserved
Table 4
Command Type
01
00
10
11
Table 5
Address
bit 7
(MSB)
bit 6
bit 5
bit 4
bit 3
0000H
PP
bit 2
bit 1
bit 0
(LSB)
CRC_E
N
ARB
DUP
0001H
Source Address
1 (= C/R) 0 (= MS)
0002H
Group Address
1 (= C/R) 0 (= MS)
Figure 14 shows the timing of the SCI interface and Table 6 the appropriate timing
parameter values.
1
3
2
SCI_CLK
SCI_RXD
6
SCI_TXD
OctalFALC_SCI_timing
Figure 14
Delta Sheet
23
OctalFALCTM
PEF 22558 E
Serial Interfaces
Table 6
No
Limit Values
Min.
Unit
Max.
170
ns
500
ns
t.b.d.
ns
t.b.d.
ns
t.b.d.
ns
ns
4.2
t.b.d.
ns
SPI Interface
Delta Sheet
24
OctalFALCTM
PEF 22558 E
Serial Interfaces
CS
SCLK
A10
SDI
x x x
11 bit address
A0
dont care
D7
SDO
8 bit data
D0
high impedance
Octal_FALC_SPI_re
Figure 15
CS
SCLK
A10
SDI
SDO
x x x
11 bit address
A0 D7
8 bit data
D0
high impedance
Octal_FALC_SPI_write
Figure 16
Delta Sheet
25
OctalFALCTM
PEF 22558 E
Serial Interfaces
7
CS
6
SCLK
4
SDI
9
11
10
high impedance
SDO
Octal_FALC_SPI_timing
Figure 17
Table 7
No.
Parameter
Limit Values
Min.
Unit
Max.
SCLK frequency
50
ns
100
ns
150
ns
50
ns
205
ns
205
ns
CS high time
100
ns
50
ns
150
ns
10
50
ns
11
Delta Sheet
t.b.d.
26
MHz
OctalFALCTM
PEF 22558 E
Clock Modes
Clock Modes
5.1
The source of every of the eight receive clocks (RCLK(8:1)) can be independently
selected out of every of the eight channels. The additional registers GPC2 to GPC6 are
used for controlling. GPC2 to GPC6 are not valid if COMP = 1. For COMP = 1 only
the source of RCLK1 can be selected by the register GPC1 of the pseudo QuadFALC1,
RCLK2,3,4 sources are the appropriate channels. Equivalent, the RCLK5 source can be
selected by the register GPC1 of the pseudo QuadFALC2 and the sources of
RCLK6,7,8 are the appropriate channels. For the principle see also Figure 18. After
reset RCLK1 is sourced by channel 1 and RCLK5 is sourced by channel 5 and switched
to the multi function ports RPC.
Note that in CT mode the DCO-R is always on.
GPC2
...
GPC1
RCLK1
RCLK2
RCLK3
RCLK4
GPC6
Pseudo QuadFALC 1
RCLK1
RCLK1
RCLK1
RCLK2
RCLK3
RCLK4
RCLK2
RCLK3
RCLK2
RCLK3
RCLK4
RCLK4
GPC1
RCLK5
RCLK6
RCLK7
RCLK8
Pseudo QuadFALC 2
RCLK5
RCLK5
RCLK6
RCLK6
RCLK5
RCLK6
RCLK7
RCLK8
RCLK7
RCLK8
RCLK7
RCLK8
COMP = 0
COMP = 1
OctalFALC_RCLK_configuration
Figure 18
5.2
The transmit clock can be automatically switched between TCLK and SCLKX. This
enables an automatic switch over between different clock sources within the system in
case the original clock source is lost. In general the clock switching is glitch free.
Delta Sheet
27
OctalFALCTM
PEF 22558 E
Clock Modes
TCLK loss is detected if the transmit clock derived from TCLK failed to occur.
Automatic transmit clock switching is controlled by the register bit CMR4.ATCS.
If the TCLK input is used directly as transmit clock XCLK, the output of the DCO-X (CUADPLL-X) is not used. The DCO-X reference clock is SCLKX. If loss of TCLK is detected,
the transmit clock will be switched automatically to the DCO-X output which is
synchronous to SCLKX if CMR4.ATCS = 1. This switching is shown in the interrupt
status bit ISR7.XCLKSS0 which is masked by IMR7.XCLKSS0. This switching cannot
be done in general without occuring of phase jumps or spikes in the transmit clock XCLK.
Additionally after loss of TCLK the transmit clock XCLK is also lossed during the
detection time for loss of TCLK,
If the transmit clock XCLK is sourced by the DCO-X output and the DCO-X reference
clock is TCLK, the DCO-X reference will be switched to SCLK after a loss of TCLK was
detected if CMR4.ATCS = 1. This switching is shown in the interrupt status bit
ISR7.XCLKSS1 which is masked by IMR7.XCLKSS1.
In that case, the transmit clock XCLK fullfils the jitter-, wander- and frequency deviationrequiements as specified for E1/T1 after the clock source of the DCO-X was changed.
Slipping of the (active) transmit buffer should be avoided.
Comment: TCLK is sourced by RCLK in normal application, so loss of TCLK happens
because of loss of RCLK.
5.3
TCLK Frequency
TCLK supports 1.544, 3.088, 6.176, 12.352 and 24.704 MHz in T1/J1 mode and 2.048,
4.096, 8.192, 16.384 and 32.768 MHz in E1 mode and in T1/J1 channel translation
mode. If COMP = 0controlling is done by the register CMR5, bits STF(2:0), if COMP =
1 controlling is done by the register CMR1, bit STF.
5.4
RCLK Frequency
RCLK supports 1.544, 3.088, 6.176, and 12.352 in T1/J1 mode and 2.048, 4.096, 8.192,
and 16.384 MHz in E1 mode and in T1/J1 channel translation mode. If COMP =
0controlling is done by the register CMR4, bits RS(1:0), if COMP = 1 controlling is
done by the register CMR1, bits RS(1:0). If the recovered clock out (of the clock data
recovery) is the source of RCLK then only 2.048 MHz (1.544,) is possible. If the DCO-R
is the source of RCLK all above described frequencies are possible.
5.5
DCO-R/DCO-X Characteristics
The corner frequencies of DCO-R and DCO-X can be adjusted in a wider range.
Proposal: The DCO-X and the DCO-R (2nd order PLLs) must have eigenfrequencies in
the range 8 Hz to 0.2 Hz, for example 8 Hz, 4 Hz, 2 Hz, 1 Hz, 0.5 Hz, 0.25 Hz, 0.125 Hz
Delta Sheet
28
OctalFALCTM
PEF 22558 E
Clock Modes
and should have an attunation factor of about 1.1 (minimum of equivalent noise
bandwidth) for minimum jitter at the output. The appropriate P- and I- factors of the PLL
loop filter and registerbits of CMR3 and CMR6 are to be defined.
The corner frequencies after reset are 2 Hz and can be switched to 0.2 Hz with the
register bit LIM2.SCF for the receive direction (DCO-R) and with the register bit
CMR5.SCFX for the transmit direction (DCO-X) if corner frequency adjust is not enabled
by the register bit CMR2.ECFAX or CMR2.ECFAR respectively.
If corner frequency adjust is enabled it can be individually configured by using the
registers CMR3, CMR4 and CMR5.
The adaption speed can be adjusted..
LIM2.SCF for DCO-R,
CMR6.SCFX for DCO-X
LIM2,
CMR6
ECFAX for DCO-X, ECFAR for DCO-R
switches
corner
frequency to
0.2 Hz in E1
CMR2
Corner
frequency CFAX (for DCO-X)CFAR (for DCO-R) CMR3
adjust
CMR5
Table
sets corner
frequency to
2 Hz in E1
Reset
Table
P
I
P
corner
frequency
2 or 0.2 Hz
in E1
P
I
corner
frequency
range 2
0.2 Hz in E1
MUX
P I
corner
frequency
range 8
0.2 Hz
CMR4
IAR (for DCO-R)
CMR6
DCOCOMPN
MUX
P I
DCO-R
(DCO-X)
Figure 19
5.6
OctalFALC_DCO_X_adjust_2
The OctalFALCTM provides a flexible clocking unit, which references to any clock in the
range of 1.02 to 20 MHz supplied on pin MCLK, see Figure 20.
The clocking unit has two different modes:
Delta Sheet
29
OctalFALCTM
PEF 22558 E
Clock Modes
registers GCM(8:1) accordingly, see formulas in GCM6 description. All eight ports
can work in E1 or T1 mode individually. After reset the clocking unit is in flexible
master clocking mode.
In the clocking fixed mode (GCM2.VFREQ_EN = 0) the tuning of the clocking unit
is done internally so that no setting of the global clock mode registers GCM(8:1) is
necessary. All eight ports must work together either in E1 or in T1 mode.
For the calculation for the appropriate register settings the flexible Master Clock
Calculator can be used which is part of the software support of the OctalFALCTM.
All required clocks for E1 or T1/J1 operation are generated by the device internally. The
global setting depends only on the selected master clock frequency and is the same for
E1 and T1/J1 because both clock rates are provided simultaneously.
To meet the E1 requirements the MCLK reference clock must have an accuracy of better
than 32 ppm. The synthesized clock can be controlled on pins RCLK, SCLKR and
XCLK.
E1 Clocks
MCLK
PLL
GCM1...GCM8
D(15:5)
T1 / J1
Clocks
channel
1 to 8
IM(1:0)
OctalFALC__F0116
Figure 20
If the (asynchronous) microcontroller interface mode is selected by IM(1:0) the PLL must
be configured either
The SPI and SCI are synchronous interfaces and therefore need defined clocks
immediately after reset, before any device configuration is done. To enable access to
Delta Sheet
30
OctalFALCTM
PEF 22558 E
Clock Modes
serial interfaces, the clock MCLK must be active and must have a defined frequency
before reset becomes inactive. Depending on the supplied MCLK frequency the internal
PLL must be configured if the SCI- or SPI-Interface mode is selected by IM(1:0). This
can be performed either
The configuration of the PLL by pinstrapping in case of serial interface modes is done in
the same way as by using the registers GCM5 and GCM6 if asynchronous micro
controller interface mode (Intel or Motorola) is selected. Calculation of the values to be
configured by pinstrapping can be done also by using the formulas described for the
registers GCM6 or by using the flexible Master Clock Calculator which is part of the
software support of the OctalFALCTM. If the serial interfaces are selected, pinstrapping
of D(15:5) configures the PLL directly, so changes causes a direct reset of the PLL.
The conditions to trigger a reset of the central clock PLL are listed in Table 8. Every reset
of the PLL causes a reset of the clock system.
Table 8
Reset Pin
active
Delta Sheet
GCM2.VFREQ_EN
Used controller
interface
x
(will be set to 1by
reset
31
A PLL reset is
made...
always
OctalFALCTM
PEF 22558 E
Clock Modes
Table 8
Reset Pin
GCM2.VFREQ_EN
Used controller
interface
inactive
0 -> 1
or
1 -> 0
5.7
A PLL reset is
made...
asynchron
(Motorola or Intel)
if GCM5 or GCM6
are written and their
values N or M
changes
SCI or SPI
if pinstrappng
values change
asynchron
(Motorola or Intel)
never
SCI or SPI
if pinstrappng
values change
asynchron
(Motorola or Intel)
if actual values of N
or M in GCM5 in
GCM6 are different
to internal settings
of the fixed mode
SCI or SPI
if pinstrap values in
are different to
internal settings of
the fixed mode.
That is not allowed
If the central clock PLL status indication bit GIS2.PLLLS changes, an interrupt is
generated. An additional bit GIS2.PLLLC is provided to indicate the change. Masking
can be made by GIMR.PLLL. The visibility of PLLLC can be set by the register bit
IPC.VISPLL.
For COMP = 1 both of the pseudo QuadFALCs have its own (interrupt) status register
GIS2 and mask register GIMR. The status of the one PLL is doubled for the two status
registers . So masking or setting of the visibility can be made Individulally in both of the
pseudo QuadFALCs.
The status bit PLLLS is only available for COMP = 1, but the status of the PLL is shown
in GIS2.PLLLS independent on the value of COMP.
.
Delta Sheet
32
OctalFALCTM
PEF 22558 E
Framer Features
Framer Features
6.1
6.2
Note: As in FALC56 V2
In T1/J1 mode, the Automatic Remote Alarm feature (AXRA) is now compliant with
ANSI T1.403-1999 (see Figure 21).(The one-second requirement for on/off must be
fulfilled.)
Delta Sheet
33
OctalFALCTM
PEF 22558 E
Framer Features
Figure 21
6.3
AXRA Requirements
The RSC interrupt can be suppressed for cleared channels to reduce the interrupt load.
Suppression mode is selected by CCR1.RSCC = 1.
6.4
In T1/J1 ESF mode the DL-bit access is improved to reduce the number of required
register accesses by 25%. For details see Figure 22 and Figure 23. The optional mode
is selected by the new register bit FMR5.DLM. The transmit direction works accordingly.
BOM-Codes can be inserted continuously without additional microcontroller access
every multiframe.
The BOM code has the following format: 11111111 0xxxxxx0 were the left bit here of
every byte is the MSB and the right one is the LSB. (11111111 is the BOM flag, xxxxxx
is the BOM code) Thats another ordering as in ANSI T1.403, 1999, table 4 !!. Sending
is done as for HDLC: LSB first. Thats consistent to the note 1) in the ANSI: rightmost
bit transmitted first.
Delta Sheet
34
OctalFALCTM
PEF 22558 E
Framer Features
...
MSB
DL15 DL13 DL11 DL9
LSB
DL7
DL5
DL3
Interrupts
DL1
DL7
DL1
DL7
DL1
DL7
DL1
Multi Frame 1
x
DL5
DL3
Multi Frame 2
x
DL5
DL3
Multi Frame 3
x
DL5
DL3
Multi Frame 4
x
Figure 22
Multi Frame 2
Multi Frame 3
Multi Frame 4
OctalFALC_DL-Bit_Access_1
...
MSB
Multi Frame 1
..
LSB
DL7
DL1
DL7
DL7
DL1
DL7
DL5
DL5
DL3
DL3
DL1
DL1
DL5
DL5
..
Figure 23
Delta Sheet
DL3
Interrupts
DL3
unvalid
unvalid
OctalFALC_DL-Bit_Access_2
35
OctalFALCTM
PEF 22558 E
CAS Features
CAS Features
7.1
The basic operation mode (serial or register based) can be selected individually for
receive and transmit direction.
If RSIG is configured on one of the RX multifunction ports RPA...RPC, serial RX-CAS
data on RSIG are used automatically. If XSIG is configured on one of the TX
multifunction ports XPA, RPB, serial TX-CAS data on XSIG are used automatically and
XS1...16 registers are ignored.
7.2
In T1 mode the function to force all robbed bits to one can be selected to be not
performed in CAS cleared channels. This mode is selected by setting register bit
XC0.BRFO1 = 1.
7.3
In T1 mode the bit robbing idle function is selectable by register bit XC0.BRIF. If this bit
is set, bit robbing information is not overwritten by the idle code in idle channels.
Delta Sheet
36
OctalFALCTM
PEF 22558 E
HDLC/BOM Controllers
HDLC/BOM Controllers
Each of the eight ports provides three HDLC/BOM Controllers. Each of these units can
be attached to either the line side (standard) or the system side (inverse). Inverse
HDLC mode is selected by setting MODE.HDLCI = 1, MODE2.HDLCI2 = 1, or
MODE3.HDLCI3 = 1 (for each of the three HDLC controllers and each of the eight
E1/T1/J1 ports individually). Note that a detection of a Out-Band loop message (BOM
code) on the line side is only possible if the HDLC controller is attached to the line side;
a detection of a BOM code on the system side is only ossible in the inverse mode of
the HDLC controller.
Each HDLC/BOM controller can be reset individually without disturbing the transmission
on the remaining channels. Use CMDR.SRES for HDLC channel 1, CMDR3.RRES and
CMDR3.SRES for HDLC channel 2, and CMDR4.RRES and CMDR4.SRES for HDLC
channel 3, respectively.
Each of the eight ports provides one signalling controller for SS7 signaling.
The signalling controller has an interrupt status bit ISR1.SUEX which shows exceeding
of the error threshold in SS7 mode. These interrupt status bit is masked by the bit
IMR1.SUEX .
The error counter for SS7 mode can be reset by setting the register bit CMDR2.RSUC.
The error threshold for SS7 mode can be configured by setting the register bit
CCR5.SUET.
After an RDO interrupt on one HDLC controller, the receive HDLC controller needs no
reset. So a receive HDLC controller reset per channel is not necessary.
Note: CMDR.RRES resets the whole RX path and therefor all HDLC channels.
The FIFO depth is doubled to 128 byte in RX, see Table 9, and 128 byte in TX (by setting
register bit CCR2.TFTS) per HDLC/BOM controller (64 byte user and 64 byte shadow
RAM).
As in the FALC56 version V2.1 the total length of the received frame can be always read
directly in registers RBCL and RBCH after a RPF interrupt, except when the threshold is
increased during reception of that frame, but additionally to the FALC56 version V2.1 bit
RBC5 will be taken into account if the FIFO depth is 64 bytes, see Table 9 as example
for the HDLC channel 1. The register bits CCR3.RFT(2:0)2 and CCR4.RFT(2:0)3 set the
FIFO depth in the same way for the HDLC channel 2 and 3 respectively.
If a HDLC frame was completely received the content of the register RSIS (HDLC
channel1, RSIS2 andRSIS3 for HDLC channel 2 and 3) will be written as last byte into
the receive FIFO.
Delta Sheet
37
OctalFALCTM
PEF 22558 E
HDLC/BOM Controllers
Table 9
# bytes
CCR1.RFT(1:0)
MODE.RFT2
Bit Positions in
RBCL Reset by a
CMDR.RMC
Command
32
00
RBC(4:0)
16
01
RBC(3:0)
10
RBC(1:0)
11
RBC0
64
xx
RBC(5:0)
HDLC
Receiver 1...3
HDLC
Transmitter 1...3
Receive Line
Interface
1...8
Receive
Buffer
Receive
System
Interface
Transmit Line
Interface
1...8
Transmit
Buffer
Transmit
System
Interface
OctalFALC_HDLC_1
Figure 24
HDLC
Transmitter 1...3
Receive Line
Interface
1...8
Receive
Buffer
Receive
System
Interface
Transmit Line
Interface
1...8
Transmit
Buffer
Transmit
System
Interface
OctalFALC_HDLC_2
Figure 25
Delta Sheet
38
OctalFALCTM
PEF 22558 E
System Interface
Switchin between HDLC and BOM (if both MODE.BRAC and MODE.HRAC are set) will
be done in the following way:
The status bit SIS.BOM reflects the actual mode of the HDLC/BOM controller.
Note that BOM codes 7EH should be avoid.
If a BOM message occurs inside of a HDLC protocoll, the HDLC protocoll (frame) is
corrupted.
System Interface
9.1
The following multiplex modes are supported, see Figure 26, were only pins RDO of the
ports are shown, and Table 10:
8-to-1 Multiplex Mode at 16 Mbit/s. Multiplexing is done on port 1. Output pins of the
other ports are set to tristate input pins of the other ports are unused.
Dual 4-to-1 Multiplex Mode at 8 Mbit/s. Multiplexing is done on port 1 and port 5.
Output pins of the other ports are set to tristate , input pins of the other ports are
unused.
Dual 4-to-1 Multiplex Mode at 16 Mbit/s. Multiplexing is done on port 1 and port 5
were four phases are unused on every port. Disjunct phases must be used on both
ports. 16 Mbit/s multiplexing is done by external logical or on the PCB. Output RDO
is driven to low level for inactive phases. Output pins of the other ports are undefined,
input pins of the other ports are unused.
Switching between 8-to-1 Multiplex Mode (using only one port) and QuadFALC
compatible 4:1 Multiplex Modes (using two or more ports) is done by the register bit
GPC6.SSI16, see Table 10.
Multiplexing of RSIG is done in the same way as shown for RDO in Figure 26.
Demultiplexing of XDI and XSIG is done vice versa.
Delta Sheet
39
OctalFALCTM
PEF 22558 E
System Interface
OctalFALC
Pseudo QuadFALC 1
8 MHz;
4-to-1
multiplex
mode
Pseudo QuadFALC 2
8 MHz;
4-to-1
multiplex
mode
RDO1
RDO5
OctalFALC
Pseudo QuadFALC 1
16 MHz;
4-to-1
multiplex
mode
Pseudo QuadFALC 2
16 MHz;
4-to-1
multiplex
mode
RDO1
external OR
OctalFALC
16 MHz;
8-to-1
multiplex
mode
RDO1
RDO5
compatible to QuadFALC
OctalFALC_multiplex_modes
Figure 26
Table 10
GPC1.SMM
GPC6:SSI16
Mode
No multiplexing
Not defined
To perform the system interface mode the following configuration of the multi function
ports must be identical for all channels:
All other assumptions to perform the system interface mode are the same as described
in the data sheet of the QuadFALC.
Delta Sheet
40
OctalFALCTM
PEF 22558 E
System Interface
9.2
The active clock edge of SYPX can be selected related to that of the other interface
transmit data and marker. Also selection of the clock edge for SYPR is possible related
to that of the other interface receive data and marker. Use register bits SIC4.SYPRCE,
or SIC4.SYPXCE. Note that the clock selection of the transmit data and marker with
exception of SYPX is done by SIC3.RESX and that of the receive data and marker with
exception of SYPR is done by SIC3.RESR.
9.3
Tristate Modes
Table 11
Tristate Configurations for the RDO, RSIG, SCLKR and RFM Pins
- RRTRI /
RTRI
- RRTRI exor RTDMT if
RTDMT is selected on MFP
RDO, RSIG
SCLKR, RFM
Constant tristate
(without pull up and
pull down resistor)
Constant tristate
(without pull up and
pull down resistor)
Never tristate
Never tristate
Tristate during
inactive channel
phases (with pull up
resistor)
Delta Sheet
41
OctalFALCTM
PEF 22558 E
System Interface
9.4
Redundancy Mode
In redundancy mode the data inputs XDI are connected together. The outputs RDO and
the signaling outputs RSIG (if used) of two channels can be connect together in the
OctalFALCTM also, because one of them is set constantly into tristate respectively while
the other is active. Figure 27 shows the application.
Both channels must be configured identically and must be supplied with the same clocks
and (transmit) data and signaling.
Switching between both channels can be done on the line side in transmit direction by a
hardware signal if the multi function pin XPA is configured as tristate input XLT by the
register bits PC1.XPC1 = 1000b. If one pin XPA is programmed as low active
(PC1.XPC1 = 1110b) and the one of the other channel as high active
(PC1.XPC1 = 1000b), no external inverter is necessary as shown in Figure 27. So
switching between both channels on line side is possible using only one signal.
Switching can also be done on the line side in transmit direction by software, if setting
the register bit XPM2.XLT. The register bit value XPM2.XLT and the pin value of XPA
are logically ored. (That means if XPA is configured as low active then
tristate = XPM2.XLT or not(XPA). )
Because the register bit XPM2.XLT and the multi function pin XPA exist individually for
every channel, switching on the line side in transmit direction can be done between
channels of different or of the same OctalFALCTM device.
Switching between both channels can be done on the system side in receive direction
by using the registerbit SIC3.RRTRI and with or without selection of the multi function
port as RTDMT. If the RTDMT function is selected the values of RTDMT and
SIC3.RRTRI are logically exored. If in one of the both channels SIC3.RRTRI is set,
RTDMT is low active because of the logical exor, and if in the other channel SIC3.RRTRI
is cleared, RTDMT is low active because of the logical exor. So switching between both
channels on system side in receive direction is possible using only one signal.
By using the XLT, XLT and RTDMT function of the multi function ports and do the
appropriate programming of the bits SIC3.RRTRI, switching between both channels can
be done on the system and the line side together with only one common signal, as shown
in Figure 27 and Table 12.
Table 12
Configuration
Register Bits
Channel 1
Channel 2
(active/stand-by) (stand-by/active)
XLT, XLT
PC1.XPC1(3:0)
1000
1110
RTDMT
PC1.RPC1(3:0)
1101
1101
Delta Sheet
42
OctalFALCTM
PEF 22558 E
System Interface
Table 12
Configuration
Register Bits
Channel 1
Channel 2
(active/stand-by) (stand-by/active)
RLM mode
LIM0.RLM
XL1
E1/T1/J1
Transmit
Line
XDI
XL2
active/stand by
RL1
E1/T1/J1
Receive
Line
SIC3.RRTRI=0
RL2
XLT
(XPA)
RDO
RSIG
RTDMT
XL1
XDI
XL2
stand-by/active
RL1
SIC3.RRTRI=1
RL2
XLT
(XPA)
RDO
RSIG
RTDMT
OctalFALC_receiver_2
Figure 27
low/
high
To fulfill these requirements the RX- and TX-pathes of the two channels must be work
synchronous to another.
Figure 28 shows a redundancy application for long haul mode using the internal analog
switch. With the configuration shown in Table 13, switching between both channels is
possible using only one board signal which is connected to XLT, XLT, RLT and RTDMT.
Because the OctalFALCTM builds the logical equivalence out of RLT and LIM0.RTRS,
the analog switches of both channels are controlled by these signal.
Delta Sheet
43
OctalFALCTM
PEF 22558 E
System Interface
XL1
E1/T1/J1
Transmit
Line
XDI
Active/stand-by
XL2
RL1
RLS
E1/T1/J1
Receive
Line
SIC3.RRTRI = 0
LIM0.RTRS = 0
RDO
RSIG
RL2
XLT
RLT RTDMT
(XPA) (RPB) (RPA)
XL1
XDI
stand-by/active
XL2
RL1
RLS
SIC3.RRTRI = 1
LIM0.RTRS = 1
Receiver_6
RDO
RSIG
RL2
XLT
RLT RTDMT
(XPA) (RPB) (RPA)
low/high
OctalFALC_receiver_6
Figure 28
Table 13
Configuration
Register Bits
Channel 1
Channel 2
(active/stand-by) (stand-by/active)
XLT, XLT
PC1.XPC1(3:0)
1000
1110
RTDMT
PC1.RPC1(3:0)
1101
1101
SIC3.RRTRI
RLT
PC2.RPC2(3:0)
1000
1000
LIM0.RTRS
Delta Sheet
44
OctalFALCTM
PEF 22558 E
Line Interface
10
Line Interface
10.1
For optimized return loss the transmit output resistance can be configured by using the
pins XL3 and XL4 as shown in Figure 29.
Generic E1/T1/J1 applications can be built where the operation mode is selected by
software without the need for external hardware changes. Note that shorts between XL1
and XL2 are not detected by the transmit line monitor, see chapter 10.2.
The principle transmitter circuit diagram is shown in Figure 29. For non-generic
applications pins XL3 and XL4 can be left open. The serial resistance can be selected
by register programming as shown in Table 14.
XL3
XL1
1%
RSER
XL2
1%
RSER
XL4
OctalFALC_Tx_2
Figure 29
Transmit Impedances
Table 14
Parameter
Serial Resistance,
accuracy + 1%
Symbol
RSER
Values
1)
Generic E1/T1/J1
PC6.TSRE = 1 (E1)
PC6.TSRE = 0 (T1/J1)
1)
7.51)
Non generic E1
PC6.TSRE = 0
1) This value refers to an ideal transformer without any parasitics. Any transformer resistance or other parasitic
resistances have to be taken into account when calculating the final value of the output serial resistors.
Delta Sheet
45
OctalFALCTM
PEF 22558 E
Line Interface
10.2
Shorts between XL1 and XL2 cannot be detected. A short between XL1 and XL2 will not
ham the device.
10.3
The transmitter includes a programmable pulse shaper to generate transmit pulse masks
according to:
For T1: FCC68; ANSI T1. 403 1999, figure 4; ITU-T G703 11/2001, figure 10 (for
different cable lengths), for measurement configuration were Rload = 100
For E1: ITU-T G703 11/2001, figure 15 (for 0 m cable length) ; ITU-T G703 11/2001,
figure 20 (for DCIM mode), for measurement configuration were Rload = 120 or Rload
= 75
To reduce the crosstalk on the received signals in long haul applications the
OctalFALCTM offers the ability to place a transmit attenuator (Line Build-Out, LBO) in the
data path. This is used only in T1 mode. LBO attenuation is selectable with the values 0,
-7.5, -15 or -22.5 dB (register bits LIM2.LBO(2:1)). ANSI T1. 403 defines only 0 to -15 dB.
10.3.1
Delta Sheet
46
OctalFALCTM
PEF 22558 E
Line Interface
Table 15
LBO
Range
Range
[dB]
[m]
[ft]
0 to 40
0 to 133
D7
22
40 to 81
133 to 266
FA
26
81 to 122
266 to 399
3D
37
5F
3F
3F
CB
7.5
---
15
---
22.5
---
Table 16
XPM0
XPM1
XPM2
hexadecimal
RSER
Z0
Transmit Line
Interface Mode
XPM0
XPM1
XPM2
[]
[]
7.51)
120
non generic
9C
03
00
7.5
75
non generic
BD
03
00
---
reset values
7B
03
40
7.5
DCIM
Mode
EF
BD
07
hexadecimal
non generic
1) The values in this row refers to an ideal application without any parasitics. Any other parasitic resistances have
to be taken into account when calculating the final value of the output serial resistors.
10.3.2
By setting of register bit XPM2.XPDIS the pulse shape will be configured by the registers
TXP(16:1) . Each of these registers define the amplitude value of one sampling point in
the symbol. A symbol is formed by 16 sampling points.
The default setting after reset for the registers TXP(16:1) generates also the E1 pulse
shape (0m), but with an unreduced amplitude. (TXP(9:16) = 00H; TXP(1:8) = 38H=
56D) No reset value for T1 mode exists. So after switching into T1 mode, an explicit new
programming like Table 17 is necessary.
Delta Sheet
47
OctalFALCTM
PEF 22558 E
Line Interface
The pulse shape configuration will be done also by the registers TXP(16:1) if LBO
attenuation is selected. The pulse shape is then determined by both the values of
TXP(16:1) and the LBO filtering.
The given values in the following tables are optimized for transformer ratio: 1 : 2.4; cable:
AWG24 and configurations listed in Table 14.
Table 17
LBO
Range
Range
[dB]
[m]
[ft]
10
0 to 40
0 to 133
46
46
46
44
44
44
44
44
16
40 to 81
133 to 266 48
50
48
46
46
44
44
44
81 to 122
266 to 399 48
50
46
44
44
44
44
55
46
46
44
44
63
63
58
50
7.5
--
--
46
46
46
44
155
--
--
46
46
46
22.5
--
--
46
46
46
Table 18
RSE
Z0
[]
[]
21)
120
7.5
12
13
14 15 16
-17 -14
-14
-4
-4
-4
-4
16
-17 -14
-14
-4
-4
-4
-4
44
16
-25 -17
-14
-4
-4
-4
-4
44
44
16
-30 -17
-17
-4
-4
-4
-4
50
50
50
50
-60 -26
-20
-12
-8
-6
-4
44
44
44
44
16
-17 -14
-14
-4
-4
-4
-4
44
44
44
44
44
16
-17 -14
-14
-4
-4
-4
-4
44
44
44
44
44
16
-17 -14
-14
-4
-4
-4
-4
10
11
12
13
14
15
16
generic
42
40
40
40
40
40
40
42
120
non generic
63
57
57
57
57
57
57
57
-4
75
generic
42
40
40
40
40
40
40
40
7.5
75
non generic
60
58
58
58
58
58
58
58
--
reset values
56
56
56
56
56
56
56
56
DCIM
Mode
generic
20
20
20
20
20
20
20
20
7.5
DCIM
mode
non generic
28
28
28
28
28
28
28
28
1)
The values in this row refers to an ideal application without any parasitics. Any other parasitic resistances
have to be taken into account when calculating the final value of the output serial resistors.
Delta Sheet
48
OctalFALCTM
PEF 22558 E
Line Interface
10.4
In general the E1 line impedance operating modes with 75 (used with coaxial cable)
or with 120 (used with twisted pair cable) line termination are selectable by switching
resistors in parallel or using special transformers with different transfer ratios in one
package (using center tap). These two options both provide only one analog front end
circuitry for both transmission media types.
The OctalFALCTM supports a software selectable generic E1/T1/J1 solution without the
need for external hardware changes by using the integrated analog switch and two
external resistors for line impedance matching, see application example in Figure 30. By
default the analog switch is off.
This allows, for example, to switch between 100 (T1/E1 twisted pair) and 75 (E1
coax) termination resistance using the external resistors RE1 = 100 and RE2 = 300 ,
see Table 19. The analog switch can be controlled by access to the register bit
LIM0.RTRS and by hardware using the receive Multi Function Ports. For that, only one
(but not more) of the receive Multi Function Ports must be configured as Receive Line
Termination (RLT) input. For controlling of the analog switch a logical equivalence is
build out of RLT and the register bit LIM0.RTRS if RLT is configured at one multi function
port.
If the analog switched is not used in an application, the pin RLS can be left open.
externally
internally
RL1
Z0
RE1
RE2
RLS
analog
switch
RL2
OctalFALC_Analog_Switches_3
Figure 30
Delta Sheet
49
OctalFALCTM
PEF 22558 E
Line Interface
Table 19
Line
Impeance
Z0
External
Resistor RE1
External
Inter- LIM0.RTRS; RLT
Resistor RE2 nal
Analog
Switc
h
120
100 (for
common
E1/T1/J1
applications)
300 (for
off
common
off
E1/T1/J1
applications)
on
100
75
Delta Sheet
50
OctalFALCTM
PEF 22558 E
Multi Function Port Features
11
Several additional functions are available on the multi function ports, see Table 20. Old
features known from QuadFALC are shown in italic. After reset, input function is
selected (SYPR or SYPX) with exception of the ports RPC were RCLK output is
selected: The register bits PC3.RPC2 have the reset value FH. (Note that PC5.CRP must
be set to 1 for an active RCLK output. After reset PC5.CRP is 0 and RCLK is pulled
up.)
Three multi function ports (MFP) for RX - so called as RPA, RPB, RPC - and two MFPs
for TX - so called as XPA, XPB - are implemented for every channel. The port levels are
reflected in the appropriate bits of the register MFPI.
The actual logical state of the 5 multifunction ports can be read out using the register
MFPI. This function together with static output signal optins in Table 20 offers general
purpose I/O functionality on unused multi function port pins.
If a port is configured as GPOH or GPOL the port level is set fix to high or low level
respectively.
Each of the input functions may only be selected once. No input function must be
selected twice or more.
Table 20
Selec- RFP
tion
Signal
XFP
Signal
0000
SYPR
ABC
Synchronous
pulse receive
input
SYPX
AB
Synchronous
pulse transmit
input
0001
RFM
ABC
Receive frame
marker output
XMFS
AB
Transmit
multiframe
synchronization
input
0010
RMFB
ABC
Receive
multiframe begin
marker output
XSIG
AB
Transmit
signaling data
input
0011
RSIGM
ABC
AB
Transmit clock
input
0100
RSIG
ABC
AB
Transmit
multiframe begin
marker output
Delta Sheet
51
OctalFALCTM
PEF 22558 E
Multi Function Port Features
Table 20
Selec- RFP
tion
Signal
XFP
Signal
0101
DLR
ABC
XSIGM
AB
Transmit
signaling marker
output
0110
FREEZE
ABC
Freeze signaling
output
DLX
AB
0111
RFSP
ABC
Frame
synchronous
pulse output
XCLK
AB
Transmit clock
output
1000
RLT
ABC
Receive line
termination
XLT
AB
Transmit line
tristate control
high active
1001
GPI
ABC
General purpose
input
GPI
AB
General purpose
input
1010
GPOH
ABC
General purpose
output high
GPOH
AB
General purpose
output high
1011
GPOL
ABC
General purpose
output low
GPOL
AB
General purpose
output low
1100
LOS
ABC
loss of signal
indication output
reserved
AB
reserved
1101
RTDMT
ABC
XDIN
AB
transmit data
negative input
1110
RDON
ABC
receive data
negative output /
bipolar violation
output
XLT
AB
Transmit line
tristate control low
active
1111
RCLK
ABC
RCLK output
reserved
AB
Delta Sheet
52
OctalFALCTM
PEF 22558 E
Test and Maintenance
12
12.1
Different PRBS modes which are using different bits and time slots in a E1/T1/J1 frame
can be selected, see Table 22.
In the so called unframed mode all bits of all slots in a E1/T1/J1 frame are used for
PRBS.
In the so called framed mode the frame byte (time slot 0) of an E1 frame or the frame
bit in a T1/J1 frame is not used for PRBS respectively.
Selection of the PRBS modes unframed and framedis done by TPC0.PRM = 00b
and TPC0.FRA.
For TPC0.PRM not 00b, each time slot of an E1/T1/J1 signal can be selected indiviually
to send and receive a PRBS signal. Selection is done by the registers PRBSTS1 to
PRBSTS4. Here the used time slot numbers are the same as used normally for
numbering of the time slots:
-In E1 frames time slot 0 (TS0) up to time slot 31 (TS31), were TS0 is the frame byte
(time slot number 0 indicates the frame byte).
-In T1/J1 frames the time slot number 0 indicates the frame bit and the time slot numbers
1 up to 24 indicates the TS1 up to TS24.
If a time slot is used or not for PRBS sending and reception is controlled by the registers
PRBSTS1..4. The number of used time slots for PRBS is so called as N. The range of
N is 1, ..., 32 for E1 and 1, ..., 25 for T1/J1 (if no channel translation mode is selected)
because of the frame bit. The time slot selection 0 up to 31 for E1 or 0 up to 24 for T1/J1
(if no channel translation mode is selected) by PBBSTS(1:4) is common for all eight ports
respectively.
If channel translation mode is selected, the time slot numbers are the same as used in
the ordering of the active time slots at the system interface (0, ..., 31), see also table 31
of QuadFALC data sheet.
The N multiple time slots are selected arbitrarily for PRBS. The PRBS data stream has
to be written into or read from the time slots consecutive respectively.
The selected time slot numbers are related to the mapping used on the system interface.
Note that deselection of time slot 0 (PRBSTS1.TS0 = 0) perfomes a framed mode for
E1/T1/J1.
For TPC0.PRM not 00b, normally all eight bits of the time slots are used for PRBS
(N 64 kbit/s). To allow CAS-BR in T1 mode, only 7 MSBs of the all time slots which
are selected for PRBS can be optionally used for PRBS to avoid CAS disturbance
(N 56 kbit/s), the eights bit of all time slots (which is the CAS bit in T1) is not used
for PRBS. Setting of this mode is performed by setting the register bits TPC0.PRM(1:0)
Delta Sheet
53
OctalFALCTM
PEF 22558 E
Test and Maintenance
to11b. Note that this mode can be used also in E1 mode, but makes no sense: In E1
CAS disturbance can be avoided by deselection of the appropriate time slot 16.
Note that the N 56 kbit/s mode is automatically a framed mode in T1 because the
frame bit in TS0 is identical to the robbed CAS bit.
Note that for N 64 kbit/s selection and selection af all time slots by PRBSTS(1:4) all
bits in the frame are used for PRBS (that is an unframed mode).
The kind of PRBS patterns (polynoms) can be selected to be 211-1, 215-1, 220-1or 223-1
by the register bits TPC0.PRP(1:0) and LCR1.LLBP, see Table 22. For definition of this
polynoms see the Standards ITU-T O.150, O.151. and TR62441. New against
FALC56v2.1 are the patterns 211-1 and 223-1 which can be selected only if TPC0.PRM
not 00b.
The transmit of PRBS pattern is enabled by register bit LCR1.XPRBS. With the register
bit LCR1.FLLB switching between not inverted and inverted transmit pattern can be
done.
The receive monitoring of PRBS patterns is enabled by register bit LCR1.EPRM. In
general, dependend on bit LCR1.EPRM the source of the interrupt status bit
ISR1.LLBSC changed, see register description. The kind of detected PRBS pattern in
the receiver is shown in the status register bits PRBSSTA.PRS. Every change of the bits
PRS in PRBSSTA sets the interrupt bit ISR1.LLBSC if register bit LCR1.EPRM is set. No
pattern is also detected if signal alarm simulation is active.
The detection of all_zero or all_ones is done over 12, 16, 21 or 24 consecutive bits,
dependent on the choosed PRBS polynom (11, 15, 20 or 23). The detection of all_zero
or all_ones is independent on LCR1.FLLB. Note that if the information about the first
reached PRBS status after the monitor was enabled (PRBS pattern detected or
inverted PRBS pattern detected) is combined with the status information all-zero
pattern detected or all-ones pattern detected, the controller can conclude the real
polarity of the all-ones or all-zeros pattern.
Because every bit error in the PRBSequence increments the bit error counter BEC, no
special status information like PRBS detected with errors is given here.
Table 21
TPC0.PRP
TPC0.PRM
LCR1.LLBP
Kind of
polynomial
00
01 or 11
211-1
01
01 or 11
215-1
10
01 or 11
220-1
11
01 or 11
223-1
Delta Sheet
54
Comment
OctalFALCTM
PEF 22558 E
Test and Maintenance
Table 21
TPC0.PRP
TPC0.PRM
LCR1.LLBP
Kind of
polynomial
Comment
xx
00
215-1
20
SW compatibel to
QuadFALC
xx
00
Table 22
2 -1
TPC0.PRM
TPC0.FRA
kind of selection
comment
00
Unframed
00
Framed
01
N x 64 kbit/s
10
Reserved
11
N x 56 kbit/s
12.2
The PPR (Periodical Performance Report, see ANSI T1.403) status which is sent out in
the data link channel of the extended superframe format (ESF/F24 only) automatically
(dependent on the bit CCR5.EPR) or manually (if setting CMDR2.XPPR to 1; then last
PPR is sent once; CMDR2.XPPR bit is cleared automatically after sending was finished)
can additionally be read from registers PPR0 and PPR1, too. Performance data is
updated once every second. Only the actual performance parameters (for t0) are
accessible via registers. New data is available immediately after the one second interrupt
is triggered and must be read before the next one-second interrupt occurs.
12.3
Automatic loop switching (activation and deactivation) based on detected In-Band Loop
codes can be done.
Detection and generation of In-Band Loop code is supported on line and system side
independent from another.
Detection, generation and loop switching is possible on all eight channels, independent
from another.
Framed and unframed In-Band loop code can be generated and detected.
Delta Sheet
55
OctalFALCTM
PEF 22558 E
Test and Maintenance
Automatic loop switching must be enabled through configuration register bits ALS.SILS
for the In-Band Loop codes coming from the system side and ALS.LILS for the In-Band
Loop codes coming from the line side respecively.
Automatic loop switching is logically ored with the appropriate loop switching by register
bits.
If a remote loop is activated by an automatic loop switching the register bit LIM0.JATT
controls also if the jitter attunator is active or not.
If ALS.LILS is set, the remote loop is activated after an activation In-Band loop code (see
ANSI T1 404, chapter 9.4.1.1.) was detected from the line side and if the local loop is not
activated by LIM0.LL = 1. The remote loop is deactivated after a deactivation In-Band
loop code (see ANSI T1 404, chapter 9.4.1.2.) was detected from the line side. (But if the
remote loop is addtionally activated by LIM0.RL = 1 the remote loop is still active,
because automatic loop switching is logically ored with the appropriate loop switching by
register bits.)
If ALS.SILS is set, the local loop is activated after an activation In-Band loop code (see
ANSI T1 404, chapter 9.4.1.1.) was detected from the system side. The local loop is
deactivated after a deactivation In-Band loop code (see ANSI T1 404, chapter 9.4.1.2.)
was detected from the system side. (But if the local loop is addtionally activated by
LIM0.LL = 1 the local loop is still active, because automatic loop switching is logically
ored with the appropriate loop switching by register bits.)
ALS.SILS and ALS.LILS both must not be set to 1 simultaneous.
If ALS.SILS or ALS.LILS are set after an In-Band loop code was detected, no automatic
loop switching is performed.
If ALS.LILS is cleared, an automatic activated remote loop is deactivated.
If ALS.SILS is cleared, an automatic activated local loop is deactivated.
The type of detected In-Band loop codes is shown in the interrupt status register bits
ISR6.(3:0)
The bits ISR6.(3:0) will be set to 1 if an appropriate In-Band code were detected,
independent if automatic loop switching is enabled or not . (Because the controller knows
if automatic loop switching is enabled, it knows if a loop is activated or not.) Code
detection status only for the line side is displayed in status register bits RSP. LLBBD and
RSP.LLBAD . Masking of ISR6.(3:0) for interrupt can be done by register bits IMR6.(3:0).
Sending of In-Band loop codes is done by the OctalFALCTM lasting for at least 5
seconds. Detection of received In-Band loop codes and automatic switching into the
loopback (activaton or deactivation) will be done after the code is lasting for at least 16
or 32 patterns or 4 or 5 seconds, dependend on the setting of the register bits
INBLDTR.INBLDT(1:0).
Delta Sheet
56
OctalFALCTM
PEF 22558 E
Test and Maintenance
Note:
1. For SF format the protocoll currently used by the carriers for network access to the
customer installation (CI) is an in-band control code. Note that E1/T1repeaters are in
general transparent, so they have not any influence on the in-band signaling.
2. If In Band Signaling is enabled in transmit direction, all data bits of all 24 time slots of
a frame are overwritten by signaling information (code). In Band Signaling is an
unchannelized signaling method. If the 1. bit of a frame (frame bit) will be also
overwritten it is the so called unframed signaling, otherwise it is called framed
signaling. This configuration can be done by the register bit LCR1.FLLB.
3. If the signaling code is used for line loop back switching it is so called as LLB code
(line loop back). Two kinds of codes exist: LLB down code for deactivation of the
loop and LLB up code for activation. The codes are defined in ANSI-T1.403, 1999
in chapter 9.4.1.1 and 9.4.1.2. respectively.
4. An In-Band loop pattern has a minimum length of about 51200 symbols (100 double
frames).
12.4
Note: For the ESF format activation and deactivation of loopbacks are performed by
using Out-Band messages (BOM) described in ANSI-T1.403, 1999 in chapter
9.4.2.The BOM code has the following format: 11111111 0xxxxxxx0 were the first
bit of every byte is the MSB and the last is the LSB. (11111111 is the BOM flag.)
Thats another ordering as in the ANSI table!!. Sending is done as for HDLC: LSB
first, 11111111 first. Thats consistent to the note 1) in the ANSI: rightmost bit
transmitted first.
The OctalFALCTM performes the following functionalities regarding the Out-band loop
codes (bit oriented messages, BOM) on all eight channels independent from each other:
Delta Sheet
57
OctalFALCTM
PEF 22558 E
Test and Maintenance
Table 23
Function
Message
00001110 11111111
00111000 11111111
00010100 11111111
00110010 11111111
00100100 11111111
12.4.1
The OctalFALCTM performes the following functionalities regarding the Out-band loop
codes (bit oriented messages, BOM) on all eight channels independent from each other:
Loop switching (Out-band loop switching) is possible by enabling of the BOM receiver
1 signaling (MODE.BRAC = 1 and CCR1.EITS = 1) and detection of the following OutBand loop messages related to ANSI-T1.403, 1999, table4:
Table 24
Function
00001110 11111111b
00111000 11111111b
00010100 11111111b
00110010 11111111b
00100100 11111111b
If the register bit CCR2.RBFE is set, BOM messages are accepted if at least seven
consecutive and identical BOM messages were received.
Dependent on the BOM mode (configured by register bits CCR1.BRM and CCR2.RBFE)
the content of register RSIS will be written as last byte into the receive FIFO.
Automatic loop switching by BOM messages is logically ored with the appropriate loop
switching by register bits.
Delta Sheet
58
OctalFALCTM
PEF 22558 E
Test and Maintenance
If ALS.SOLS is set, the payload loop is activated after the payload loopback activate
code was detected from the line side or the system side and if the local loop is not
activated by LIM0.LL = 1. The payload loop is deactivated after an appropriate
deactivation Out-Band loop code was detected from the line side or the system side. (But
if the payload loop is additionally activated by FMR2.PLB = 1 the payload loop is still
active, because automatic loop switching is logically ored with the appropriate loop
switching by register bits.)
If ALS.LOLS is set, the remote loop is activated after the line loopback activate code
was detected from the line side or the system side and if the local loop is not activated
by LIM0.LL = 1. The remote loop is deactivated after the line loopback deactivate
code was detected from the line side or the system side. (But if the remote loop is
additionally activated by LIM0.RL = 1 the remote loop is still active, because automatic
loop switching is logically ored with the appropriate loop switching by register bits.)
If the remote loop is activated by an automatic loop switching the register bit LIM0.JATT
controls also if the jitter attenuator is active or not.
ALS.SOLS and ALS.LOLS both can be set to 1 simultaneous.
Because BOM messages coming from the system side are not included in the E1/T1/J1
standards, receive of these BOM messages and the possibility of automatic loop
switching (ALS.SOLS) are features of the OctalFALCTM. It has to be handle carefully to
avoid deadlocks.
If ALS.SOLS or ALS.LOLS are set after an Out-Band loop code was detected, no
automatic loop switching is performed.
If ALS.LOLS is cleared, an automatic activated remote loop is deactivated.
If ALS.SOLS is cleared, an automatic activated payload loop is deactivated.
The kind of performed automatic loop switching caused by the appropriate detected Outband message is shown in the register bits ISR6.(7:4). Masking of ISR6.(7:4) for
controlling of the interrupt can be done by register bits IMR6.(7:4). If an Out-band
message were detected, the appropriate register bits ISR6.(7:4) will be set to 1,
independent if automatic loop switching has been enabled. (Because the micro controller
knows if automatic loop switching is enabled, it knows if a loop is activated or not.)
A detection of an Out-band loop message (BOM) universal loopback deactivate sets
both bits ISR6.SOLSD and ISR6.LOLSD, independent if a loop is active (switched) or
not. Dependent on ALS.LOLS or ALS.SOLS the remote or the payload loopback is
switched off respectively.
A received BOM message causes setting of the interrupt bit ISR0.RME and is stored in
the receive FIFO, marked with a BOM frame.
Note that detection of Out-band Loop messages (BOM codes) is only possible either on
the line side or the system side, dependent on the configuration of the HDLC controller:
If the HDLC/BOM controller 1 is attached to the line side (MODE.HDLCI = 0) only BOM
messages coming from the line side can be detected. If the HDLC/BOM controller is
Delta Sheet
59
OctalFALCTM
PEF 22558 E
Test and Maintenance
attached to the system side (MODE.HDLCI = 1), so called inverse configuration) only
BOM messages coming from the system side can be detected. BOM messages coming
from the system side are not included in (ANSI-)standards, but can be handled by the
OctalFALCTM.
12.5
The kind of count up behaviour of the frame error counter FEC can be controlled by the
register bit DEC.FECC because there are differences in the ANSI standard T1-403
between 1995 and 1999:
-FEC count up will be done also if a severely error occurs as it is described in ANSI-T1403 1995: DEC.FECC = 0.
-FEC count up is not done if a simultaneous severely error occurs as described in ANSIT1-403 1999: DEC.FECC = 1.
Note that the FEC status is stored in the registers FECH and FECL.
12.6
An SEF interrupt statusbit ISR7.SEFEI and an appropriate mask register bit IMR7.SEFEI
is provided, which shows SEF errors according to ANSI-T1.231:
6.1.2.2.2: An SEF defect is determined by examining contiguous time windows for
frame bit errors. For SF, the window size is 0.75 ms, and only the Ft-bits are examined.
For ESF, the window size is 3 ms, and only the frame pattern sequence (FPS) bits are
examined.
An SEF defect occurs when two or more frame bit errors in a window are detected. An
SEF defect is terminated when the signal is in-frame and there are less than two frame
bit errors in a window.
Note that an AIS-CI and an AIS signal (alarm indication signal), or a signal that is OOF
(out of frame), will typically cause an SEF defect.
12.7
The TAP (Test Access Port) is conform to the IEEE standard 1149.1-2001.
Complete Boundary Scan Number: (MSB...LSB) = 0001 0000 0000 1101 1110 0000
1000 0011B. It consists on:
Version Number (1st 4 bits) = 0001B
Part Number (next 16 bits) = 0000 0000 1101 1110B
Manufacturer ID (next 11 bits) = 0000 1000 001B
LSB = 1B
Delta Sheet
60
OctalFALCTM
PEF 22558 E
Supported Standards
13
Supported Standards
ANSI T1.231
ITU-T G.812
ITU-T G.733
ITU-T JG.733
JEDECJ-STD-020A-1999-04
JEDECJ-STD-020B-1999-07
14
Development Support
14.1
IBIS Model
14.2
Development Tools
An EASY22558 evaluation board will be provided for device demonstration and testing.
15
Register Functions
After reset or if COMP = 1, the behavior is the same as for QuadFALC V2.1. and any
new functions are not valid. Full software compatibility is realized. Any new function to
be used must be enabled explicitly.
The higher address part of all global registers is 00H, that of the port (channel) specific
ones include the channel number 1 to 8 and is marked in the following tables withxxH.
For the description of the registers see the datasheet of the OctalFALCTM (Users
Manual).
15.1
The following global registers require specific handling, depending on the compatibility
mode selection. See Figure 31 to Figure 32 for more detail.
Delta Sheet
61
OctalFALCTM
PEF 22558 E
Register Functions
QuadFALC V2.1:
CIS (global)
GIS (per channel)
PLLL
---
---
---
---
---
PLLL
---
---
---
PLLL
---
---
---
---
---
GIS (A10=CS2=x)
GIS (A10=x)
GIS2 (A10=x)
---
---
---
---
---
PLLIC
PLLLS
PLLLC
OctalFALC_Registers_1
Figure 31
For the OctalFALCTM in compatibility mode (pin COMP = 1) the nomenclature for the
register bits of CIS for A10 = 0 (pseudo-QuadFALC 2, GIS8 to GIS5) is taken to declare
the apropriate channels 8 to 5, but the name of the bits is also GIS4 to GIS1 as for A10
= 1.
Delta Sheet
62
OctalFALCTM
PEF 22558 E
Register Functions
QuadFALC V2.1:
VSTR
Pseudo-QuadFALC 1
Pseudo-QuadFALC 2
DSTR (A10=CS2=0; CS1=1)
DSTR (A10=x)
OctalFALC_Registers_2
Figure 32
15.2
The register GPC1 (global port configuration register 1) is used in the QuadFALC to
configure the sources of FSC out of the 4 channels. In compatibility mode of the
OctalFALCTM (pin COMP = 1) this register must have the same function. That means
one GPC1 register exists in every of the both pseudo QuadFALCs. So with these one
GPC1register its only possible to control a 4:1 multiplexer. But really eight channels
exists in the OctalFALCTM and therefor 8:1 multiplexing must be performed, because
only one FSC/SEC pin exists in the OctalFALCTM. Figure 33 shows the principle of the
solution using an additional 2:1 multiplexer.
Delta Sheet
63
OctalFALCTM
PEF 22558 E
Register Functions
A(9:0)
GPC1, address 85
CSFP(1:0)
FSS(1:0)
CS1
COMP = 1
Pseudo QuadFALC 1
enable
CSFP(1:0)
GPC1, address 85
FSS(1:0)
SEC/FSC
CS2
Pseudo QuadFALC 2
GPC1, address 85
A(10:0)
CSFP(1:0)
COMP = 0
FSS(2:0)
enable
SEC/FSC
OctalFALC_SEC_configuration
Figure 33
The 2:1 multiplexer is controlled by the register bits GPC1.CSFP(1:0) of the second
Pseudo QuadFALC. Enable of the SEC/FSC pin as output is performed by the register
bits GPC1.CSFP(1:0) of the first and the second Pseudo QuadFALC were all are logical
ored.
In not compatibility mode the one global GPC2 register is used instead of the both GPC1
registers in compatibility mode.
15.3
Only the additional registers or registers with additional bits compared to the
QuadFALC V2.1 are listed below. For detailed register description see the
datasheet of the OctalFALCTM (Users Manual).
Delta Sheet
64
OctalFALCTM
PEF 22558 E
Register Functions
Table 25
Offset Address
MODE_E
Mode Register
03H
IPC_E
08H
CCR2_E
0AH
RDICR_E
0BH
IMR3_E
17H
IMR4_E
18H
IMR5_E
19H
IMR6_E
1AH
XPM2_E
28H
SIC4_E
2AH
LIM0_E
36H
SIC3_E
40H
CMR4_E
41H
CMR5_E
42H
CMR6_E
43H
CMR1_E
44H
CMR2_E
45H
CMR3_E
48H
PC1_E
80H
PC2_E
81H
PC3_E
82H
PC5_E
Port Configuration 5
84H
GPC1_E
85H
PC6_E
Port Configuration 6
86H
CMDR3_E
Command Register 3
88H
CMDR4_E
Command Register 4
89H
GPC2_E
8AH
CCR3_E
8BH
CCR4_E
8CH
CCR5_E
8DH
Delta Sheet
65
OctalFALCTM
PEF 22558 E
Register Functions
Table 25
Offset Address
MODE2_E
Mode Register 2
8EH
MODE3_E
Mode Register 3
8FH
GCM2_E
93H
GCM4_E
95H
XFIFO2L_E
9CH
XFIFO2H_E
9DH
XFIFO3L_E
9EH
XFIFO3H_E
9FH
TSE0_E
A0H
TSBS2_E
A2H
TSBS3_E
A3H
TSS2_E
A4H
TSS3_E
A5H
GIMR_E
A7H
TPC0_E
A8H
TXP1_E
TX Pulse Template 1
C1H
TXP2_E
TX Pulse Template 2
C2H
TXP3_E
TX Pulse Template 3
C3H
TXP4_E
TX Pulse Template 4
C4H
TXP5_E
TX Pulse Template 5
C5H
TXP6_E
TX Pulse Template 6
C6H
TXP7_E
TX Pulse Template 7
C7H
TXP8_E
TX Pulse Template 8
C8H
TXP9_E
TX Pulse Template 9
C9H
TXP10_E
TX Pulse Template 10
CAH
TXP11_E
TX Pulse Template 11
CBH
TXP12_E
TX Pulse Template 12
CCH
TXP13_E
TX Pulse Template 13
CDH
TXP14_E
TX Pulse Template 14
CEH
TXP15_E
TX Pulse Template 15
CFH
Delta Sheet
66
OctalFALCTM
PEF 22558 E
Register Functions
Table 25
Offset Address
TXP16_E
TX Pulse Template 16
D0H
GPC3_E
D3H
GPC4_E
D4H
GPC5_E
D5H
GPC6_E
D6H
INBLDTR_E
D7H
ALS_E
D9H
PRBSTS1_E
DBH
PRBSTS2_E
DCH
PRBSTS3_E
DDH
PRBSTS4_E
DEH
IMR7_E
DFH
Table 26
Offset
Address
4A
VSTR_E
6E
GIS_E
6F
CIS_E
90
RBC2_E
91
RBC3_E
9A
SIS3_E
9B
RSIS3_E
A9
SIS2_E
AA
RSIS2_E
AB
MFPI_E
AC
ISR6_E
AD
GIS2_E
D8
ISR7_E
DA
PRBSTA_E
Delta Sheet
67
OctalFALCTM
PEF 22558 E
Register Functions
Table 26
Offset
Address
E7
DSTR_E
FE
CLKSTAT_E
Table 27
Offset
Address
MODE_T
Mode Register
03H
IPC_T
08H
CCR1_T
09H
CCR2_T
0AH
IMR3_T
17H
IMR4_T
18H
IMR5_T
19H
IMR6_T
1AH
FMR5_T
21H
XC0_T
Transmit Control 0
22H
XPM2_T
28H
SIC4_T
2AH
LIM0_T
36H
SIC3_T
40H
CMR4_T
41H
CMR5_T
42H
CMR6_T
43H
CMR1_T
44H
CMR2_T
45H
CMR3_T
48H
DEC_T
60H
PC1_T
Port Configuration 1
80H
PC2_T
Port Configuration 2
81H
PC3_T
Port Configuration 3
82H
Delta Sheet
68
OctalFALCTM
PEF 22558 E
Register Functions
Table 27
Offset
Address
PC4_T
Port Configuration 4
83H
PC5_T
Port Configuration 5
84H
GPC1_T
85H
PC6_T
Port Configuration 6
86H
CMDR3_T
Command Register 3
88H
CMDR4_T
Command Register 4
89H
GPC2_T
8AH
CCR3_T
8BH
CCR4_T
8CH
MODE2_T
Mode Register 2
8EH
MODE3_T
Mode Register 3
8FH
GCM2_T
93H
GCM4_T
95H
XFIFO2L_T
9CH
XFIFO2H_T
9DH
XFIFO3L_T
9EH
XFIFO3H_T
9FH
TSE0_T
A0H
TSBS2_T
A2H
TSBS3_T
A3H
TSS2_T
A4H
TSS3_T
A5H
GIMR_T
A7H
TPC0_T
A8H
TXP1_T
TX Pulse Template 1
C1H
TXP2_T
TX Pulse Template 2
C2H
TXP3_T
TX Pulse Template 3
C3H
TXP4_T
TX Pulse Template 4
C4H
TXP5_T
TX Pulse Template 5
C5H
TXP6_T
TX Pulse Template 6
C6H
Delta Sheet
69
OctalFALCTM
PEF 22558 E
Register Functions
Table 27
Offset
Address
TXP7_T
TX Pulse Template 7
C7H
TXP8_T
TX Pulse Template 8
C8H
TXP9_T
TX Pulse Template 9
C9H
TXP10_T
TX Pulse Template 10
CAH
TXP11_T
TX Pulse Template 11
CBH
TXP12_T
TX Pulse Template 12
CCH
TXP13_T
TX Pulse Template 13
CDH
TXP14_T
TX Pulse Template 14
CEH
TXP15_T
TX Pulse Template 15
CFH
TXP16_T
TX Pulse Template 16
D0H
GPC3_T
D3H
GPC4_T
D4H
GPC5_T
D5H
GPC6_T
D6H
INBLDTR_T
D7H
ALS_T
D9H
PRBSTS1_T
DBH
PRBSTS2_T
DCH
PRBSTS3_T
DDH
PRBSTS4_T
DEH
IIMR7_T
DFH
Table 28
Offset
Address
VSTR_T
4AH
GIS_T
6EH
CIS_T
6FH
RBC2_T
90H
RBC3_T
91H
Delta Sheet
70
OctalFALCTM
PEF 22558 E
Register Functions
Table 28
Offset
Address
SIS3_T
9AH
RSIS3_T
9BH
RFIFO2L_T
9CH
RFIFO2H_T
9DH
RFIFO3L_T
9EH
RFIFO3H_T
9FH
SIS2_T
A9H
RSIS2_T
AAH
MFPI_T
ABH
ISR6_T
ACH
GIS2_T
ADH
PPR0_T
D1H
PPR1_T
D2H
ISR7_T
D8H
PRBSTA_T
DAH
DSTR_T
E7H
CLKSTAT_T
FEH
Delta Sheet
71
OctalFALCTM
PEF 22558 E
External Signals
16
External Signals
In addition to the signals known from QuadFALC, several add-on functions are
provided.
The logic symbol is shown in Figure 1.
A signal list is given in Table 29.
Only additional signals or signals with extended functions against the
QuadFALC V2.1 are listed. For functional description of the other signals see the
QuadFALC V2.1 Data Sheet (Users Manual) or OctalFALCTM Data Sheet (Users
Manual).
If a pin function is controlled by a register (e.g. multi function pins) the reset configuration
of this pin like I/O, tristate, PD and PU is given by the reset value of the appropriate
register.
Table 29
Pin No.
I/O Signals
Ball
No.
Name
Pin
Buffer Function
Type Type
7A
RLS21
IO
3A
RLS22
IO
3T
RLS23
IO
7R
RLS24
IO
11T
RL1.5
RDIP5
ROID5
RL2.5
RDIN5
RCLKI5
Receive Clock 5
9T
10T
RLS25
IO
13T
RL1.6
RDIP6
ROID6
Delta Sheet
72
OctalFALCTM
PEF 22558 E
External Signals
Table 29
Pin No.
Ball
No.
Name
Pin
Buffer Function
Type Type
15T
RL2.6
RDIN6
RCLKI6
Receive Clock 6
14T
RLS26
IO
13A
RL1.7
RDIP7
ROID7
RL2.7
RDIN7
RCLKI7
Receive Clock 7
15A
14A
RLS27
IO
11A
RL1.8
RDIP8
ROID8
RL2.8
RDIN8
RCLKI8
Receive Clock 8
10A
10B
RLS28
IO
7C
XL3.1
6C
XL4.1
4C
XL3.2
3C
XL4.2
Delta Sheet
73
OctalFALCTM
PEF 22558 E
External Signals
Table 29
Pin No.
Ball
No.
Name
Pin
Buffer Function
Type Type
4P
XL3.3
3P
XL4.3
7N
XL3.4
6N
XL4.4
11N
XL1.5
XDOP5
XOID5
XL2.5
XDON5
XFM5
10N
11P
XL3.5
10P
XL4.5
14N
XL1.6
XDOP6
XOID6
XL2.6
XDON6
XFM6
13N
14P
XL3.6
13P
XL4.6
Delta Sheet
74
OctalFALCTM
PEF 22558 E
External Signals
Table 29
Pin No.
Ball
No.
Name
Pin
Buffer Function
Type Type
14D
XL1.7
XDOP7
XOID7
XL2.7
XDON7
XFM7
13D
14C
XL3.7
13C
XL4.7
11E
XL1.8
XDOP8
XOID8
XL2.8
XDON8
XFM8
10E
11D
XL3.8
10D
XL4.8
Delta Sheet
75
OctalFALCTM
PEF 22558 E
External Signals
Table 29
Pin No.
Ball
No.
Name
Pin
Buffer Function
Type Type
8B
COMP
PU
6B
IM1
PU
4B
IM0
PU
Delta Sheet
76
OctalFALCTM
PEF 22558 E
External Signals
Table 29
Pin No.
Name
Pin
Buffer Function
Type Type
K12
J12
J15
J16
J14
J13
Delta Sheet
A10
PU
CS2
PU
Chip Select 2
Low active chip select for second
pseudo QuadFALC if COMP = 1B
and if microcontroller mode (Intel,
Motorola) is selected, see Table 1 and
Table 30
A5
PU
A5
PU
A4
PU
A4
PU
A3
PU
A3
PU
A2
PU
A2
PU
A1
PU
A1
PU
77
OctalFALCTM
PEF 22558 E
External Signals
Table 29
Pin No.
Ball
No.
Name
Pin
Buffer Function
Type Type
G16
A0
PU
A0
PU
D15
IO
PU
PLL10
PU
D14
IO
PU
PLL9
PU
D13
IO
PU
PLL8
PU
D12
IO
PU
PLL7
PU
D11
IO
PU
PLL6
PU
D10
IO
PU
PLL5
PU
D9
IO
PU
PLL4
PU
1F
2F
3F
4F
1G
2G
3G
Delta Sheet
78
OctalFALCTM
PEF 22558 E
External Signals
Table 29
Pin No.
Ball
No.
Name
Pin
Buffer Function
Type Type
1H
D8
IO
PU
PLL3
PU
D7
IO
PU
PLL2
PU
D6
IO
PU
PLL1
PU
D5
IO
PU
PLL0
PU
D2
IO
PU
SCI_CLK
SCLK
D1
IO
PU
SCI_RXD
PU
SDI
PU
D0
IO
PU
SCI_TXD
PP or
oD
SDO
PU
2H
1J
3H
3K
1K
2K
Delta Sheet
79
OctalFALCTM
PEF 22558 E
External Signals
Table 29
Pin No.
Ball
No.
Name
Pin
Buffer Function
Type Type
12H
CS
PU
Chip Select
Low active chip select if SPI or SCI
interface mode is selected or if COMP =
0B and microcontroller mode (Intel,
Motorola) is selected, see Table 1
CS1
PU
Chip Select 1
Low active chip select for first pseudo
QuadFALC if COMP = 1B and if
microcontroller mode (Intel, Motorola)
is selected, see Table 1 and Table 30.
INT
Interrupt Output
if COMP = 0B
INT1
Interrupt Output 1
Interrupt output of first pseudo
QuadFALC if COMP = 1B
14H
INT2
Interrupt Output 2
Interrupt output of second pseudo
QuadFALC if COMP = 1B
14G
READY
Data Ready
(Intel Bus Mode)
DTACK
Data Acknowledge
(Motorola Bus Mode)
11H
Clock Signals
-
16P
SCLKR5
IO
PU
16M
SCLKR6
IO
PU
13F
SCLKR7
IO
PU
16E
SCLKR8
IO
PU
12M
SCLKX5
IO
PU
16L
SCLKX6
IO
PU
12F
SCLKX7
IO
PU
16D
SCLKX8
IO
PU
System Interface
-
15P
Delta Sheet
RDO5
80
OctalFALCTM
PEF 22558 E
External Signals
Table 29
Pin No.
Ball
No.
Name
Pin
Buffer Function
Type Type
10M
RDO6
15F
RDO7
13E
RDO8
11M
XDI5
14L
XDI6
9F
XDI7
15C
XDI8
Multifunction Ports
-
1B
RPA1
IO
PU/-
2D
RPB1
IO
PU/-
7E
RPC1
IO
PU/-
6E
RPA2
IO
PU/-
8E
RPB2
IO
PU/-
9E
RPC2
IO
PU/-
4L
RPA3
IO
PU/-
2L
RPB3
IO
PU/-
1L
RPC3
IO
PU/-
4M
RPA4
IO
PU/-
5M
RPB4
IO
PU/-
2N
RPC4
IO
PU/-
16R
RPA5
IO
PU/-
15N
RPB5
IO
PU/-
16N
RPC5
IO
PU/-
13M
RPA6
IO
PU/-
13L
RPB6
IO
PU/-
15L
RPC6
IO
PU/-
16F
RPA7
IO
PU/-
14F
RPB7
IO
PU/-
10F
RPC7
IO
PU/-
12E
RPA8
IO
PU/-
Delta Sheet
81
OctalFALCTM
PEF 22558 E
External Signals
Table 29
Pin No.
Ball
No.
Name
Pin
Buffer Function
Type Type
15D
RPB8
IO
PU/-
11F
RPC8
IO
PU/-
3E
XPA1
IO
PU/-
2E
XPB1
IO
PU/-
5F
XPA2
IO
PU/-
6F
XPB2
IO
PU/-
7L
XPA3
IO
PU/-
2M
XPB3
IO
PU/-
1P
XPA4
IO
PU/-
1R
XPB4
IO
PU/-
14M
XPA5
IO
PU/-
15M
XPB5
IO
PU/-
12L
XPA6
IO
PU/-
11L
XPB6
IO
PU/-
14E
XPA7
IO
PU/-
15E
XPB7
IO
PU/-
16C
XPA8
IO
PU/-
16B
XPB8
IO
PU/-
Pinstrapping Overview
Pin
Used
Pinstrapping Function
COMP
always
IM(1:0)
always
Delta Sheet
82
OctalFALCTM
PEF 22558 E
Package
Table 30
Pin
Used
Pinstrapping Function
A(10)
only in micro
controller
interface
modes
A(5:0)
only in SCI
interface
mode
D(15:5)
only in SCI or
SPI interface
mode
17
Package
Delta Sheet
83
OctalFALCTM
PEF 22558 E
Package
A16
Index Marking
T1
0.3 MIN.
0.25 C
0.2
256x
0.25 M C A B
0.1 M C
0.5 0.1
1.5 MAX.
15 x 1 = 15
A1
RY
A
IN
IM
L
RE
17 0.1
17 0.1
Index Marking
GPA09431
Figure 34
Delta Sheet
OctalFALCTM
PEF 22558 E
Electrical Characteristics
18
Electrical Characteristics
18.1
Table 31 defines the maximum voltages and temperature which may be applied to the
device without damage.
Table 31
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note/Test
Condition
Ambient temperature
under bias
TA
-40
+85
Storage temperature
TSTG
TML3
-65
+125
+225
According to IPS
J-STD 020
+245
According to
Infineon internal
standard
Moisture Level 3
temperature
VDD
-0.5
3.30
4.50
VDDC
-0.5
1.80
2.40
VDDP
-0.4
3.30
4.50
Supply voltage
(receiver, analog)
VDDR
-0.4
3.30
4.50
Supply voltage
(transmitter, analog)
VDDX
-0.4
3.30
4.50
VRLmax
-0.8
4.50
RL1/RL2
-0.4
4.50
except VDDC,
RL1/RL2
Delta Sheet
85
OctalFALCTM
PEF 22558 E
Electrical Characteristics
Table 31
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note/Test
Condition
VESD,HBM
2000
VESD,CDM
500
According to
ESD Association
Standard
DS5.3.1 - 1999
Attention: Absolute Maximum Ratings are stress ratings only, and functional
operation and reliability under conditions beyond those defined in the
normal operating conditions is not guaranteed. Stresses above the
maximum ratings are likely to cause permanent damage to the chip.
18.2
Operating Range
Table 32 defines the maximum voltages and temperature which may be applied to
guarantee proper operation.
Table 32
Operating Range
Parameter
Min.
Typ.
Max.
Unit Note/Test
Condition
TA
VDD
-40
+85
3.13
3.30
3.46
3.3 V 5%
VDDC
1.62
1.80
1.98
1.8 V 10%
VDDP
3.13
3.30
3.46
3.3 V 5%
Supply voltage
(receiver, analog)
VDDR
3.13
3.30
3.46
3.3 V 5%
Supply voltage
(transmitter, analog)
VDDX
3.13
3.30
3.46
3.3 V 5%
VRL
VDDR
RL1, RL2
Ambient temperature
Supply voltage (pads,
digital)
Delta Sheet
Symbol
Values
1)
+0.3V
86
OctalFALCTM
PEF 22558 E
Electrical Characteristics
Table 32
Parameter
Symbol
VID
VSS
VSSR
VSSX
Values
Min.
Typ.
Max.
Unit Note/Test
Condition
-0.4
3.46
3.3 V 5%
Note: VDD, VDDR and VDDX have to be connected to the same voltage level.
18.3
Table 33
DC Characteristics
DC Characteristics
Parameter
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Average power supply
current (analog line
interface mode, single
power supply)
Delta Sheet
Symbol
Values
Min.
Typ.
Max.
Unit Note/Test
Condition
VIL
VIH
VOL
VOH
IDDE1
0.4
0.8
1)
2.0
3.46
1)
VSS
0.45
2.4
VDD
IOL = + 2 mA 2)
IOH = - 2 mA2)
t.b.d.
t.b.d.
mA
E1 application
LIM1.DRS = 0B
VSEL = 1B;
PRBS pattern
IDDT1
t.b.d.
t.b.d.
mA
T1 application
LIM1.DRS = 0B
VSEL = 1B
PRBS pattern
IDDE1
t.b.d.
t.b.d.
mA
E1 application
LIM1.DRS = 0B
VSEL = 1B
All-One pattern
IDDT1
t.b.d.
t.b.d.
mA
T1 application
LIM1.DRS = 0B
VSEL = 1B
All-One pattern
87
OctalFALCTM
PEF 22558 E
Electrical Characteristics
Table 33
DC Characteristics (contd)
Parameter
Average power supply
current (digital line
interface mode, single
power supply)
Symbol
IDD
IL11
Input leakage current
IIL12
Input pullup current
IP
Output leakage current IOZ1
Input leakage current
Values
Min.
Typ.
Max.
Unit Note/Test
Condition
t.b.d.
t.b.d.
mA
LIM1.DRS = 1B3)
VSEL = 1B
15
VIN =VDD4)
VIN =VSS 4)
VIN =VSS
VOUT = tristate
VSS < Vmeas <
VDD
measured
against VDD and
VSS;
all except XL1/2
Transmitter leakage
current
ITL
30
XL1/2 = VDDX;
XPM2.XLT = 1
30
XL1/2 = VSSX;
XPM2.XLT = 1
Transmitter output
impedance
RX
applies to
XL1and XL25)
Transmitter output
current
IX
105
mA
XL1, XL2
Differential peak
voltage of a mark
VX
2.15
Voltage between
XL1 and XL2
VR12
-0.45
3.8
RL1, RL2
-0.75
4.1
RZ signals,
during T1 pulse
over-/undershoot
only
4.00
RL1, RL2
4.63
RZ signals,
during T1 pulse
over-/undershoot
only
Receiver differential
VRL12
peak voltage of a mark
(between RL1 and RL2)
Delta Sheet
88
OctalFALCTM
PEF 22558 E
Electrical Characteristics
Table 33
DC Characteristics (contd)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note/Test
Condition
Receiver input
impedance
ZR
50
5)
Receiver sensitivity
SRLH
-43
dB
RL1, RL2
E1 mode
-36
RL1, RL2
T1 mode
Delta Sheet
89
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