ECE380 Digital Logic: Design of Finite State Machines Using CAD Tools
ECE380 Digital Logic: Design of Finite State Machines Using CAD Tools
ECE380 Digital Logic: Design of Finite State Machines Using CAD Tools
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User defined data types
• The TYPE keyword will be used to define a
new data type used to represent states in the
FSM
Representing states
• A SIGNAL is defined, of the user-defined
State_type, to represent the flip-flop
outputs
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Design example
• Create a VHDL description for a circuit that detects a
’11’ input sequence on an input, w
reset
w=1
w=0 A/z=0 B/z=0
w=0
w=0 w=1
C/z=1
Recall the Moore state
diagram for the circuit
w=1
Electrical & Computer Engineering Dr. D. J. Jackson Lecture 31-5
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VHDL design example continued
PROCESS ( resetn, clk ) ELSE
BEGIN y <= C;
IF resetn = ‘0’ THEN END IF;
y <= A; WHEN C =>
ELSIF (clk’EVENT AND clk=‘1’) THEN
IF w=‘0’ THEN
CASE y IS
y <= A;
WHEN A =>
ELSE
IF w=‘0’ THEN
y <= A; y <= C;
ELSE END IF;
y <= B; END CASE;
END IF; END IF;
WHEN B => END PROCESS
IF w=‘0’ THEN z <= ‘1’ WHEN y=C ELSE ‘0’;
y <= A; END Behavior;
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Alternate VHDL description
ARCHITECTURE Behavior OF detect IS WHEN C =>
TYPE State_type IS (A,B,C); IF w=‘0’ THEN
SIGNAL y_present, y_next: State_type; y_next <= A;
BEGIN ELSE
PROCESS(w,y_present) y_next <= C;
BEGIN END CASE;
CASE y_present IS END PROCESS;
WHEN A => PROCESS(clk,resetn)
IF w=‘0’ THEN BEGIN
y_next <= A; IF resetn=‘0’ THEN
ELSE y_present <= A;
y_next <= B; ELSIF(clk’EVENT AND clk=‘1’) THEN
WHEN B => y_present <= y_next;
IF w=‘0’ THEN END IF;
y_next <= A; END PROCESS
ELSE z <=‘1’ WHEN y_present=C ELSE ‘0’;
y_next <= C; END Behavior;
Or
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VHDL code of a Mealy FSM
• A Mealy FSM can be described in a similar manner as
a Moore FSM
• The state transitions are described in the same way
as the original VHDL example
• The major difference in the case of a Mealy FSM is
the way in which the code for the output is written
• Recall the Mealy state diagram for the ’11’ sequence
detector
reset
1/0
0/0