Module 1

System Bus in Computer Architecture-

What Is A System Bus?

• A bus is a set of electrical wires (lines) that connects the various

hardware components of a computer system.
• It works as a communication pathway through which information flows
from one hardware component to the other hardware component.

A bus that connects major components (CPU, memory and I/O devices) of a
computer system is called as a System Bus.

Why Do We Need Bus?

• A computer system is made of different components such as memory,

ALU, registers etc.
• Each component should be able to communicate with other for proper
execution of instructions and information flow.
• If we try to implement a mesh topology among different components, it
would be really expensive.
• So, we use a common component to connect each necessary
component i.e. BUS.

Components Of A System Bus-

The system bus consists of three major components-

1. Data Bus
2. Address Bus
3. Control Bus

1) Data Bus-

• As the name suggests, data bus is used for transmitting the data /
instruction from CPU to memory/IO and vice-versa.
• It is bi-directional.

Data Bus Width

• The width of a data bus refers to the number of bits (electrical wires) that the
bus can carry at a time.
 • Each line carries 1 bit at a time. So, the number of lines in data bus
determine how many bits can be transferred parallely.
• The width of data bus is an important parameter because it determines how
much data can be transmitted at one time.
Examples-
• A 32-bit bus has thirty two (32) wires and thus can transmit 32 bits of data at
a time.
• A 64-bit bus has sixty four (64) wires and thus can transmit 64 bits of data at
a time.

2) Control Bus-

• As the name suggests, control bus is used to transfer the control and
timing signals from one component to the other component.
• The CPU uses control bus to communicate with the devices that are
connected to the computer system.
• The CPU transmits different types of control signals to the system
components.
• It is bi-directional.

What Are Control & Timing Signals?

Control signals are generated in the control unit of CPU.

Timing signals are used to synchronize the memory and I/O
operations with a CPU clock.

Typical control signals hold by control bus-

• Memory read – Data from memory address location to be
placed on data bus.
• Memory write – Data from data bus to be placed on memory
address location.
• I/O Read – Data from I/O address location to be placed on
data bus.
• I/O Write – Data from data bus to be placed on I/O address
location.

Other control signals hold by control bus are interrupt, interrupt

acknowledge, bus request, bus grant and several others.
The type of action taking place on the system bus is indicated
by these control signals.

Example-

When CPU wants to read or write data, it sends the memory

read or memory write control signal on the control bus to
perform the memory read or write operation from the main
memory. Similarly, when the processor wants to read from an
I/O device, it generates the I/O read signal.

3) Address Bus-

• As the name suggests, address bus is used to carry address

from CPU to memory/IO devices.
• It is used to identify the particular location in memory.
• It carries the source or destination address of data i.e. where
to store or from where to retrieve the data.
• It is uni-directional.

Example-

When CPU wants to read or write data, it sends the memory

read or memory write control signal on the control bus to
perform the memory read or write operation from the main
memory and the address of the memory location is sent on the
address bus.
 Address Bus Width

• The width of address bus determines the amount of physical

memory addressable by the processor.
• In other words, it determines the size of the memory that the
computer can use.

CPU And Memory Registers

Central Processing Unit (CPU)

What is a CPU?
A Central Processing Unit is the most important component of
a computer system. A CPU is a hardware that performs data
input/output, processing and storage functions for a computer system.
A CPU can be installed into a CPU socket. These sockets are generally
located on the motherboard. CPU can perform various data processing
operations. CPU can store data, instructions, programs, and
intermediate results.
.
Different Parts of CPU
Now, the CPU consists of 3 major units, which are:
1. Memory or Storage Unit
2. Control Unit
3. ALU(Arithmetic Logic Unit)
Here, in this diagram, the three major components are also shown. So,
let us discuss these major components:
Memory or Storage Unit
As the name suggests this unit can store instructions, data, and
intermediate results. The memory unit is responsible for transferring
information to other units of the computer when needed. It is also
known as an internal storage unit or the main memory or the primary
storage or Random Access Memory (RAM) as all these are storage
devices.
Its size affects speed, power, and performance. There are two types of
memory in the computer, which are primary memory and secondary
memory. Some main functions of memory units are listed below:
• Data and instructions are stored in memory units which are
required for processing.
• It also stores the intermediate results of any calculation or task
when they are in process.
• The final results of processing are stored in the memory units
before these results are released to an output device for giving the
output to the user.
• All sorts of inputs and outputs are transmitted through the memory
unit.
Control Unit
As the name suggests, a control unit controls the operations of all parts
of the computer but it does not carry out any data processing operations.
For executing already stored instructions, It takes instructions from the
memory unit and then decodes the instructions after that it executes
those instructions. So, it controls the functioning of the computer. It’s
main task is to maintain the flow of information across the processor.
Some main functions of the control unit are listed below:
• Controlling of data and transfer of data and instructions is done by
the control unit among other parts of the computer.
• The control unit is responsible for managing all the units of the
computer.
• The control unit is responsible for communication with Input and
output devices for the transfer of data or results from memory.
• The control unit is not responsible for the processing of data or
storing data.
ALU (Arithmetic Logic Unit)
ALU (Arithmetic Logic Unit) is responsible for performing arithmetic
and logical functions or operations. It consists of two subsections,
which are:
• Arithmetic Section
• Logic Section
Arithmetic Section: By arithmetic operations, we mean operations
like addition, subtraction, multiplication, and division, and all these
operation and functions are performed by ALU. Also, all the complex
operations are done by making repetitive use of the mentioned
operations by ALU.
Logic Section: By Logical operations, we mean operations or
functions like selecting, comparing, matching, and merging the data,
and all these are performed by ALU.
The main function of a computer processor is to execute instruction and
produce an output. CPU work are Fetch, Decode and Execute are the
fundamental functions of the computer.
• Fetch: the first CPU gets the instruction. That means binary
numbers that are passed from RAM to CPU.
• Decode: When the instruction is entered into the CPU, it needs to
decode the instructions. with the help of ALU(Arithmetic Logic
Unit) the process of decode begins.
• Execute: After decode step the instructions are ready to execute
• Store: After execute step the instructions are ready to store in the
memory.
Types of CPU
We have three different types of CPU:
• Single Core CPU: The oldest type of computer CPUs is single
core CPU. These CPUs were used in the 1970s. these CPUs only
have a single core that preform different operations. This means
that the single core CPU can only process one operation at a single
time. single core CPU CPU is not suitable for multitasking.
• Dual-Core CPU: Dual-Core CPUs contain a single Integrated
Circuit with two cores. Each core has its cache and controller.
Quad-Core CPU: Quad-Core CPUs contain two dual-core
processors present within a single integrated circuit (IC) or chip. A
quad-core processor contains a chip with four independent cores.
These cores read and execute various instructions provided by the
CPU. Quad Core CPU increases the overall speed for programs.
Without even boosting the overall clock speed it results in higher
performance.

Register Memory
Register memory is the smallest and fastest memory in a computer. It
is not a part of the main memory and is located in the CPU in the form
of registers, which are the smallest data holding elements. A register
temporarily holds frequently used data, instructions, and memory
address that are to be used by CPU. They hold instructions that are
currently processed by the CPU. All data is required to pass through
registers before it can be processed. So, they are used by CPU to
process the data entered by the users.

Registers hold a small amount of data around 32 bits to 64 bits. The

speed of a CPU depends on the number and size (no. of bits) of registers
that are built into the CPU. Registers can be of different types based on
their uses. Some of the widely used Registers include Accumulator or
AC, Data Register or DR, the Address Register or AR, Program
Counter (PC), I/O Address Register, and more.

Architecture of Register Memory

o This architecture is driven by instructions, through which
operations are to be carried out on the registers and memory.
o An operation can have two operands: one of them can be in
memory and the other one in a register.

o The numbers of registers in the CPU are fewer, and they are also
small in size. Its size is fewer than 64 bits.
 o The computer provides instructions for the registration number
and the register's address. Various register identifiers include R0,
R1, R7, SP, and PC.

Types and Functions of Computer Registers:

The fetching, decoding, and execution operations are the three
important roles that computer registers play. The register gathers and
stores user-provided data instructions at the designated location. The
instructions are deciphered and processed in order to provide the user
with the desired output. Processing is carried out in accordance with
user requirements. The computer system uses a variety of registers to
store data and reduce memory utilization. Every register used by the
CPU has a unique function.

o Data Register: It is a 16-bit register, which is used to store

operands (variables) to be operated by the processor. It
temporarily stores data, which is being transmitted to or received
from a peripheral device.
o Program Counter (PC): It holds the address of the memory
location of the next instruction, which is to be fetched after the
current instruction is completed.
o Instructor Register: It is a 16-bit register. It stores the
instruction which is fetched from the main memory.
o Accumulator Register: It is a 16-bit register, which is used to
store the results produced by the system.
o Address Register: It is a 12-bit register that stores the address of
a memory location where instructions or data is stored in the
memory.
o I/O Address Register: Its job is to specify the address of a
particular I/O device.
o I/O Buffer Register: Its job is to exchange the data between an
I/O module and the CPU.

Use of Register Memory

 o The registers allow for the speedy acceptance, storage, and
transmission of data, and any kind of register is utilized to carry
out the precise tasks that the CPU requires. Users do not need to
be very knowledgeable about the register because the CPU holds
it as temporary memory and a data buffer.
o Registers act as buffers for copying data from main memory so
that the processor can access it whenever it is needed.

PROGRAM COUNTER
The program counter (PC), commonly called the instruction
pointer (IP) in Intel x86 and Itanium microprocessors, and
sometimes called the instruction address
register (IAR), the instruction counter, or just part of the instruction
sequencer, is a processor register that indicates where a computer is
in its program sequence.
Usually, the PC is incremented after fetching an instruction, and holds
the memory address of ("points to") the next instruction that would be
executed.
.
A branch provides that the next instruction is fetched from elsewhere
in memory. A subroutine call not only branches but saves the
preceding contents of the PC somewhere. A return retrieves the saved
contents of the PC and places it back in the PC, resuming sequential
execution with the instruction following the subroutine call.

Hardware implementation
In a simple central processing unit (CPU), the PC is a digital
counter (which is the origin of the term "program counter") that may
be one of several hardware registers. The instruction cycle begins with
a fetch, in which the CPU places the value of the PC on the address
bus to send it to the memory. The memory responds by sending the
contents of that memory location on the data bus. (This is the stored-
program computer model, in which a single memory space contains
both executable instructions and ordinary data. Following the fetch,
the CPU proceeds to execution, taking some action based on the
memory contents that it obtained. At some point in this cycle, the PC
will be modified so that the next instruction executed is a different
one (typically, incremented so that the next instruction is the one
starting at the memory address immediately following the last
memory location of the current instruction).
Like other processor registers, the PC may be a bank of binary
latches, each one representing one bit of the value of the PC. The
number of bits (the width of the PC) relates to the processor
architecture. If the PC is a binary counter, it may increment when a
pulse is applied to its COUNT UP input, or the CPU may compute
some other value and load it into the PC by a pulse to its LOAD input.
To identify the current instruction, the PC may be combined with
other registers that identify a segment or page. This approach permits
a PC with fewer bits by assuming that most memory units of interest
are within the current vicinity.

Consequences in machine architecture

Use of a PC that normally increments assumes that what a computer
does is execute a usually linear sequence of instructions. Such a PC is
central to the von Neumann architecture. Thus programmers write a
sequential control flow even for algorithms that do not have to be
sequential. The resulting “von Neumann bottleneck” led to research
into parallel computing, including non-von Neumann
or dataflow models that did not use a PC; for example, rather than
specifying sequential steps, the high-level programmer might specify
desired function and the low-level programmer might specify this
using combinatory logic.
This research also led to ways to making conventional, PC-based,
CPUs run faster, including:

• Pipelining, in which different hardware in the CPU executes

different phases of multiple instructions simultaneously.
• The very long instruction word (VLIW) architecture, where a
single instruction can achieve multiple effects.
• Techniques to predict out-of-order execution and prepare
subsequent instructions for execution outside the regular sequence.

Consequences in high-level programming

Modern high-level programming languages still follow the sequential-
execution model and, indeed, a common way of identifying
programming errors is with a “procedure execution” in which the
programmer's finger identifies the point of execution as a PC would.
The high-level language is essentially the machine language of a
virtual machine, too complex to be built as hardware but instead
emulated or interpreted by software.
However, new programming models transcend sequential-execution
programming:

• When writing a multi-threaded program, the programmer may

write each thread as a sequence of instructions without specifying
the timing of any instruction relative to instructions in other
threads.
• In event-driven programming, the programmer may write
sequences of instructions to respond to events without specifying
an overall sequence for the program.
• In dataflow programming, the programmer may write each section
of a computing pipeline without specifying the timing relative to
other sections.

Accumulator

An accumulator is a type of register included in a CPU. It acts as a

temporary storage location which holds an intermediate value in
mathematical and logical calculations. Intermediate results of an
operation are progressively written to the accumulator, overwriting
the previous value. For example, in the operation "3 + 4 + 5," the
accumulator would hold the value 3, then the value 7, then the value
12. The benefit of an accumulator is that it does not need to be
explicitly referenced, which conserves data in the operation statement.
In modern CPUs, accumulators are replaced by general-purpose
registers because they offer more flexibility. However, accumulators
may still be in some special-purpose processors.

Micro operations
In computer central processing units, micro-operations (also known
as micro-ops) are the functional or atomic, operations of a processor.
These are low level instructions used in some designs to implement
complex machine instructions. They generally perform operations on
data stored in one or more registers. They transfer data between
registers or between external buses of the CPU, also performs
arithmetic and logical operations on registers. In executing a
program, operation of a computer consists of a sequence of
instruction cycles, with one machine instruction per cycle. Each
instruction cycle is made up of a number of smaller units – Fetch,
Indirect, Execute and Interrupt cycles. Each of these cycles involves
series of steps, each of which involves the processor registers. These
steps are referred as micro-operations. the prefix micro refers to the
fact that each of the step is very simple and accomplishes very little.
Figure below depicts the concept being discussed
here.

Miniature tasks are performed on the information put away in the registers
inside the computer chip. They are utilized to perform math and intelligent
activities, as well as to move information among registers and memory. A
few instances of miniature tasks include:
1.Load: This miniature activity loads information from memory into a
register.
2.Store: This miniature activity stores information from a register into
memory.
3.Add: This miniature activity adds two qualities and stores the outcome in a
register.
4.Subtract: This miniature activity deducts two qualities and stores the
outcome in a register.
5.And: This miniature activity plays out a legitimate AND procedure on two
qualities and stores the outcome in a register.
6.Or: This miniature activity plays out a legitimate OR procedure on two
qualities and stores the outcome in a register.
7.Not: This miniature activity plays out a legitimate NOT procedure on a
worth and stores the outcome in a register.
8.Shift: This miniature activity moves the pieces of a worth to the left or right.
9.Rotate: This miniature activity pivots the pieces of a worth to the left or
right.
Miniature activities are consolidated to frame more elevated level guidelines
and tasks. For instance, an option activity might be executed utilizing various
miniature tasks, including a heap activity to stack the qualities into registers,
an add activity to play out the option, and a store activity to store the
outcome in memory.

Instruction Register
An instruction register holds a machine instruction that is currently
being executed. In general, a register sits at the top of the memory
hierarchy. A variety of registers serve different functions in a central
processing unit (CPU) – the function of the instruction register is to
hold that currently queued instruction for use.

In a typical CPU, in addition to an accumulator, there are registers

such as an address register, a data register and an index register, along
with the instruction register. The CPU performs fetch, decode and
execute operations on memory units according to its use of the
registers. All of this serves the purpose of the memory processing that
is at the heart of the CPU which is why some experts call registers
“the most important part of the CPU.” In a sense, the instruction
register is particularly important in that it holds the “active” memory
value that is being worked on at a given time.

Register Transfer Language (RTL)

In symbolic notation, it is used to describe the micro-operations
transfer among registers. It is a kind of intermediate representation
(IR) that is very close to assembly language, such as that which is
used in a compiler.The term “Register Transfer” can perform micro-
operations and transfer the result of operation to the same or other
register.
Micro-operations :
The operation executed on the data store in registers are called micro-
operations. They are detailed low-level instructions used in some
designs to implement complex machine instructions.
Register Transfer :
The information transformed from one register to another register is
represented in symbolic form by replacement operator is called
Register Transfer.
Replacement Operator :
In the statement, R2 <- R1, <- acts as a replacement operator. This
statement defines the transfer of content of register R1 into register
R2.
There are various methods of RTL –

1. General way of representing a register is by the name of the

register enclosed in a rectangular box as shown in (a).

2. Register is numbered in a sequence of 0 to (n-1) as shown in (b).

3. The numbering of bits in a register can be marked on the top of the

box as shown in (c).

4. A 16-bit register PC is divided into 2 parts- Bits (0 to 7) are

assigned with lower byte of 16-bit address and bits (8 to 15) are
assigned with higher bytes of 16-bit address as shown in (d).
Basic symbols of RTL :
Symbol Description Example

Letters and MAR, R1,

Denotes a Register
Numbers R2

R1(8-bit)
() Denotes a part of register
R1(0-7)

<- Denotes a transfer of information R2 <- R1

Specify two micro-operations of R1 <- R2

,
Register Transfer R2 <- R1

P : R2 <-
: Denotes conditional operations R1
if P=1
 Symbol Description Example

Naming Denotes another name for an

Ra := R1
Operator (:=) already existing register/alias

Register Transfer Operations:

The operation performed on the data stored in the registers are
referred to as register transfer operations.
There are different types of register transfer operations:
1. Simple Transfer – R2 <- R1
The content of R1 are copied into R2 without affecting the content of
R1. It is an unconditional type of transfer operation.
2. Conditional Transfer –

It indicates that if P=1, then the content of R1 is transferred to R2. It

is a unidirectional operation.
3. Simultaneous Operations –
If 2 or more operations are to occur simultaneously then they are
separated with comma (,).
 If the control function P=1, then load the content of R1 into R2 and at
the same clock load the content of R2 into R1.

Instruction Fetch and Decode

The CPU begins program execution by fetching them one at a time.
Fetch, decode and execute cycle are the three steps that the CPU
repetitively performs to complete one program instruction. The
control unit decodes the machine instructions following the
instruction format.

• Steps Involved in Instruction Fetch and Decode

A computer program comprises a series of program statements, also
known as program instructions. Each program instruction
accomplishes a specific task. The program instructions are binary
machine instructions that the CPU can directly execute. The operating
system loads the machine instructions into the main memory RAM to
begin program execution.

Instruction Cycle
In the instruction cycle, the essential operation of the CPU is the time
required to execute and fetch a complete instruction. Fetch, decode
and execute cycle are the three steps that the CPU repetitively
performs to complete one program instruction.

The instruction cycle comprises three main stages and is also

addressed as the fetch-decode-execute cycle or fetch-execute cycle
because of the steps involved.

They are as follows:

1. Fetch stage

2. Decode stage

3. Execute stage.

Steps Involved in Fetch Cycle

Fetch Cycle: The Program Counter contains the address of the

instruction that has to be next executed at the start of the fetch cycle
(PC).

Step 1: The address in the program counter is transferred to the

memory address register (MAR), which is the only register connected
to the address lines of the system bus.

Step 2: The MAR address is added to the address bus. The control
unit then issues a READ command on the control bus, and the result
is displayed on the data bus before being copied into the memory
buffer register (MBR). The program counter is increased by one to
prepare for the next instruction. ( These two actions can be performed
concurrently to save time.)

Step 3: The MBR’s content is transferred to the instruction register

(IR).

An essential Fetch Cycle also consists of four micro-operations,

which can be represented symbolically as follows:
 Here, a clock is available for timing purposes, and it emits clock
pulses at regular intervals. Each micro-operation can be completed in
the time of a single time unit. You can define a time unit by each
clock pulse. As a result, all-time teams have the same duration.

1. Move the contents of the PC to MAR.

2. MAR-specified memory location contents are to be copied to the
MBR. The process increases the PC’s content.
3. Copy the contents of the MBR to the IR.
4. Both the second and the third micro-operations occur during the
second time unit.

Steps Involved in Instruction Fetch and Decode

Let’s take a look at the steps involved in the instruction cycle from the
beginning to the end:

Step 1: Fetch Phase – The first phase of the instruction cycle

Here, the sequence counter (SC) is set to zero at the start of the
instruction cycle.

SC – 0

Step 2: Fetch phase occurring at Clock Pulse (T-0)

Here, the instruction cycle stores the address of the next instruction in
the program counter (PC) register. The PC’s content (address) is
assigned to the address register in the first clock cycle (T-0) ( AR).

PC – AR

Step 3: Fetch phase occurring at Clock Pulse 1

In the next clock cycle (T-1), the instruction is read from memory and
loaded into the instruction register (IR), while the program counter
(PC) is also incremented by one. The program counter (PC) now
points to the memory address of the next instruction to be retrieved.

PC – PC+1 AND IR -M [AR]

 The Instruction Register (IR) is a 16-bit register capable of storing
instructions in 16-bit format. The three components of the 16-bit
instruction format (0 to 11 bit) are:

1. Addressing Mode (15th bit)

2. OPCODE (12, 13, 14 bit)
3. Operand Address

Step 4: Decode Phase occurring at Clock Pulse (T-2)

The CPU’s control unit decodes the program instruction once it is

loaded into the instruction register (IR). A Decode Phase is the second
phase of the instruction cycle.

The instruction is decoded by the CPU’s control unit based on the

operation code (OPCODE), determined by three bits (bit 12, 13, 14).

Step 5: Decode Instruction Type occurring at Clock Pulse (T-2)

The CPU’s control unit must first decode the type of instruction. The
three types of education are:

1. Memory reference instruction

2. Register reference instruction
3. Input/output instruction.

The 3 X 8 decoder determines the type of instruction. The D7 value

determines the type of instruction. The three-bit OPCODE can have
eight distinct values, starting with (DO, D1, D2, ….., D6, D7).
Alternatively, the OPCODE can have values ranging from DO – 000
to D7 111.

Step 6: Decode Addressing Mode occurring at Clock Pulse (T-3)

If D7 is set to zero, the instruction type is a memory reference. When

D7 is set to 1, the instruction type can be a register reference type or
an input/output instruction. The instruction type is register reference
type if D7 equals one and I equals 0. If D7 and I are both 1, the
instruction type is input/output.
After deciding on the type of instructions and making a subsequent
decision, the decode phase concludes. The value of I in the 15th bit
determines the decode phase.

Technicalities involved in Indirect Cycle

After fetching an instruction, the next step involves fetching source

operands. You can retrieve the source operand by using indirect
addressing. However, you are free to bring it employing any
addressing modes. There is no need to bring the register-based
operands. Still, you may require to store the result in the main
memory following the execution of the opcode.

The following micro-operations are carried out:

Step 1: The instruction cycle transfers the instruction’s address field

to the MAR. It leads to obtaining the operand’s address.

Step 2: Through the process of direct addressing, the IR’s address

field is updated from the MBR.

Step 3: The current state of IR through the direct addressing mode

would have been different if indirect addressing had occurred.

However, note that the IR is now in a preparation stage for the

execution cycle, but it skips it for a moment to consider the Interrupt
Cycle.

Data Movement and manipulation in

Computer Organization
Data Manipulation Instructions Data manipulation instructions
perform operations on data and provide computational capabilities for
the computer. The data manipulation instructions in a typical
computer are usually divided into three basic types as follows.
1. Arithmetic instructions
2. Logical and bit manipulation instructions
3. Shift instructions
Let’s discuss them one by one.
1. Arithmetic instructions: The four basic operations are addition,
subtraction, multiplication, and division. Most computers provide
instructions for all four operations. Typical Arithmetic
Instructions –
 Name Mnemonic Example Explanation

It will increment the

register B by 1
Increment INC INC B B<-B+1

It will decrement the

register B by 1
Decrement DEC DEC B B<-B-1

It will add contents of

register B to the
contents of
the accumulator
and store the result in
the accumulator
Add ADD ADD B AC<-AC+B

It will subtract the

contents of register B
from the contents of the
accumulator and store
the result in the
accumulator
Subtract SUB SUB B AC<-AC-B
 It will multiply the
contents of register B
with the contents of the
accumulator and store
the result in the
accumulator
Multiply MUL MUL B AC<-AC*B

It will divide the

contents of register B
with the contents of the
accumulator and store
the quotient in the
accumulator
Divide DIV DIV B AC<-AC/B

It will add the contents

of register B and the
carry flag with the
contents of the
accumulator and store
the result in the
Add with ADDC accumulator
carry ADDC B AC<-AC+B+Carry flag
 It will subtract the
contents of register B
and the carry flag from
the contents of the
accumulator and store
the result in the
Subtract with accumulator
borrow SUBB SUBB B AC<-AC-B-Carry flag

It will negate a value by

finding 2’s complement
of its single operand.
This means simply
Negate(2’s operand by -1.
complement) NEG NEG B B<-B’+1

1. Logical and Bit Manipulation Instructions: Logical instructions

perform binary operations on strings of bits stored in registers.
They are helpful for manipulating individual bits or a group of
bits. Typical Logical and Bit Manipulation Instructions –
 Name Mnemonic Example Explanation

It will set the

accumulator to 0
Clear CLR CLR AC<-0

It will complement the

accumulator
Complement COM COM A AC<-(AC)’

It will AND the contents

of register B with the
contents of accumulator
and store
it in the accumulator
AND AND AND B AC<-AC AND B

It will OR the contents

of register B with the
contents of accumulator
and store it
in the accumulator
OR OR OR B AC<-AC OR B

It will XOR the contents

of register B with the
contents of the
accumulator and
store it in the
accumulator
Exclusive-OR XOR XOR B AC<-AC XOR B
 It will set the carry flag
to 0
Clear carry CLRC CLRC Carry flag<-0

It will set the carry flag

to 1
Set carry SETC SETC Carry flag<-1

It will complement the

carry flag
Complement Carry flag<- (Carry
carry COMC COMC flag)’

Enable It will enable the

interrupt EI EI interrupt

Disable It will disable the

interrupt DI DI interrupt

1. Shift Instructions: Shifts are operations in which the bits of a

word are moved to the left or right. Shift instructions may specify
either logical shifts, arithmetic shifts, or rotate-type
operations. Typical Shift Instructions –
 Name Mnemonic

Logical shift right SHR

Logical shift left SHL

Arithmetic shift right SHRA

Arithmetic shift left SHLA

Rotate right ROR

Rotate left ROL

Rotate right through carry RORC

Rotate left through carry ROLC

Control Unit Organization

Control Unit is the part of the computer’s central processing unit
(CPU), which directs the operation of the processor. It was included
as part of the Von Neumann Architecture by John von Neumann. It is
the responsibility of the Control Unit to tell the computer’s memory,
arithmetic/logic unit and input and output devices how to respond to
the instructions that have been sent to the processor. It fetches internal
instructions of the programs from the main memory to the processor
instruction register, and based on this register contents, the control
unit generates a control signal that supervises the execution of these
instructions. A control unit works by receiving input information to
which it converts into control signals, which are then sent to the
central processor. The computer’s processor then tells the attached
hardware what operations to perform. The functions that a control unit
performs are dependent on the type of CPU because the architecture
of CPU varies from manufacturer to manufacturer. Examples of
devices that require a CU are:
• Control Processing Units(CPUs)
• Graphics Processing Units(GPUs)

Functions of the Control Unit –

1. It coordinates the sequence of data movements into, out of, and
between a processor’s many sub-units.
2. It interprets instructions.
3. It controls data flow inside the processor.
4. It receives external instructions or commands to which it converts
to sequence of control signals.
5. It controls many execution units(i.e. ALU, data buffers and
registers) contained within a CPU.
6. It also handles multiple tasks, such as fetching, decoding,
execution handling and storing results.
Types of Control Unit – There are two types of control units:
Hardwired control unit and Microprogrammable control unit.
1. Hardwired Control Unit – In the Hardwired control unit, the
control signals that are important for instruction execution control
are generated by specially designed hardware logical circuits, in
which we can not modify the signal generation method without
physical change of the circuit structure. The operation code of an
instruction contains the basic data for control signal generation. In
the instruction decoder, the operation code is decoded. The
instruction decoder constitutes a set of many decoders that decode
different fields of the instruction opcode. As a result, few output
lines going out from the instruction decoder obtains active signal
values. These output lines are connected to the inputs of the matrix
that generates control signals for execution units of the computer.
This matrix implements logical combinations of the decoded
signals from the instruction opcode with the outputs from the
matrix that generates signals representing consecutive control unit
states and with signals coming from the outside of the processor,
e.g. interrupt signals. The matrices are built in a similar way as a
programmable logic
arrays.

Control signals for an instruction execution have to be generated

 not in a single time point but during the entire time interval that
corresponds to the instruction execution cycle. Following the
structure of this cycle, the suitable sequence of internal states is
organized in the control unit. A number of signals generated by the
control signal generator matrix are sent back to inputs of the next
control state generator matrix. This matrix combines these signals
with the timing signals, which are generated by the timing unit
based on the rectangular patterns usually supplied by the quartz
generator. When a new instruction arrives at the control unit, the
control units is in the initial state of new instruction fetching.
Instruction decoding allows the control unit enters the first state
relating execution of the new instruction, which lasts as long as the
timing signals and other input signals as flags and state information
of the computer remain unaltered. A change of any of the earlier
mentioned signals stimulates the change of the control unit state.
This causes that a new respective input is generated for the control
signal generator matrix. When an external signal appears, (e.g. an
interrupt) the control unit takes entry into a next control state that is
the state concerned with the reaction to this external signal (e.g.
interrupt processing). The values of flags and state variables of the
computer are used to select suitable states for the instruction
execution cycle. The last states in the cycle are control states that
commence fetching the next instruction of the program: sending
the program counter content to the main memory address buffer
register and next, reading the instruction word to the instruction
register of computer. When the ongoing instruction is the stop
instruction that ends program execution, the control unit enters an
operating system state, in which it waits for a next user directive.
2. Microprogrammable control unit – The fundamental difference
between these unit structures and the structure of the hardwired
control unit is the existence of the control store that is used for
storing words containing encoded control signals mandatory for
instruction execution. In microprogrammed control units,
subsequent instruction words are fetched into the instruction
register in a normal way. However, the operation code of each
instruction is not directly decoded to enable immediate control
signal generation but it comprises the initial address of a
microprogram contained in the control store.
• With a single-level control store: In this, the instruction
opcode from the instruction register is sent to the control store
address register. Based on this address, the first microinstruction
of a microprogram that interprets execution of this instruction is
read to the microinstruction register. This microinstruction
contains in its operation part encoded control signals, normally
as few bit fields. In a set microinstruction field decoders, the
fields are decoded. The microinstruction also contains the
address of the next microinstruction of the given instruction
microprogram and a control field used to control activities of the
microinstruction address
generator.

The last mentioned field decides the addressing mode

(addressing operation) to be applied to the address embedded in
the ongoing microinstruction. In microinstructions along with
conditional addressing mode, this address is refined by using the
processor condition flags that represent the status of
computations in the current program. The last microinstruction
in the instruction of the given microprogram is the
 microinstruction that fetches the next instruction from the main
memory to the instruction register.
• With a two-level control store: In this, in a control unit with a
two-level control store, besides the control memory for
microinstructions, a nano-instruction memory is included. In
such a control unit, microinstructions do not contain encoded
control signals. The operation part of microinstructions contains
the address of the word in the nano-instruction memory, which
contains encoded control signals. The nano-instruction memory
contains all combinations of control signals that appear in
microprograms that interpret the complete instruction set of a
given computer, written once in the form of nano-
instructions.

In this way, unnecessary storing of the same operation parts of

microinstructions is avoided. In this case, microinstruction word
can be much shorter than with the single level control store. It
gives a much smaller size in bits of the microinstruction
memory and, as a result, a much smaller size of the entire
control memory. The microinstruction memory contains the
control for selection of consecutive microinstructions, while
those control signals are generated at the basis of nano-
 instructions. In nano-instructions, control signals are frequently
encoded using 1 bit/ 1 signal method that eliminates decoding.

Advantages of a well-designed Control Unit:

Efficient instruction execution: A well-designed control unit can

execute instructions more efficiently by optimizing the instruction
pipeline and minimizing the number of clock cycles required for each
instruction.
Improved performance: A well-designed control unit can improve
the performance of the CPU by increasing the clock speed, reducing
the latency, and improving the throughput.
Support for complex instructions: A well-designed control unit can
support complex instructions that require multiple operations,
reducing the number of instructions required to execute a program.
Improved reliability: A well-designed control unit can improve the
reliability of the CPU by detecting and correcting errors, such as
memory errors and pipeline stalls.
Lower power consumption: A well-designed control unit can reduce
power consumption by optimizing the use of resources, such as
registers and memory, and reducing the number of clock cycles
required for each instruction.
Better branch prediction: A well-designed control unit can improve
branch prediction accuracy, reducing the number of branch
mispredictions and improving performance.
Improved scalability: A well-designed control unit can improve the
scalability of the CPU, allowing it to handle larger and more complex
workloads.
Better support for parallelism: A well-designed control unit can
better support parallelism, allowing the CPU to execute multiple
instructions simultaneously and improve overall performance.
Improved security: A well-designed control unit can improve the
security of the CPU by implementing security features such as
address space layout randomization and data execution prevention.
Lower cost: A well-designed control unit can reduce the cost of the
CPU by minimizing the number of components required and
improving manufacturing efficiency.
Disadvantages of a poorly-designed Control Unit:

Reduced performance: A poorly-designed control unit can reduce

the performance of the CPU by introducing pipeline stalls, increasing
the latency, and reducing the throughput.
Increased complexity: A poorly-designed control unit can increase
the complexity of the CPU, making it harder to design, test, and
maintain.
Higher power consumption: A poorly-designed control unit can
increase power consumption by inefficiently using resources, such as
registers and memory, and requiring more clock cycles for each
instruction.
Reduced reliability: A poorly-designed control unit can reduce the
reliability of the CPU by introducing errors, such as memory errors
and pipeline stalls.
Limitations on instruction set: A poorly-designed control unit may
limit the instruction set of the CPU, making it harder to execute
complex instructions and limiting the functionality of the CPU.
Inefficient use of resources: A poorly-designed control unit may
inefficiently use resources such as registers and memory, leading to
wasted resources and reduced performance.
Limited scalability: A poorly-designed control unit may limit the
scalability of the CPU, making it harder to handle larger and more
complex workloads.
Poor support for parallelism: A poorly-designed control unit may
limit the ability of the CPU to support parallelism, reducing the
overall performance of the system.
Security vulnerabilities: A poorly-designed control unit may
introduce security vulnerabilities, such as buffer overflows or code
injection attacks.
Higher cost: A poorly-designed control unit may increase the cost of
the CPU by requiring additional components or increasing the
manufacturing complexity.

Instruction formate and addressing modes of basic

computer
Addressing Modes
The addressing modes help us specify the way in which an operand’s effective
address is represented in any given instruction. Some addressing modes allow
referring to a large range of areas efficiently, like some linear array of addresses
along with a list of addresses. The addressing modes describe an efficient and
flexible way to define complex effective addresses.

The programs are generally written in high-level languages, as it’s a convenient way
in which one can define the variables along with the operations that a programmer
performs on the variables. This program is later compiled so as to generate the
actual machine code. A machine code includes low-level instructions.

A set of low-level instructions has operands and opcodes. An addressing mode has
no relation with the opcode part. It basically focuses on presenting the address of the
operand in the instructions.

Addressing Modes Types

The addressing modes refer to how someone can address any given memory
location. Five different addressing modes or five ways exist using which this can be
done.

You can find the list below, showing the various kind of addressing modes:

• Implied Mode
• Immediate Mode
• Register Mode
• Register Indirect Mode
• Autodecrement Mode
• Autoincrement Mode
• Direct Address Mode
• Indirect Address Mode
• Indexed Addressing Mode

Effective Address (EA)

The effective address refers to the address of an exact memory location in which an
operand’s value is actually present. Now explain all of the addressing modes.

Implied Mode
In the implied mode, the operands are implicitly specified in the definition of
instruction. For instance, the “complement accumulator” instruction refers to an
implied-mode instruction. It is because, in the definition of the instruction, the
operand is implied in the accumulator register. All the register reference instructions
are implied-mode instructions that use an accumulator.

Immediate Mode
In the immediate mode, we specify the operand in the instruction itself. Or, in simpler
words, instead of an address field, the immediate-mode instruction consists of an
operand field. An operand field contains the actual operand that is to be used in
conjunction with an operation that is determined in the given instruction. The
immediate-mode instructions help initialize registers to a certain constant value.

Register Mode
In the register mode, the operands exist in those registers that reside within a CPU.
In this case, we select a specific register from a certain register field in the given
instruction. The k-bit field is capable of determining one 2k register.

Register Indirect Mode

In the register indirect mode, the instruction available to us defines that particular
register in the CPU whose contents provides the operand’s address in the memory.
In simpler words, any selected register would include the address of an operand
instead of the operand itself.

The reference to a register is equivalent to specifying any memory address. The pros
of using this type of instruction are that an instruction’s address field would make use
of fewer bits to select a register than would be require when someone wants to
directly specify a memory address.

Autodecrement or the Autoincrement Mode

The Autodecrement or Autoincrement mode is very similar to the register indirect
mode. The only exception is that the register is decremented or incremented before
or after its value is used to access memory. When the address stored in the register
defines a data table in memory, it is very crucial to decrement or increment the
register after accessing the table every time. It can be obtained using the decrement
or increment instruction.

Direct Address Mode

In the direct address mode, the address part of the instruction is equal to the
effective address. The operand would reside in memory, and the address here is
given directly by the instruction’s address field. The address field would specify the
actual branch address in a branch-type instruction.

Indirect Address Mode

In an indirect address mode, the address field of an available instruction gives that
address in which the effective address gets stored in memory. The control fetches
the instruction available in the memory and then uses its address part in order to
(again) access memory to read its effective address.

Indexed Addressing Mode

In the indexed addressing mode, the content of a given index register gets added to
an instruction’s address part so as to obtain the effective address. Here, the index
register refers to a special CPU register that consists of an index value. An
instruction’s address field defines the beginning address of any data array present in
memory.