Unit-1

Computer: A computer is a combination of hardware and software resources

which integrate together and provides various functionalities to the user. Hardware
are the physical components of a computer like the processor, memory devices,
monitor, keyboard etc. while software is the set of programs or instructions that are
required by the hardware resources to function properly.
There are a few basic components that aids the working-cycle of a computer i.e. the
Input- Process- Output Cycle and these are called as the functional components of a
computer. It needs certain input, processes that input and produces the desired
output. The input unit takes the input, the central processing unit does the processing
of data and the output unit produces the output. The memory unit holds the data and
instructions during the processing.
Digital Computer: A digital computer can be defined as a programmable machine
which reads the binary data passed as instructions, processes this binary data, and
displays a calculated digital output. Therefore, Digital computers are those that work
on the digital data.

Details of Functional Components of a Digital Computer

 Input Unit :The input unit consists of input devices that are attached to the
computer. These devices take input and convert it into binary language that
 the computer understands. Some of the common input devices are keyboard,
mouse, joystick, scanner etc.
 Central Processing Unit (CPU) : Once the information is entered into the
computer by the input device, the processor processes it. The CPU is called
the brain of the computer because it is the control center of the computer. It
first fetches instructions from memory and then interprets them so as to know
what is to be done. If required, data is fetched from memory or input device.
Thereafter CPU executes or performs the required computation and then
either stores the output or displays on the output device. The CPU has three
main components which are responsible for different functions – Arithmetic
Logic Unit (ALU), Control Unit (CU) and Memory registers
 Arithmetic and Logic Unit (ALU) : The ALU, as its name suggests performs
mathematical calculations and takes logical decisions. Arithmetic calculations
include addition, subtraction, multiplication and division. Logical decisions
involve comparison of two data items to see which one is larger or smaller or
equal.
 Control Unit : The Control unit coordinates and controls the data flow in and
out of CPU and also controls all the operations of ALU, memory registers and
also input/output units. It is also responsible for carrying out all the
instructions stored in the program. It decodes the fetched instruction,
interprets it and sends control signals to input/output devices until the required
operation is done properly by ALU and memory.
 Memory Registers : A register is a temporary unit of memory in the CPU.
These are used to store the data which is directly used by the processor.
Registers can be of different sizes(16 bit, 32 bit, 64 bit and so on) and each
register inside the CPU has a specific function like storing data, storing an
instruction, storing address of a location in memory etc. The user registers can
be used by an assembly language programmer for storing operands,
intermediate results etc. Accumulator (ACC) is the main register in the ALU
and contains one of the operands of an operation to be performed in the ALU.
 Memory : Memory attached to the CPU is used for storage of data and
instructions and is called internal memory The internal memory is divided into
many storage locations, each of which can store data or instructions. Each
memory location is of the same size and has an address. With the help of the
address, the computer can read any memory location easily without having to
 search the entire memory. when a program is executed, it’s data is copied to
the internal memory and is stored in the memory till the end of the execution.
The internal memory is also called the Primary memory or Main memory.
This memory is also called as RAM, i.e. Random Access Memory. The time
of access of data is independent of its location in memory, therefore this
memory is also called Random Access memory (RAM). Read this
for different types of RAMs
 Output Unit : The output unit consists of output devices that are attached with
the computer. It converts the binary data coming from CPU to human
understandable form. The common output devices are monitor, printer, plotter
etc.

Interconnection between Functional Components

A computer consists of input unit that takes input, a CPU that processes the input
and an output unit that produces output. All these devices communicate with each
other through a common bus. A bus is a transmission path, made of a set of
conducting wires over which data or information in the form of electric signals, is
passed from one component to another in a computer. The bus can be of three types
– Address bus, Data bus and Control Bus.
Following figure shows the connection of various functional components:
The address bus carries the address location of the data or instruction. The data bus
carries data from one component to another and the control bus carries the control
signals. The system bus is the common communication path that carries signals
to/from CPU, main memory and input/output devices. The input/output devices
communicate with the system bus through the controller circuit which helps in
managing various input/output devices attached to the computer.
System Bus in Computer Architecture-

What Is A System Bus?

 A bus is a set of electrical wires (lines) that connects the various hardware
components of a computer system.
 It works as a communication pathway through which information flows from
one hardware component to the other hardware component.
A bus that connects major components (CPU, memory and I/O devices) of a
computer system is called as a System Bus.
Why Do We Need Bus?

 A computer system is made of different components such as memory, ALU,

registers etc.
 Each component should be able to communicate with other for proper
execution of instructions and information flow.
 If we try to implement a mesh topology among different components, it would
be really expensive.
 So, we use a common component to connect each necessary component i.e.
BUS.
Components Of A System Bus-

The system bus consists of three major components-

 1) Data Bus-
 As the name suggests, data bus is used for transmitting the data / instruction
from CPU to memory/IO and vice-versa.
 It is bi-directional.
Examples-
 A 32-bit bus has thirty two (32) wires and thus can transmit 32 bits of data at
a time.
 A 64-bit bus has sixty four (64) wires and thus can transmit 64 bits of data at
a time

2) Control Bus-
 As the name suggests, control bus is used to transfer the control and timing
signals from one component to the other component.
 The CPU uses control bus to communicate with the devices that are connected
to the computer system.
 The CPU transmits different types of control signals to the system
components.
 It is bi-directional.
 What Are Control & Timing Signals?

Control signals are generated in the control unit of CPU.

Timing signals are used to synchronize the memory and I/O operations with
a CPU clock.
Typical control signals hold by control bus-
 Memory read – Data from memory address location to be placed on data bus.
 Memory write – Data from data bus to be placed on memory address
location.
 I/O Read – Data from I/O address location to be placed on data bus.
 I/O Write – Data from data bus to be placed on I/O address location.
Other control signals hold by control bus are interrupt, interrupt
acknowledge, bus request, bus grant and several others.
The type of action taking place on the system bus is indicated by these control
signals.
Example-
When CPU wants to read or write data, it sends the memory read or memory
write control signal on the control bus to perform the memory read or write
operation from the main memory. Similarly, when the processor wants to read
from an I/O device, it generates the I/O read signal.
3) Address Bus-
 As the name suggests, address bus is used to carry address from CPU to
memory/IO devices.
 It is used to identify the particular location in memory.
 It carries the source or destination address of data i.e. where to store or from
where to retrieve the data.
 It is uni-directional.
 Example
 When CPU wants to read or write data, it sends the memory read or memory write
control signal on the control bus to perform the memory read or write operation from
the main memory and the address of the memory location is sent on the address
bus.
 If CPU wants to read data stored at the memory location (address) 4, the CPU send
the value 4 in binary on the address bus.

What is Bus Arbitration?

Bus Arbitration refers to the process by which the current bus master accesses and then leaves
the control of the bus and passes it to another bus requesting processor unit. The controller that has
access to a bus at an instance is known as a Bus master.
A conflict may arise if the number of DMA controllers or other controllers or processors try to
access the common bus at the same time, but access can be given to only one of those. Only one
processor or controller can be Bus master at the same point in time. To resolve these conflicts, the
Bus Arbitration procedure is implemented to coordinate the activities of all devices requesting
memory transfers. The selection of the bus master must take into account the needs of various
devices by establishing a priority system for gaining access to the bus. The Bus Arbiter decides
who would become the current bus master.

 A device that initiates data transfers on the bus at any given time is called a bus master.
 In a computer system, there may be more than one bus master such as a DMA controller
or a processor etc.
 These devices share the system bus and when a current master bus relinquishes another bus
can acquire the control of the processor.
 Bus arbitration is a process by which next device becomes the bus controller by transferring
bus mastership to another bus.
Types of Bus Arbitration
There are two types of bus arbitration namely
1. Centralised Arbitration.
2. Distributed Arbitration.
Only single bus arbiter performs the required arbitration and it can be either a processor or a
separate DMS controller.
There are three arbitration schemes which run on centralized arbitration.
 a) Daisy Chaining − It is a simple and cheaper method where all the masters use the same
line for making bus requests.
 b) Polling Method − In this method, the controller is used to generate address lines for the
master. For example, if there are 8 masters connected in a system at least 3 address lines
are required.
 c) Independent Request − In this scheme, each bus has its own bus request and a grant.
The built-in priority decoder selects the highest priority requests and asserts the system.
Distributed Arbitration

 Here, all the devices participate in the selection of the next bus master.
 Each device on the bus is assigned a4 bit identification number.
  When one or more devices request control of the bus, they assert the start arbitration signal
and place their 4-bit identification numbers on arbitration lines through ARB3.
 Each device compares the code and changes its bit position accordingly.
 It does so by placing a 0 at the input of their drive.
 The distributed arbitration is highly reliable because the bus operations are not dependant
on devices.

 Register Transfer
 The term Register Transfer refers to the availability of hardware logic circuits that can
perform a given micro-operation and transfer the result of the operation to the same or
another register.
 Most of the standard notations used for specifying operations on various registers are stated
below.

o The memory address register is designated by MAR.

o Program Counter PC holds the next instruction's address.
o Instruction Register IR holds the instruction being executed.
o R1 (Processor Register).
o We can also indicate individual bits by placing them in parenthesis. For instance, PC (8-
15), R2 (5), etc.
o Data Transfer from one register to another register is represented in symbolic form by
means of replacement operator. For instance, the following statement denotes a transfer of
the data of register R1 into register R2.
1. R2 ← R1
o Typically, most of the users want the transfer to occur only in a predetermined control
condition. This can be shown by following if-then statement:
If (P=1) then (R2 ← R1); Here P is a control signal generated in the control section.
o It is more convenient to specify a control function (P) by separating the control variables
from the register transfer operation. For instance, the following statement defines the data
transfer operation under a specific control function (P).
1. P: R2 ← R1
The following image shows the block diagram that depicts the transfer of data from R1 to R2.
Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs of the register R1
are connected to the 'n' inputs of register R2.

Memory Transfers:
Memory transfers simply mean to a transfer from a specific location of memory to a register.
However a memory transfer can be either ways. It can work either from Memory to Register or
from Register to Memory.
 A transfer from Memory to Register is called READ operation.
 A transfer from Register to Memory is called WRITE operation.

Memory Read Operation: A memory read operation first searches for a location in the memory
and then transfers the value located at that location to a register. Ex.:
Memory Transfer
Most of the standard notations used for specifying operations on memory transfer are stated below.
o The transfer of information from a memory unit to the user end is called a Read operation.
o The transfer of new information to be stored in the memory is called a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the memory transfer
operations.
o The address register is designated by AR and the data register by DR.
o Thus, a read operation can be stated as:
1. Read: DR ← M [AR]
o The Read statement causes a transfer of information into the data register (DR) from the
memory word (M) selected by the address register (AR).
o And the corresponding write operation can be stated as:
1. Write: M [AR] ← R1
o The Write statement causes a transfer of information from register R1 into the memory
word (M) selected by address register (AR).
Memory Write Operation: A memory write operation simply extracts data from a register and
transfers it to a memory location. Ex.:

Addressing Modes–
The term addressing modes refers to the way in which the operand of an instruction is
specified. The addressing mode specifies a rule for interpreting or modifying the address field
of the instruction before the operand is actually executed.
Addressing modes are discussed below:
 Implied mode:: In implied addressing the operand is specified in the instruction itself. In
this mode the data is 8 bits or 16 bits long and data is the part of instruction.Zero address
instruction are designed with implied addressing mode.

Example: CLC (used to reset Carry flag to 0)

 Immediate addressing mode (symbol #):In this mode data is present in address field of
instruction .Designed like one address instruction format.
Note:Limitation in the immediate mode is that the range of constants are restricted by size
 of address field.

Example: MOV AL, 35H (move the data 35H into AL register)
 Register mode: In register addressing the operand is placed in one of 8 bit or 16 bit
general purpose registers. The data is in the register that is specified by the instruction.
Here one register reference is required to access the data.

Example: MOV AX,CX (move the contents of CX register to AX register)

 Register Indirect mode: In this addressing the operand’s offset is placed in any one of the
registers BX,BP,SI,DI as specified in the instruction. The effective address of the data is in
the base register or an index register that is specified by the instruction.
Here two register reference is required to access the data.

Types of Addressing Modes

Addressing Modes in computer architecture are further divided into the following parts:
1. Implied/ Implicit Addressing Mode
2. Immediate Addressing Mode
3. Register Direct Addressing Mode
4. Register Indirect Addressing Mode
5. Auto-Increment Addressing Mode
6. Auto-Decrement Addressing Mode
7. Direct Addressing Mode
8. Indirect Addressing Mode
9. Displacement Addressing Mode
10. Relative Addressing Mode
11. Indexed Addressing Mode
12. Base Register Addressing Mode
13. Stack Addressing Mode
Implied/ Implicit Addressing Mode
The operands are implicitly specified in the instruction’s definition.
Consider the example, the instruction “complement accumulator” is an implied-mode instruction
as the operand in the accumulator register is implied in the instruction definition. All register
reference the instructions that use an accumulator are implied-mode instructions. Zero-address
instructions in a stack-organized computer are also implied-mode instructions because the
operands are implied to be on top of the stack.
Immediate Addressing Mode
The operand is defined in the instruction itself. This mode instruction has an operand field
instead of an address field. The operand field contains the actual operand used with the specified
operation in the instruction. The immediate-mode instructions help initialize registers to a
constant value.

For example, ADD 8 will increment the value stored in the accumulator by 8.
Register Direct Addressing Mode
The operands that reside within the CPU are stored in the registers. The specific register is
selected from a register field in the instruction. No reference to the memory is required to fetch
the operand. The only difference between the Direct addressing mode and the register direct
addressing mode is that the instruction address field refers to a CPU register instead of the main
memory.

Advantage: This mode provides faster memory access to the operands.

Disadvantage: It has limited address space, and using multiple registers can help boost the
performance, but it complicates the instructions.
Register Indirect Addressing Mode
The instruction defines a register in the CPU that stores the effective address of the operand in
memory. Only one reference to the memory is required to fetch the operand. The specified
register contains the address of the operand instead of the operand. The only difference between
the Indirect addressing mode and the register indirect addressing mode is that the instruction
address field refers to a CPU register.

For example: ADD R1, R2: Here, the content of R2 is added to R1. R1 R2 represents registers.
Advantage: The instruction address field uses fewer bits to select a register than required to
specify a memory address directly. Direct Addressing Mode
The effective address of the operand resides in the address field of the instruction.
The operand resides in the memory, and the address field of the instruction gives its address.
Only one reference to the memory is required to fetch the operand, and no additional calculations
need to be done to find the effective address of the operand. It is also known as absolute
addressing mode.

For example, ADD X will increment the value stored in the accumulator by the value stored at
X's memory.

Indirect Addressing Mode

The address field of the instruction gives the address of the memory location that contains the
effective address of the operand. Two references to the memory are required to fetch the
operand: The control fetches the instruction from memory and uses its address part to reaccess
the memory that stores the effective address. This addressing mode slows down the execution as
it requires multiple memory lookups to find the operand.
Displacement Addressing Mode
The indexed register content is added to the instruction’s address part to obtain the effective
address of the operand.

EA = A + (R)
Here, the address field holds two values, A: Base value R: displacement value.
Relative Addressing Mode
This mode is another version of the displacement address mode. The program counter’s content
is added to the instruction’s address part to obtain the effective address.

EA = A + (PC)
Here, EA: Effective address, PC: program counter.

The instruction’s address part is usually a signed number that can be positive or negative. After
the instruction’s address is fetched, the value of the program counter increases immediately,
irrespective of whether the fetched instruction has been executed or not. PC: It contains the
address of the next instruction to be executed.
The program counter contains the number 422, and the address part of the instruction contains
the number 17. The instruction at location 421 is read during the fetch phase, and the program
counter is then incremented by one to 422 + 17 = 439.
Indexed Addressing Mode
The index register’s content is added to the instruction’s address to obtain the effective address.
EA = content of index register + Instruction address part

Multiplication Algorithm in Signed Magnitude Representation

Multiplication of two fixed point binary number in signed magnitude representation is done with
process of successive shift and add operation.

In the multiplication process we are considering successive bits of the multiplier, least significant
bit first.
If the multiplier bit is 1, the multiplicand is copied down else 0’s are copied down.
The numbers copied down in successive lines are shifted one position to the left from the previous
number.
Finally numbers are added and their sum form the product.
The sign of the product is determined from the sign of the multiplicand and multiplier. If they are
alike, sign of the product is positive else negative.
//////////

Half - Adder
A Half-adder circuit needs two binary inputs and two binary outputs. The input variable shows the
augend and addend bits whereas the output variable produces the sum and carry. We can
understand the function of a half-adder by formulating a truth table. The truth table for a half-adder
is:

o 'x' and 'y' are the two inputs, and S (Sum) and C (Carry) are the two outputs.
o The Carry output is '0' unless both the inputs are 1.
o 'S' represents the least significant bit of the sum.
The simplified sum of products (SOP) expressions is:
S = x'y+xy', C = xy

The logic diagram for a half-adder circuit can be represented as:

Full - Adder
This circuit needs three binary inputs and two binary outputs. The truth table for a full-adder is:
 o Two of the input variable 'x' and 'y', represent the two significant bits to be added.
o The third input variable 'z', represents the carry from the previous lower significant
position.
o The outputs are designated by the symbol 'S' for sum and 'C' for carry.
o The eight rows under the input variables designate all possible combinations of 0's, and 1's
that these variables may have.
o The input-output logical relationship of the full-adder circuit may be expressed in two
Boolean functions, one for each output variable.
o Each output Boolean function can be simplified by using a unique map method.
Maps for a full-adder:

The logic diagram for a full-adder circuit can be represented as:

What is Half Adder?
Half Adder is a combinational logic circuit that is designed by connecting one EX-OR gate and
one AND gate. The half-adder circuit has two inputs: A and B, which add two input digits and
generate a carry and a sum.

Half Adder

The output obtained from the EX-OR gate is the sum of the two numbers while that obtained by
AND gate is the carry. There will be no forwarding of carry addition because there is no logic gate
to process that. Thus, this is called the Half Adder circuit.
Logical Expression of Half Adder
The Logical Expression for half added is given as
Sum = A ⊕ B
Carry = A AND B
Truth Table of Half Adder

The Truth Table for Half Added is Given as

What is Full Adder ?
Full Adder is the circuit that consists of two EX-OR gates, two AND gates, and one OR gate. Full
Adder is the adder that adds three inputs and produces two outputs which consist of two EX-OR
gates, two AND gates, and one OR gate. The first two inputs are A and B and the third input is an
input carry as C-IN. The output carry is designated as C-OUT and the normal output is designated
as S which is SUM.

Full Adder
The equation obtained by the EX-OR gate is the sum of the binary digits. While the output obtained
by AND gate is the carry obtained by addition.

Logical Expression of Full Adder

Given Below is the Logical Expression of Full Adder
SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin
CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕ B)
Truth Table of Full Adder

Given Below is the truth Table of Full Adder

Sum and Carry Operation
In both Half Adders and Full Adders, Sum is the output of the addition of the two inputs and Carry
is the output which is an overflow of the output position and needs to be shifted to the next higher
position while adding successive bit inputs.
 Sum (S): It results from the XOR gate, which is a logic gate that adds two or more bits
together in the same way that you add in base 2 with no acknowledgement of carry from
the previous bit.
 Carry (C or Cout): It is the output of the AND operation in the case of the Half Adder or
both AND and OR Operations in the case of the Full Adder to indicate that a ‘1’ has to be
carried over to the next bit position.