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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 3, MARCH 2003

Understanding MOSFET Mismatch

for Analog Design
Patrick G. Drennan, Member, IEEE, and Colin C. McAndrew, Senior Member, IEEE

AbstractDespite the significance of matched devices in analog

circuit design, mismatch modeling for design application has been
lacking. This paper addresses misconceptions about MOSFET
mismatch for analog design. t mismatch does not follow a simplistic 1 ( area) law, especially for wide/short and narrow/long
devices, which are common geometries in analog circuits. Further,
t and gain factor are not appropriate parameters for modeling
mismatch. A physically based mismatch model can be used to
obtain dramatic improvements in prediction of mismatch. This
model is applied to MOSFET current mirrors to show some
nonobvious effects over bias, geometry, and multiple-unit devices.
Index TermsAnalog circuits, mismatch, semiconductor device
modeling, SPICE.

I. INTRODUCTION

ISMATCH is the differential performance of two or

more devices on a single integrated circuit (IC). It is
widely recognized that mismatch is key to precision analog
IC design. Historically, mismatch has been treated as an art
rather than a science, relying on past experience and unproven
or uncharacterized effects. Exacerbating the situation is a
fundamental lack of modeling and understanding of mismatch
over bias and geometry. In an EE Times article discussing
intradie parameter variations (i.e., mismatch), Nassif stated,
The problem isnt the amount of variability. Its that we tend
to turn variability into uncertainty by not modeling it. [1].
Without an accurate mismatch model, designers are forced to
include substantial design margin or risk yield loss [2], both of
which cost money and time.
Most approaches to mismatch modeling are based on hand
analysis of the simple MOSFET draincurrent relationship in
). These models
the saturated region (i.e.,
(e.g., [3][7]) are based on parametric extensions of [8], but they
lack the same fundamental basis. None of these models are applicable in all bias regions. This is a critical requirement of a
mismatch model, since matched MOSFETs are used in weak
(i.e., low-current low-power design) and strong inversion, in
linear and saturated regions, across body bias.
Although these methods are perceived as simple approaches,
it has been our experience that the practical implementation is
complex. Model inadequacies across geometry and bias create
characterization dilemmas, which lead to thick, difficult-to-understand mismatch reports and partitioning of the bias and
geometry space into multiple bins or categories. Design appliManuscript received July 25, 2002; revised November 14, 2002.
The authors are with Motorola Inc., Tempe, AZ 85284 USA (e-mail:
pdrennan@motorola.com, mcandrew@ieee.org).
Digital Object Identifier 10.1109/JSSC.2002.808305

cation of , , and
mismatch is not obvious. Additional
publications [9][11] have focused on the underlying fabrication contributions to mismatch variation, which is useful for
technology development, but none of these have satisfactorily
described mismatch in a manner relevant to design.
This paper describes a mismatch model that is conducive to
design and has been used exclusively at Motorola for the past
several years. A key aspect of this model is that the mismatch
is characterized in same domain (e.g., ) using the same tools
(i.e., SPICE) and models (e.g., BSIM) that are used for design.
Since SPICE models provide the most accurate and complete
description of device electrical behavior as it relates to design,
this approach assures that the most appropriate, accurate mismatch prediction is obtained, limited only by the SPICE model
and the nature of the collected data.
This paper highlights the physical basis for mismatch.
A model is described that is applicable across all bias
and geometry conditions, including phenomena such as
source/drain series resistance, body bias effects, shortchannel/reverse-short-channel effects, narrow-width/inversenarrow-width effects, mobility degradation, and graded-channel
effects. Equally important, this approach is directly intended for
design. This model is used in several current-mirror examples
to demonstrate some nonobvious effects.
II. MISMATCH MODEL
The basis for mismatch modeling was proposed in [12]
and [13]. Here, the notion of local variation was introduced,
as Fig. 1 shows. For local variation, the fluctuations in the
observed length depend on the width of the device

and likewise for observed width

(2)
The local variation of parameters such as sheet resistance,
channel dopant concentration, mobility, and gate oxide thickness have an area dependency
(3)
represents the process parameter of
where the subscript
interest. Physically, the edge variation in (1) and (2) and
area dependent variation in (3) result from polysilicon/metal
edge grains, photoresist edge roughness, dopant clustering,
gate-oxide thickness/permittivity variations, etc. Qualitatively,
local variations decrease as the device size increases since the

0018-9200/03$17.00 2003 IEEE

DRENNAN AND McANDREW: UNDERSTANDING MOSFET MISMATCH FOR ANALOG DESIGN

451

TABLE I
RELEVANT PROCESS AND ELECTRICAL PARAMETERS

Fig. 1. Global variation and local variation. For local variation, the variance
in length depends on the width.

parameters average over a greater distance or area. This is

contrasted with global process parameter variation which is
independent of length and width . As per [14], mismatch
(i.e., intradie parameter variation) is comprised of local variation but traditional interdie (die-to-die) variation, used for best
case and worst case models and statistical simulation, contains
both global and local components. In fact, in many instances of
technology, device-type, geometry, and bias, the local variation
component dominates the interdie variation [15]. This implies
an additional geometric dependence that is rarely accounted for
in interdie statistical models [16].
The model in (1) was derived by evaluating the local length
and
in Fig. 1) across the entire width and finding
(e.g.,
the second moment (i.e., the standard deviation) of the effective
length. An alternative derivation [8] has been used to describe
mismatch behavior over geometry. This model assumes that the
observed variation for a given parameter is the convolution of
the small-signal parameter spatial variation over the device area.
This model is identical to (3). Perimeter contributions to mismatch were not addressed in [8], but a similar derivation results
in (1).
Although the model in [8] was derived correctly, it is incorand gain factor . These
rectly applied to threshold voltage
two parameters are combined to produce the mismatch
(4)
One immediately apparent problem is the physical basis for
these parameters. As pointed out in [17] and later in [18], if the
underlying cause for mismatch variation is the gate-oxide thickwill
ness , it will be accounted for in both and , thus,
be overestimated by a factor as large as two.
For mismatch modeling, one can consider two types of
parameters: process and electrical (see Table I). Process
parameters are those physically independent parameters that

control the electrical behavior of a device. Electrical parameters

are those parameters that are of interest to the designer.
mismatch does not belong in either category.
is not a process parameter. depends on
,
and
(the effective value of which depends on body bias), through
the short-channel effect and reverse-short-channel effect,
through the narrow-width and inverse-narrow-width
and
effect. In addition, 0.18- m and smaller technologies use halo
or pocket ion implantations which introduce new length and
width dependencies. This means that the relationship
(5)
is physically incorrect, and measured data from many technologies confirm this. In [4], the attempt was made to accommodate
the otherwise anomalous scaling behavior by using the effective
), but this is not approlength and width (i.e.,
priate for the same reason that short and narrow channel effects
and
. In practice, the
are not modeled with just with
geometric scaling inadequacies of (5) are often circumvented
by creating local models for geometric subsets of the overall
designable geometry space. This approach introduces practical
complexities and discontinuities in the model.
mismatch is often assumed to be the input offset voltage
which is an electrical parameter, but
mismatch
(6)
Even using the simplistic mismatch relationship in (4), it is apis not the input offset voltage, because neither
parent that
nor
is constant over bias, especially for graded-channel
is. The consedevices such as the halo-implanted device, yet
quences of this distinction will be made apparent in Section III.
Inadequate geometry selection in the mismatch test structure
design of experiments hides the shortcomings of (5). Several
. Barring any
different gate areas are used to extract the
other considerations, often these geometries are selected about
. This establishes a self-fulfilling situation in which an
erroneous model appears to fit the data well. Departures in the
true mismatch behavior from the assumed model cannot be detected and evaluated. Large model prediction errors result for
wide/short and narrow/long MOSFETs. These geometries are
critical to analog design.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 3, MARCH 2003

(4) and (5). A detailed discussion of the characteristics of these

plots is given in [18].
Applying (8) to MOSFET mismatch produces
geometry

(10)

where the geometric dependency of the process parameter variation is given in (1)(3). Expanding (10) gives

Fig. 2. Graphical depiction of the propagation of variance.

A physically complete and accurate mismatch model is given

in [18] for MOSFETs and [19] for bipolar junction transistors
(BJTs). All mismatch models are based on the propagation of
variance (POV) relationship depicted in Fig. 2. For a given independent variable and a dependent variable
(7)
as described by
Considering the range of possible values of
the probability density function (pdf) of and building a pdf
yields the POV relationship
(8)
where is any electrical parameter and is the th independent
process parameter, listed in Table I. In the case of MOSFETs,
normal distributions are assumed. For BJT mismatch models,
log-normal distributions are required for some parameters, but
that is outside the scope of this paper. For MOS mismatch
models other than [18], the partial derivatives in (8) are based
on the simplistic model
(9)
and as process parameters, and
or extensions of (9), with
as the electrical parameter. Combining (9) and (8) yields (4).
The mismatch model in [18] is more complete since it uses
BSIM3 (or another SPICE MOSFET model) to evaluate the partial derivative in (8), which is substantially more accurate than
using a simple analytic model like (9). Unlike the mismatch
model in (4), [18] is valid in the linear and saturation regions,
for subthreshold, weak inversion, and strong inversion conditions, and for all geometries, as shown in the plots of measured
and simulated data for nMOS transistors in Fig. 3. A partial
comparison of the modeling approaches is given across bias in
Fig. 4 and across geometry in Fig. 5, for a nMOS device in a
0.25- m CMOS technology. It is worth noting that the comparison of models in Figs. 4 and 5 are given for large gate voltages
(1.8 and 2.5 V). As the gate voltage decreases, the departure
in modeling approaches increases. Clearly, there is a significant improvement of the model [18] over the standard approach,

(11)
above a variable indicates a normalized paraThe tilde
meter. For characterization, the vector on the left side of (11)
mismatch standard deviations collected across
is a set of
many dies for many biases and geometries, typically hundreds
of combinations. The combinations are chosen so that the
process parameter mismatch variances are observable in the
mismatch data, with a unique and unconfounded solution. For
only significantly affects
for short devices in
instance,
, so we measure mismatch under
the linear region for high
cannot be considered in
these conditions. Conversely,
mismatch characterization schemes that contain , , and/or
mismatch measurements, because it is not reflected in
those parameters. This is a likely explanation of the results
obtained in [22].
The large middle matrix in (11) contains the squares of the
sensitivities of with respect to each of the process parameters.
Each row of sensitivities is numerically evaluated using SPICE
at the bias and geometry conditions at which the corresponding
is measured. Hence, the bias conditions and geometries for
the measured devices must be chosen to ensure that each process
parameter can be uniquely observed above the measurement
error.
Given the first two matrices in (11), the rightmost vector
of process parameters can be calculated using analytic simple
linear regression. This method is called back propagation of
variance (BPV). Essentially, process parameter variations are
over bias and
extracted that best explain the measured
geometry. Each process parameter is assumed to be independent. If a correlation exists between process parameters, that is
an indication that a wrong or incomplete set of process parameters has been selected. Correlations can always be addressed
with the inclusion of the appropriate set of independent process
and
(or
) mismatch are
parameters. For instance,
partially correlated, depending on the relative contribution of

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453

Fig. 3. Array of plots of measured and simulated mismatch data for an nMOS device on a 0.18-m technology [20]. The geometry selection is based upon the
design of experiments in [21]. Circle, square, and diamond symbols are measured data at V
0:1 V; 0:9 V; and 1:8 V, respectively. Lines are model at the
same conditions.

with principle component analysis (PCA), which is strictly

empirical with no physical basis or interpretation.
Note that the process parameters in the right-side vector of
(11) contain the local variation geometric scaling as prescribed
by (1)(3). This means that geometric scaling is applied to both
the variance and the sensitivity components on the right side of
(8). The geometric scaling affects the sensitivities through the
underlying SPICE MOSFET model.
III. MISMATCH APPLICATION

Fig. 4. NMOS I mismatch over bias, 0.25-m CMOS technology, W=L =

7=0:56 m = 2:5 V. Symbols are data.

. An appropriate reparameterization of
and mismatch
,
, , and
. BPV should not be confused
would use

An accurate mismatch model is not useful unless it can be

practically used for design. The specific intention of the characterization approach described here is its application in SPICE
through Monte Carlo or sensitivity analysis. We use MOSFET
current mirrors to illustrate some nonobvious mismatch phenomena. Similar analysis can be used for other applications such
as differential pairs and much larger circuit blocks.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 3, MARCH 2003

NMOS I mismatch versus L, 0.25-m CMOS technology, W 7 m,

= 2:5; V = 2:5 V. Symbols are data.

Fig. 5.

Fig. 6. Three-dimensional (3-D) plot of I mismatch versus L and W for an

nMOS current mirror, I = 10 A, 0.13-m CMOS technology.

Fig. 7.

3-D plot of

mismatch versus geometry, graded-channel nMOS, at

= 10 A, 0.25-m BiCMOS technology.

I mismatch and the underlying process parameter contributions for

L = 25 m in Fig. 7. gc subscript indicates parameters specific to the graded
Fig. 8.

channel.

A. Geometry and Bias Interrelationship

What is the best way to size devices in a current mirror to meet
matching requirements? A MOSFET current mirror is biased
with a current, so the gate voltage depends on geometry. Intuincreases,
itively, as the gate overdrive voltage
have less impact on the misthose parameters that effect
match. This is even apparent in (4).
increases, the intrinsic mismatch decreases as per
As
increases to supply the same ref(1)(3). At the same time,
erence current. Both the sensitivity local parameter components
.
in (8) also decrease, constructively combining to decrease
increases, the intrinsic mismatch compoHowever, as
decreases. These two effects offset
nent decreases, but
each other, and as Fig. 6 shows, can give rise to little or no
improvement in mismatch with increasing . Depending on
the underlying dominant mismatch process parameters, better
matching can be obtained without consuming additional area,
aspect ratio. This improvement
simply by changing the
comes at the expense of reduced dynamic range since
increases and, hence, the linear/saturation transition point for
(i.e.,
) increases.
For graded-channel MOSFETs [23] (and halo-implanted
devices), the geometry and bias tradeoff can have a much
more profound impact, as Fig. 7 shows. Here, a dramatic
ratios.
improvement in mismatch is obtained with small

To further explore this, a cut along

m in Fig. 7 is given
in Fig. 8. For wider devices, the mismatch is dominated by
the dopant concentration and the length of the graded-channel
region. Since the channel dopant concentration is highest in the
graded-channel region (versus the bulk dopant concentration),
this region effectively sets the threshold voltage of the device.
increases, thereby reducing the senAs the device narrows,
to the graded-channel components. Of particular
sitivity of
interest is that the geometric dependency of is determined
by the local process parameter definition, but the geometric
dependency of the graded-channel regions is determined by
the sensitivity component of (10) and (11). Mismatch does not
on mismatch
blindly depend on area alone. The impact of
also means that mismatch is not constant if the reference
current is not constant, such as in an active load (see Fig. 9).
Thus, current mirror mismatch depends strongly on and
not . Proper sizing of MOSFETs in current mirrors requires a
mismatch model that is accurate over both bias and geometry.
B. NMOS or PMOS?
A common question is, Which matches better, nMOS or
pMOS? The answer depends on how a device is biased. With
voltage bias, there is no consistent trend across technologies.
With current bias, the lower mobility for pMOS means that

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455

TABLE III
IMPACT OF MULTIPLE UNIT DEVICES ON CURRENT MIRROR MISMATCH FOR A
IS SCALED
2 2 m nMOS DEVICE ON A 0.13-m CMOS PROCESS. I
FOR THE REFERENCE DEVICE TO MAINTAIN CONSTANT VOLTAGE BIAS

Fig. 9. Current mirror I mismatch versus I

CMOS technology.

FOR 2
ON A 0.4-

MISMATCH

, W=L

= 2=2 m, 0.13-m

TABLE II
NMOS AND PMOS DEVICES
m-POWER BiCMOS PROCESS

2 2 m

dividing the 20- m device mismatch by

. This consistency
is an important consideration when selecting the geometric
dependency in the rightmost vector in (11).
Where integer current scaling is desired, the matching of a
1 : ratio differs from an : 1 ratio. If devices are placed in
parallel, each device contributes additional mismatch variance.
The situation for current mirrors is slightly different, because
multiple-unit devices in the reference transistor are mapped
through the gate voltage. As Table III shows, the majority of
the improvement from using multiple parallel devices is gained
by using them for the output, not the reference device.
IV. CONCLUSION

a larger
is required to supply the same reference or tail
current, thereby improving the mismatch as compared with an
nMOS device. Table II shows this effect for complementary
standard-logic nMOS and pMOS devices in a 0.4- m-power
BiCMOS process. In almost all cases, complementary pMOS
devices will appear to have better matching than nMOS when
biased with current. More generally, mismatch tradeoffs appear
differently to characterization and device engineers (who typically bias devices with voltages) than to design engineers (who
mismatch
often bias devices with current). Metrics such as
may not be particularly meaningful. Device-type, geometry, and
bias comparisons for mismatch must be performed in the design
application.
C. Multiple-Unit Devices
Wide/short MOSFETs are often used in design, particularly
is needed.
in differential pair applications where a high
These devices are broken up into smaller unit MOSFETs and
combined to compact the layout and to reduce parasitic source
and drain junction capacitances. When multiple-unit devices
are placed in parallel, the process parameter variance component in (10) increases by a factor of , because each MOSFET
contains its own local parameter variation. On the other hand,
the squared sensitivities decrease by a factor of n , because
each device has less impact of the current. Thus, overall
decreases by a factor of
, per (10). This is consistent with
the definition of local parameter variation. For example, an
- m-wide
80- m-wide device can be broken up into
devices. Neglecting width effects, the mismatch variability for
a single 20- m-wide device will be twice the variability of
the 80- m-wide device per (1) and (3), which is the same as

Accurate mismatch modeling is needed to avoid parametric

yield loss and overdesign. The common approach to MOSFET
mismatch modeling, based on and , leads to inaccurate predictions over geometry and bias. Mismatch modeling based on
physical process parameters is significantly more accurate.
In addition, because the approach is based on physical
uncorrelated process parameters, the characterization procedure
identifies the parameters that have the greatest contribution
to mismatch. This helps process technologists identify key
areas to work on when trying to optimize a process for best
mismatch.
REFERENCES
[1] R. Wilson, The dirty little secret: Engineers at design forum vexed by
rise in process variations at the die level, EE Times, p. 1, Mar. 25, 2002.
[2] K. Bult and A. Buchwald, An embedded 240-mW 10-b 50-MS/s
CMOS ADC in 1-mm , IEEE J. Solid-State Circuits, vol. 32, pp.
18871895, Dec. 1997.
[3] S. C. Wong et al., A CMOS mismatch model and scaling effects, IEEE
Electron Device Lett., vol. 18, pp. 261263, June 1997.
[4] S. Lovett et al., Characterizing the mismatch of submicron MOS transistors, in IEEE Int. Conf. Microelectronic Test Structures, vol. 9, Mar.
1996, pp. 3942.
[5] T. Serrano-Gotarredona and B. Linares-Barranco, A new five-parameter MOS transistor mismatch model, IEEE Electron Device Lett., vol.
21, pp. 3739, Jan. 2000.
[6] Q. Zhang et al., SPICE modeling and quick estimation of MOSFET
mismatch based on BSIM3 model and parametric tests, IEEE J. SolidState Circuits, vol. 36, pp. 15921595, Oct. 2001.
[7] J. A. Croon et al., An easy-to-use mismatch model for the MOS transistor, IEEE J. Solid-State Circuits, vol. 37, pp. 10561064, Aug. 2002.
[8] M. J. Pelgrom et al., Matching properties of MOS transistors, IEEE J.
Solid-State Circuits, vol. 24, pp. 14331440, Oct. 1989.
[9] H. P. Tuinhout and M. Vertregt, Test structures for investigation of metal
coverage effects on MOSFET matching, in IEEE Int. Conf. Microelectronic Test Structures, Mar. 1997, pp. 179183.

456

[10] H. P. Tuinhout et al., Effects of gate depletion and boron penetration on

matching of deep submicron CMOS transistors, in IEEE Int. Electron
Devices Meeting, Dec. 1997, pp. 631634.
, Impact of ion implantation statistics on V fluctuations in MOS[11]
FETs: comparison between Decarborane and Boron channel implants,
in Proc. VLSI Symp., 2000, pp. 134135.
[12] J. B. Shyu et al., Random errors in MOS capacitors, IEEE J. SolidState Circuits, vol. SC-17, pp. 948955, Dec. 1982.
, Random error effects in matched MOS capacitors and current
[13]
sources, IEEE J. Solid-State Circuits, vol. SC-19, pp. 10701076, Dec.
1984.
[14] C. C. McAndrew, Modeling for circuit simulation, in Proc. IEEE
Custom Integrated Circuits Conf., Education Session, May 2000, pp.
E11.
[15] R. Difrenza et al., Comparison between matching parameters and fluctuations at the wafer level, in Proc. IEEE Int. Conf. Microelectronic
Test Structures, Apr. 2002, pp. 241246.
[16] C. C. McAndrew and P. G. Drennan, Unified statistical modeling for
circuit simulation, in Proc. 5th Int. Conf. Modeling and Simulation of
Microsystems, Apr. 2002, pp. 715718.
[17] K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, Characterization and modeling of mismatch in MOS transistors for precision
analog design, IEEE J. Solid-State Circuits, vol. SC-21, pp. 10571066,
Dec. 1986.
[18] P. G. Drennan and C. C. McAndrew, A comprehensive MOSFET mismatch model, in Proc. IEEE Int. Electron Devices Meeting, Dec. 1999,
pp. 167170.
, A comprehensive vertical BJT mismatch model, in Proc. IEEE
[19]
Bipolar/BiCMOS Circuits and Technology Meeting, Sept. 1998, pp.
8386.
[20] J. Kirchgessner et al., A 0.18-m SiGe : C RFBiCMOS technology
for wireless and gigabit optical communication applications, in Proc.
IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Sept. 2001,
pp. 151154.
[21] P. G. Drennan, Diffused resistor mismatch modeling and characterization, in Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting,
Sept. 1999, pp. 2730.
[22] M. Bolt, Matching properties of MOS transistors and delay line chains
with self-aligned source/drain contacts, in Proc. IEEE Int. Conf. Microelectronic Test Structures, Mar. 1996, pp. 2125.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 3, MARCH 2003

BiCMOS
[23] F. K. Chai et al., A cost-effective 0.25-m L
technology featuring graded-channel CMOS (GCMOS) and a
quasi-self-aligned (QSA) NPN for RF wireless applications, in Proc.
IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Sept. 2000,
pp. 110113.

Patrick G. Drennan (M96) received the B.S. degree in microelectronic engineering and the M.S. degree in electrical engineering from the Rochester Institute of Technology, Rochester, NY, in 1991 and
1993, respectively, and the Ph.D. degree in electrical
engineering from Arizona State University, Tempe,
in 1999.
He joined Motorola, Semiconductor Products
Sector, Tempe, in 1992, where he is currently a
Distinguished Member of the Technical Staff. His
professional interests include mismatch modeling,
simulation, monitoring, and debugging for analog circuit design.

Colin C. McAndrew (S82M84SM90) received

the B.E. (Hons) degree in electrical engineering from
Monash University, Melbourne, Victoria, Australia,
in 1978, and the M.A.Sc. and Ph.D. degrees in
systems design engineering from the University
of Waterloo, Waterloo, ON, Canada, in 1982 and
1984, respectively.
From 1978 to 1980 and from 1984 to 1987, he was
with the Herman Research Laboratories, State Electricity Commission, Victoria. From 1987 to 1995, he
was with AT&T Bell Laboratories, Allentown, PA.
Since 1995, he has been with Motorola, Tempe, AZ, and is currently Director
of the Enabling Technology Center. His research interests are in compact and
statistical modeling and characterization for circuit simulation.
Dr. McAndrew is on the Technical Program Committees for the IEEE
Bipolar/BiCMOS Circuits and Technology Meeting, the IEEE International
Conference on Microelectronic Test Structures, and the IEEE Custom Integrated Circuits Conference, and is an Editor of the IEEE TRANSACTIONS ON
ELECTRON DEVICES.