ST24/25C02, ST24C02R

ST24/25W02
SERIAL 2K (256 x 8) EEPROM
NOT FOR NEW DESIGN

1 MILLION ERASE/WRITE CYCLES with

40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
3V to 5.5V for ST24x02 versions
2.5V to 5.5V for ST25x02 versions
1.8V to 5.5V for ST24C02R version only
HARDWARE WRITE CONTROL VERSIONS:
ST24W02 and ST25W02
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 4
BYTES)
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH-UP
PERFORMANCES
ST24C/W02 are replaced by the M24C02
ST25C/W02 are replaced by the M24C02-W
ST24C02R is replaced by the M24C02-R

1
PSDIP8 (B)
0.25mm Frame

SO8 (M)
150mil Width

Figure 1. Logic Diagram

VCC

DESCRIPTION
This specification covers a range of 2K bits I2C bus
EEPROM products, t he ST24/25C02, the
ST24C02R and ST24/25W02. In the text, products
are referred to as ST24/25x02, where "x" is: "C" for
Standard version and "W" for hardware Write Control version.
Table 1. Signal Names
E0-E2

Chip Enable Inputs

SDA

Serial Data Address Input/Output

SCL

Serial Clock

MODE

Multibyte/Page Write Mode

(C version)

WC

Write Control (W version)

VCC

Supply Voltage

VSS

Ground

November 1997
This is information on a product still in production but not recommended for new design

3
E0-E2
SCL

SDA
ST24x02
ST25x02
ST24C02R

MODE/WC*

VSS
AI00788D

Note: WC signal is only available for ST24/25W02 products.

1/16

ST24/25C02, ST24C02R, ST24/25W02

Figure 2A. DIP Pin Connections

Figure 2B. SO Pin Connections

ST24x02
ST25x02
ST24C02R
E0
E1
E2
VSS

8
7
6
5

1
2
3
4

ST24x02
ST25x02
ST24C02R
VCC
MODE/WC
SCL
SDA

E0
E1
E2
VSS

AI00789D

1
2
3
4

8
7
6
5

VCC
MODE/WC
SCL
SDA

AI00790E

Table 2. Absolute Maximum Ratings (1)

Symbol

Value

Unit

Ambient Operating Temperature

40 to 125

TSTG

Storage Temperature

65 to 150

TLEAD

Lead Temperature, Soldering

215
260

TA

Parameter

VIO

Input or Output Voltages

VCC

Supply Voltage

VESD

(SO8 package)
(PSDIP8 package)

Electrostatic Discharge Voltage (Human Body model)

Electrostatic Discharge Voltage (Machine model)

(3)

(2)

40 sec
10 sec

0.6 to 6.5

0.3 to 6.5

4000

500

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 ).
3. EIAJ IC-121 (Condition C) (200pF, 0 ).

DESCRIPTION (contd)
The ST24/25x02 are 2K bit electrically erasable
programmable memories (EEPROM), organized
as 256 x 8 bits. They are manufactured in SGSTHOMSONs Hi-Endurance Advanced CMOS
technology which guarantees an endurance of one
million erase/write cycles with a data retention of
40 years. The memories operate with a power
supply value as low as 1.8V for the ST24C02R only.
Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
The memories are compatible with the I 2C standard, two wire serial interface which uses a bi-direc2/16

tional data bus and serial clock. The memories

carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I2C bus definition. This is used together with 3 chip enable inputs
(E2, E1, E0) so that up to 8 x 2K devices may be
attached to the I2C bus and selected individually.
The memories behave as a slave device in the I2C
protocol with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition generated by the
bus master. The START condition is followed by a
stream of 7 bits (identification code 1010), plus one
read/write bit and terminated by an acknowledge
bit.

ST24/25C02, ST24C02R, ST24/25W02

Table 3. Device Select Code

Device Code

Chip Enable

RW

Bit

b7

b6

b5

b4

b3

b2

b1

b0

Device Select

E2

E1

E0

RW

Note: The MSB b7 is sent first.

Table 4. Operating Modes (1)

Mode

RW bit

MODE

Bytes

Current Address Read

Random Address Read

0
1

Initial Sequence
START, Device Select, RW = 1
START, Device Select, RW = 0, Address,
reSTART, Device Select, RW = 1

Sequential Read

1 to 256

Byte Write

START, Device Select, RW = 0

VIH

START, Device Select, RW = 0

VIL

START, Device Select, RW = 0

Multibyte Write

(2)

Page Write

Similar to Current or Random Mode

Notes: 1. X = VIH or VIL

2. Multibyte Write not available in ST24/25W02 versions.

When writing data to the memory it responds to the

8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are terminated with a STOP condition.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3).

Serial Data (SDA). The SDA pin is bi-directional

and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-ORed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 3).
Chip Enable (E2 - E0). These chip enable inputs
are used to set the 3 least significant bits (b3, b2,
b1) of the 7 bit device select code. These inputs
may be driven dynamically or tied to VCC or VSS to
establish the device select code.
Mode (MODE). The MODE input is available on pin
7 (see also WC feature) and may be driven dynamically. It must be at VIL or VIH for the Byte Write
mode, VIH for Multibyte Write mode or VIL for Page
Write mode. When unconnected, the MODE input
is internally read as a VIH (Multibyte Write mode).
Write Control (WC). An hardware Write Control
feature (WC) is offered only for ST24W02 and
ST25W02 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cycle. The Write Control signal is used to enable (WC = VIH) or disable (WC =
VIL) the internal write protection. When unconnected, the WC input is internally read as VIL and
the memory area is not write protected.

3/16

ST24/25C02, ST24C02R, ST24/25W02

SIGNAL DESCRIPTIONS (contd)
The devices with this Write Control feature no
longer support the Multibyte Write mode of operation, however all other write modes are fully supported.
Refer to the AN404 Application Note for more detailed information about Write Control feature.
DEVICE OPERATION
I2C Bus Background
The ST24/25x02 support the I2C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for synchronisation. The ST24/25x02 are always slave
devices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x02 continuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.

Stop Condition. STOP is identified by a low to high

transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition terminates communication between the ST24/25x02
and the bus master. A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input. During data input the ST24/25x02
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device operation the SDA signal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.
Memory Addressing. To start communication between the bus master and the slave ST24/25x02,
the master must initiate a START condition. Following this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.

Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus

20
VCC
16

RL max (k)

RL
12

RL

SDA
MASTER

CBUS

SCL

8
CBUS
4
VCC = 5V
0
100

200
CBUS (pF)

4/16

300

400
AI01100

ST24/25C02, ST24C02R, ST24/25W02

Table 5. Input Parameters (1) (TA = 25 C, f = 100 kHz )

Symbol

Parameter

Test Condition

Min

Max

Unit

CIN

Input Capacitance (SDA)

pF

CIN

Input Capacitance (other pins)

pF

20

ZWCL

WC Input Impedance (ST24/25W02)

VIN 0.3 VCC

ZWCH

WC Input Impedance (ST24/25W02)

VIN 0.7 VCC

500

tLP

Low-pass filter input time constant

(SDA and SCL)

k
100

ns

Note: 1. Sampled only, not 100% tested.

Table 6. DC Characteristics
(TA = 0 to 70C, 20 to 85C or 40 to 85C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol

Parameter

Test Condition

ILI

Input Leakage Current

ILO

Output Leakage Current

ICC

ICC1

ICC2

ICC3

ICC4

Max

Unit

0V VIN VCC

0V VOUT VCC
SDA in Hi-Z

Supply Current (ST24 series)

VCC = 5V, fC = 100kHz

(Rise/Fall time < 10ns)

mA

Supply Current (ST25 series)

VCC = 2.5V, fC = 100kHz

mA

VIN = VSS or VCC,

VCC = 5V

100

VIN = VSS or VCC,

VCC = 5V, fC = 100kHz

300

VIN = VSS or VCC,

VCC = 2.5V

VIN = VSS or VCC,

VCC = 2.5V, fC = 100kHz

50

VIN = VSS or VCC,

VCC = 3.6V

20

VIN = VSS or VCC,

VCC = 3.6V, fC = 100kHz

60

VIN = VSS or VCC,

VCC = 1.8V

10

VIN = VSS or VCC,

VCC = 1.8V, fC = 100kHz

20

Supply Current (Standby)

(ST24 series)

Supply Current (Standby)

(ST25 series)

Supply Current (Standby)

(ST24C02R)

Supply Current (Standby)

(ST24C02R)

Min

VIL

Input Low Voltage (SCL, SDA)

0.3

0.3 VCC

VIH

Input High Voltage (SCL, SDA)

0.7 VCC

VCC + 1

VIL

Input Low Voltage

(E0-E2, MODE, WC)

0.3

0.5

VIH

Input High Voltage

(E0-E2, MODE, WC)

VCC 0.5

VCC + 1

VOL

Output Low Voltage (ST24 series)

IOL = 3mA, VCC = 5V

0.4

Output Low Voltage (ST25 series)

IOL = 2.1mA, VCC = 2.5V

0.4

IOL = 1mA, VCC = 1.8V

0.3

Output Low Voltage

(ST24C02R)

5/16

ST24/25C02, ST24C02R, ST24/25W02

Table 7. AC Characteristics
(TA = 0 to 70C, 20 to 85C or 40 to 85C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol

Alt

tCH1CH2

tR

tCL1CL2

Max

Unit

Clock Rise Time

tF

Clock Fall Time

300

ns

tDH1DH2

tR

Input Rise Time

tDL1DL1

tF

Input Fall Time

300

ns

tCHDX

(1)

tSU:STA

Parameter

Min

4.7

Clock Pulse Width High

Clock High to Input Transition

tCHCL

tHIGH

tDLCL

tHD:STA

Input Low to Clock Low (START)

tCLDX

tHD:DAT

Clock Low to Input Transition

tCLCH

tLOW

Clock Pulse Width Low

4.7

tDXCX

tSU:DAT

Input Transition to Clock Transition

250

ns

tCHDH

tSU:STO

Clock High to Input High (STOP)

4.7

tDHDL

tBUF

Input High to Input Low (Bus Free)

4.7

tAA

Clock Low to Next Data Out Valid

0.3

tCLQX

tDH

Data Out Hold Time

300

fC

fSCL

Clock Frequency

100

kHz

tWR

Write Time

10

ms

tCLQV

tW

(2)

(3)

3.5

s
ns

Notes: 1. For a reSTART condition, or following a write cycle.

2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.

DEVICE OPERATION (contd)

AC MEASUREMENT CONDITIONS
Input Rise and Fall Times

50ns

Input Pulse Voltages

0.2VCC to 0.8VCC

Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC

Figure 4. AC Testing Input Output Waveforms

0.8VCC

0.2VCC

0.7VCC
0.3VCC
AI00825

6/16

The 4 most significant bits of the device select code

are the device type identifier, corresponding to the
I2C bus definition. For these memories the 4 bits
are fixed as 1010b. The following 3 bits identify the
specific memory on the bus. They are matched to
the chip enable signals E2, E1, E0. Thus up to 8 x
2K memories can be connected on the same bus
giving a memory capacity total of 16K bits. After a
START condition any memory on the bus will identify the device code and compare the following 3
bits to its chip enable inputs E2, E1, E0.
The 8th bit sent is the read or write bit (RW), this
bit is set to 1 for read and 0 for write operations.
If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time.

ST24/25C02, ST24C02R, ST24/25W02

Figure 5. AC Waveforms

tCHCL

tCLCH

SCL
tDLCL

tDXCX

tCHDH

SDA IN
tCHDX
START
CONDITION

tCLDX

tDHDL

SDA
INPUT

SDA
CHANGE

STOP &
BUS FREE

SCL
tCLQV

tCLQX
DATA VALID

SDA OUT

DATA OUTPUT

tDHDL
SCL
tW
SDA IN
tCHDH
STOP
CONDITION

tCHDX
WRITE CYCLE

START
CONDITION
AI00795

7/16

ST24/25C02, ST24C02R, ST24/25W02

Figure 6. I2C Bus Protocol

SCL

SDA
START
CONDITION

SCL

SDA

MSB

SDA
INPUT

SDA
CHANGE

STOP
CONDITION

ACK

START
CONDITION

SCL

SDA

MSB

ACK

STOP
CONDITION

AI00792

Write Operations
The Multibyte Write mode (only available on the
ST24/25C02 and ST24C02R versions) is selected
when the MODE pin is at VIH and the Page Write
mode when MODE pin is at VIL. The MODE pin may
be driven dynamically with CMOS input levels.
Following a START condition the master sends a
device select code with the RW bit reset to 0. The
memory acknowledges this and waits for a byte
address. The byte address of 8 bits provides access to 256 bytes of the memory. After receipt of
the byte address the device again responds with
an acknowledge.
8/16

For the ST24/25W02 versions, any write command

with WC = 1 will not modify the memory content.
Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition. The Write mode
is independant of the state of the MODE pin which
could be left floating if only this mode was to be
used. However it is not a recommended operating
mode, as this pin has to be connected to either VIH
or VIL, to minimize the stand-by current.

ST24/25C02, ST24C02R, ST24/25W02

Multibyte Write. For the Multibyte Write mode, the
MODE pin must be at VIH. The Multibyte Write
mode can be started from any address in the
memory. The master sends from one up to 4 bytes
of data, which are each acknowledged by the memory. The transfer is terminated by the master generating a STOP condition. The duration of the write
cycle is tW = 10ms maximum except when bytes
are accessed on 2 rows (that is have different
values for the 6 most significant address bits A7A2), the programming time is then doubled to a
maximum of 20ms. Writing more than 4 bytes in the
Multibyte Write mode may modify data bytes in an
adjacent row (one row is 8 bytes long). However,
the Multibyte Write can properly write up to 8
consecutive bytes only if the first address of these
8 bytes is the first address of the row, the 7 following
bytes being written in the 7 following bytes of this
same row.

Page Write. For the Page Write mode, the MODE

pin must be at VIL. The Page Write mode allows up
to 8 bytes to be written in a single write cycle,
provided that they are all located in the same row
in the memory: that is the 5 most significant memory address bits (A7-A3) are the same. The master
sends from one up to 8 bytes of data, which are
each acknowledged by the memory. After each
byte is transfered, the internal byte address counter
(3 least significant bits only) is incremented. The
transfer is terminated by the master generating a
STOP condition. Care must be taken to avoid address counter roll-over which could result in data
being overwritten. Note that, for any write mode,
the generation by the master of the STOP condition
starts the internal memory program cycle. All inputs
are disabled until the completion of this cycle and
the memory will not respond to any request.

Figure 7. Write Cycle Polling using ACK

WRITE Cycle
in Progress

START Condition
DEVICE SELECT
with RW = 0

NO
First byte of instruction
with RW = 0 already
decoded by ST24xxx

ACK
Returned
YES

NO

Next
Operation is
Addressing the
Memory

YES

Send
Byte Address

ReSTART

STOP

Proceed
WRITE Operation

Proceed
Random Address
READ Operation

AI01099B

9/16

ST24/25C02, ST24C02R, ST24/25W02

Figure 8. Write Modes Sequence (ST24/25C02 and ST24C02R)

ACK

BYTE ADDR

DATA IN

R/W
ACK

MULTIBYTE
AND
PAGE WRITE

ACK

STOP

DEV SEL

START

BYTE WRITE

ACK

START

DEV SEL

ACK

BYTE ADDR

ACK
DATA IN 1

DATA IN 2

R/W
ACK

ACK

STOP

DATA IN N

AI00793

Minimizing System Delays by Polling On ACK.

During the internal write cycle, the memory disconnects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (tW) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be reduced by an ACK polling sequence issued by the
master. The sequence is as follows:
Initial condition: a Write is in progress (see Figure 7).
Step 1: the master issues a START condition
followed by a device select byte (1st byte of
the new instruction).
Step 2: if the memory is busy with the internal
write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory
has terminated the internal write cycle, it will
respond with an ACK, indicating that the memory is ready to receive the second part of the
next instruction (the first byte of this instruction was already sent during Step 1).

10/16

Read Operations
Read operations are independent of the state of the
MODE pin. On delivery, the memory content is set
at all "1s" (or FFh).
Current Address Read. The memory has an internal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Address Read mode, following a START condition,
the master sends a memory address with the RW
bit set to 1. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter. This counter is then incremented.
The master does NOT acknowledge the byte output, but terminates the transfer with a STOP condition.
Random Address Read. A dummy write is performed to load the address into the address
counter, see Figure 10. This is followed by another
START condition from the master and the byte
address is repeated with the RW bit set to 1. The
memory acknowledges this and outputs the byte
addressed. The master have to NOT acknowledge
the byte output, but terminates the transfer with a
STOP condition.

ST24/25C02, ST24C02R, ST24/25W02

Figure 9. Write Modes Sequence with Write Control = 1 (ST24/25W02)

WC
ACK

BYTE ADDR

ACK
DATA IN

STOP

DEV SEL

START

BYTE WRITE

ACK

R/W

WC
ACK
DEV SEL

START

PAGE WRITE

ACK

BYTE ADDR

ACK
DATA IN 1

DATA IN 2

R/W

WC (cont'd)
ACK
DATA IN N

STOP

PAGE WRITE
(cont'd)

ACK

AI01101B

Sequential Read. This mode can be initiated with

either a Current Address Read or a Random Address Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in sequence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte output, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-

ically incremented after each byte output. After a

count of the last memory address, the address
counter will roll- over and the memory will continue
to output data.
Acknowledge in Read Mode. In all read modes
the ST24/25x02 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
low during this time, the ST24/25x02 terminate the
data transfer and switches to a standby state.

11/16

ST24/25C02, ST24C02R, ST24/25W02

Figure 10. Read Modes Sequence

ACK

DATA OUT

STOP

START

DEV SEL

NO ACK

R/W

ACK
RANDOM
ADDRESS
READ

BYTE ADDR

R/W

ACK

START

DEV SEL

DATA OUT

R/W

ACK

ACK

DATA OUT 1

NO ACK

DATA OUT N

R/W

ACK

START

DEV SEL *

ACK

BYTE ADDR

R/W

ACK

ACK
DEV SEL *

START

SEQUENTIAL
RANDOM
READ

NO ACK

STOP

SEQUENTIAL
CURRENT
READ

ACK
DEV SEL *

START

START

DEV SEL *

ACK

STOP

CURRENT
ADDRESS
READ

ACK

DATA OUT 1

R/W

NO ACK

STOP

DATA OUT N

AI00794C

Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.

12/16

ST24/25C02, ST24C02R, ST24/25W02

ORDERING INFORMATION SCHEME

Example:

ST24C02

Operating Voltage
ST24C02

TR

Range

3V to 5.5V

Standard

ST24W02

3V to 5.5V

Hardware Write Control

ST25C02

2.5V to 5.5V

Standard

ST25W02

2.5V to 5.5V

Hardware Write Control

ST24C02R

1.8V to 5.5V

Standard

Package

Notes:

PSDIP8
0.25mm Frame

SO8 150mil Width

Temperature Range
1

0 to 70 C

5*

20 to 85 C

40 to 85 C

3*

40 to 125 C

Option
TR

Tape & Reel

Packing

3 * Temperature range on special request only.

5 * Temperature range for ST24C02R only.

Parts are shipped with the memory content set at all "1s" (FFh).
For a list of available options (Operating Voltage, Range, Package, etc...) refer to the current Memory
Shortform catalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.

13/16

ST24/25C02, ST24C02R, ST24/25W02

PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

mm

Symb
Typ

inches

Min

Max

3.90

A1

Min

Max

5.90

0.154

0.232

0.49

0.019

A2

3.30

5.30

0.130

0.209

0.36

0.56

0.014

0.022

B1

1.15

1.65

0.045

0.065

0.20

0.36

0.008

0.014

9.20

9.90

0.362

0.390

6.00

6.70

0.236

0.264

7.80

0.307

7.62

E1
e1

2.54

eA
eB

Typ

0.300

0.100

10.00

3.00

0.394

3.80

0.118
8

PSDIP8

A2
A1
B

A
L

e1

eA
eB

B1
D

E1

1
PSDIP-a

Drawing is not to scale

14/16

0.150

ST24/25C02, ST24C02R, ST24/25W02

SO8 - 8 lead Plastic Small Outline, 150 mils body width

mm

Symb
Typ

inches

Min

Max

1.35

A1

Min

Max

1.75

0.053

0.069

0.10

0.25

0.004

0.010

0.33

0.51

0.013

0.020

0.19

0.25

0.007

0.010

4.80

5.00

0.189

0.197

3.80

4.00

0.150

0.157

5.80

6.20

0.228

0.244

0.25

0.50

0.010

0.020

0.40

0.90

0.016

0.035

1.27

CP

Typ

0.050

8
0.10

0.004

SO8

h x 45
A
C
B

CP

e
D

A1

SO-a

Drawing is not to scale

15/16

ST24/25C02, ST24C02R, ST24/25W02

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1997 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I2C Components by SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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