03 Fetch Unit Operation

Fetch Unit Operation
CSE 141L Lab 2
Hot off the presses!

La Jolla, CA -- Thirty-three dedicated processor design teams have
successfully created new design concepts for highly optimized
Supergarbage execution engines.
JHacker90, speaking for the group of happy hackers, said "It was a
heroic effort, but nothing that couldn't be handled with perseverance
and a large pizza." When queried about the rapidly exploding
processor design industry in San Diego, executives at Intel
corporation answered curtly "We don't comment on our competition, no
matter how awesome."
Meanwhile, the US Patent Office has decided to open a new branch in
San Diego to handle the imminent wave of patent filings that are sure
to ensue.
Upon receipt of the news, Jake Ivring, of UnificationITY, Inc, was
seen raising his fist to the sky and proclaiming: "Finally! We will
crush that meddlesome Boatorola Corp! To Supergarbage and Beyond!"
Lab 2A Status
Great progress by everyone
Almost halfway to a fully working
processor!
Amnesty policy:
By end of today (4/13): 0% penalty
By end of tomorrow (4/14): 5% penalty
Front-End vs Back-End
Front-end fetches instructions (Lab 2)
Reads from instruction memory

Stores fetched instructions in FIFO
Predicts which addresses to fetch
Back-end executes instructions (Lab 3)
Pulls instructions from front-ends FIFO

Reads/writes to data memory
Must check correctness of front-end prediction.
Why separate fetch from execution?
Pipelined Fetch Unit

Fetch unit split into two separate stages
Address Calculation
Determines what address goes into
SRAM
FIFO storage
Stores instruction address and SRAM
output into FIFO
restart_i
Control
load_data_valid_o
load_store_valid_i
sel_mux[3:0]
fifo_enque
ram_we
fifo_clear
store_en_i
0
instruction_valid_o
pc_r[9:0]
mux0
+1
+offset
restart_addr _i[9:0]
instruction_data_o[16:0]
FIFO
mux1
0
0
restart_addr_r [9:0]
ip_in.instr
mux2
deque_i
1
load_store_addr_i [9:0]
instruction_addr_o[9:0]
ip_in.addr
pc_next
load_store_addr_r [9:0]
SRAM
mux3
store_data_r [16:0]
fifo_empty fifo_full
store_data _i[16:0]
offset [9:0]
sign
extend
Address Calculation (AC)
ram_data [4:0]
load_data_o[16:0]
Datapath
FIFO Store (FS)
Fetch Pipeline In Action

Cycle #
0x0: add $1, $2, $3
0x1: sub $3, $3, $4
0x2: bez $3, 0x10
0x12: add $7, $5, $9
0x13: ...
AC
FS
AC
Prediction
known here
FS
AC
FS
AC
FS
AC
...
Restarting Fetch
Cycle #
0x2: bez $3, 0x10
0x12: add $7, $5, $9
0x13: mul $7, $7, $4
0x3: add $3, $6, $7
0x4: ...
AC
FS
AC
FS
AC
Clear FIFO. Why?
FS
X
AC
back-end
detects
mispredict!
restart @
0x3
FS
AC
...
Stalling for loads/stores

Cycle #
0x5: add $1, $2, $3
0x6: sub $3, $3, $4
0x7: muli $3, 0x8
0x8: add $7, $5, $9
AC
FS
AC
Load addr 0x30

asserted
FS
Load
AC
FS
AC
FS
Stalled on Full FIFO

Cycle #
0x5: add $1, $2, $3
0x6: sub $3, $3, $4
0x7: muli $3, 0x8
0x8: add $7, $5, $9
AC
FS
FIFO Full
asserted
FIFO Full
FS deasserted
AC
AC
FS
AC
FS
AC
FS
Lab 2B:
Fetch Unit Control
restart_i
Control
load_data_valid_o
load_store_valid_i
sel_mux[3:0]
store_en_i
0
instruction_valid_o
fifo_enque fifo_clear
ram_we
pc_r[9:0]
mux0
+1
+offset
restart_addr _i[9:0]
instruction_data_o[16:0]
FIFO
mux1
0
0
restart_addr_r [9:0]
ip_in.instr
mux2
deque_i
1
load_store_addr_i [9:0]
instruction_addr_o[9:0]
ip_in.addr
pc_next
load_store_addr_r [9:0]
SRAM
mux3
store_data_r [16:0]
fifo_empty fifo_full
store_data _i[16:0]
offset [9:0]
sign
extend
Address Calculation (AC)
ram_data [4:0]
load_data_o[16:0]
Datapath
FIFO Store (FS)
Control logic
implementation
Fetch unit is pipelined
Not modeled as a finite state machine
Each pipeline stage depends on a subset
of the control signals
Need to identify which signals those

are
Simplified
Implementation Stategy
For each pipeline stage, ask yourself the following

questions:
What control signals are needed for the datapath

during this stage?
What does each of these signals do?

What inputs do I need to correctly set those
control signals?
Encode relationship between control input and

output using Verilog
A Simple Example
Address Calculation stage:
What are the control signals associated with that

stage?
sel_mux[3:0], ...
What does sel_mux[0] do?
Selects between PC+1 and PC+offset
What is value of sel_mux[0] based on?
P bit: dictactes whether we branch or not

Anything else?

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Fetch Unit Operation

CSE 141L Lab 2

Hot off the presses!

Front-end fetches instructions (Lab 2)

Reads from instruction memory

Back-end executes instructions (Lab 3)

Pulls instructions from front-ends FIFO

Why separate fetch from execution?

Pipelined Fetch Unit

Address Calculation (AC)

Fetch Pipeline In Action

Clear FIFO. Why?

Stalling for loads/stores

Load addr 0x30

Stalled on Full FIFO

Address Calculation (AC)

Need to identify which signals those

For each pipeline stage, ask yourself the following

What control signals are needed for the datapath

What does each of these signals do?

Encode relationship between control input and

Address Calculation stage:

What are the control signals associated with that

What does sel_mux[0] do?

Selects between PC+1 and PC+offset

What is value of sel_mux[0] based on?

P bit: dictactes whether we branch or not

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