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Code No: V3121/R07 Set No. 1

III B.Tech I Semester Regular Examinations, November 2009
DIGITAL IC APPLICATIONS
( Common to Electronics & Communication Engineering and Electronics &
Instrumentation Engineering)
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Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????
1. (a) Design a CMOS transistor circuit with the functional behavior as
f (x) = (a + b) ( c + d)
Also draw the relevant circuit diagram.

(b) Distinguish between static and dynamic power dissipation of a CMOS circuit.
Derive the expression for dynamic power dissipation. [8+8]
2. (a) Design a TTL three-state NAND gate and explain the operation with the help
of function table.
(b) Compute the maximum fan-out for the following cases.
i. 74LS driving 74F
ii. 74F driving 74AS
iii. 74AS driving 74LS
iv. 74AS driving 74F [8+8]
3. (a) Explain the various data types supported by VHDL. Give the necessary ex-
amples.
(b) Discuss the steps in VHDL design flow. [8+8]
4. Design a logic circuit to detect prime number of a 5-bit input. Write the structural
VHDL program for the same. [16]
5. Design a two-digit BCD adder with logic gates. Using this logic write the VHDL
program. In structural style of modeling. [8+8]
6. Write VHDL program for 8-bit comparator circuit. Using this entity write VHDL
program for 24-bit comparator. Show the additional logic used for this purpose use
structural style or modeling. [16]
7. (a) Define clock skew. Explain how clock skew leads to incorrect outputs in syn-
chronous circuits. Design one logic circuit that minimizes clock skew.
(b) Design an 8-bit universal parallel-in and serial out shift register with a control
input. Shift-left operation with control input 1 and shift-right operation with
control input 0 is to be performed. [8+8]
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8. (a) How many ROM bits are required to build a 16-bit adder/subtractor with
mode control, carry input, carry output and two’s complement overflow out-
put? Show the block schematic with all inputs and outputs?
(b) Explain the functional behavior of Static RAM cell. Show the internal struc-
ture of 8x4 static RAM and explain. [8+8]
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1. (a) Design a 4-input CMOS OR-AND-INVERT gate. Explain the circuit with the
help of logic diagram and function table?
(b) Explain the following terms with reference to CMOS logic.
i. Logic ‘0’ and Logic ‘1’
ii. Noise margin
iii. Power supply rails
iv. Propagation delay [10+6]
2. (a) Mention the DC noise margin levels of ECL 10K family.

(b) A single pull-up resistor to +5V is used to provide a constant-1 logic source
to 15 different 74LS00 inputs. What is the maximum value of this resistor?
How much high state DC noise margin can be provided in this case? [6+10]
3. (a) Write a VHDL Entity and Architecture for a 3-bit synchronous counter using
Flip-Flops.
(b) Explain the use of Packages. Give the syntax and structure of a package in
VHDL. [8+8]
4. (a) Design a logic circuit to detect prime number of a 4-bit input? Write the
VHDL program for the above design?
(b) Design the logic circuit and write a data-flow style VHDL program for the
following function? [8+8]
F (P ) = ΣA,B,C,D (1, 5, 6, 7, 9, 13) + d (4, 15)
5. Design a two-digit BCD adder with logic gates. Using this logic write the VHDL
program. In structural style of modeling. [8+8]
6. (a) Write a behavioral VHDL program to compare 16-bit signed and unsigned
integers.
(b) Design a priority encoder with 8 inputs? Write a VHDL program for the same
in structural style. [8+8]
7. Show the logic diagram of 74×175 IC and write VHDL program for this IC in data
flow style. Using this entity develop the program for 16-bit register and show the
corresponding circuit also explain how the register is cleared? [16]
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8. (a) Explain how a 4×4 binary multiplier can be designed using 256×8 ROM.
(b) How many ROM bits are required to build a 16-bit adder/subtractor with
mode control, carry input, carry output and two’s complement overflow out-
put? Show the block schematic with all inputs and outputs. [8+8]
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1. (a) Draw the logic diagram equivalent to the internal structure of CMOS 4-input
NAND gate. Explain the operation with the help of function table.
(b) Compare HC, HCT, VHC and VHCT CMOS logic families with the help of
input specifications and with VCC from 4.5V to 5.5V. [8+8]
2. (a) Draw the circuit diagram of basic CMOS gate and explain the operation.
(b) List out different categories of characteristics in a TTL data sheet. Discuss
electrical and switching characteristics of 74LS00. [8+8]
3. (a) Write a VHDL Entity and Architecture for the following function?
F(x) = a ⊕ b ⊕ c
Also draw the relevant logic diagram.

(b) Explain the use of Packages Give the syntax and structure of a package in
VHDL [8+8]
4. (a) Explain data-flow design elements of VHDL.

following function. [8+8]
F (X) = ΣA,B,C,D (1, 4, 5, 7, 12, 14, 15) + d (3, 11)
5. A mechanical disk rotates in a circle in different positions. Two successive positions

differ with an angle of 15o . Provide an encoding mechanism for every position of
the disk. The disk in the mechanical system outputs this encoded information to
detect the exact position. Design a decoder with an enable input to identify the
position of the disk. [16]
6. Design an 8×8 combinational multiplier. Determine the worst case propagation

delay. Write a VHDL data flow program for the same. [16]
7. (a) Design a switch debouncer circuit using 74×109 IC. Explain the operation
using timing diagram.
(b) Discuss the logic circuit of 74×377 register. Write a VHDL program for the
same in structural style. [8+8]
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8. (a) How many ROM bits are required to build a 16-bit adder/subtractor with
mode control, carry input, carry output and two?s complement overflow out-
put? Show the block schematic with all inputs and outputs?
(b) Design an 8×4 diode ROM using 74×138 for the following data starting from
the first location. [8+8]
B, 2, 4, F, A, D, F, E
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?????
1. (a) Explain how to estimate sinking current for low output and sourcing current
for high output of CMOS gate.
(b) Analyze the fall time of CMOS inverter output with RL = 100Ω, VL = 2.5V and CL =
10P F . Assume VL as stable state voltage. [8+8]
2. (a) Mention the DC noise margin levels of ECL 10K family.

(b) A single pull-up resistor to +5V is used to provide a constant-1 logic source
to 15 different 74LS00 inputs. What is the maximum value of this resistor?
How much high state DC noise margin can be provided in this case? [6+10]
3. (a) Write a VHDL Entity and Architecture for a 3-bit synchronous counter using
Flip-Flops.
(b) Explain the use of Packages. Give the syntax and structure of a package in
VHDL. [8+8]
4. (a) What is the importance of time dimension in VHDL and explain its function.
following function. [8+8]
F (X) = ΣA,B,C,D (0, 1, 3, 5, 14) + d (8, 15)
5. (a) Design a 32 to 1 multiplexer using four 74×151 multiplexers and 74X139

decoder.
(b) Realize the following expression using 74×151 IC [8+8]
f (Y ) = AB + BC + AC
6. A simple floating-point encoder converts 16-bit fixed-point data using four high
order bits beginning with MSB. Design the logic circuit and write VHDL data-flow
program. [16]
7. (a) What is the difference between ring counter and Johnson ring counter? Design
a self-correcting 4-bit, 4-state ring counter with a single circulating 0 using
74×194.
(b) Explain how serial data communication is possible using 74×166 as transmitter
and 74×164 as receiver. [8+8]
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8. (a) Determine the ROM size needed to realize the logic function performed by
74×153 and 74×139.
(b) Design an 8×8 diode ROM using 74×138 for the following data starting from
the first location. [8+8]
AB, 52, 74, 0F, CA, 9D, 2F, E6
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www.andhracolleges.

com The Complete Information About Colleges in Andhra Pradesh

Code No: V3121/R07 Set No. 1

1. (a) Design a CMOS transistor circuit with the functional behavior as

Also draw the relevant circuit diagram.

Seminar Topics - Scholarships - Admission/Entrance Exam Notifications

Code No: V3121/R07 Set No. 1

Code No: V3121/R07 Set No. 2

2. (a) Mention the DC noise margin levels of ECL 10K family.

F (P ) = ΣA,B,C,D (1, 5, 6, 7, 9, 13) + d (4, 15)

Code No: V3121/R07 Set No. 2

Code No: V3121/R07 Set No. 3

Also draw the relevant logic diagram.

4. (a) Explain data-flow design elements of VHDL.

F (X) = ΣA,B,C,D (1, 4, 5, 7, 12, 14, 15) + d (3, 11)

5. A mechanical disk rotates in a circle in different positions. Two successive positions

6. Design an 8×8 combinational multiplier. Determine the worst case propagation

Code No: V3121/R07 Set No. 3

Code No: V3121/R07 Set No. 4

2. (a) Mention the DC noise margin levels of ECL 10K family.

F (X) = ΣA,B,C,D (0, 1, 3, 5, 14) + d (8, 15)

5. (a) Design a 32 to 1 multiplexer using four 74×151 multiplexers and 74X139

Code No: V3121/R07 Set No. 4

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