Ece361 - Ee 2010 S1

CONFIDENTIAL EE/APR2010/ECE361
UNIVERSITI TEKNOLOGI MARA

FINAL EXAMINATION
COURSE DIGITAL SYSTEM II

COURSE CODE ECE361
EXAMINATION APRIL 2010
TIME 3 HOURS
INSTRUCTIONS TO CANDIDATES
1. This question paper consists of five (5) questions.
2. Answer ALL questions in the Answer Booklet. Start each answer on a new page.
3. Do not bring any material into the examination room unless permission is given by the
invigilator.
Please check to make sure that this examination pack consists of:
i) the Question Paper

ii) an Answer Booklet - provided by the Faculty
DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

This examination paper consists of 5 printed pages
© Hak Cipta Universiti Teknologi MARA CONFIDENTIAL
CONFIDENTIAL 2 EE/APR2010/ECE361
QUESTION 1
a) What is the main purpose of arithmetic/logic unit (ALU) and draw its basic
architecture.
(5 marks)
b) Indicate the maximum number of possible output for a 5-input decoder. Then draw
the logic symbol of an Active-High 3 to 8 decoder and complete Table 1 for this type
of decoder.
INPUT OUTPUT
100
110
Table 1
(3 marks)
c) Implement a full-adder using suitable decoder and OR gates. Make sure you show all
the required steps in your design.
(8 marks)
d) Explain 2 types of timing defects (hazards) in combinational logic circuits.

(4 marks)
QUESTION 2
a) Briefly explain the meaning of:
i) Random Access Memory

ii) Programmable Logic Devices
(4 marks)
b) A machine has a 10K bytes memory system. The memory system is built using the
following specifications:
2K bytes ROM beginning at address 2000H

8K bytes SRAM beginning at address 4000H
The connections pins of the SRAM and ROM used is shown in Figure Q2b(i) and
Figure Q2b(ii).
Based on the memory system that has been specified above:
i) Determine the number of chips needed for both SRAM and ROM.
ii) Determine the address range for SRAM and PROM,
iii) Draw a memory map for this memory system
iv) Design a schematic diagram of the memory system by using 3-to-8 decoders
and suitable logic gates (if required).

CONFIDENTIAL 3 EE/APR 2010/ECE361
iv) Design a schematic diagram of the memory system by using 3-to-8 decoders
and suitable logic gates (if required).
Address Data
lines lines
Figure Q2b(i)
Address Data
lines lines
Figure Q2b(ii)
(16 marks)
QUESTION 3
a) With the aid of diagrams, explain what is a synchronous and asynchronous

sequential circuit.
(4 marks)
b) Design a modulo-12 asynchronous counter by showing it's circuit, truth table,

counting sequence and timing diagram.
(16 marks)

QUESTION 4
a) State two (2) advantages of R/2R ladder DAC compared to binary weighted resistor
DAC.
(2 marks)
b) Design and draw a 4-bit binary-weighted resistor DAC with reference voltage,
VREF = 5V and resolution voltage = 1.0V. Clearly label all the main parts of this DAC.
Determine the value of all resistors for Rf = 2 k f l
(8 marks)
c) For an ADC clock frequency of 1 kHz, compute the full scale conversion time for 4-bit
Successive-Approximation , 4-bit digital ramp and 4-bit flash ADC.
(4 marks)
d) An 8-bit DAC produces an output voltage of 5.0V for an input code of 01100110,
what will the value of Vout be for an input code of 10101010. Then, find the full scale
voltage of the DAC.
(6 marks)
QUESTION 5
a) Mr Sven wishes to design a remote controller to change channels for his Dota
satellite TV system, which has only 4 channels. Help him to solve his problem by
illustrating the logic circuit for his project by using combinations of 2 to 1 MUXs.
Write down the Boolean expression of the circuit when Mr Sven switches to channel
1, 2 and 4. Assume that the TV system starts from channel 1.
(7 marks)
b) State the main difference between Ring and Twisted Ring /Johnson counter.
(4 marks)

c) Figure Q5c shows an incomplete and wrongly connected Twisted Ring / Johnson
counter. Analyze the circuit and redraw the correct circuit.
(5 marks)
A B C
SET SET SET

D Q D Q D Q
> > >
CLR Q CLR Q CLR Q
Figure Q5c
d) Digital systems are quickly replacing old analog ones. State four (4) advantages of
digital technologies based on what you have learned in this course.
(4 marks)
END OF QUESTION PAPER

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CONFIDENTIAL EE/APR2010/ECE361

UNIVERSITI TEKNOLOGI MARA

COURSE DIGITAL SYSTEM II

1. This question paper consists of five (5) questions.

i) the Question Paper

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

d) Explain 2 types of timing defects (hazards) in combinational logic circuits.

a) Briefly explain the meaning of:

i) Random Access Memory

2K bytes ROM beginning at address 2000H

Based on the memory system that has been specified above:

© Hak Cipta Universiti Teknologi MARA CONFIDENTIAL

a) With the aid of diagrams, explain what is a synchronous and asynchronous

b) Design a modulo-12 asynchronous counter by showing it's circuit, truth table,

© Hak Cipta Universiti Teknologi MARA CONFIDENTIAL

© Hak Cipta Universiti Teknologi MARA CONFIDENTIAL

SET SET SET

END OF QUESTION PAPER

© Hak Cipta Universiti Teknologi MARA CONFIDENTIAL

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