ADNS-9800

LaserStreamTM Gaming Sensor

Data Sheet

Description

Features

The ADNS-9800 LaserStream gaming sensor comprises

of sensor and VCSEL in a single chip-on-board (COB)
package. ADNS-9800 provides enhanced features like programmable frame rate, programmable resolution, configurable sleep and wake up time to suit various PC gamers
preferences.

x Small form factor chip-on-board package

The advanced class of VCSEL was engineered by Avago

Technologies to provide a laser diode with a single longitudinal and a single transverse mode.
This LaserStream gaming sensor is in 16-pin integrated
chip-on-board (COB) package. It is designed to be used
with ADNS-6190-002 small form factor (SFF) gaming laser
lens to achieve the optimum performance featured in this
document. These parts provide a complete and compact
navigation system without moving part and laser calibration process is NOT required in the complete mouse form,
thus facilitating high volume assembly.

Theory of Operation
The sensor is based on LaserStream technology, which
measures changes in position by optically acquiring
sequential surface images (frames) and mathematically
determining the direction and magnitude of movement.
It contains an Image Acquisition System (IAS), a Digital
Signal Processor (DSP), and a four wire serial port. The IAS
acquires microscopic surface images via the lens and illumination system. These images are processed by the
DSP to determine the direction and distance of motion.
The DSP calculates the 'x and 'y relative displacement
values. An external microcontroller reads the 'x and 'y
information from the sensor serial port. The microcontroller then translates the data into PS2, USB, or RF signals
before sending them to the host PC or game console.

x Dual power supply selections, 3 V or 5 V

x VDDIO range: 1.65 3.3 V
x 16-bits motion data registers
x High speed motion detection up to 150 ips and
acceleration up to 30 g
x Advanced technology 832-865 nm wavelength VCSEL
x Single mode lasing
x No laser power calibration needed
x Compliance to IEC/EN 60825-1 Eye Safety
Class 1 laser power output level
On-chip laser fault detect circuitry
x Self-adjusting frame rate for optimum performance
x Motion detect pin output
x Internal oscillator no external clock input needed
x Enhanced Programmability
Frame rate up to 12,000 fps
1 to 5 mm lift detection
Resolution up to 8200 cpi with ~200 cpi step
X and Y axes independent resolution setting
Register enabled Rest Modes
Sleep and wake up times

Applications
x Corded and cordless gaming laser mice
x Optical trackballs
x Motion input devices

CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.

Pinout of ADNS-9800 Optical Mouse Sensor

Pin No

Pin Name for 5 V mode

Pin Name for 3 V mode

Description

+VCSEL

+VCSEL

Positive Terminal Of VCSEL

LASER_NEN

LASER_NEN

LASER Enable (Active Low Output)

NCS

NCS

Chip Select (Active Low Input)

MISO

MISO

Serial Data Output (Master In/Slave Out)

SCLK

SCLK

Serial Clock Input

MOSI

MOSI

Serial Data Input (Master Out/Slave In)

MOTION

MOTION

Motion Detect (Active Low Output)

XYLASER

XYLASER

Laser Current Output Control

VDD5

VDD3

5 V input for 5 V mode

3 V Input for 3 V mode

10

PWR_OPT (GND)

PWR_OPT (VDD3)

Power Option:
Connect to GND for 5 V Mode
Connect to VDD3 for 3 V Mode

11

GND

GND

Analog Ground

12

REFB

VDD3

3 V Regulator Output for 5 V Mode

3 V Input for 3 V Mode

13

REFA

REFA

1.8 V Regulator Output

14

DGND

DGND

Digital Ground

15

VDDIO

VDDIO

IO Voltage Input (1.65 3.3 V)

16

-VCSEL

-VCSEL

Negative Terminal Of VCSEL

16

15

14

13

12

11

10

Product Code
Date Code
Lot Code

Item

Marking

Remarks

Product Number

A9800

Date Code

XYYWWZV

X = Subcon Code
YYWW = Date Code
Z = Sensor Die Source
V = VCSEL Die Source

Lot Code

VVV

Numeric

Figure 1. Pinout of ADNS-9800 Optical Mouse Sensor

2

Figure 2. Package outline drawing

Overview of Laser Mouse Sensor Assembly

Section B-B
2.40
0.094 Top of PCB to Surface
7.40
0.291 Bottom of lens flange to Surface
10.75 Top of Sensor to Surface
0.423

Note: Dimensions in millimeters/inches and for reference only.

Figure 3. 2D Assembly drawing of ADNS-9800 sensor and ADNS-6190-002 lens coupled with PCB and base plate

Figure 4. Isometric drawing of ADNS-9800 sensor and ADNS-6190-002 lens

12.96

5.02
Pin #1

Optical Center

14 X 1.78

12.60

10.90

6.30

1.70

0.50

16 X 0.80

Figure 5. Recommended PCB mechanical cutouts and spacing

Assembly Recommendation
1. Insert the COB sensor and all other electrical components into the application PCB.
2. This sensor package is only qualified for wave-solder
process.
3. Wave-solder the entire assembly in a no-wash soldering
process utilizing a solder fixture. The solder fixture is
needed to protect the sensor during the solder process.
The fixture should be designed to expose the sensor
leads to solder while shielding the optical aperture
from direct solder contact.
4. Place the lens onto the base plate. Care must be taken
to avoid contamination on the optical surfaces.
5. Remove the protective kapton tapes from the optical
aperture of the sensor and VCSEL respectively. Care
must be taken to keep contaminants from entering the
aperture.

6. Insert the PCB assembly over the lens onto the base
plate. The sensor package should self-align to the lens.
The optical position reference for the PCB is set by the
base plate and lens. The alignment guide post of the
lens locks the lens and integrated molded lead-frame
DIP sensor together. Note that the PCB motion due to
button presses must be minimized to maintain optical
alignment.
7. Optional: The lens can be permanently locked to the
sensor package by melting the lens guide posts over
the sensor with heat staking process.
8. Install the mouse top case. There must be a feature in
the top case (or other area) to press down onto the
sensor to ensure the sensor and lenses are interlocked
to the correct vertical height.

9%86
'
'
*1'
6+,(/'







R1
1k

HEADER 5

H1







R6
10R

CON1

20R
20R

1R

R2







C4
1uF/10V

-7$*

C5
100nF

R7
1k

9''

PIN HEADER 2.54MM10P/D

9''

R5
10R

R3
R4

C2
10nF

J1

C3
20pF

9&&

C10
1uF/10V

R10
1k

C11
20pF

C9
100nF

9&&

Figure 6a. Schematic Diagram for 5 V Corded Mouse

&

5
:
*
%

9&&







RIGHT
ZA

0&8

3
3

3
3
3
3
3
3

36&/.
30,62
3026,
31&6
3
3
3
3
3
3
3
3
3
3

&RQQHFWWR3&%

PCB SOCKET 2MM8P/D

9''

C8
100nF

CON2

&&.567
3&'

3
3

95(*,1
9%86
'
'

U1

LEFT

MIDDLE 
ZB













C7
4.7uF/10V

9''


























P1

&3,

D1
R12

C12
100nF

-CPI 
P3

P2

966

&3,

-XPSZLUHWR3&%

LED1
LED2
LED3

YELLOW

YELLOW
D3

YELLOW
D2

470R

R14

470R

R13






RIGHT
ZA

/HIW&OLFN

PIN HEADER 2MM8P/D

CON3

C1
100nF

SW1

&RQQHFWWR3&%

LEFT

MIDDLE 
ZB


LEFT

R8
10k

9''

&3,,QGLFDWLRQ/('

LED3

LED2

470R

9&&

LED1






ZB
ZA
LEFT
RIGHT
MIDDLE
+CPI
-CPI

+CPI 

9&&
:3
+2/'
966

((3520

25LC040P

&6
6&.
6,
62

U2

9''

SCLK
MISO
MOSI
NCS
MOTION






100k

R11

SCLK
MISO
MOSI
NCS
MOTION








1R

R15

J2


9&6(/9(
9&6(/9(
;</$6(5
9'',2
9''9''

9''

RIGHT

C6
100nF

SW2

ZB
ZA

100nF

C18

470pF

C15

9''

9&&





&20
%
$

Q1

SW3

100nF




100nF

C21

P6

P5

P4

-CPI

+CPI
SW4

&3,

SW5

&3,

3.3uF/16V

C20

-XPS:LUHWR3&%

966

&3,

&3,

10uF/10V

C23

4.7uF/10V

C19

C22
100nF

9''

9''

9''

C16

J4

J3

9''

C14
1uF/10V

1) USB Connector as near as possible to MCU

2) Capacitors trace length must be <5mm
3) 470pF capacitor should be placed at the center
top above A9800

Notes:
<<PCB Design Consideration>>

0LGGOH&OLFN

C24 
100nF

MIDDLE

R16
10k

9''

9''

9''

C13
10nF

9&&

6HQVRU%ORFN

=(QFRGHU

5LJKW&OLFN

R9
10k

9''

9''

C17












NTA4151P

Q2

10uF/10V

3:5B237

/$6(5B1(1
6&/.
0,62
026,
ADNS-9800
1&6
5()$
027,21
9''5()%

U3

9''

9''




'

Application Circuits

'*1'



9''

C8051F347
*1'


*1'


PAD2

P1




SW1
 SLIDE SW SPDT

[$$%DWWHU\%ORFN

%

BT2
BATTERY

BT1
BATTERY

2))

R1
180k

R2
820k

3RZHU6XSSO\%ORFN

9287
)%

6:

NOTE:
2AA Battery 1.5V connected in series

%

21




9%$7

C2
4.7uF/4V

9%$7
(1

U1
TPS61070

C3
4.7uF/4V

C4
4.7uF/4V




,UHJ

C5
10uF/6.3V

PAD2

P2

9''

Figure 6b. Schematic Diagram for 3 V Cordless Mouse

,V\V

C1
4.7uF/4V




*1'










C6
10uF/6.3V

P3

C18
1uF/6.3V

6HQVRU%ORFN

ADNS-9800

9&6(/
9'',2
'*1'
5()$
9''
*1'
3:5B237
9''

470pF

C8

9&6(/
/65B1(1
1&6
0,62
6&/.
026,
027,21
;<B/65

U3

C9
100nF
9''












C10
100nF

,VHQVRU
Q2
PAD2
NTA4151P

9''

SW2

C12
100nF

C11
100nF

0LGGOH&OLFN

9''

SW3

/HIW&OLFN

R4
1K

9''

%XWWRQV%ORFN

C7
10uF/6.3V

C19
3.3uF/4V

D1
LED_BLUE

R3
1K

9''

$
%
&20

P6
PAD3

SW4

PUSH BUTTON

SW?

5HVROXWLRQ&KDQJH





9''

52))521 ',6$%/(

52152)) (1$%/(

%$77(5</(9(/'(7(&7,21

127(6

R?
47k

9''

R11 R12
27K 27K

R?
0R

MMBT2222A

Q3




R9
60R4

R10
OPEN

9%$7

9''

=(QFRGHU%ORFN

Q1

P4
PAD2

PAD2

R6
0R

9''

P5

5LJKW&OLFN

R5
499R

D2
LED_YELLOW

/(',QGLFDWRU%ORFN

NOTE:
R2 = 820k ; VDD = 2.8V
R2 = 910k ; VDD = 3.0V
R2 = 1M ; VDD = 3.3V










R7
0R

C14
100nF

TI_CC2510





SW?

SW?

6KHHW 

RI

5HYLVLRQ 
-DQ

U2

X?


C16
100nF

C?
22pF

26MHz

Horizontal Scroll (Switch)

C?
22pF

R?

$IILQH[,QQRYDWLRQ6GQ%KG
7DPDQ3HULQGXVWULDQ%D\DQ/HSDV

/RWQG)ORRU3HVDUD.J-DZD

ZZZ DIILQH[ FRP P\

,1129$7,21

AFFINEX

1pF

1.2nH

L?

100pF
L?
12nH

C?
1pF

56K

C?




C?

100pF

C?

C17
100nF

PAD2

C?
1.8pF

0R
1.2nH

*+]6LQJOH(QGHG$QWHQQD%ORFN

R?

L?
C?
1.5pF

R?
0R

AT?
ANTENNA

2))

%/,1.,1*216(&2))6(&

/2:%$79

Horizontal Scroll (Switch)



















2))

%/,1.,1*216(&2))6(&

/2:%$79

C21
22nF

216(&

216(&

&3,

C20
22nF

2))

216(&

&3,

9''

2))

2))

&3,'()$8/7

P?

216(&

2))

&3,

,PFX

/('3B

/('3B

,1',&$7,21

/(',1',&$7,217$%/(

+RUL]RQWDO6FUROO6ZLWFK%ORFN

$9''

;26&B4

;26&B4

$9''

5)B3

5)B1

$9''

$9''

5%,$6

C15
100nF

'DWH 

7LPH  



3URMHFW1R

7LWOH

R8
0R

9''



&(17(5B3$'

86(-803(5:,5(

127(6

J2

J1

3B

3B

3B

3B

3B

3B

3B

'9''

3B

C13
100nF

9%$7

J?

9''

PCB_SOCKET_2X5P









L1
4.7uH




F
H







3B
'9''


3B


3B
3B


3B





3B
3B


62&'HEXJ)ODVK%ORFN



3B
3B


5(6(7B1
3B


'&283/
3B


*8$5'

$9''B'5(*
3B;62&B4


3B;26&B4


9%$7



Design Considerations for Improving ESD Performance

ADNS-9800

Power and control

GND
VDD 3/REFB
REFA
VDDIO

Serial Port and Register

VDD 5/VDD 3

Image

Oscalator

NCS
SCLK
MOSI
MISO
MOTION

DGND
PWR_OPT

-VCSEL

LASER Drive

XYLASER
LASER_NEN

VCSEL

+VCSEL

Figure 7. Block diagram of ADNS-9800

Regulatory Requirements
x Passes FCC B and worldwide analogous emission limits
when assembled into a mouse with shielded cable and
following Avago recommendations.
x Passes IEC-1000-4-3 radiated susceptibility level when
assembled into a mouse with shielded cable and
following Avago recommendations.
x Passes EN61000-4-4/IEC801-4 EFT tests when assembled
into a mouse with shielded cable and following Avago
recommendations.
x Provides sufficient ESD creepage/clearance distance to
withstand discharge up to 15 KV when assembled into
a mouse according to usage instructions above.
x Passes IEC/EN 60825-1 Eye Safety Class 1 when
operating with the laser output power pre-calibrated
by Avago Technologies without external hardware and
software control of laser current.
Parameter

Symbol

Laser
output
power

LOP

Min.

Max.

Units Notes

716

PW

Class 1 limit with

ADNS-6190-002
lens.

For improved electrostatic discharge performance, typical

creepage and clearance distance are shown in the table
below. Assumption: base plate construction as per the
Avago supplied 3D model file when use with ADNS-6190002 lens. The lens flange can be sealed (i.e. glued) to the
base plate. Note that the lens material is polycarbonate
and therefore, cyanoacrylate based adhesives or other
adhesives that may damage the lens should NOT be used.
Clearance
Typical Distance (mm)
Creepage

1.8
ADNS-6190-002
17.3

Eye Safety
The ADNS-9800 sensor and the associated components in
the schematics of Figure 6 are intended to comply with
Class 1 Eye Safety Requirements of IEC 60825-1. Avago
Technologies calibrates the sensors laser output power
(LOP) to Class 1 eye safety level and store the registers
values that control the LOP prior shipping out, thus no
LOP calibration is required in complete mouse system at
manufacturer site.
ADNS-9800 sensor is designed to maintain the laser
output power using ADNS-6190-002 lens within Class 1
Eye Safety requirements over components manufacturing tolerances under the recommended operating conditions and application circuits of Figure 6 as specified in
this document. Under normal operating conditions, the
sensor generates the drive current for the VCSEL. Increasing the LOP by other means on hardware and software
can result in a violation of the Class 1 eye safety limit of
716 PW. For more information, please refer to Eye Safety
Application Note.

LASER Drive Mode

The laser is driven in pulsed mode during normal operation.
A calibration mode is provided which drives the laser in
continuous (CW) operation for testing purpose.
The default setting of laser is in Forced_Disable mode,
which the laser is turned OFF. The laser have to be turned
ON during power up sequence by setting Forced_ Disabled
bit (Bit-0) of LASER_CTRL0 register to 0.

Disabling the LASER

LASER_NEN is connected to the gate of an external
P-channel MOSFET transistor which, when ON connects
REFB to the laser. In normal operation, LASER_NEN is low.
In the case of a fault condition, LASER_NEN goes high to
turn the transistor off and disconnect REFB from the laser.

LASER Output Power (LOP)

Single Fault Detection

The LOP can be measured for testing purpose as per steps

below.

ADNS-9800 sensor is able to detect a short circuit or fault

condition at VCSEL pin, which could lead to excessive
laser output power. A leakage path to ground on this
node will trigger the fault detection circuit, which will turn
off the laser drive current source and set the LASER_NEN
output high. When used in combination with external
component as shown in the block diagram below, the
system will prevent excessive laser power for a resistive
path at XY_LASER by shutting off the laser. In addition
to the ground path fault detection described above, the
fault detection circuit is periodically checking for proper
operation by internally generating a path to ground with
the laser turned off via LASER_NEN. If the VCSEL pin is
shorted to VDD5, VDD3, REFA or REFB pin, this test will fail
and will be reported as a fault.

1. Power up reset the mouse system.

2. Enable the laser by setting Forced_Disabled bit of
LASER_CTRL0 register (address 0x20) to 0.
3. Enable the Calibration mode by writing 010b to bits
[3,2,1] of LASER_CTRL0 register (address 0x20) to set
the laser to continuous (CW) mode.
4. Measure the LOP at the navigation surface plane.
The pre-calibrated LOP value at typical operating supply
voltage and temperature of 25 5 C should not exceeding
506 PW, otherwise the LOPmax limit in the Absolute
Maximum Rating is applicable. The following conditions
apply:
x The system is operated within the recommended
operating supply voltage and temperature range.
x In 3 V mode, the VDD3 value is no greater than 300 mV
above its value at the time of adjustment. In 5 V mode,
REFB should be used to drive the PMOSFET connecting
to VCSEL.
x No allowance for optical power meter accuracy is
assumed.

VDD 3 / REFB
(Pin 12)
Microcontroller

ADNS-9800
S
LASER DRIVER

LASER_NEN

P_MOSFET

VDD 3
D
fault control
block

VCSEL

Serial port

+VCSEL

voltage sense

470 pF
current set

-VCSEL

GND

Figure 8. Single Fault Detection and Eye-safety Feature Block Diagram

Absolute Maximum Ratings

Parameter

Symbol

Minimum

Maximum

Units

Storage Temperature

TS

-40

85

255

Lead-Free Solder Temp

Supply Voltage

VDD5

-0.5

5.5

VDD3

-0.5

3.4

VDDIO

-0.5

3.4

kV

ESD (Human body model)

-0.5

Notes
For 10 seconds, 1.8 mm below seating plane.
See soldering reflow profile in Figure 9.

All Pins

Input Voltage

VIN

VDDIO+ 0.5

All I/O Pins

Laser Output Power

LOPmax

716

PW

Class 1 Eye Safety Limit

VCSEL DC Forward Current

IF

mA

For maximum duration of 240 hrs

Applicable when driving VCSEL externally and
internally using sensors laser registers setting
Refer to reliability datasheet

VCSEL Reverse Voltage

VR

I = 10 PA

Notes:
1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are the stress ratings
only and functional operation of the device at these or any other condition beyond those indicated for extended period of time may affect device
reliability.
2. The inherent design of this component causes it to be sensitive to electrostatic discharge. The ESD threshold is listed above. To prevent ESDinduced damage, take adequate ESD precautions when handling this product.

Recommended Operating Conditions

Parameter

Symbol

Minimum Typical

Maximum

Units

Operating Temperature

TA

40

Supply voltage

Power supply rise time

Notes

VDD5

4.0

5.0

5.25

Volts

Including Supply Noise for 5 V mode

VDD3

2.7

2.8

3.3

Volts

Including Supply Noise for 3 V mode

VDDIO

1.65

3.3

Volts

Including noise.

VRT5

100

ms

0 to 5.0 V for 5 V mode

VRT3

100

ms

0 to 2.8 V for 3 V mode

100

mVp-p

50 kHz 50 MHz

MHz

Active drive, 50% duty cycle

2.62

mm

Results in +/- 0.22 mm minimum DOF.

Refer to Figure 10.

150

ips

inch/sec

Supply noise (Sinusoidal)

VNA

Serial Port Clock Frequency

fSCLK

Distance from lens reference

plane to surface

Speed

2.18

2.40

Acceleration

30

In Run mode only

Load Capacitance

Cout

100

pF

MOTION, MISO

Frame Rate

FR

12,000

fps

Frame per second

VCSEL Peak Wavelength

865

nm

Laser Output Power

LOP

506

PW

832

Z
Figure 9. Distance from lens reference plane to surface, Z
10

Operating LOP when assembled with

ADNS-6190-002 lens and internally
driven by the sensor

AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. (Typical values at 25 C, VDD3 = 2.8 V, VDDIO = 1.8 V)
Parameter

Symbol

Minimum

Motion delay after reset

tMOT-RST

30

Shutdown

tSTDWN

Wake from shutdown

tWAKEUP

Forced Rest enable

tREST-EN

Wake from Forced Rest

tREST-DIS

MISO rise time

tr-MISO

MISO fall time

tf-MISO

MISO delay after SCLK

tDLY-MISO

MISO hold time

thold-MISO

MOSI hold time

Typical

Maximum

Units Notes
ms

From SW_RESET register write to valid

motion, assuming motion is present

ms

From Shutdown mode active to low

current

ms

From Shutdown mode inactive to

valid motion. Notes: A RESET must be
asserted after a shutdown. Refer to
Shutdown section, also note tMOT-RST

From RESTEN bits set to low current

From RESTEN bits cleared to valid

motion

50

200

ns

CL = 100 pF

50

200

ns

CL = 100 pF

120

ns

From SCLK falling edge to MISO data

valid, no load conditions

200

ns

Data held until next falling SCLK edge

thold-MOSI

200

ns

Amount of time data is valid after SCLK

rising edge

MOSI setup time

tsetup-MOSI

120

ns

From data valid to SCLK rising edge

SPI time between write

commands

tSWW

120

Ps

From rising SCLK for last bit of the first

data byte, to rising SCLK for last bit of
the second data byte.

SPI time between write

and read commands

tSWR

120

Ps

From rising SCLK for last bit of the first

data byte, to rising SCLK for last bit of
the second address byte.

SPI time between read

and subsequent commands

tSRW
tSRR

20

Ps

From rising SCLK for last bit of the first

data byte, to falling SCLK for the first
bit of the address byte of the next
command.

SPI read address-data delay

tSRAD

100

Ps

From rising SCLK for last bit of the

address byte, to falling SCLK for first
bit of data being read.

NCS inactive after motion

burst

tBEXIT

500

ns

Minimum NCS inactive time after

motion burst before next SPI usage

NCS to SCLK active

tNCS-SCLK

120

ns

From last NCS falling edge to first SCLK

rising edge

SCLK to NCS inactive

(for read operation)

tSCLK-NCS

120

ns

From last SCLK rising edge to NCS

rising edge, for valid MISO data transfer

SCLK to NCS inactive

(for write operation)

tSCLK-NCS

20

Ps

From last SCLK rising edge to NCS

rising edge, for valid MOSI data transfer

NCS to MISO high-Z

tNCS-MISO

500

ns

From NCS rising edge to MISO

high-Z state

MOTION rise time

tr-MOTION

50

200

ns

CL = 100 pF

MOTION fall time

tf-MOTION

50

200

ns

CL = 100 pF

Transient Supply Current

IDDT5

85

mA

Max supply current during a VDD5 ramps

from 0 to 5.0 V

IDDT3

65

mA

Max supply current during a VDD3 ramps

from 0 to 2.8 V

11

500
30

DC Electrical Specifications
Electrical Characteristics over recommended operating conditions.
For 3 V mode, Typical values at 25 C, VDD = 2.8 V, VDDIO = 2.8 V. For 5 V mode, Typical values at 25 C, VDD = 5.0 V,
VDDIO = REFB
Parameter

Symbol

Typical

Maximum

Units

Notes

DC Supply Current with

Variable Frame Rate SROM
& in 3 V mode

IDD_RUN3_LOW

Minimum

18

20

mA

IDD_RUN3_MED

24.5

27.5

mA

IDD_RUN3_HIGH

33

45

mA

Average current, including

LASER current. No load on
MISO, MOTION.

IDD_REST1

0.26

0.4

mA

IDD_REST2

0.12

0.2

mA

IDD_REST3

0.08

0.15

mA

DC Supply Current in 3 V mode

IDD_RUN3

33

45

mA

DC Supply Current in 5 V mode

IDD_RUN5

36

50

mA

Peak Supply Current

IDDP3

60

mA

65

mA

For 5 V mode

45

85

mA

NCS, SCLK, MOSI = VDDIO

MISO = GND

3.05

3.25

Do not connect this pin as a

supply to other chips other than
the integrated VCSEL and VDDIO

0.3*VDDIO

SCLK, MOSI, NCS

SCLK, MOSI, NCS

mV

SCLK, MOSI, NCS

10

mA

Vin = 0.7*VDDIO, SCLK,

MOSI, NCS

0.3*VDDIO

Iout = 1 mA, MISO, MOTION

Iout = -1 mA, MISO, MOTION

0.3*VREFB

Iout = 1 mA, LASER_NEN

Iout = -0.5mA, LASER_NEN

10

pF

MOSI, NCS, SCLK

IDDP5
Shutdown Supply Current

IDDSTDWN

REFB Output Voltage

VREFB

Input Low Voltage

VIL

Input High Voltage

VIH

Input Hysteresis

VI_HYS

100

Input Leakage Current

Ileak

Output Low Voltage,

MISO, MOTION

VOL

Output High Voltage,

MISO, MOTION

VOH

Output Low Voltage, LASER_NEN

VOL

Output High Voltage, LASER_NEN

VOH

Input Capacitance

Cin

12

2.85

For 3 V mode

0.7*VDDIO

0.7*VDDIO

0.7*VREFB

Resolution (cpi)

Sensors Typical Performance Characteristics

Resolution Vs. Z
Straight Line At 45 Degrees, Path Length = 4 inches; Speed = 6 ips ; Resolution = 1600 cpi

1800
1600
1400
1200
1000
800
600
400
200
0

White Paper
Photo Paper
Manila
Spruce Wood
Black Formica
White Formica
White Delrin

1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4
Distance from Lens Reference Plane to Navigation Surface, Z (mm)
Figure 10. Mean Resolution vs. Z at default resolution at 1600 cpi

Typical Path Deviation

Largest Single Perpendicular Deviation From A Straight Line At 45 Degrees
Path Length = 4 inches; Speed = 6 ips; Resolution = 1600 cpi
Maximum Distance (Mouse Counts)

30

White Paper
Photo Paper
Manila
Spruce Wood
Black Formica
White Formica
White Delrin

25
20
15
10
5
0
1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4
Distance from Lens Reference Plane to Navigation Surface, Z (mm)

Relative Responsivity

Figure 11. Average Error vs. Distance at default resolution at 1600 cpi (mm)

Relative Responsivity Vs. Wavelength

1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
400

450

500

550

Figure 12. Wavelength Responsivity

13

600

650 700 750

Wavelength (nm)

800

850

900

950

1000

Synchronous Serial Port

Motion Pin

The synchronous serial port is used to set and read parameters in the ADNS-9800 Sensor, and to read out the motion
information. The serial port is also used to load PROM data
into the ADNS-9800 Sensor.

The motion pin is an active low output that signals the

micro-controller when motion has occurred. The motion
pin is lowered whenever the motion bit is set; in other
words, whenever there is data in the Delta_X_L, Delta_XH,
Delta_Y_L or Delta_Y_H registers. Clearing the motion
bit (by reading Delta_X_L, Delta_XH, Delta_Y_L and
Delta_Y_H, or writing to the Motion register) will put the
motion pin high.

The port is a four wire port. The host micro-controller

always initiates communication; the ADNS-9800 Sensor
never initiates data transfers. SCLK, MOSI, and NCS may be
driven directly by a micro-controller. The port pins may be
shared with other SPI slave devices. When the NCS pin is
high, the inputs are ignored and the output is tri-stated.
The lines that comprise the SPI port are:

SCLK : Clock input. It is always generated by the master

(the micro-controller).

MOSI : Input data. (Master Out/Slave In)

MISO : Output data. (Master In/Slave Out)
NCS : Chip select input (active low). NCS needs to be low to
activate the serial port; otherwise, MISO will be high
Z, and MOSI & SCLK will be ignored. NCS can also be
used to reset the serial port in case of an error.

14

Chip Select Operation

The serial port is activated after NCS goes low. If NCS is
raised during a transaction, the entire transaction is
aborted and the serial port will be reset. This is true for all
transactions including PROM download. After a transaction is aborted, the normal address-to-data or transactionto-transaction delay is still required before beginning the
next transaction. To improve communication reliability,
all serial transactions should be framed by NCS. In other
words, the port should not remain enabled during periods
of non-use because ESD and EFT/B events could be interpreted as serial communication and put the chip into an
unknown state. In addition, NCS must be raised after each
burst-mode transaction is complete to terminate burstmode. The port is not available for further use until burstmode is terminated.

Write Operation
Write operation, defined as data going from the micro-controller to the ADNS-9800 Sensor, is always initiated by the
micro-controller and consists of two bytes. The first byte contains the address (seven bits) and has a 1 as its MSB to
indicate data direction. The second byte contains the data. The ADNS-9800 Sensor reads MOSI on rising edges of SCLK.
NCS
1

10

11

12

13

14

15

16

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

A6

SCLK
MOSI
MISO

MOSI Driven by Micro-Controller

Figure 13. Write Operation

SCLK

MOSI
tHold, MOSI
tsetup, MOSI
Figure 14. MOSI Setup and Hold Time

Read Operation
A read operation, defined as data going from the ADNS-9800 Sensor to the micro-controller, is always initiated by the
micro-controller and consists of two bytes. The first byte contains the address, is sent by the micro-controller over MOSI,
and has a 0 as its MSB to indicate data direction. The second byte contains the data and is driven by the ADNS-9800
Sensor over MISO. The sensor outputs MISO bits on falling edges of SCLK and samples MOSI bits on every rising edge of
SCLK.
NCS
SCLK
Cycle #

A6

A5

A4

A3

A2

A1

10

11

12

13

14

15

16

D7

D6

D5

D4

D3

D2

D1

D0

SCLK
MOSI
MISO

A0

tSRAD delay

Figure 15. Read Operation

SCLK
tHOLD-MISO

tDLY-MISO
MISO

D0

Figure 16. MISO Delay and Hold Time

15

NOTE: The minimum high state of SCLK is also the minimum MISO data hold time of the
ADNS-9800 Sensor. Since the falling edge of SCLK is actually the start of the next read or
write command, the ADNS-9800 Sensor will hold the state of data on MISO until the falling
edge of SCLK.

Required timing between Read and Write Commands (tsxx)

There are minimum timing requirements between read and write commands on the serial port.
tSWW

SCLK
Address

Data

Address

Write Operation

Data
Write Operation

Figure 17. Timing between two write commands

If the rising edge of the SCLK for the last data bit of the second write command occurs before the tsww delay, then the
first write command may not complete correctly.
tSWR
t
t
t

SCLK
Address

Data

Address
t
t
t

Write Operation

Next Read Operation

Figure 18. Timing between write and read commands

If the rising edge of SCLK for the last address bit of the read command occurs before the tswr required delay, the write
command may not complete correctly.
tSRW & tSRR

tSRAD for read

t
t
t

SCLK
Address

Data

Address
t
t
t

Read Operation

Next Read or
Write Operation

Figure 19. Timing between read and either write or subsequent read commands

During a read operation SCLK should be delayed at least tSRAD after the last address data bit to ensure that the Sensor
has time to prepare the requested data.
The falling edge of SCLK for the first address bit of either the read or write command must be at least TSRR or TSRW after
the last SCLK rising edge of the last data bit of the previous read operation. In addition, during a read operation SCLK
should be delayed after the last address data bit to ensure that the ADNS-9800 Sensor has time to prepare the requested
data.

16

Burst Mode Operation

Burst mode is a special serial port operation mode which may be used to reduce the serial transaction time for three
predefined operations: motion read, PROM download and frame capture. The speed improvement is achieved by continuous data clocking to or from multiple registers without the need to specify the register address, and by not requiring
the normal delay period between data bytes.

Motion Burst Read

Reading the Motion_Burst register activates this mode. The ADNS-9800 sensor will respond with the contents of the
Motion, Observation, Delta_X_L, Delta_X_H, Delta_Y_L, Delta_Y_H, Pixel Statistic, Shutter and Frame period registers in
that order. After sending the register address, the micro-controller must wait one frame, and then begin reading data.
All data bits can be read with no delay between bytes by driving SCLK at the normal rate. The data are latched into the
output buffer after the last address bit is received. After the burst transmission is complete, the micro-controller must
raise the NCS line for at least tBEXIT to terminate burst mode. The serial port is not available for use until it is reset with
NCS, even for a second burst transmission.
tSRAD
t
t
t

SCLK
Motion_Burst Register Address

Read First Byte

t
t
t

First Read Operation

Read Second Byte

Read Third Byte

Figure 20. Motion Burst Timing

Procedure to start motion burst:

1. Lower NCS
2. Write 0x50 to Motion_Burst register.
3. Wait for one frame. (This only applicable in Run mode for wakeup but not require for rest mode)
4. Start reading SPI Data continuously up to 14bytes. Motion burst may be terminated by pulling NCS high for at least
tBEXIT.
5. To read new motion burst data, repeating from step 1.
6. Write any value to Motion register (address 0x02) to clear any residual motion.
Motion burst reporting:
BYTE [00] = Motion

BYTE [07] = Pixel_Sum

BYTE [01] = Observation

BYTE [08] = Maximum_Pixel

BYTE [02] = Delta_X_L

BYTE [09] = Minimum_Pixel

BYTE [03] = Delta_X_H

BYTE [10] = Shutter_Upper

BYTE [04] = Delta_Y_L

BYTE [11] = Shutter_Lower

BYTE [05] = Delta_Y_H

BYTE [12] = Frame_Period_Upper

BYTE [06] = SQUAL

BYTE [13] = Frame_Period_Lower

Note: In rest mode, motion burst data is always available or in other words, motion burst data can be read from Motion_Burst register even in rest
modes.

17

SROM Download
This function is used to load the Avago supplied firmware file contents into the ADNS-9800 after sensor power up
sequence. The firmware file is an ASCII text file. There are 2 methods of SROM downloading in ADNS-9800: 1.5 K and
3 K bytes. 1.5 K SROM download will only download 1.5 K bytes data into the first half of SROM and leave the rest empty,
while 3 K SROM download will download the full 3 K bytes data into SROM. They can be selected through Configuration_IV register, where default setting is 1.5 K SROM download. In the current version of ADNS-9800 sensor, 3 K bytes of
SROM will be used.
SROM download procedure:
1. Select the 3 K bytes SROM size at Configuration_IV register, address 0x39
2. Write 0x1d to SROM_Enable register for initializing
3. Wait for one frame
4. Write 0x18 to SROM_Enable register again to start SROM downloading
5. Write SROM file into SROM_Load_Burst register, 1st data must start with SROM_Load_Burst register address. All the
SROM data must be downloaded before SROM start running.
exit burst mode
tBEXIT 1 Ms
NCS
2 reg writes, see text

SROM_Enable reg write

address key data

MOSI

SROM_Load reg write

byte 1
address

1 frame
period

byte 2

byte 3070

address

enter burst
mode

SCLK
tNCS-SCLK
>120 ns

10 Ms
120 Ms

15 Ms

15 Ms
160 Ms
Soonest to read SROM_ID

Figure 21. SROM Download Burst Mode

Frame Capture
This is a fast way to download a full array of pixel values from a single frame. This mode disables navigation and overwrites any downloaded firmware. A hardware reset is required to restore navigation, and the SROM firmware must be
reloaded.
To trigger the capture, write to the Frame_Capture register. The next available complete 1 frame image will be stored to
memory. The data are retrieved by reading the Pixel_Burst register once using the normal read method, after which the
remaining bytes are clocked out by driving SCLK at the normal rate. If the Pixel_Burst register is read before the data is
ready, it will return all zeros.
Procedure of Frame Capture:
1. Reset the chip by writing 0x5a to Power_Up_Reset register (address 0x3a).
2. Enable laser by setting Forced_Disable bit (Bit-7) of LASER_CTRL) register to 0.
3. Write 0x93 to Frame_Capture register.
4. Write 0xc5 to Frame_Capture register.
5. Wait for two frames.
6. Check for first pixel by reading bit zero of Motion register. If = 1, first pixel is available.
7. Continue read from Pixel_Burst register until all 900 pixels are transferred.
8. Continue step 3-7 to capture another frame.
Note: Manual reset and SROM download are needed after frame capture to restore navigation for motion reading.

18

exit burst mode

tBEXIT 4 Ms
NCS
2 reg write to enter
frame capture mode
address
data

MOSI

frame capture reg

address

pixel dump reg read

address

100 Ms

soonest to begin again

enter burst
mode
SCLK
Wait for
2 frames

tNCS-SCLK
>120 ns

tLOAD
15 Ms

tSRAD

MISO

P1

P900

P2

Figure 22. Frame Capture Burst Mode

Cable
Top Xray View of Mouse

Positive Y
LB

RB
Positive X
1

A9800

16

expanded view of the

surface as viewed
through the lens

last output
29

59

89 119 149 179 209 239 269 299 329 359 389 419 449 479 509 539 569 599 629 659 689 719 749 779 809 839 869 899

28

58

88 118 148 178 208 238 268 298 328 358 388 418 448 478 508 538 568 598 628 658 688 718 748 778 808 838 868 898

27

57

31

61

91 121 151 181 211 241 271 301 331 361 391 421 451 481 511 541 571 601 631 661 691 721 751 781 811 841 871

30

60

90 120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720 750 780 810 840 870

t
etc.

rst output

Figure 23. Pixel Map (Surface referenced)

19

842 872

Power Up
The ADNS-9800 Sensor does not perform an internal power up self-reset; the Power_Up_Reset register must be written
every time power is applied. The appropriate sequence is as follows:
1. Apply power to VDD5/VDD3 and VDDIO in any order
2. Drive NCS high, and then low to reset the SPI port.
3. Write 0x5a to Power_Up_Reset register (address 0x3a).
4. Wait for at least 50ms time.
5. Read from registers 0x02, 0x03, 0x04, 0x05 and 0x06 (or read these same 5 bytes from burst motion register) one time
regardless of the motion pin state.
6. SROM download.
7. Enable laser by setting Forced_Disable bit (Bit-7) of LASER_CTRL0 register (address 0x20) to 0.
During power-up there will be a period of time after the power supply is high but before any clocks are available. The
table below shows the state of the various pins during power-up and reset.
State of Signal Pins After VDD is Valid
Pin

On Power-Up

NCS High before Reset

NCS Low before Reset

After Reset

NCS

Functional

Hi

Low

Functional

MISO

Undefined

Undefined

Functional

Depends on NCS

SCLK

Ignored

Ignored

Functional

Depends on NCS

MOSI

Ignored

Ignored

Functional

Depends on NCS

MOTION

Undefined

Undefined

Undefined

Functional

LASER_NEN

Undefined

Undefined

Undefined

Functional

20

Shutdown
The ADNS-9800 can be set in Shutdown mode by writing 0xb6 to register 0x3b. The SPI port should not be accessed
when Shutdown mode is asserted, except the power-up command (writing 0x5a to register 0x3a). (Other ICs on the
same SPI bus can be accessed, as long as the sensors NCS pin is not asserted.) The table below shows the state of various
pins during shutdown. To deassert Shutdown mode:
1. Drive NCS high, then low to reset the SPI port.
2. Write 0x5a to Power_Up_Reset register (address 0x3a).
3. Wait for at least 50 ms time.
4. Clear observation register.
5. Wait at least one frame and check observation register, Bit[5:0] must be set.
6. Read from registers 0x02, 0x03, 0x04, 0x05 and 0x06 (or read these same 5 bytes from burst motion register) one time
regardless of the motion pin state.
7. Enable laser by setting Forced_Disable bit (Bit-7) of LASER_CTRL0 register to 0.
8. Any register setting must then be reloaded.
Pin

Status when Shutdown Mode

NCS

Functional 1

MISO

Undefined 2

SCLK

Ignore if NCS = 1 3

MOSI

Ignore if NCS = 1 4

LASER_NEN

High(off )

MOTION

Undefined 2

Notes:
1. NCS pin must be held to 1 (high) if SPI bus is shared with other devices. It is recommended to hold to 1 (high) during Power Down unless powering
up the Sensor. It must be held to 0 (low) if the sensor is to be re-powered up from shutdown (writing 0x5a to register 0x3a).
2. Depends on last state. MISO should be configured to drive LOW during shutdown to meet the low current consumption as specified in
the datasheet. This can be achieved by reading Inverse_Product_ID register (address 0x3f ) since the return value (0xcc) on MISO line ends in a 0
(low state).
3. SCLK is ignored, if NCS is 1 (high). It is functional if NCS is 0 (low).
4. MOSI is ignored, if NCS is 1 (high). If NCS is 0 (low), any command present on the MOSI pin will be ignored except power-up command (writing 0x5a
to register 0x3a).
There are long wakeup times from shutdown and forced Rest. These features should not be used for power management during normal mouse
motion.

21

Registers
The ADNS-9800 registers are accessible via the serial port. The registers are used to read motion data and status as well
as to set the device configuration.
Address

Register

Read/Write

Default Value

0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0a
0x0b
0x0c
0x0d
0x0e
0x0f
0x10
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1a
0x1b
0x1c
0x1d
0x1e
0x1f
0x20
0x21- 0x23
0x24
0x25
0x26
0x27 - 0x29
0x2a
0x2e
0x2f
0x30 - 0x38
0x39
0x3a
0x3b
0x3c - 0x3e
0x3f
0x40 0x41
0x42
0x43 0x4f
0x50
0x62
0x64

Product_ID
Revision_ID
Motion
Delta_X_L
Delta_X_H
Delta_Y_L
Delta_Y_H
SQUAL
Pixel_Sum
Maximum_Pixel
Minimum_Pixel
Shutter_Lower
Shutter_Upper
Frame_Period_Lower
Frame_Period_Upper
Configuration_I
Configuration_II
Frame_Capture
SROM_Enable
Run_Downshift
Rest1_Rate
Rest1_Downshift
Rest2_Rate
Rest2_Downshift
Rest3_Rate
Frame_Period_Max_Bound_Lower
Frame_Period_Max_Bound_Upper
Frame_Period_Min_Bound_Lower
Frame_Period_Min_Bound_Upper
Shutter_Max_Bound_Lower
Shutter_Max_Bound_Upper
LASER_CTRL0
Reserved
Observation
Data_Out_Lower
Data_Out_Upper
Reserved
SROM_ID
Lift_Detection_Thr
Configuration_V
Reserved
Configuration_IV
Power_Up_Reset
Shutdown
Reserved
Inverse_Product_ID
Reserved
Snap_Angle
Reserved
Motion_Burst
SROM_Load_Burst
Pixel_Burst

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

0x33
0x03
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x20
0x4e
0xc0
0x5d
0x12
0x00
0x00
0x00
0x32
0x01
0x1f
0x09
0xbc
0x31
0xc0
0x5d
0xa0
0x0f
0x20
0x4e
0x81

R/W
R
R

0x00
Undefined
Undefined

R
R/W
R/W

0x00
0x10
0x12

R/W
W
W

0x00
NA
Undefined

0xcc

R/W

0x06

R
W
R

0x00
Undefined
0x00

22

Product_ID

Address: 0x00

Access: Read Only

Reset Value: 0x33

Bit 7
Field PID7

PID6

PID5

PID4

PID3

PID2

PID1

PID0

Data Type: 8-bit unsigned integer

USAGE: This value is a unique identification assigned to this model only. The value in this register does not change; it
can be used to verify that the serial communications link is functional.

Revision_ID

Address: 0x01

Access: Read Only

Reset Value: 0x03

Bit 7
Field RID7

RID6

RID5

RID4

RID3

RID2

RID1

RID0

Data Type: 8-bit unsigned integer

USAGE: This register contains the current IC revision, the revision of the permanent internal firmware. It is subject to
change when new IC versions are released.

23

Motion

Address: 0x02

Access: Read Only

Reset Value: 0x00

Bit 7

Field MOT

Reserved

Reserved

OP_Mode1

OP_Mode0

FRAME_
Pix_First

Data Type: Bit field

USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If the MOT
bit is set, Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H register should be read in sequence to get the
accumulated motion. Read this register before reading the Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H
registers as reading this register freezes the Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H register values. If
Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H registers are not read before the Motion register is read for the
second time, the data in Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H will be lost. Writing anything to this
register clears the MOT bit, Delta_X_L, Delta_X_H, Delta_Y_L and Delta_Y_H registers. The written data byte is
not saved.
It also tells if laser fault, laser power setting status and operating mode in current frame.
Field Name

Description

MOT

Motion since last report or Shutdown

0 = No motion
1 = Motion occurred, data ready for reading in Delta_X_L, Delta_X_H,
Delta_Y_L and Delta_Y_H registers

FAULT

LP_Valid

Indicates that the XY_LASER is shorted to GND.

0 = no fault detected
1 = fault detected
Laser Power Settings

0 = Laser power register values do not have complementary values

1 = laser power is valid
OP_Mode[1:0]

Operating mode of the sensor

00 = Run
01 = Rest 1
10 = Rest 2
11 = Rest 3
FRAME_Pix_First

This bit is set to indicate first pixel in frame capture.

0 = Frame capture data not from pixel 0,0

1 = Frame capture data is from pixel 0,0

24

Delta_X_L

Address: 0x03

Access: Read Only

Reset Value: 0x00

Bit 7

Field X7

X6

X5

X4

X3

X2

X1

X0

Data Type: 16 bits 2s complement number. Lower 8 bits of Delta_X.

USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading it clears the
register.
Motion

-32768

-32767

-2

-1

+1

+2

8000

8001

FE

FF

00

01

02

Delta_X

Delta_X_H

Address: 0x04

Access: Read Only

Reset Value: 0x00

Bit 7
Field X15

+32766 +32767

7FFE

7FFF

X14

X13

X12

X11

X10

X9

X8

Data Type: 16 bits 2s complement number. Upper 8 bits of Delta_X.

USAGE: Delta_X_H must be read after Delta_X_L to have the full motion data. Reading it clears the register.

Delta_Y_L

Address: 0x05

Access: Read Only

Reset Value: 0x00

Bit 7

Field Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Data Type: 16 bits 2s complement number. Lower 8 bits of Delta_Y.

USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading it clears the register.
Motion

-32768

-32767

-2

-1

+1

+2

8000

8001

FE

FF

00

01

02

Delta_Y

Delta_Y_H

Address: 0x06

Access: Read Only

Reset Value: 0x00

Bit 7
Field Y15

+32766 +32767

7FFE

7FFF

Y14

Y13

Y12

Y11

Y10

Y9

Y8

Data Type: 16 bits 2s complement number. Upper 8 bits of Delta_Y.

USAGE: Delta_Y_H must be read after Delta_Y_L to have the full motion data. Reading it clears the register.
NOTES: Avago RECOMMENDS that registers 0x02, 0x03, 0x04, 0x05 and 0x06 to be read sequentially.
25

SQUAL

Address: 0x07

Access: Read Only

Reset Value: 0x00

Bit 7
Field SQ7

SQ6

SQ5

SQ4

SQ3

SQ2

SQ1

SQ0

Data Type: Upper 8-bits of a 10-bit unsigned integer.

USAGE: The SQUAL (Surface quality) register is a measure of the number of valid features visible by the sensor in the
current frame. Use the following formula to find the total number of valid features.
Number of Features = SQUAL Register Value * 4
The maximum SQUAL register value is 169. Since small changes in the current frame can result in changes in
SQUAL, variations in SQUAL when looking at a surface are expected. The graph below shows 800 sequentially
acquired SQUAL values, while a sensor was moved slowly over white paper. SQUAL is nearly equal to zero if
there is no surface below the sensor. SQUAL remains fairly high throughout the Z-height range which allows
illumination of most pixels in the sensor.
SQUAL Values (White Paper)
At Z = 2.4 mm, Circle@7.5" diameter, Speed = 6 ips
200

SQUAL (Count)

150
100
50
0
1

51

101 151 201 251 301 351 401 451 501 551 601 651 701 751
Count

Figure 24. SQUAL Values at 1600 cpi (White Paper)

Mean SQUAL Vs. Z (White Paper)
1600 cpi, Circle@7.5" diameter, Speed = 6 ips
140

Avg-3sigma
Avg
Avg+3sigma

SQUAL (Count)

120
100
80
60
40
20
0
1.6

1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
Distance from Lens Reference Plane to Navigation Surface (mm)

Figure 25. Mean SQUAL vs. Z (White Paper)

26

3.4

Pixel_Sum

Address: 0x08

Access: Read Only

Reset Value: 0x00

Bit 7
Field AP7

AP6

AP5

AP4

AP3

AP2

AP1

AP0

Data Type: High 8-bits of an unsigned 17-bit integer.

USAGE: This register is used to find the average pixel value. It reports the upper byte of a 17-bit counter which sums
all 900 pixels in the current frame. It may be described as the full sum divided by 512. To find the average pixel
value, follows the formula below.
Average Pixel = Register Value * 512 / 900 @ Register Value / 1.76
The maximum register value is 223 (127 * 900 / 512 truncated to an integer). The minimum register value is 0.
The pixel sum value can change every frame.

Maximum_Pixel

Address: 0x09

Access: Read Only

Reset Value: 0x00

Bit 7
Field MP7

MP6

MP5

MP4

MP3

MP2

MP1

MP0

Data Type: Seven bit number.

USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 127. The maximum pixel value
can be adjusted every frame.

Minimum_Pixel

Address: 0x0A

Access: Read Only

Reset Value: 0x00

Bit 7
Field MinP7

MinP6

MinP5

MinP4

MinP3

MinP2

MinP1

MinP0

Data Type: Seven bit number.

USAGE: Minimum Pixel value in current frame. Minimum value = 0, maximum value = 127. The maximum pixel value
can be adjusted every frame.

Shutter_Lower

Address: 0x0B

Access: Read Only

Reset Value: 0x20

Bit 7

Field S7

S6

S5

S4

S3

S2

S1

S0

Data Type: Seven bit number.

USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 127. The maximum pixel value
can be adjusted every frame.

27

Shutter_Upper

Address: 0x0C

Access: Read Only

Reset Value: 0x4e

Bit 7
Field S15

S14

S13

S12

S11

S10

S9

S8

Data Type: 16-bit unsigned number.

USAGE: Units are clock cycles of internal oscillator (nominally 50 MHz). Read Shutter_Upper first, then Shutter_Lower.
They should be read consecutively. The shutter is adjusted to keep the average pixel values within normal
operating ranges. The shutter value is checked and automatically adjusted to a new value if needed on every
frame when operating in default mode. The shutter value can be set manually by disabling the AGC using the
Configuration_II register and writing to the Shutter_Maximum_Bound registers. Because the automatic frame
rate feature is related to shutter value it may also be appropriate to enable the fixed frame rate mode using
the Configuration_II register. The maximum value of the shutter is dependent upon the setting in the Shutter_
Maximum_Bound registers.
Shown below is a graph of 800 sequentially acquired shutter values, while the sensor was moved slowly over
white paper.
Shutter Values (White Paper)
At Z = 2.4 mm, Circle@7.5" diameter, Speed = 6 ips
120

Shutter Value

100
80
60
40
20
0
1

51 101 151 201 251 301 351 401 451 501 551 601 651 701 751
Count

Figure 26. Shutter Values at 5000 cpi (White Paper)

Mean Shutter vs Z (White Paper)
1600 cpi, Circle@7.5" diameter, Speed = 6 ips
300

Avg-3sigma
Avg
Avg+3sigma

Shutter Value

250
200
150
100
50
0
1.6

1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
Distance from Lens Reference Plane to Navigation Surface, Z (mm)

Figure 27. Mean Shutter vs. Z (White Paper)

28

3.4

Frame_Period_Lower

Address: 0x0D

Access: Read Only

Reset Value: 0xc0

Bit 7
Field FP7

FP6

FP5

FP4

FP3

FP2

FP1

FP0

Frame_Period_Upper

Address: 0x0E

Access: Read Only

Reset Value: 0x5d

Bit 7
Field FP15

FP14

FP13

FP12

FP11

FP10

FP9

FP8

Data Type: 16-bit unsigned integer.

USAGE: Read these registers to determine the current frame period, or indirectly the frame rate. Units are clock cycles
of the internal oscillator (nominally 50 MHz). The formula is:
Frame Rate = Clock Frequency / Register Value
To read from the registers, read Frame_Period_Upper first followed by Frame_Period_Lower. To set the frame
rate manually, disable automatic frame rate mode via the Configuration_II register and write the desired count
value to the Frame_Period_Maximum_Bound registers.

Configuration_I

Address: 0x0F

Access: R/W

Reset Value: 0x09

Bit 7

Field Reserved

Reserved

RES5

RES4

RES3

RES2

RES1

RES0

Data Type: Bit Field.

USAGE: This register sets the resolution on XY axes or X axis only. The approximate resolution value for each register
setting can be calculated using the following formula. Each bit change is ~200 cpi. The maximum write value is
0x29, which the resolution setting is approximately 8200 cpi.
Resolution value (counts per inch, cpi) RES [5:0] x 200
For example:
Configuration_I Register Value

Approximate Resolution (cpi)

Description

0x01

200

Minimum

0x09

1800

Default

0x24

7200

0x29

8200

Maximum

Note: Rpt_Mod bit in Configuration_II register is used to select CPI reporting mode either XY axes resolution
setting in sync or independent setting for X-axis and Y-axis respectively. Refer to Configuration_V register for
Y-axis resolution setting.

29

Configuration_II

Address: 0x10

Access: R/W

Reset Value: 0x00

Bit 7

Field F_Rest1

F_Rest0

Rest_En

NAGC

Fixed_FR

Rpt_Mod

Data Type: Bit Field.

USAGE: This register is used to change configuration of sensor.
When the sensor is put into Force Rest function via F_Rest[1:0], the operation mode of sensor will change from
current mode to the next desired Rest mode and stay at the desired Rest mode until the Force Rest mode is
released. Once Force Rest mode is released, the sensor will resume to normal operation from the desired Rest
mode and auto downshift to the next level of Rest modes if no motion or recover to Run mode if motion is
detected.
For example:
Current
mode

Next desired
mode

Force Rest
mode action

After Force Rest mode is released

(F_Rest[1:0] = 00)

Run

Rest1

Force Rest1
F_Rest[1:0] = 01

Resume to normal operation from REST1, auto

downshift to Rest2, then Rest3 in sequence
if no motion or back to Run mode if motion
detected.

Run

Rest2

Force Rest2
F_Rest[1:0] = 10

Resume to normal operation from REST2, auto

downshift to Rest3 if no motion or back to Run
mode if motion detected.

Run

Rest3

Force Rest3
F_Rest[1:0] = 11

Resume to normal operation from REST3, stay

in Rest3 if no motion or back to Run mode if
motion detected.

Field Name

Description

F_Rest[1:0]

Puts chip into Rest mode

00 = Normal operation
01 = Force Rest1
10 = Force Rest2
11 = Force Rest3
Rest_En

Enable Rest mode

0 = Normal operation without REST modes

1 = REST modes enabled
NAGC

Disable AGC. Shutter value will be set to the value in the

Shutter_Maximum_Bound registers.

0 = no, AGC is active

1 = yes, AGC is disabled
Fixed_FR

Fixed frame rate (disable automatic frame rate control). When this bit
is set the frame rate will be set by the value in the Frame_Period_
Maximum_Bound registers.

0 = automatic frame rate

1 = fixed frame rate
Rpt_Mod

Select CPI reporting mode.

0 = XY axes CPI setting in sync

1 = CPI setting independently for X-axis and Y-axis. Configuration_I
register sets X-axis resolution, while Configuration_V register sets
Y-axis resolution.
Bit[1:0]

30

Must be set to 00

Frame_Capture

Address: 0x12

Access: R/W

Reset Value: 0x00

Bit 7

Field FC7

FC6

FC5

FC4

FC3

FC2

FC1

FC0

Data Type: Bit Field.

USAGE: Used to capture the next available complete 1 frame of pixel values to be stored to SROM RAM. Writing to this
register will cause any firmware loaded in the SROM to be overwritten and stops navigation. A hardware reset
and SROM download are required to restore normal operation for motion reading. Refer to Frame Capture
section for use details.

SROM_Enable

Address: 0x13

Access: Write Only

Reset Value: 0x00

Bit 7
Field SE7

SE6

SE5

SE4

SE3

SE2

SE1

SE0

Data Type: 8 Bit number.

USAGE: Write to this register to start either SROM download or SROM CRC test. See SROM Download section for details
SROM download procedure.
SROM CRC test can be performed to check for the successful of SROM downloading procedure. SROM CRC
test is only valid after SROM downloaded. Navigation is halted and the SPI port should not be used during this
SROM CRC test. Avago recommends reading the Motion register to determine the laser fault condition before
performing the SROM CRC test.
SROM CRC test procedure is as below:
1. Write 0x15 to SROM_Enable register to start SROM CRC test.
2. Wait for at least 10 ms.
3. Read the CRC value from Data_Lower and Data_Upper registers.

Run_Downshift

Address: 0x14

Access: R/W

Reset Value: 0x32

Bit 7

Field RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

Data Type: 8 Bit number.

USAGE: This register set the Run to Rest 1 downshift time. Default value is 500 ms. Use the formula below for
calculation.

Run Downshift time (ms) = RD[7:0] x 10

Default = 50 x 10 = 500 ms

All the above values are calculated base on system clock, which expected to have 20% tolerance.

31

Rest1_Rate

Address: 0x15

Access: R/W

Reset Value: 0x01

Bit 7

Field R1R7

R1R6

R1R5

R1R4

R1R3

R1R2

R1R1

R1R0

Data Type: 8 Bit number.

USAGE: This register set the Rest 1 frame rate. Default value is 20 ms. Use the formula below for calculation.

Rest1 frame rate = (R1R[7:0] + 1) x 10 ms.

Default = (1 + 1) x 10 = 20 ms

All the above values are calculated base on 100 Hz Hibernate clock, which expected to have 40% tolerance.

Rest1_Downshift

Address: 0x16

Access: R/W

Reset Value: 0x1f

Bit 7

Field R1D7

R1D6

R1D5

R1D4

R1D3

R1D2

R1D1

R1D0

Data Type: 8 Bit number.

USAGE: This register set the Rest 1 to Rest 2 downshift time. Default value is 9920 ms. Use the formula below for
calculation.

Rest1 Downshift time = R1D[7:0] x 16 x Rest1_Rate.

Default = 31 x 16 x 20 = 9920 ms

All the above values are calculated base on 100 Hz Hibernate clock, which expected to have 40% tolerance.

Rest2_Rate

Address: 0x17

Access: R/W

Reset Value: 0x09

Bit 7

Field R2R7

R2R6

R2R5

R2R4

R2R3

R2R2

R2R1

R2R0

Data Type: 8 Bit number.

USAGE: This register set the Rest 2 frame rate. Default value is 100 ms. Use the formula below for calculation.

Rest2 frame rate = (R2R[7:0] + 1) x 10 ms.

Default = (9 + 1) x 10 = 100 ms

All the above values are calculated base on 100 Hz Hibernate clock, which expected to have 40% tolerance.

32

Rest2_Downshift

Address: 0x18

Access: R/W

Reset Value: 0xbc

Bit 7

Field R2D7

R2D6

R2D5

R2D4

R2D3

R2D2

R2D1

R2D0

Data Type: 8 Bit number.

USAGE: This register set the Rest 2 to Rest 3 downshift time. Default value is 10mins. Use the formula below for
calculation.

Rest2 Downshift time = R2D[7:0] x 32 x Rest2_Rate.

Default = 188 x 32 x 100 = 601600 ms = 10 mins

All the above values are calculated base on 100 Hz Hibernate clock, which expected to have 40% tolerance.

Rest3_Rate

Address: 0x19

Access: R/W

Reset Value: 0x31

Bit 7

Field R3R7

R3R6

R3R5

R3R4

R3R3

R3R2

R3R1

R3R0

Data Type: 8 Bit number.

USAGE: This register set the Rest 3 frame rate. Default value is 500 ms. Use the formula below for calculation.

Rest3 frame rate = (R3R[7:0] + 1) x 10 ms.

Default = (49 + 1) x 10 = 500 ms

All the above values are calculated base on 100 Hz Hibernate clock, which expected to have 40% tolerance.

33

Frame_Period_Max_Bound_Lower

Address: 0x1A

Access: R/W

Reset Value: 0xc0

Bit 7

Field FBM7

FBM6

FBM5

FBM4

FBM3

FBM2

FBM1

FBM0

Frame_Period_Max_Bound_Upper

Address: 0x1B

Access: R/W

Reset Value: 0x5d

Bit 7

Field FBM15

FBM14

FBM13

FBM12

FBM11

FBM10

FBM9

FBM8

Data Type: 16-bit unsigned integer.

USAGE: This value sets the maximum frame period (the MINIMUM frame rate) which may be selected by the automatic
frame rate control, or sets the actual frame period when operating in manual mode. To read from the registers,
read Upper first followed by Lower. To write to the registers, write Lower first, followed by Upper. Units are clock
cycles of the internal oscillator (nominally 50 MHz). The formula is:

Frame Rate (Frames/second, fps) = Clock Frequency / Register Value

To set the frame rate manually, disable automatic frame rate mode via the Configuration_II register and write
the desired count value to these registers. Writing to the Frame_Period_Max_Bound_Upper and Lower registers
also activates any new values in the following registers:
Frame_Period_Max_Bound_Upper and Lower
Frame_Period_Min_Bound_Upper and Lower
Shutter_Max_Bound_Upper and Lower
Any data written to these registers will be saved but will not take effect until the write to the Frame_Period_
Max_Bound_Upper and Lower is complete. After writing to this register, two complete frame times are required
to implement the new settings. Writing to any of the above registers before the implementation is complete
may put the chip into an undefined state requiring a reset.
The three bound registers must also follow this rule when set to non-default values. There is no protection
against illegal register settings, which can impact the navigation.

Frame_Period_Max_Bound Frame_Period_Min_Bound + Shutter_Max_Bound.

The following table lists some Frame Period example values with a 50 MHz clock.
Frame Period

34

Frame_Period Register Value

Frame Rate

Decimal

Hex

Upper

Lower

2,000

25,000

61a8

61

a8

2,083

24,000

5dc0

5d

c0

7,200

6944

1b20

1b

20

12,000

5000

0fa0

0f

a0

Frame_Period_Min_Bound_Lower

Address: 0x1C

Access: R/W

Reset Value: 0xa0

Bit 7

Field FBm7

FBm6

FBm5

FBm4

FBm3

FBm2

FBm1

FBm0

Frame_Period_Min_Bound_Upper

Address: 0x1D

Access: R/W

Reset Value: 0x0f

Bit 7

Field FBm15

FBm14

FBm13

FBm12

FBm11

FBm10

FBm9

FBm8

Data Type: 16-bit unsigned integer.

USAGE: This value sets the minimum frame period (the MAXIMUM frame rate) which may be selected by the automatic
frame rate control. Units are clock cycles of the internal oscillator (nominally 50MHz). The minimum allowed
write value is 0fa0, the maximum is 61a8. The Frame Rate formula is

Frame Rate (Frames/second, fps) = Clock Rate / Register Value

To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed
by Upper, then write anything to the Frame_Period_Max_Bound Lower and Upper registers to activate the new
setting. A good practice is to read the content of the Frame_Period_Max_Bound registers and write it back.
Reading this register will return the most recent value that was written to it. However, the value will take effect
only after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_
Max_Bound_Upper, wait at least two frame times before writing to Frame_Period_Min_Bound_Upper or Lower
again. Refer to Frame_Period_Max_Bound register USAGE for details.
In addition, the three bound registers must also follow this rule when set to non-default values:

Frame_Period_Max_Bound Frame_Period_Min_Bound + Shutter_Max_Bound.

35

Shutter_Max_Bound_Lower

Address: 0x1E

Access: R/W

Reset Value: 0x20

Bit 7

Field SB7

SB6

SB5

SB4

SB3

SB2

SB1

SB0

Shutter_Max_Bound_Upper

Address: 0x1F

Access: R/W

Reset Value: 0x4e

Bit 7

Field SB15

SB14

SB13

SB12

SB11

SB10

SB9

SB8

Data Type: 16-bit unsigned integer.

USAGE: This value sets the maximum allowable shutter value when operating in automatic mode. Units are clock cycles
of the internal oscillator (nominally 50 MHz). Since the automatic frame rate function is based on shutter value,
the value in these registers can limit the range of the frame rate control.
To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed
by Upper, then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers to activate the
new setting. A good practice is to read the content of the Frame_Period_Max_Bound registers and write it
back. To set the shutter manually, disable the AGC via the Configuration_I register and write the desired value
to these registers.
Reading this register will return the most recent value that was written to it. However, the value will take effect
only after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_
Max_Bound_Upper, wait at least two frame times before writing to Shutter_Max_Bound_Upper or Lower
again.
In addition, the three bound registers must also follow this rule when set to non-default values:

Frame_Period_Max_Bound Frame_Period_Min_Bound + Shutter_Max_Bound.

LASER_CTRL0

Address: 0x20

Access: R/W

Reset Value: 0x81

Bit 7

Field Reserved

Reserved

Reserved

Reserved

CW2

CW1

CW0

Force_
Disabled

Data Type: Bit field

USAGE: This register is used to control the laser drive mode.
Field Name

Description

CW[2:0]

Laser drive mode

Write 010b to bits [3,2,1] to set the laser to continuous ON (CW) mode.

Write 000b to exit laser continuous ON mode, all other values are
not recommended.
Reading the Motion register (0x02) will reset the value to 000b and exit
laser continuous ON mode.
Force_Disabled

LASER force disabled

0 = LASER_NEN normal

1 = LASER_NEN force disabled

36

Observation

Address: 0x24

Access: R/W

Reset Value: 0x00

Bit 7

Field OB7

OB6

OB5

OB4

OB3

OB2

OB1

OB0

Data Type: Bit field

USAGE: The user must clear the register by writing 0x00, wait for one frame, and read the register. The active processes
will have set their corresponding bit. This register may be used as part of a recovery scheme to detect a problem
caused by EFT/B or ESD.
Field Name

Description

OB6

0 = chip is not running SROM code

OB[5:0]

Set once per frame

1 = chip is running SROM code

Data_Out_Lower

Address: 0x25

Access: Read Only

Reset Value: Undefined

Bit 7
Field DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

Data_Out_Upper

Address: 0x26

Access: Read Only

Reset Value: Undefined

Bit 7
Field DO15

DO14

DO13

DO12

DO11

DO10

DO9

DO8

Data Type: 16-bit word.

USAGE: Data in these registers come from the SROM CRC test. The data can be read out in either order. The SROM CRC
test is initiated by writing 0x15 to SROM_Enable register.
CRC Result

Data_Out_Upper

Data_Out_Lower

SROM CRC test

BE

EF

SROM_ID

Address: 0x2A

Access: Read Only

Reset Value: 0x00

Bit 7
Field SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

Data Type: 8-bit unsigned integer.

USAGE: Contains the revision of the downloaded Shadow ROM (SROM) firmware. If the firmware has been successfully
downloaded and the chip is operating out of SROM, this register will contain the SROM firmware revision;
otherwise it will contain 0x00.

37

Lift_Detection_Thr

Address: 0x2E

Access: R/W

Reset Value: 0x10

Bit 7

Field Reserved

Reserved

Reserved

LD_Thr4

LD_Thr3

LD_Thr2

LD_Thr1

LD_Thr0

Data Type: 8-bit unsigned integer.

USAGE: To configure the lift detection from the nominal Z-height of 2.4 mm of navigation system when ADNS-9800
sensor is coupled with ADNS-6190-002 lens. Higher value will result in higher lift detection. Different surfaces
will have different lift detection values with same setting due to different surface characteristic.

Configuration_V

Address: 0x2F

Access: R/W

Reset Value: 0x09

Bit 7

Field ResY7

ResY6

ResY5

ResY4

ResY3

ResY2

ResY1

ResY0

Data Type: Bit field.

USAGE: This register allows the user to change the Y-axis resolution when the sensor is configured to have indepedent
X-axis and Y-axis resolution reporting mode via Rpt_Mod bit = 1 in Configuration_II register. The setting in
this register will be inactive if Rpt_Mod bit = 0. The approximate resolution value for each register setting can
be calculated using the following formula. Each bit change is~200cpi. The minimum write value is 0x01 and
maximum is 0x29.

Resolution value (counts per inch, cpi) = RES [7:0] x 200

Configuration_IV

Address: 0x39

Access: R/W

Reset Value: 0x00

Bit 7

Field Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

SROM_Size Reserved

Data Type: Bit field

USAGE: The correct SROM file size must be selected before loading the SROM to sensor. The current SROM is 3 K Bytes
size.
Field Name

Description

SROM_Size

= 0: 1.5K SROM download

= 1: 3K SROM download

38

Power_Up_Reset

Address: 0x3A

Access: Write Only

Reset Value: 0xNA

Bit 7
Field PUR7

PUR6

PUR5

PUR4

PUR3

PUR2

PUR1

PUR0

Data Type: 8-Bit integer.

USAGE: Write 0x5a to this register to reset the chip. All settings will revert to default values. Reset is required after
recovering from shutdown mode and restore normal operation after Frame Capture.

Shutdown

Address: 0x3B

Access: Write Only

Reset Value: Undefined

Bit 7
Field OB7

OB6

OB5

OB4

OB3

OB2

OB1

OB0

Data Type: 8-Bit integer.

USAGE: Write 0xb6 to set the chip to shutdown mode, use POWER_UP_RESET register to power up the chip. Refer to
Shutdown section for more details.

Inverse_Product_ID

Address: 0x3F

Access: Read Only

Reset Value: 0xcc

Bit 7
Field PID7

PID6

PID5

PID4

PID3

PID2

PID1

PID0

Data Type: 8-Bit unsigned integer.

USAGE: This value is the inverse of the Product_ID, located at the inverse address. It is used to test the SPI port
hardware.

Snap_Angle

Address: 0x42

Access: R/W

Reset Value: 0x06

Bit 7

Field Snap_En

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Data Type: Bit field

USAGE: This register is used to enable or disable the Angle Snapping function. When it is enabled, actual movement
ranges from 5degrees from X or Y-axis, it will be snapped to the closest axis. For example, if the sensor moves
at +/- 2degree from X-axis, the output motion data will be snapped to X-axis at 0degree.
Field Name

Description

Snap_En

Angle Snapping function

= 0: Disable
= 1 : Enable

39

Motion_Burst

Address: 0x50

Access: Read Only

Reset Value: 0x00

Bit 7
Field MB7

MB6

MB5

MB4

MB3

MB2

MB1

MB0

Data Type: 8-Bit unsigned integer.

USAGE: The Motion_Burst register is used for high-speed access to the Motion, Delta_X_L, Delta_X_H, Delta_Y_L,
Delta_Y_H, SQUAL, Pixel_Sum, Maximum_Pixel, Minimum_Pixel, Shutter_Upper, Shutter_Lower, Frame_
Period_Upper and Frame_Period_Lower registers. See Burst Mode-Motion Read section for use details. Write
any value to this register will clear all motion burst data.

SROM_Load_Burst

Address: 0x62

Access: W

Reset Value: Undefined

Bit 7
Field SL7

SL6

SL5

SL4

SL3

SL2

SL1

SL0

Data Type: 8-Bit unsigned integer.

USAGE: The SROM_Load_Burst register is used for high-speed programming SROM from an external PROM or microcontroller. See SROM Download section for use details.

Pixel_Burst

Address: 0x64

Access: Read Only

Reset Value: 0x00

Bit 7
Field PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

Data Type: 8-Bit unsigned integer.

USAGE: The Pixel_Burst register is used for high-speed access to all the pixel values for one complete frame capture,
without writing to the register address to obtain each pixel data. The data pointer is automatically incremented
after each read so all 900 pixel values may be obtained by reading this register 900 times. See Frame Capture
section for use details.

For product information and a complete list of distributors, please go to our web site:

www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright 2005-2012 Avago Technologies. All rights reserved.
AV02-2998EN - January 13, 2012