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Set-Reset Circuit
Using 7 Segment
Display
Submitted by:
Olid, Shaira Mae (Prototype)
Merlo, Aljune M. (Documentation)
Collado, Jairo Joshua (Prototype)
Mangubat, Raymond (Documentation)

Submitted to:
Engr. Golbandrio Teo
April 7, 2016

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CHAPTER 1
THE PROBLEM AND ITS BACKGROUND
Introduction
Digital counters are needed everywhere in this digital world,
and 7 segment display is one the best component to display the
numbers. Counters are needed in object/products counters,
digital stopwatches, calculators, timers etc. To use the 7 segment
with ease, there is a 7 segment driver IC which is IC CD4026, so
we are building 7 segment counter circuit using 4026 IC.
Background of the Study
In digital logic and computing, a counter is a device which
stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock
signal. The most common type is a sequential digital logic circuit
with an input line called the "clock" and multiple output lines. The
values on the output lines represent a number in the binary or
BCD number system. Each pulse applied to the clock input
increments or decrements the number in the counter.

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A counter circuit is usually constructed of a number of flipflops connected in cascade. Counters are a very widely-used
component in digital circuits, and are manufactured as separate
integrated circuits and also incorporated as parts of larger
integrated circuits.
Statement of the Problem
The need of the people to have a digital counters for tallying
is the idea for this project. Tallying is very important especially to
those in the field of statistics.
Scope and Delimitations
The project is only confined to a two separate 2-digit
counter, and a set and reset button. Therefore can only display
00-99.
Significance of the Study
The study will be beneficial to the following:
For Students will serve as reference for their projects
For Teachers will serve as their tools or modules for
teaching
For Others or for anyone who wants to have an easy to
build digital counter

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CHAPTER 2
THEORETICAL FRAMEWORK
Review of Related Literature & Studies
In electronics, a flip-flop or latch is a circuit that has two
stable states and can be used to store state information. A flipflop is a bistable multivibrator. The circuit can be made to change
state by signals applied to one or more control inputs and will
have one or two outputs. It is the basic storage element in
sequential logic. Flip-flops and latches are a fundamental building
block of digital electronics systems used in computers,
communications, and many other types of systems.
Flip-flops and latches are used as data storage elements. A
flip-flop stores a single bit (binary digit) of data; one of its two
states represents a "one" and the other represents a "zero". Such

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data storage can be used for storage of state, and such a circuit
is described as sequential logic. When used in a finite-state
machine, the output and next state depend not only on its current
input, but also on its current state (and hence, previous inputs). It
can also be used for counting of pulses, and for synchronizing
variably-timed input signals to some reference timing signal.

Flip-flops can be either simple (transparent or opaque) or

clocked (synchronous or edge-triggered). Although the term flipflop has historically referred generically to both simple and
clocked circuits, in modern usage it is common to reserve the
term flip-flop exclusively for discussing clocked circuits; the
simple ones are commonly called latches.[1][2]
Using this terminology, a latch is level-sensitive, whereas a
flip-flop is edge-sensitive. That is, when a latch is enabled it
becomes transparent, while a flip flop's output only changes on a
single type (positive going or negative going) of clock edge.
A bistable multivibrator has two stable states, as indicated
by the prefix bi in its name. Typically, one state is referred to
as set and the other as reset. The simplest bistable device,
therefore, is known as a set-reset, or S-R, latch.

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To create an S-R latch, we can wire two NOR gates in such a

way that the output of one feeds back to the input of another,
and vice versa, like this:

The Q and not-Q outputs are supposed to be in opposite

states. I say supposed to because making both the S and R
inputs equal to 1 results in both Q and not-Q being 0. For this
reason, having both S and R equal to 1 is called
an invalid or illegal state for the S-R multivibrator. Otherwise,
making S=1 and R=0 sets the multivibrator so that Q=1 and
not-Q=0. Conversely, making R=1 and S=0 resets the
multivibrator in the opposite state. When S and R are both equal
to 0, the multivibrators outputs latch in their prior states.
Note how the same multivibrator function can be implemented
in ladder logic, with the same results:

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By definition, a condition of Q=1 and not-Q=0 is set. A

condition of Q=0 and not-Q=1 is reset. These terms are
universal in describing the output states of any multivibrator
circuit.

The astute observer will note that the initial power-up

condition of either the gate or ladder variety of S-R latch is such
that both gates (coils) start in the de-energized mode. As such,
one would expect that the circuit will start up in an invalid
condition, with both Q and not-Q outputs being in the same
state. Actually, this is true! However, the invalid condition is
unstable with both S and R inputs inactive, and the circuit will

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quickly stabilize in either the set or reset condition because one

gate (or relay) is bound to react a little faster than the other. If
both gates (or coils) were precisely identical, they would
oscillate between high and low like an astable multivibrator
upon power-up without ever reaching a point of stability!
Fortunately for cases like this, such a precise match of
components is a rare possibility.
It must be noted that although an astable (continually
oscillating) condition would be extremely rare, there will most
likely be a cycle or two of oscillation in the above circuit, and
the final state of the circuit (set or reset) after power-up would
be unpredictable. The root of the problem is a race
condition between the two relays CR1 and CR2.
A race condition occurs when two mutually-exclusive
events are simultaneously initiated through different circuit
elements by a single cause. In this case, the circuit elements
are relays CR1 and CR2, and their de-energized states are
mutually exclusive due to the normally-closed interlocking
contacts. If one relay coil is de-energized, its normally-closed
contact will keep the other coil energized, thus maintaining the
circuit in one of two states (set or reset). Interlocking
prevents both relays from latching. However, if both relay coils
start in their de-energized states (such as after the whole circuit
has been de-energized and is then powered up) both relays will

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race to become latched on as they receive power (the single

cause) through the normally-closed contact of the other relay.
One of those relays will inevitably reach that condition before
the other, thus opening its normally-closed interlocking contact
and de-energizing the other relay coil. Which relay wins this
race is dependent on the physical characteristics of the relays
and not the circuit design, so the designer cannot ensure which
state the circuit will fall into after power-up.
Race conditions should be avoided in circuit design
primarily for the unpredictability that will be created. One way
to avoid such a condition is to insert a time-delay relay into the
circuit to disable one of the competing relays for a short time,
giving the other one a clear advantage. In other words, by
purposely slowing down the de-energization of one relay, we
ensure that the other relay will always win and the race
results will always be predictable. Here is an example of how a
time-delay relay might be applied to the above circuit to avoid
the race condition:

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When the circuit powers up, time-delay relay contact TD 1 in

the fifth rung down will delay closing for 1 second. Having that
contact open for 1 second prevents relay CR 2 from energizing
through contact CR1 in its normally-closed state after power-up.
Therefore, relay CR1 will be allowed to energize first (with a 1second head start), thus opening the normally-closed
CR1 contact in the fifth rung, preventing CR2 from being
energized without the S input going active. The end result is
that the circuit powers up cleanly and predictably in the reset
state with S=0 and R=0.

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It should be mentioned that race conditions are not

restricted to relay circuits. Solid-state logic gate circuits may
also suffer from the ill effects of race conditions if improperly
designed. Complex computer programs, for that matter, may
also incur race problems if improperly designed. Race problems
are a possibility for any sequential system, and may not be
discovered until some time after initial testing of the system.
They can be very difficult problems to detect and eliminate.
A practical application of an S-R latch circuit might be for
starting and stopping a motor, using normally-open, momentary
pushbutton switch contacts for both start (S) and stop (R)
switches, then energizing a motor contactor with either a CR 1 or
CR2 contact (or using a contactor in place of CR 1 or CR2).
Normally, a much simpler ladder logic circuit is employed, such
as this:

In the above motor start/stop circuit, the CR 1 contact in

parallel with the start switch contact is referred to as a seal-in

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contact, because it seals or latches control relay CR 1 in the

energized state after the startswitch has been released. To
break the seal, or to unlatch or reset the circuit,
the stop pushbutton is pressed, which de-energizes CR1 and
restores the seal-in contact to its normally open status. Notice,
however, that this circuit performs much the same function as
the S-R latch. Also note that this circuit has no inherent
instability problem (if even a remote possibility) as does the
double-relay S-R latch design.
In semiconductor form, S-R latches come in prepackaged
units so that you dont have to build them from individual gates.
They are symbolized as such:

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Definition of Terms
Counter- is an apparatus used for counting.
Sequential logic- is a form of binary circuit design that
employs one or more inputs and one or more outputs
Flip-flops- also called bistable gates, are digital logic
circuits that can be in one of two states. Flip-flops maintain
their state indefinitely until an input pulse called a trigger is
received. When a trigger is received, the flip-flop outputs
change state according to defined rules and remain in those
states until another trigger is received. Flip-flop circuits are
interconnected to form the logic gates for the digital
integrated circuits (IC s) used in memory chips and
microprocessors. Flip-flops can be used to store one bit, or
binary digit, of data. The data may represent the state of a
sequencer, the value of a counter, an ASCII character in a
computer's memory or any other piece of information.

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CHAPTER 3
TECHNICAL SPECIFICATIONS
Hardware Specifications
The components we used are the following:
Seven Segment Display
It consists 8 LEDs, each LED used to illuminate one segment/line
of the unit and the 8thLED used to illuminate DOT in 7 segment
display. We can refer each line/segment "a,b,c,d,e,f,g" and for dot
character we will use "h". There are 10 pins, in which 8 pins are
used to refer a,b,c,d,e,f,g and h/dp, the two middle pins are
common anode/cathode of all he LEDs.

IC 4026

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IC 4026 is used to drive common cathode 7 segment display. In

common cathode 7 segment display cathodes of all the LEDs are
connected together, and all the positive terminals are left alone.

Push button
Press-ON-Press-OFF soft toggle action, where a short button press
of a tactile switch latches the circuit ON and another toggles it
back OFF; or, A Press-ON-Hold-OFF action, where a short press
turns power to a circuit ON, but a longer button hold is needed to
toggle it OFF.

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Miscellaneous
Resistors (1k ohms)

Capacitors (0.1 uF and 22uF)

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Software Specifications

Multisim
Multisim simulation and circuit design software gives
engineers the advanced analysis and design capabilities to
optimize performance, reduce design errors, and shorten time to
prototype. Intuitive NI tools result in saved printed circuit board
(PCB) iterations and significant cost savings

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Logisim
Logisim is an educational tool for designing and simulating
digital logic circuits. With its simple toolbar interface and
simulation of circuits as you build them, it is simple enough to
facilitate learning the most basic concepts related to logic
circuits. With the capacity to build larger circuits from smaller
subcircuits, and to draw bundles of wires with a single mouse
drag, Logisim can be used (and is used) to design and simulate
entire CPUs for educational purposes.

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CHAPTER 4
PRESENTATION AND ANALYSIS OF THE FINDINGS
Applications
Digital counters and 7 segment display are used in the following:
Digital clock
Calculator
Electronic meters
Pulse counter
Advantages and Disadvantages
Easy to build circuit
It can use up to 2 or more 7 segment each one having an IC
4026

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It can be used as a tallying purpose or pulse counter

Monostable circuit used for the sync of the counter to count
up, must use correct capacitors to get the correct length of
how long the circuit will count up
Sensitive IC 4026.
It requires a lot of time to achieved correct connection to
each pins up to 7 segment display.

CHAPTER 5
CONCLUSIONS & RECOMMENDATIONS
Conclusions
Using IC4026 and 7 segment display comes a simple digital
counter with set-reset function. The complexity of the circuit
might be confusing but being careful with regards to the
schematic diagram is the key.
Recommendations
We highly recommend this project to anyone who wants to
build a simple digital counter with a set and reset function for any
educational or whatever purposes it may serve. And because the
project can only display 00-99, we recommend others to build a
digital counter with more 7 segment display.

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References
http://circuitdigest.com/electronic-circuits/555-timerseven-segment-counter-circuit
http://electroniccircuitsforbeginners.blogspot.com/2010/1
1/applications-of-sequential-logic.html
http://www.tutorialspoint.com/computer_logical_organizati
on/digital_counters.html
http://www.ni.com/example/14496/en/
http://whatis.techtarget.com/definition/counter
http://www.allaboutcircuits.com/textbook/digital/chpt10/s-r-latch/

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Appendices
RESEARCHERS

Circuit

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Finished Product

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Researchers Profile
ALJUNE M. MERLO
Address
Contact Number
Email

:177 ULNA Street, West Fairview, Quezon City.

:09107353545
:almerlss012@gmail.com
PERSONALINFORMATION

Nickname
Age
Date of Birth
Place of Birth
Gender
Height
Weight
Civil Status
Religion
Language/s Spoken
Name of Father
Occupation
Name of Mother
Occupation

: Al
: 19 years old
: March 12, 1997
: San Carlos, Negros Occidental
: Male
: 56
: 48 kgs
: Single
: Roman Catholic
: Filipino/English
: Alejandro Merlo
: Vendor
:Juana Merlo
: Housewife
EDUCATIONAL BACKGROUND

Tertiary

: Quezon City Polytechnic University

Bachelor of Science in Electronics and Communications Engineering
673 Quirino Hi-way, San Bartolome, Novaliches Quezon City
2013-Present

Secondary

: Sauyo High School

2nd Laguna Street, Sauyo, Novaliches, Quezon City.
2009-2013

Primary

: Sauyo Elementary School

Del Nacia Village, Sauyo, Novaliches, Quezon City.
2003-2009

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SHAIRA MAE OLID

Address
Contact Number
Email

:Lot 15 Cmpd 10 King William Street, Kasiyahan Village, Novaliches, Q.C

:09988642670
:olidshaira@gmail.com
PERSONALINFORMATION

Nickname
Age
Date of Birth
Place of Birth
Gender
Height
Weight
Civil Status
Religion
Language/s Spoken
Name of Father
Occupation
Name of Mother
Occupation

: Shai
: 19 years old
: December 09, 1996
: Quezon City
: Female
: 52
: 60 kgs
: Single
: Roman Catholic
: Filipino/English
: Ferdinand T. Olid
: Hospital Employee
:Liezl A. Olid
: Housewife
EDUCATIONAL BACKGROUND

Tertiary

: Quezon City Polytechnic University

Bachelor of Science in Electronics and Communications Engineering
673 Quirino Hi-way, San Bartolome, Novaliches Quezon City
2013-Present

Secondary

: Francisco School
#046 Quirino Highway Baesa, Quezon City.
2009-2013

Primary

: Placido Del Mundo Elementary School

Talipapa, Quezon City.
2003-2009

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RAYMOND MANGUBAT
Address
Contact Number
Email

:Blk 10 Lot 20, Mirandaville, Bryg, Kaligayaha Novaliches, Q.C

:09186350468
:mangubatraymond30@gmail.com
PERSONALINFORMATION

Nickname
Age
Date of Birth
Place of Birth
Gender
Height
Weight
Civil Status
Religion
Language/s Spoken
Name of Father
Occupation
Name of Mother
Occupation

: Mond
: 23 years old
: November 30,1992
: Quezon City
: Male
: 56
: 59 kgs
: Single
: Roman Catholic
: Filipino/English
: Loloy Mangubat
: Welder
:Evelyn Mangubat
: Great Mom,
EDUCATIONAL BACKGROUND

Tertiary

: Quezon City Polytechnic University

Bachelor of Science in Electronics and Communications Engineering
673 Quirino Hi-way, San Bartolome, Novaliches Quezon City
2013-Present

Secondary

: Novaliches High School

TS-Crus Lakandula st,Brgy,Kaligayahan Novaliches, Quezon City.
2006-2011

Primary

: San Agustis Elemntery School,

San, Agustin Bryg, Kaligayahan Novaliches Quezon City.
2000-2006

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JAIRO JOSHUA COLLADO

Address
Contact Number
Email

:Blk 10 Lot 20, Mirandaville, Bryg, Kaligayaha Novaliches, Q.C

:09186350468
:mangubatraymond30@gmail.com
PERSONALINFORMATION

Nickname
Age
Date of Birth
Place of Birth
Gender
Height
Weight
Civil Status
Religion
Language/s Spoken
Name of Father
Occupation
Name of Mother
Occupation

: Jairo
: 20 years old
: November 22,1995
: Quezon City
: Male
: 59
: 85 kgs
: Single
: Christian
: Filipino/English
: Rodolfo Collado
: Retired Businessman
:Milagros Collado
: Government Employee
EDUCATIONAL BACKGROUND

Tertiary

: Quezon City Polytechnic University

Bachelor of Science in Electronics and Communications Engineering
673 Quirino Hi-way, San Bartolome, Novaliches Quezon City
2013-Present

Secondary

: San Francisco Highs School

Misamis St. Proj,6 Brgy. Bagong Pag asa
2008-2012

Primary

: People Of Grace Christian School

Judge Jimenez St. Cor. Kamuning St. Brgy Sacred heart.
2002-2008

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REACTION PAPER FOR

ACADEMIC EXPOSURE
ACTIVITIES

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The project was part of our academic curriculum which

enable us to perform and create certain ideas, methods and to
improve our skills using electronic components. This project is
started in the middle of March 2016.
Background
Timers were originally designed to fulfill a need in industry
for a means of keeping time on certain devices. Originally, these
timers were mechanical devices and used clockwork mechanisms
as a means of keeping a regular time (Timer, 2006). The invention
of two electromechanical timer designs allowed for more precise
time measurement. The first uses the principle of heat expansion
to increase the temperature of a metal finger made of two
different metals with differing rates of thermal expansion (Timer,
2006). As electric current flows through the metal, it begins to
heat and one side expands more quickly than the other which, in
turn, moves the electrical contact away from an electrical switch
contact. The second uses a small AC motor which turns at a
predetermined rate due to the application of an alternating
current (Timer, 2006). Finally, digital timers were invented. Digital
logic circuits are now so cheap that it has become a better
investment to buy a digital timer than a mechanical or
electromechanical timer. Individual timers are implemented with

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single chip circuits, similar to a watch (Timer, 2006). The 555

timer used in this project is a combination of a digital logic circuit
and analogue component
Summary of Learnings
We learned the functions of the following components that
has been used in our project to build the circuit of it.
555 timer 555 timers are integrated timing circuits which
are used commonly as a source of clock pulses to drive
subsequent timer circuits.
IC 4026 is a 4000 series IC. It is a CMOS seven-segment
counter IC and can be operated at very low power. It is a
decade counter, counts in decimal digits (0-9).
7-segment Display an LED or Light Emitting Diode, is a solid
state optical PN-Junction diode which emits light energy in
the form of photos. Usually be seen in the as digital
indicators which involves numerical forms.

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These are the main components which we used in order to

make the project. By combining the components and following
the schematic diagram that we used for basis, and several tries to
run the circuit, we have completed and finished the project. The
connection of wires to the components are the trickiest part of
assembling of the circuit, yet we manage to finish it.
Analysis/Synthesis
By the combination of the following components, which consist
of RESISTORS, CAPACITORS, and IC 4026, CMOS 7-SEGMENT
COUNTER. We have created a project which can provide counting

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of numbers for the purpose of tallying certain topics, which

involves students. By the guidance of certain tutorial sites, we
have assembled this project, includes certain specifics like an
additional 7segment counters.

Conclusion and Recommendation

Based on our experience, the more components we used,
the more complex the circuit would be, and will be difficult to
analyze yet, the result would be more satisfying. Being careless
and not paying attention in the schematic would be a problem in
assembling the circuit, because there are some schematics that
are not that accurate. This type of project is very useful because
of the counting process. But it needs to be improved and add
more specifications. Due to limited resources, we manage to
accomplish this type of project. We recommend to add more

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functions, although the complexity of the circuit would be more

difficult.