a

FEATURES
Enhanced Replacements for LF412 and TL082
AC PERFORMANCE
Settles to 60.01% in 1.0 ms
16 V/ms min Slew Rate (AD712J)
3 MHz min Unity Gain Bandwidth (AD712J)

Dual Precision, Low Cost,

High Speed, BiFET Op Amp
AD712
CONNECTION DIAGRAMS
TO-99
(H) Package

Plastic Mini-Dip (N) Package

SOIC (R) Package
and
Cerdip (Q) Package

DC PERFORMANCE
0.30 mV max Offset Voltage: (AD712C)
5 mV/8C max Drift: (AD712C)
200 V/mV min Open-Loop Gain (AD712K)
4 mV p-p max Noise, 0.1 Hz to 10 Hz (AD712C)
Surface Mount Available in Tape and Reel in Accordance with EIA-481A Standard
MIL-STD-883B Parts Available
Single Version Available: AD711
Quad Version: AD713
Available in Plastic Mini-DIP, Plastic SOIC, Hermetic
Cerdip, Hermetic Metal Can Packages and Chip Form

PRODUCT DESCRIPTION

The AD712 is a high speed, precision monolithic operational

amplifier offering high performance at very modest prices. Its
very low offset voltage and offset voltage drift are the results of
advanced laser wafer trimming technology. These performance
benefits allow the user to easily upgrade existing designs that use
older precision BiFETs and, in many cases, bipolar op amps.
The superior ac and dc performance of this op amp makes it
suitable for active filter applications. With a slew rate of 16 V/s
and a settling time of 1 s to 0.01%, the AD712 is ideal as a
buffer for 12-bit D/A and A/D Converters and as a high-speed
integrator. The settling time is unmatched by any similar IC
amplifier.
The combination of excellent noise performance and low input
current also make the AD712 useful for photo diode preamps.
Common-mode rejection of 88 dB and open loop gain of
400 V/mV ensure 12-bit performance even in high-speed unity
gain buffer circuits.
The AD712 is pinned out in a standard op amp configuration
and is available in seven performance grades. The AD712J and
AD712K are rated over the commercial temperature range of
0C to +70C. The AD712A, AD712B and AD712C are rated
over the industrial temperature range of 40C to +85C. The
AD712S and AD712T are rated over the military temperature
range of 55C to +125C and are available processed to MILSTD-883B, Rev. C.

Extended reliability PLUS screening is available, specified over

the commercial and industrial temperature ranges. PLUS
screening includes 168-hour burn-in, as well as other environmental and physical tests.
The AD712 is available in an 8-pin plastic mini-DIP, SOIC,
cerdip, TO-99 metal can, or in chip form.
PRODUCT HIGHLIGHTS

1. The AD712 offers excellent overall performance at very

competitive prices.
2. Analog Devices advanced processing technology and with
100% testing guarantees a low input offset voltage (0.3 mV
max, C grade, 3 mV max, J grade). Input offset voltage is
specified in the warmed-up condition. Analog Devices laser
wafer drift trimming process reduces input offset voltage
drifts to 5 V/C max on the AD712C.
3. Along with precision dc performance, the AD712 offers excellent dynamic response. It settles to 0.01% in 1 s and
has a 100% tested minimum slew rate of 16 V/s. Thus this
device is ideal for applications such as DAC and ADC buffers which require a combination of superior ac and dc performance.
4. The AD712 has a guaranteed and tested maximum voltage
noise of 4 V p-p, 0.1 to 10 Hz (AD712C).
5. Analog Devices well-matched, ion-implanted JFETs ensure
a guaranteed input bias current (at either input) of 50 pA
max (AD712C) and an input offset current of 10 pA max
(AD712C). Both input bias current and input offset current
are guaranteed in the warmed-up condition.

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700
Fax: 617/326-8703

AD712SPECIFICATIONS (V = 15 V @ T = +25C unless otherwise noted)

S

Parameter

Min

INPUT OFFSET VOLTAGE1

Initial Offset
TMIN to TMAX
vs. Temp
vs. Supply
76
TMIN to TMAX
76/76/76
Long-Term Offset Stability
INPUT BIAS CURRENT2
VCM = 0 V
VCM = 0 V @ TMAX
VCM = 10 V
INPUT OFFSET CURRENT
VCM = 0 V
VCM = 0 V @ TMAX

AD712J/A/S
Typ
0.3
7
95

INPUT VOLTAGE NOISE

OPEN-LOOP GAIN

3
110

Units

0.3
0.6
5

mV
mV
V/C
dB
dB
V/Month

15
50
3.2
75

pA
nA
pA

10
0.3/0.7/11

25
0.6/1.6/26

5
0.1/0.3/5

25
0.6/1.6/26

5
0.3

10
0.7

pA
nA

0.3
0.6
5
10
120
90

mV
mV
V/C
pA
dB
dB

4.0
200
20
1.0
0.0003

MHz
kHz
V/s
s
%

3/1/1
4/2/2
20/20/20
25

1.0/0.7/0.7
2.0/1.5/1.5
10
25
120
90

3.4

4.0
200
20
1.0
0.0003

18
1.2

3.4
18
1.2

1.2

3 1012i5.5
3 1012i5.5

3 1012i5.5
3 1012i5.5

3 1012i5.5
3 1012i5.5

ipF
ipF

20
+14.5, 11.5

20
+14.5, 11.5

20
+14.5, 11.5

+VS 2

88
84
84
80

VS + 4

5.0

86
86
76
74

0.01
400

200
100

200
100

+13, 12.5 +13.9, 13.3

612
+13.8, 13.1
25

618
6.8

64.5

15
5.0

+VS 2 V

VS + 4

2
45
22
18
16

0.01

15

+VS 2

88
84
84
80

80
80
76
74

150
400
100/100/100

64.5

86
86

Max

20
1.3

OUTPUT CHARACTERISTICS
Voltage
+13, 12.5
+13.9, 13.3
12/ 12/612 +13.8, 13.1
Current
25
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current

0.1

1.0/0.7/0.7
2.0/1.5/1.5
10

15

2
45
22
18
16

INPUT CURRENT NOISE

AD712C
Typ

75
1.7/4.8/77
100

VS + 4

76
76/76/76
70
70/70/70

7
100

80
80

Min

20
0.5/1.3/20

4.0
200
20
1.0
0.0003

INPUT VOLTAGE RANGE

Differential3
Common-Mode Voltage4
TMIN to TMAX
Common-Mode
Rejection Ratio
VCM = 10 V
TMIN to TMAX
VCM = 11 V
TMIN to TMAX

0.2

3/1/1
4/2/2
20/20/20

Max

75
1.7/4.8/77
100

FREQUENCY RESPONSE
Small Signal Bandwidth
Full Power Response
Slew Rate
Settling Time to 0.01%
Total Harmonic Distortion
INPUT IMPEDANCE
Differential
Common Mode

AD712K/B/T
Typ

25
0.6/1.6/26

120
90

16

Min

15

MATCHING CHARACTERISTICS
Input Offset Voltage
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
Crosstalk @ f = 1 kHz
@ f = 100 kHz

3.0

Max

94
90
90
84

dB
dB
dB
dB

2
45
22
18
16

V p-p
nV/Hz
nV/Hz
nV/Hz
nV/Hz

0.01

pA/Hz

400

V/mV
V/mV

+13, 12.5 +13.9, 13.3

612
+13.8, 13.1
25

618
6.0

64.5

15
5.0

V
V
mA

618
5.6

V
V
mA

NOTES
1
Input Offset Voltage specifications are guaranteed after 5 minutes of operation at T A = +25C.
2
Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +25C. For higher temperatures, the current doubles every 10C.
3
Defined as voltage between inputs, such that neither exceeds 10 V from ground.
4
Typically exceeding 14.1 V negative common-mode voltage on either input results in an output phase reversal.
Specifications subject to change without notice.

REV. A

AD712
ABSOLUTE MAXIMUM RATINGS 1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Internal Power Dissipation2
Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and VS
Storage Temperature Range (Q, H) . . . . . . . . 65C to +150C
Storage Temperature Range (N, R) . . . . . . . . 65C to +125C
Operating Temperature Range
AD712J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
AD712A/B/C . . . . . . . . . . . . . . . . . . . . . . . . 40C to +85C
AD712S/T . . . . . . . . . . . . . . . . . . . . . . . . . 55C to +125C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Thermal Characteristics:
8-Pin Plastic Package:
JA = 165C/Watt
8-Pin Cerdip Package:
JC = 22C/Watt; JA = 110C/Watt
8-Pin Metal Can Package:
JC = 65C/Watt; JA = 150C/Watt
8-Pin SOIC Package:
JA = 100C
3
For supply voltages less than 18 V, the absolute maximum input voltage is equal
to the supply voltage.

ORDERING GUIDE
Model

Temperature
Range

Package
Description

AD712ACHIPS
AD712AH
AD712AQ
AD712BH
AD712BQ
AD712CH
AD712CQ
AD712JN
AD712JR
AD712JR-REEL
AD712JR-REEL7
AD712KN
AD712KR
AD712KR-REEL
AD712KR-REEL7
AD712SCHIPS
AD712SQ
AD712SQ/883B
AD712TQ
AD712TQ/883B

40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
0C to +70C
55C to +125C
55C to +125C
55C to +125C
55C to +125C
55C to +125C

Bare Die
8-Pin Metal Can
8-Pin Ceramic DIP
8-Pin Metal Can
8-Pin Ceramic DIP
8-Pin Metal Can
8-Pin Ceramic DIP
8-Pin Plastic DIP
8-Pin Plastic SOIC
8-Pin Plastic SOIC
8-Pin Plastic SOIC
8-Pin Plastic DIP
8-Pin Plastic SOIC
8-Pin Plastic SOIC
8-Pin Plastic SOIC
Bare Die
8-Pin Ceramic DIP
8-Pin Ceramic DIP
8-Pin Ceramic DIP
8-Pin Ceramic DIP

METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm)
Contact factory for latest dimensions.

REV. A

Package
Option
H-08A
Q-8
H-08A
Q-8
H-08A
Q-8
N-8
R-8
R-8
R-8
N-8
R-8
R-8
R-8
Q-8
Q-8
Q-8
Q-8

AD712Typical Characteristics

Figure 1. Input Voltage Swing vs.

Supply Voltage

Figure 2. Output Voltage Swing vs.

Supply Voltage

Figure 3. Output Voltage Swing

vs. Load Resistance

Figure 4. Quiescent Current vs.

Supply Voltage

Figure 5. Input Bias Current vs.

Temperature

Figure 6. Output Impedance vs.

Frequency

Figure 7. Input Bias Current vs.

Common Mode Voltage

Figure 8. Short Circuit Current

Limit vs. Temperature

Figure 9. Unity Gain Bandwidth vs.

Temperature

REV. A

AD712

Figure 10. Open-Loop Gain and

Phase Margin vs. Frequency

Figure 13. Common Mode Rejection vs. Frequency

Figure 16. Total Harmonic Distortion vs. Frequency

REV. A

Figure 11. Open-Loop Gain vs.

Supply Voltage

Figure 14. Large Signal Frequency

Response

Figure 17. Input Noise Voltage

Spectral Density

Figure 12. Power Supply Rejection

vs. Frequency

Figure 15. Output Swing and Error

vs. Settling Time

Figure 18. Slew Rate vs. Input

Error Signal

AD712

Figure 20. T.H.D. Test Circuit

Figure 19. Slew Rate vs. Temperature

Figure 21. Crosstalk Test Circuit

Figure 22a. Unity Gain Follower

Figure 22b. Unity Gain Follower

Pulse Response (Large Signal)

Figure 22c. Unity Gain Follower

Pulse Response (Small Signal)

Figure 23a. Unity Gain Inverter

Figure 23b. Unity Gain Inverter Pulse

Response (Large Signal)

Figure 23c. Unity Gain Inverter

Pulse Response (Small Signal)

REV. A

AD712
OPTIMIZING SETTLING TIME

Most bipolar high-speed D/A converters have current outputs;

therefore, for most applications, an external op amp is required
for current-to-voltage conversion. The settling time of the converter/op amp combination depends on the settling time of the
DAC and output amplifier. A good approximation is:
t S Total = (t S DAC )2 + (t S AMP )2

The settling time of an op amp DAC buffer will vary with the
noise gain of the circuit, the DAC output capacitance, and with
the amount of external compensation capacitance across the
DAC output scaling resistor.
Settling time for a bipolar DAC is typically 100 to 500 ns. Previously, conventional op amps have required much longer settling
times than have typical state-of-the-art DACs; therefore, the
amplifier settling time has been the major limitation to a
high-speed voltage-output D-to-A function. The introduction of
the AD711/712 family of op amps with their 1 s (to 0.01% of
final value) settling time now permits the full high-speed capabilities of most modern DACs to be realized.

In addition to a significant improvement in settling time, the

low offset voltage, low offset voltage drift, and high open-loop
gain of the AD711/AD712 family assures 12-bit accuracy over
the full operating temperature range.
The excellent high-speed performance of the AD712 is shown in
the oscilloscope photos of Figure 25. Measurements were taken
using a low input capacitance amplifier connected directly to the
summing junction of the AD712 both photos show the worst
case situation: a full-scale input transition. The DACs 4 k
[10 k||8 k=4.4 k] output impedance together with a 10 k
feedback resistor produce an op amp noise gain of 3.25. The
current output from the DAC produces a 10 V step at the op
amp output (0 to 10 V Figure 25a, 10 V to 0 V Figure 25b.)
Therefore, with an ideal op amp, settling to 1/2 LSB ( 0.01%)
requires that 375 V or less appears at the summing junction.
This means that the error between the input and output (that
voltage which appears at the AD712 summing junction) must be
less than 375 V. As shown in Figure 25, the total settling time
for the AD712/AD565 combination is 1.2 microseconds.

Figure 24. 10 V Voltage Output Bipolar DAC

a. (Full-Scale Negative Transition)

b. (Full-Scale Positive Transition)

Figure 25. Settling Characteristics for AD712 with AD565A

REV. A

AD712
OP AMP SETTLING TIME A MATHEMATICAL MODEL

The design of the AD712 gives careful attention to optimizing

individual circuit components; in addition, a careful tradeoff was
made: the gain bandwidth product (4 MHz) and slew rate
(20 V/s) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction in
phase margin (and therefore stability). Thus designed, the
AD712 settles to 0.01%, with a 10 V output step, in under
1 s, while retaining the ability to drive a 250 pF load capacitance when operating as a unity gain follower.
If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency of /2, Equation 1 will accurately describe the small signal behavior of the circuit of Figure 26a, consisting of an op amp connected as an I-to-V converter at the
output of a bipolar or CMOS DAC. This equation would completely describe the output of the system if not for the op amps
finite slew rate and other nonlinear effects.
Equation 1.
VO
R
=
I IN
R(C f = CX ) 2 GN

s +
+ RC f s + 1

where 2 =op amps unity gain frequency

simple inverting op amp is being simulated OR it is the combined capacitance of the DAC output and the op amp input if
the DAC buffer is being modeled.

Figure 26b. Simplified Model of the AD712

Used as an Inverter

In either case, the capacitance CX causes the system to go from

a one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Since the value of CX can be estimated with reasonable
accuracy, Equation 2 can be used to choose a small capacitor,
CF, to cancel the input pole and optimize amplifier response.
Figure 27 is a graphical solution of Equation 2 for the AD712
with R = 4 k.

GN = noise gain of circuit 1 + R

O
This equation may then be solved for Cf:
Equation 2.
Cf =

2 GN 2 RC X + (1 GN )
+
R
R

In these equations, capacitor CX is the total capacitor appearing

the inverting terminal of the op amp. When modeling a DAC
buffer application, the Norton equivalent circuit of Figure 26a
can be used directly; capacitance CX is the total capacitance of
the output of the DAC plus the input capacitance of the op amp
(since the two are in parallel).
Figure 27. Value of Capacitor CF vs. Value of CX

The photos of Figures 28a and 28b show the dynamic response
of the AD712 in the settling test circuit of Figure 29.

Figure 26a. Simplified Model of the AD712 Used as a

Current-Out DAC Buffer

When RO and IO are replaced with their Thevenin VIN and RIN
equivalents, the general purpose inverting amplifier of Figure
26b is created. Note that when using this general model, capacitance CX is EITHER the input capacitance of the op amp if a

Figure 28a. Settling Characteristics 0 to +10 V Step

Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)

REV. A

AD712
TO-99 (H) Package

Figure 28b. Settling Characteristics 0 to 10 V Step

Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)

The input of the settling time fixture is driven by a flat-top pulse

generator. The error signal output from the false summing node
of A1 is clamped, amplified by A2 and then clamped again. The
error signal is thus clamped twice: once to prevent overloading
amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. The Tektronix oscilloscope preamp type
7A26 was carefully chosen because it does not overload with
these input levels. Amplifier A2 needs to be a very high speed
FET-input op amp; it provides a gain of 10, amplifying the error
signal output of A1.
GUARDING

The low input bias current (15 pA) and low noise characteristics
of the AD712 BiFET op amp make it suitable for electrometer
applications such as photo diode preamplifiers and picoampere
current-to-voltage converters. The use of a guarding technique
such as that shown in Figure 30, in printed circuit board layout
and construction is critical to minimize leakage currents. The
guard ring is connected to a low impedance potential at the
same level as the inputs. High impedance signal lines should not
be extended for any unnecessary length on the printed circuit
board.

Figure 30. Board Layout for Guarding Inputs

D/A CONVERTER APPLICATIONS

The AD712 is an excellent output amplifier for CMOS DACs.

It can be used to perform both 2 quadrant and 4 quadrant operation. The output impedance of a DAC using an inverted
R-2R ladder approaches R for codes containing many 1s, 3R for
codes containing a single 1, and for codes containing all zero,
the output impedance is infinite.
For example, the output resistance of the AD7545 will modulate between 11 k and 33 k. Therefore, with the DACs internal feedback resistance of 11 k, the noise gain will vary from
2 to 4/3. This changing noise gain modulates the effect of the
input offset voltage of the amplifier, resulting in nonlinear DAC
amplifier performance.
The AD712K with guaranteed 700 V offset voltage minimizes
this effect to achieve 12-bit performance.
Figures 31 and 32 show the AD712 and AD7545 (12-bit
CMOS DAC) configured for unipolar binary (2-quadrant multiplication) or bipolar (4-quadrant multiplication) operation. Capacitor C1 provides phase compensation to reduce overshoot
and ringing.

Figure 29. Settling Time Test Circuit

REV. A

Plastic Mini-DIP (N) Package

and Cerdip (Q) Package

AD712
NOISE CHARACTERISTICS

The random nature of noise, particularly in the 1/f region,

makes it difficult to specify in practical terms. At the same time,
designers of precision instrumentation require certain guaranteed maximum noise levels to realize the full accuracy of their
equipment.
The AD712C grade is specified at a maximum level of 4.0 V
p-p, in a 0.1 to 10 Hz bandwidth. Each AD712C receives a
100% noise test for two 10-second intervals; devices with any
excursion in excess of 4.0 V are rejected. The screened lot is
then submitted to Quality Control for verification on an AQL
basis.
All other grades of the AD712 are sample-tested on an AQL
basis to a limit of 6 V p-p, 0.1 to 10 Hz
DRIVING THE ANALOG INPUT OF AN A/D CONVERTER

Figure 31. Unipolar Binary Operation

An op amp driving the analog input of an A/D converter, such

as that shown in Figure 34, must be capable of maintaining a
constant output voltage under dynamically changing load conditions. In successive-approximation converters, the input current
is compared to a series of switched trial currents. The comparison point is diode clamped but may deviate several hundred
millivolts resulting in high frequency modulation of A/D input
current. The output impedance of a feedback amplifier is made
artificially low by the loop gain. At high frequencies, where the
loop gain is low, the amplifier output impedance can approach
its open loop value. Most IC amplifiers exhibit a minimum open
loop output impedance of 25 due to current limiting resistors.

Figure 32. Bipolar Operation

R1 and R2 calibrate the zero offset and gain error of the DAC.
Specific values for these resistors depend upon the grade of
AD7545 and are shown below.
Table I. Recommended Trim Resistor Values vs. Grades
of the AD7545 for VDD = +5 V
TRIM
RESISTOR JN/AQ/SD KN/BQ/TD LN/CQ/UD GLN/GCQ/GUD

R1
R2

500
150

200
68

100
33

20
6.8

Figure 34. AD712 as ADC Unity Gain Buffer

Figures 33a and 33b show the settling time characteristics of the
AD712 when used as a DAC output buffer for the AD7545.

a. Source Current = 2 mA
a. Full-Scale Positive
Transition

b. Sink Current = 1 mA

Figure 35. ADC Input Unity Gain Buffer Recovery Times

b. Full-Scale Negative
Transition

Figure 33. Settling Characteristics for AD712 with AD7545

10

REV. A

AD712
The use of a high performance amplifier such as the AD712 will
minimize both dc and ac errors in all active filter applications.

A few hundred microamps reflected from the change in converter

loading can introduce errors in instantaneous input voltage. If
the A/D conversion speed is not excessive and the bandwidth of
the amplifier is sufficient, the amplifiers output will return to
the nominal value before the converter makes its comparison.
However, many amplifiers have relatively narrow bandwidth
yielding slow recovery from output transients. The AD712 is
ideally suited to drive high speed A/D converters since it offers
both wide bandwidth and high open-loop gain.

SECOND ORDER LOW PASS FILTER

Figure 38 depicts the AD712 configured as a second order

Butterworth low pass filter. With the values as shown, the corner
frequency will be 20 kHz; however, the wide bandwidth of the
AD712 permits a corner frequency as high as several hundred
kilohertz. Equations for component selection are shown below.
R1 = R2 = user selected (typical values: 10 k 100 k)

DRIVING A LARGE CAPACITIVE LOAD

The circuit in Figure 36 employs a 100 isolation resistor

which enables the amplifier to drive capacitive loads exceeding
1500 pF; the resistor effectively isolates the high frequency feedback from the load and stabilizes the circuit. Low frequency
feedback is returned to the amplifier summing junction via the
low pass filter formed by the 100 series resistor and the load
capacitance, CL. Figure 37 shows a typical transient response
for this connection.

C1 (in farads ) =

1.414
0.707
C2 =
(2)( f cutoff )(R1)
(2)( f cutoff )(R1)

Figure 38. Second Order Low Pass Filter

An important property of filters is their out-of-band rejection.

The simple 20 kHz low pass filter shown in Figure 38, might be
used to condition a signal contaminated with clock pulses or
sampling glitches which have considerable energy content at
high frequencies.
Figure 36. Circuit for Driving a Large Capacitive Load

The low output impedance and high bandwidth of the AD712

minimize high frequency feedthrough as shown in Figure 39.
The upper trace is that of another low-cost BiFET op amp
showing 17 dB more feedthrough at 5 MHz.

Figure 37. Transient Response RL = 2 k, CL = 500 pF

ACTIVE FILTER APPLICATIONS

In active filter applications using op amps, the dc accuracy of

the amplifier is critical to optimal filter performance. The
amplifiers offset voltage and bias current contribute to output
error. Offset voltage will be passed by the filter and may be amplified to produce excessive output offset. For low frequency
applications requiring large value input resistors, bias currents
flowing through these resistors will also generate an offset voltage.
In addition, at higher frequencies, an op amps dynamics must
be carefully considered. Here, slew rate, bandwidth, and
open-loop gain play a major role in op amp selection. The slew
rate must be fast as well as symmetrical to minimize distortion.
The amplifiers bandwidth in conjunction with the filters gain
will dictate the frequency response of the filter.

REV. A

Figure 39.
9-POLE CHEBYCHEV FILTER

Figure 40 shows the AD712 and its dual counterpart, the

AD711, as a 9-pole Chebychev filter using active frequency dependent negative resistors (FDNR). With a cutoff frequency of
50 kHz and better than 90 dB rejection, it may be used as an
anti-aliasing filter for a 12-bit Data Acquisition System with
100 kHz throughput.
As shown in Figure 40, the filter is comprised of four FDNRs
(A, B, C, D) having values of 4.9395 3 1015 and 5.9276 3
1015 farad-seconds. Each FDNR active network provides a
two-pole response; for a total of 8 poles. The 9th pole consists
11

AD712
0.001 F capacitors must be selected for 1% or better matching
and all resistors should have 1% or better tolerance.

C1020b-20-3/88

of a 0.001 F capacitor and a 124 k resistor at Pin 3 of amplifier A2. Figure 41 depicts the circuits for each FDNR with the
proper selection of R. To achieve optimal performance, the

Figure 40. 9-Pole Chebychev Filter

Figure 42. High Frequency Response for 9-Pole

Chebychev Filter

Figure 41. FDNR for 9-Pole Chebychev Filter

OUTLINE DIMENSIONS
Mini-DIP (N) Package

Cerdip (Q) Package

TO-99 (H) Package

SOIC (R) Package

12

PRINTED IN U.S.A.

Dimensions shown in inches and (mm).

REV. A