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    Clock Dividers Made Easy

    Uploaded by

    anubhaw2004
    This document discusses clock dividers and duty cycles. It explains that a clock divider takes an input signal frequency and generates an output signal with a lower frequency that is a ratio of the input. A 50% duty cycle means the signal is active for half the period. Dividing a clock by an even number always produces a 50% duty cycle output. For odd divisions, two clocks can be generated at half the output frequency with a 90 degree phase difference, and XOR'ing them produces the output with a 50% duty cycle. Non-integer divisions cannot achieve exactly 50% duty cycle but can get close using look-up tables.

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    Clock Dividers Made Easy

    Uploaded by

    anubhaw2004
    71 views25 pages
    This document discusses clock dividers and duty cycles. It explains that a clock divider takes an input signal frequency and generates an output signal with a lower frequency that is a ratio of the input. A 50% duty cycle means the signal is active for half the period. Dividing a clock by an even number always produces a 50% duty cycle output. For odd divisions, two clocks can be generated at half the output frequency with a 90 degree phase difference, and XOR'ing them produces the output with a 50% duty cycle. Non-integer divisions cannot achieve exactly 50% duty cycle but can get close using look-up tables.

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    It about the Clock Dividers.

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    89208169 Clock Dividers Made Easy

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    This document discusses clock dividers and duty cycles. It explains that a clock divider takes an input signal frequency and generates an output signal with a lower frequency that is a ratio of the input. A 50% duty cycle means the signal is active for half the period. Dividing a clock by an even number always produces a 50% duty cycle output. For odd divisions, two clocks can be generated at half the output frequency with a 90 degree phase difference, and XOR'ing them produces the output with a 50% duty cycle. Non-integer divisions cannot achieve exactly 50% duty cycle but can get close using look-up tables.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    71 views25 pages

    Clock Dividers Made Easy

    Uploaded by

    anubhaw2004
    This document discusses clock dividers and duty cycles. It explains that a clock divider takes an input signal frequency and generates an output signal with a lower frequency that is a ratio of the input. A 50% duty cycle means the signal is active for half the period. Dividing a clock by an even number always produces a 50% duty cycle output. For odd divisions, two clocks can be generated at half the output frequency with a 90 degree phase difference, and XOR'ing them produces the output with a 50% duty cycle. Non-integer divisions cannot achieve exactly 50% duty cycle but can get close using look-up tables.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 25

    Clock Dividers Made Easy

    WHAT IS A CLOCK DIVIDER ?

     A CLOCK DIVIDER or FREQUENCY DIVIDER is


    an electronic circuit that takes an input signal with a frequency , fin,
    and generates an output signal with a frequency:

    where n is an integer.
    WHAT IS 50 % DUTY CYCLE ?

     the duty cycle is the fraction of time that a system is in an "active" state.

     In a periodic phenomenon, the ratio of the duration of the phenomenon in


    a given period to the period.

    duty cycle
    where
    τ is the duration that the function is active high (normally when the
    signal is greater than zero);
    Τ is the period of the function.
    WHY 50 % DUTY CYCLE

     Duty cycle tells the time intervals devoted to starting, running,


    stopping, and idling when a device is used for intermittent duty.
     It tells a machine's rated capacity to continuously perform work
    under normal conditions. It generally applies to mechanical devices
    such as printers, in which case it would indicate the number of
    pages that can be printed per month without a problem.
     In engineering :
    The ratio of a device operating versus cooling down. An 80% duty
    cycle means that it is capable of running 80% of a specified time
    period and turned off for the remainder.
     In radar engineering :
    Duty cycle (or duty factor) is a measure of the fraction of the time a
    radar is transmitting.

     In metallurgy :
    Duty cycle gives the percentage of time that current flows in
    equipment over a specific period during electric resistance welding.
     Dividing a clock by an even number always generates
    50% duty cycle output.

     Sometimes it is necessary to generate a 50% duty cycle


    frequency even when the input clock is divided by an
    odd or non-integer number. This paper talks about
    implementation of unusual clock dividers.
    Odd integer division with
    50% duty cycle
    The easiest way to create an odd divider with a 50% duty
    cycle is to generate two
    clocks at half the desired output frequency with a
    quadrature-phase relationship (constant 90° phase
    difference between the two clocks).
    You can then generate the output frequency by
    exclusive-ORing the two waveforms together.
     STEP I: Create a counter that counts from 0 to (N –1)
    and always clocks on the rising edge of the input clock.

     STEP II: Take two toggle flip-flops and generate their


    enables as follows:
    tff1_en : T FF1 enabled when the counter value = 0
    tff2_en : T FF2 enabled when the counter value = (2 for
    Divide by 3 counter , 3 for Divide by 5 counter, 4 for
    Divide by 7 counter and likewise).
     STEP III :
    div1 : output of T FF1 triggered on rising edge
    of input clock (ref_clk).
    div2 : output of T FF2 triggered on falling edge
    of input clock (ref_clk).
     STEP IV :
    Final output clock: clkout (Divide by N) is
    generated by XORing the div1 and div2
    waveforms.
    Non-integer division (duty cycle
    not 50%)
    Alternative approach for
    divide by-N

    All the circuits use combinatorial feedback around


    a LUT (look up table) that works perfectly
    Divide by 1.5
    ( LUT implementation)
    CONCLUSION

     The circuits are simple , efficient and are cheaper and


    faster.
     In case of non-integer clock dividers (divide by
    1.5,divide by 2.5 etc) one cannot get anything better
    than 40 % - 60 % duty cycle with a digital circuits.
    THANK YOU

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