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    MWO SI Brochure

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    AWR Corporation
    Microwave office® For signal integrity signal integrity solution for High-speed Designs Using AWR’s ACE technology, Multitest is able to accurately and efficiently simulate PCB interfaces prior to fabrication. This gives our customers the confidence they need before they even receive our hardware. Ryan Satrom, Signal Integrity Engineer Multitest AWR signal integrity (SI) solution incorporates key elements of our flagship Microwave Office design suite along side Synopsys’ world class HSPICE®

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    MWO SI Brochure

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    AWR Corporation
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    Microwave office® For signal integrity signal integrity solution for High-speed Designs Using AWR’s ACE technology, Multitest is able to accurately and efficiently simulate PCB interfaces prior to fabrication. This gives our customers the confidence they need before they even receive our hardware. Ryan Satrom, Signal Integrity Engineer Multitest AWR signal integrity (SI) solution incorporates key elements of our flagship Microwave Office design suite along side Synopsys’ world class HSPICE®

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    Microwave office® For signal integrity signal integrity solution for High-speed Designs Using AWR’s ACE technology, Multitest is able to accurately and efficiently simulate PCB interfaces prior to fabrication. This gives our customers the confidence they need before they even receive our hardware. Ryan Satrom, Signal Integrity Engineer Multitest AWR signal integrity (SI) solution incorporates key elements of our flagship Microwave Office design suite along side Synopsys’ world class HSPICE®

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    59 views4 pages

    MWO SI Brochure

    Uploaded by

    AWR Corporation
    Microwave office® For signal integrity signal integrity solution for High-speed Designs Using AWR’s ACE technology, Multitest is able to accurately and efficiently simulate PCB interfaces prior to fabrication. This gives our customers the confidence they need before they even receive our hardware. Ryan Satrom, Signal Integrity Engineer Multitest AWR signal integrity (SI) solution incorporates key elements of our flagship Microwave Office design suite along side Synopsys’ world class HSPICE®

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    Microwave

    Office® For
    Signal Integrity
    Signal Integrity Using AWR’s ACE technology, Multitest is able to accurately
    Solution for and efficiently simulate PCB interfaces prior to fabrication.
    High-Speed Designs This gives our customers the confidence they need before
    they even receive our hardware.

    Ryan Satrom, Signal Integrity Engineer


    Multitest

    AWR signal integrity (SI) solution incorporates key elements of our flagship
    Microwave Office design suite along side Synopsys’ world class HSPICE® spice
    simulator in order to provide engineers with the tools they need to meet the
    demanding and challenging needs of today’s high-data-rate designs. With speeds
    increasing from hundreds of megabits per second to gigabits per second, high-data-
    rate digital signals deviate from the “norm” and become analog in nature, requiring
    an entirely new approach to design. That is, high-frequency design tools, including
    electromagnetic (EM) simulation, are essential when designing systems operating
    at these speeds. This fact, plus the increased number of variables that must be
    addressed when creating high-speed designs, is precisely why Microwave Office for
    Signal Integrity (also known as AWR SI) exists.

    Productivity-focused Design Flow


    Ready for today’s high-speed designs AWR SI can concurrently manage
    multiple stack-ups, or technology files, representing the integrated circuits (ICs),
    their packages, the printed circuit board (PCB), and all associated die-to-board
    electrical models. This gives you much more flexibility for verification. It is no
    longer necessary to extract macro-models of IC-level components for simulation
    with package- and PCB-level models – you can now co-design module-level
    Gbps interconnects with driver and receiver circuitry at the transistor level
    or using IBIS macromodels, while including the effects of bond-wires and
    surface-mount PCB devices. Packaging limitations and die constraints can
    be taken into account early in the design process, so that you can avoid
    after-the-fact design problems that come from oversimplied off-die load
    model, and eliminate the painful debugging process of trying to fix them

    user-flexible Design Environment


    An AWR founding principle is that our customers should be able to
    integrate tools from third parties to give them the most complete solution
    at different stages of the design process. That commitment continues
    today with an even greater array of options than ever.

    HSPICE simulation AWR SI seamlessy integrates HSPICE from Synopsys


    — the gold standard for over 25 years in IC circuit simulation. All major
    foundries provide HSPICE transistor models for sign-off simulation, and
    chip vendors provide either IBIS or triple-DES encrypted netlists for
    HSPICE. The HSPICE integration also includes a special interface layer to
    enforce passivity and causality on imported S-parameter data sets.
    Frequency- and time-domain simulation (APLAC®/HSPICE) Adaptively mapping
    chip/package/board layouts to simulation-ready models, AWR SI enables you to Design issues are compounded when the
    simulate in both frequency- and time-domain and to migrate between the two, previously packaged IC is integrated onto a PCB
    all the while combining transistor level or IBIS models, S-parameter files, HSPICE that includes of bond wires, bumps, and vias.
    encrypted netlists, and more.

    EM Socket™: plug and play with third-party EM point tools AWR’s EM Socket
    integrates popular EM solvers into the flow -- without leaving AWR SI. Choose tools
    like AWR’s own ACE™, AXIEM™ or EMSight™, as well as those from vendors like
    CST, Sonnet, Zeland, and more… as high performing high speed interconnects are
    best modeled in the frequency-domain with EM technologies such as these.

    PCB and packaging co-design support Integration of existing pre-designed PCB


    and package layouts is supported by AWR SI through AWR Connected™ and Alliance
    Partners for third-party products from Mentor Graphics, Cadence and others.

    use-Model Specific features


    As clock rates and signal speeds increase, inclusion of high-frequency
    electromagnetic effects are necessary to model the
    complexities of fast, leading-edge signals, variable
    fanouts, dense interconnects, and complex loads
    and receivers. AWR SI offers multiple ways to
    generate signals for high-speed digital design and
    analysis:

    • Tuning – AWR SI’s real-time tuning gives


    immediate feedback regarding design
    performance but, more importantly, it
    provides a ready way to evaluate multiple
    “what if” scenarios.

    • Eye diagram – One of the best visual aids for


    evaluating the robustness of a high-speed
    data design; Eye diagram is fully supported
    within AWR SI and a comprehensive set of eye
    measurements is provided like jitter,
    under/overshoot, rise/fall time, eye quality
    factor and more.
    Eye diagram – AWR SI and HSPICE produce accurate signal integrity
    simulation results by combining the best nonlinear I/O buffer models
    available with 100 GHz validated distributed element models.
    www.awrcorp.com
    www.awr.tv

    USA Key Features of Microwave Office


    Corporate Headquarters for Signal Integrity
    AWR Corporation
     Powerful, concurrent, and unified signal integrity analysis environment for
    1960 E. Grand Avenue, Suite 430
    high-frequency/high-speed designs
    El Segundo, CA 90245
     Simultaneously consider interconnects across IC, package, and PCB
    +1 310 726 3000
     Synopsys’ HSPICE for fast and accurate time-domain simulation
    +1 310 726 3005 (fax)
     AWR’s APLAC high-speed, high-capacity harmonic balance and transient
    Japan simulator for comprehensive and accurate frequency/time-domain simulation

    AWR Japan KK  Supports signals from hardware, IBIS models, MatLab co-simulation, and
    encrypted HSPICE
    Level 5, 711 Building
     ACE automatic circuit extraction technology provides 10,000x speed
    7-11-18 Nishi-Shinjuku, Shinjuku-ku
    improvement over EM simulation
    Tokyo 160-0023 Japan
     Intelligent Net™ (iNet) technology extracts interconnects across
    +81 3 5937 4803 multiple technology domains

    Korea  EM Socket for easy access to multiple EM simulation and


    analysis tools, including AWR’s ACE, AXIEM and EMSight
    AWR Korea Co. Ltd. technologies
    B-1412, Intellige-II, 24 Jeongja-dong,
     Imports/supports a variety of models, including circuit
    Bundang-gu, Seongnam-si, netlist, multiple models such as circuit netlist (SPICE or
    Gyeonggi-do, South Korea, 463-811 Spectre format), IBIS, S-parameter block, etc.

    +82.31.603.7772~3  Third party PCB and package co-design support from.


    Cadence, Mentor, and others (optional)
    UK  Visualization, including real-time tuning for what if
    AWR UK analysis, eye diagrams for performance checks, and
    more
    2 Hunting Gate
    Hitchin, Herts
    SG4 0TJ, UK
    +44 (0) 1462 428 428

    Finland
    AWR – APLAC
    Lars Sonckin kaari 16
    FI-02600 Espoo, Finland
    +358 10 834 5900

    France
    AWR France
    140 Avenue Champs Elysees
    75008 Paris, France
    +33 1 70 36 19 63

    Copyright © 2010 AWR Corporation. All rights reserved. AWR and the AWR logo, Microwave Office and
    APLAC are registered trademarks and AXIEM, ACE, AWR Connected, EMSight, EM Socket and Intelligent Net
    are trademarks of AWR Corporation. All others are the property of their respective holders.

    BR-MWO-SI-2010.5.10

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